AN3338 STMICROELECTRONICS | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1 Inverter design concept and SLLIMM solution
- 1.1 Product synopsis
- 1.2 Product line-up and nomenclature
- 1.3 Internal circuit
- 1.4 Absolute maximum ratings
- 2 Electrical characteristics and functions
- 2.1 IGBTs
- 2.2 Freewheeling diodes
- 2.3 High voltage gate drivers
- 2.3.1 Logic inputs
- 2.3.2 High voltage level shift
- 2.3.3 Undervoltage lockout
- 2.3.4 Dead time and interlocking function management
- 2.3.5 Comparators for fault sensing
- 2.3.6 Short-circuit protection and smart shutdown function
- 2.3.8 Current sensing shunt resistor selection
- 2.3.9 RC filter network selection
- 2.3.10 Overtemperature protection
- 2.3.11 Op amps for advanced current sensing
- 2.3.12 Bootstrap circuit
- 2.3.13 Bootstrap capacitor selection
- 2.3.14 Initial bootstrap capacitor charging
- 3 Package
- 3.1 DBC substrate
- 3.2 PCB
- 3.3 Package structure
- 3.4 Package outline and dimensions
- 3.5 Input and output pins description
- 4 Power losses and dissipation
March 2015 Doc ID 18441 Rev 4 1/72 AN3338 Application note SLLIMM™ small low-loss intelligent molded module By Carmelo Parisi and Giovanni Tomasello Introduction In recent years the variable speed motor control market has required high performance solutions able to satisfy the increasing energy saving requirements, compactness, reliability, and system costs in home appliances, such as washing machines, dish washers, refrigerators, air conditioning compressor drives, and in low power industrial applications, such as sewing machines, pumps, tools, etc. To meet these market needs, STMicroelectronics has developed a new family of compact, high efficiency, dual-in-line intelligent power modules, with optional extra features, called small low-loss intelligent molded module (SLLIMM™). The SLLIMM product family combines optimized silicon chips, integrated in three main inverter blocks:
- power stage – six short-circuit rugged IGBTs – six freewheeling diodes
- driving network – three high voltage gate drivers – discrete gate resistors – three bootstrap diodes
- protection and optional features – op amps for advanced current sensing – comparators for fault protection against overcurrent and short-circuit – NTC sensor for temperature control – smart shutdown function – dead time, interlocking function and undervoltage lockout. Thanks to the state of art DBC mounting technology, the fully isolated SLLIMM package (SDIP) offers extremely low thermal resistance with optimum cost-effectiveness and quality level. Compared to discrete-based inverters, including power devices, and driver and protection circuits, the SLLIMM family provides a high integrated level that means simplified circuit design, reduced component count, smaller weight, and high reliability. The aim of this application note is to provide a detailed description of SLLIMM products, providing guidelines to motor drive designers for an efficient, reliable, and fast design when using the new ST SLLIMM family.
Table 8. Interlocking function truth table of STGIPS14K60, STGIPL14K60, STGIPS20K60, and ST-
1 Inverter design concept and SLLIMM solution
size, and cost constraints required in a number of markets. sensors for protections and feedback signals for controls. of components and the significant stray inductances and dispersions in the board layout. reliability and quality level. of protection, and lower propagation delay time. Figure 1. Inverter motor drive block diagram
1.1 Product synopsis
- washing machines
- dish washers
- refrigerators
- air conditioning compressor drives
- sewing machines
- pumps
- tools
- low power industrial applications The main features and integrated functions can be summarized as follows:
- 600 V, 10 - 30 A ratings
- 3-phase IGBT inverter bridge including: – six low-loss and short-circuit protected IGBTs – six low forward voltage drop and soft recovery freewheeling diodes
- three control ICs for gate driving and protection including: – smart shutdown function – comparator for fault protection against overcurrent and short-circuit – op amps for advanced current sensing – three integrated bootstrap diodes – interlocking function – undervoltage lockout
Figure 2. Discrete-based inverter vs. SLLIMM solution comparison
AN3338 Inverter design concept and SLLIMM solution
1.2 Product line-up and nomenclature
Table 1. SLLIMM line-up(1)
- For additional information and the complete product portfolio, refer to www.st.com/modules.
Features
Basic version Fully featured version STGIPS10K60A STGIPS14K60 STGIPL 14K60 STGIPS20K60 STGIPL20K60 Voltage (V) 600 600 600 600 600 Current @ TC=25 °C (A) 10 14 15 18 20 RthJC max. single IGBT Package type SDIP-25L SDIP-25L SDIP-38L SDIP-25L SDIP-38L Package size DBC substrate Yes Yes Yes Yes Yes NTC Yes No Yes No Yes Integrated bootstrap diode Yes Yes Yes Yes Yes SD function No Yes Yes Yes Yes Comparator for fault protection No Yes (1 pin) Yes (3 pins) Yes (1 pin) Yes (3 pins) Smart shutdown function No Yes Yes Yes Yes Op amps for advanced current sensing No No Yes No Yes Interlocking function Yes Yes Yes Yes Yes Undervoltage lockout Yes Yes Yes Yes Yes Open emitter configuration Yes (3 pins) Yes (3 pins) Yes (3 pins) Yes (3 pins) Yes (3 pins) 3.3 / 5 V input interface compatibility Yes Yes Yes Yes Yes High side IGBT input signal Active High Active High Active High Active High Active High Low side IGBT input signal Active High Active Low Active Low Active Low Active Low
Figure 4. SLLIMM nomenclature
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1.3 Internal circuit
Figure 5. Internal circuit of STGIPS10K60A
Figure 6. Internal circuit of STGIPS14K60 and STGIPS20K60
1.4 Absolute maximum ratings
Figure 7. Internal circuit of STGIPL14K60 and STGIPL20K60
- VPN: supply voltage applied between P-NU, NV, NW
- VPN(surge): supply voltage (surge) applied between P-NU, NV, NW
- VCES: collector emitter voltage The power stage of SLLIMM is based on IGBTs (and freewheeling diodes) having 600 V VCES rating. Considering the SLLIMM internal stray inductances during the commutations, which can generate up to 100 V of surge voltage, the maximum surge voltage between P-N PN(surge)) allowed is 500 V. At the same time, the maximum supply voltage (in steady- state) applied between P-N (VPN) allowed is 450 V because of an additional 50 V of surge voltage generated by the stray inductance between the SLLIMM and the DC-link capacitor. Figure 8 shows the parasitic inductances of the output stage. It is possible to note that there are two major components, the first is due to the internal layout of SLLIMM, while the second is due to the layout of the board.
Table 2. Inverter part of STGIPL14K60
- Applied between HIN U, HINV, HINW; LINU, LINV, LINW and GND.
- Calculated according to the iterative Equation 1.
- Pulse width limited by max. junction temperature.
- ±IC: each IGBT continuous collector current The allowable DC current continuously flowing at collector electrode (T C = 25 °C). The IC parameter is calculated according to Equation 1.
- tSCW: short-circuit withstand time The IGBTs incorporated inside the SLLIMM are tailored for a motor control application, therefore, short-circuit self-protection is one of the main module features. tSCW represents the short-circuit, non-repetitive, withstand time. If the short-circuit conditions exceed the above specifications, the lifetime of the device is drastically shortened. It is strongly recommended that the SLLIMM should not be operated under these conditions.
Figure 8. Stray inductance components of output stage
- VCC: low voltage power supply VCC represents the supply voltage of the control part. A local filtering is recommended to enhance the SLLIMM noise immunity. Generally, the use of one electrolytic capacitor (with a greater value but not negligible ESR) and a good quality (low ESR, low ESL) filter capacitor (hundreds of nF), faster than the electrolytic one to provide current, is suggested. Small filter capacitors are already connected inside the SLLIMM, directly on the involved pins (see internal circuits Figure 5, 6, and 7). Please refer to Table 4 in order to properly drive the SLLIMM.
Table 3. Control part of STGIPL14K60 Table 4. Supply voltage and operation behavior turned on. A perfect functionality cannot be guaranteed. 13.5 V – 18 V Recommended value (see relevant datasheets). increasing short-circuit broken risk and EMI issues.
21 V Control circuit is destroyed. Absolute max. rating is 21 V.
- Except for STGIPS10K60A. For further information please refer to the relevant datasheet.
Table 5. Total STGIPL14K60 system
2 Electrical characteristics and functions
In this section the main electrical characteristics of the power stage are discussed, together with a detailed description of all the SLLIMM functions.
2.1 IGBTs
The SLLIMM achieves power savings in the inverter stage thanks to the use of IGBTs manufactured with the proprietary advanced PowerMESH™ process. These power devices, optimized for the typical motor control switching frequency, offer an excellent trade-off between voltage drop (VCE(sat)) and switching speed (tfall), and therefore minimize the two major sources of energy loss, conduction and switching, reducing the environmental impact of daily-use equipment. A full analysis on the power losses of the complete system is reported in Section 4: Power losses and dissipation. This IGBT family is capable of surviving short-circuits lasting up to 5 microseconds, as expected by targeted applications.
2.2 Freewheeling diodes
The Turbo 2 ultrafast high voltage diodes have been adequately selected for the SLLIMM family and carefully tuned to achieve the best t rr/VF trade-off and softness as freewheeling diodes in order to further improve the total performance of the inverter and significantly reduce the electromagnetic interference (EMI) in motor control applications which are quite sensitive to this phenomena.
2.3 High voltage gate drivers
The SLLIMM is equipped with a versatile high voltage gate driver IC (HVIC), designed using BCD offline (Bipolar, CMOS, and DMOS) technology (see Figure 9) and particularly suited to field oriented control (FOC) motor driving applications, able to provide all the functions and current capability necessary for high side and low side IGBT driving. This driver can be used in all applications where high voltage shifted control is necessary and it includes a patented internal circuitry which replaces the external bootstrap diode. Each high voltage gate driver chip controls two IGBTs in half bridge topology, offering the basic functions such as dead time, interlocking, integrated bootstrap diode, and also the advanced features such as smart shutdown (patented), fault comparator, and a dedicated high performance op amp for advanced current sensing. A schematic summary of the features by device are listed in Table 1. In this application note the main characteristics of a high voltage gate drive related to the SLLIMM are discussed. For a greater understanding, please refer to the AN2738 application note.
2.3.1 Logic inputs
management for further details). therefore saving cost, board space and number of components. Figure 11. Logic input configuration for STGIPS10K60A
Figure 12. Logic input configuration for STGIPS14K60, STGIPL14K60, STGIPS20K60, and Table 6. Integrated pull-up/down resistor values
2.3.2 High voltage level shift
The built-in high voltage level shift allows direct connection between the low voltage control inputs and the high voltage power half bridge in any power application up to 600 V. It is obtained thanks to the BCD offline technology which integrates, in the same die bipolar devices, low and medium voltage CMOS for analog and logic circuitry and high voltage DMOS transistors with a breakdown voltage in excess of 600 V. This key feature eliminates the need for external optocouplers, resulting in significant savings regarding component count and power losses. Other advantages are high-frequency operation and short input-to- output delays.
2.3.3 Undervoltage lockout
The SLLIMM supply voltage VCC is continuously monitored by an undervoltage lockout (UVLO) circuitry which turns off the gate driver outputs when the supply voltage goes below the V CC_thOFF threshold specified on the datasheet and turns on the IC when the supply voltage goes above the VCC_thON voltage. A hysteresis of about 1.5 V is provided for noise rejection purposes. The high voltage floating supply Vboot is also provided with a similar undervoltage lockout circuitry. When the driver is in UVLO condition, both gate driver outputs are set to low level, setting the half bridge power stage output to high impedance. The timing chart of undervoltage lockout, plotted in Figure 13, is based on the following steps:
- t1: when the VCC supply voltage raises the VCC_thON threshold, the gate driver starts to work after the next input signal HIN/LIN is on. The circuit state becomes RESET.
- t2: input signal HIN/LIN is on and the IGBT is turned on.
- t3: when the VCC supply voltage goes below the VCC_thOFF threshold, the UVLO event is detected. The IGBT is turned off in spite of input signal HIN/LIN. The state of the circuit is now SET.
- t4: the gate driver re-starts once the V CC supply voltage again raises the VCC_thON threshold.
- t5: input signal HIN/LIN is on and the IGBT is turned on again.
2.3.4 Dead time and inte rlocking function management
is ignored and results as delayed until the end of the dead time. The dead time is internally set at 320 ns as the typical value of STGIPS10K60A. Figure 13. Timing chart of undervoltage lockout function Table 7. Interlocking function truth table of STGIPS10K60A
STGIPS20K60, and STGIPL20K60 products are described. Table 8. Interlocking function truth table of STGIPS14K60, STGIPL14K60, STGIPS20K60, and
2.3.5 Comparators for fault sensing
comparators, they can be separately used in order to implement three independent controls. Figure 14. Timing chart of dead time function
2.3.6 Short-circuit protecti on and smart shutdown function
The SLLIMM is able to monitor the output current and provide protection against overcurrent and short-circuit conditions in a very short time (comparator triggering to high/low side driver turn-off propagation delay t isd = 200 ns), thanks to the smart shutdown function. This feature is based on an innovative patented circuitry which provides an intelligent fault management operation and greatly reduces the protection intervention delay independently on the protection time duration which can be set as desired by the device user. As already mentioned in Section 2.3.5: Comparators for fault sensing and shown in Figure 10, each comparator input can be connected to an external shunt resistor, RSHUNT, in order to implement a simple overcurrent detection function. An RC filter network (R SF and CSF) is necessary to prevent erroneous operation of the protection. The output signal of the comparators is fed to an integrated MOSFET with the open drain available on the SD /OD pin, shared with the SD input. When the comparator triggers, the device is set in shutdown state and all its outputs are set to low level, leaving the half bridge in tri-state. In common overcurrent protection architectures, usually the comparator output is connected to the SD input and an external RC network (R SD and CSD) is connected to this SD/OD line in order to provide a mono-stable circuit which implements a protection time when a fault condition occurs. Contrary to common fault detection systems, the new smart shutdown structure allows to immediately turn off the output gate driver in the case of fault, without waiting for the external capacitor to be discharged. This strategy minimizes the propagation delay between the fault detection event and the actual outputs switch off. In fact, the time delay between the fault and outputs disabling is not dependent on the RC value of the external SD circuitry but, thanks to the new architecture, has a preferential path internally in the driver. Then the device immediately turns off the driver outputs and latches the turn-on of the open drain switch, until the SD signal has reached its lower threshold. After the SD signal goes below the lower threshold, the open drain is switched off (see Figure 16). The smart shutdown system provides the possibility to increase the value of the external RC network across the SD pin (sized to fix the disable time generated after the fault event) as much as desired by the user without compromising the intervention time delay of the SLLIMM protection. A block diagram of the smart shutdown architecture is depicted in Figure 15.
pin are avoided if the fault signal remains steady at high level.
2.3.7 Timing chart of short-circuit protection and smart shutdown function
- t1: when the output current is lower than the max. allowed level, the SLLIMM is working in normal operation.
- t2: when the output current reaches the max. allowed level (I SC), the overcurrent/short- circuit event is detected and the protection is activated. The voltage across the shunt resistor, and then on the C IN pin, exceeds the VREF value, the comparator triggers, setting the device in shutdown state and both its outputs are set to low level leading the half bridge to tri-state. The smart shutdown switches off the IGBT gate (HVG, LVG) through a preferential path (200 ns as typical internal delay time) and, at the same time, it switches on the M1 internal MOSFET. The SD signal starts the discharge phase and its value drops with a time constant τA. The time constant τA value is given by:
Figure 15. Smart shutdown equivalent circuitry
- t3: the SD signal reaches the lower threshold Vsd_L_THR and the control unit switches off the input HIN and LIN. The smart shutdown is disabled (M1 off) and SD can rise up with a time constant τB, given by: Equation 3
- t4: when the SD signal reaches the upper threshold V sd_H_THR, the system is re- enabled.
2.3.8 Current sensing shunt resistor selection
pin and ground (see Figure 10) are used to realize the overcurrent detection. the shunt resistor, must be minimized in order to avoid undesired short-circuit detection. Figure 16. Timing chart of smart shutdown function
- Defining of the overcurrent threshold value (I OC_th). For example, it can be fixed considering the IGBT typical working current in the application and adding 20-30% as overcurrent.
- Calculation of the shunt resistor value according to the conditioning network. An example of the conditioning network is shown in
Figure 22. Further details can be found in the user manuals listed (see References 7, References 8, and References 9).
- Selection of the closest shunt resistor commercial value.
- Calculation of the power rating of the shunt resistor, taking into account that this parameter is strongly temperature dependent. Therefore, the power derating ratio of the shunt resistor, ΔP(T)%, shown in the manufacturer's datasheet, must be considered in the calculation as follows: Equation 4 where IRMS is the IGBT RMS working current. For a proper selection of the shunt resistor, a safety margin of at least 30% is recommended on the calculated power rating. )%T(P IR )T(P RMSSHUNT SHUNT Δ
2.3.9 RC filter network selection
different control technique and short-circuit protection, as shown in Figure 17. recommended to be set in the range of 1~2 µs. Figure 17. Examples of SC protection circuit
- t1: collector current I C starts to rise. SC event is not detected yet due to the RC network on the CIN pin
- t2: voltage on VCIN reaches the VREF. SC event is detected and the smart shutdown starts to turn off the SLLIMM.
- t3: the SLLIMM is definitively turned off in less than 300 ns (including the t d(off) time of IGBT) from SC detection. Finally, the total disable time is t3-t2 and the total SC action time is t3-t1.
2.3.10 Overtemperature protection
or overcurrent protection, but only for slow changes in temperature monitoring. Figure 18. Example of SC event
For a proper sizing of the voltage divider, first of all the maximum allowed temperature level (TOT_Max) must be fixed, consequently the thermistor resistance is given by Equation 7, as well as by Figure 19. The value of ROT resistance can be calculated by using the voltage divider formula: Equation 8 taking into account that, if T = TOT_Max then V-(TOT_Max) = VNTC_th. The maximum allowed power on the thermistor should not exceed 50 mW in all the operating range, in order to guarantee a safe working condition and avoid power consumption affecting the temperature meas urement through self-heating. Therefore, considering (T = T OT_Max), it must be: Equation 9 Finally, to increase the noise immunity of the NTC thermistor, it is recommended to parallel a decoupling capacitor (C OT), whose value must be between 10 to 100 nF.
2.3.11 Op amps for advanced current sensing
The SLLIMM devices, in the SDIP-38L package, integrate also three operational amplifiers optimized for field oriented control (FOC) applications. In a typical FOC application the currents in the three half bridges are sensed using a shunt resistor. The analog current information is transformed into a discontinuous sense voltage signal, having the same frequency as the PWM signal driving the bridge. The sense voltage is a bipolar analog signal, whose sign depends on the direction of the current (see Figure 21): DD OTNTC OT VR)T(R R)T(V ⋅+=− mW50 RR VRIR OTNTC DDNTC NTC ≤ ⋅=⋅
7, References 8, and References 9).
2.3.12 Bootstrap circuit
DC+) and negative (VDC-) DC bus during the running conditions. series. An internal charge pump provides the DMOS driving voltage. Figure 23. The floating supply capacitor discharge current path”). This circuit is iterated for all three half bridges. Figure 23. Bootstrap circuit
The value of the CBOOT capacitor should be calculated according to the application condition and must take the following into account:
- voltage across CBOOT must be maintained at a value higher than the undervoltage lockout level for the IC driver. This enables the high side IGBT to work with a correct gate voltage (lower dissipation and better overall performances). Bear in mind that if a voltage below the UVLO threshold is applied on the bootstrap channel, the IC disables itself (no output) without any fault signal.
- the voltage across C BOOT is affected by different components such as drop across the integrated bootstrap structure, drop across the low side IGBT, and others.
- when the high side IGBT is on, the CBOOT capacitor discharges mainly to provide the right IGBT gate charge but other phenomena must be considered such as leakage currents, quiescent current, etc.
2.3.13 Bootstrap capacitor selection
A simple method to properly size the bootstrap capacitor considers only the amount of charge that is needed when the high voltage side of the driver is floating and IGBT gate is driven once. This approach does not take into account either the duty cycle of the PWM, or the fundamental frequency of the current. During the bootstrap capacitor charging phase, the low side IGBT is on and the voltage across C BOOT (VCBOOT) can be calculated as follows: Equation 10 where: VCC: supply voltage of gate driver VF: bootstrap diode forward voltage drop VCE(sat)max: maximum emitter collector voltage drop of low side IGBT VRDS(on): DMOS voltage drop The dimension of the bootstrap capacitance CBOOT value is based on the minimum voltage drop (ΔVCBOOT) to guarantee when the high side IGBT is on, and must be: Equation 11 under the condition: Equation 12 where: VGE(min): minimum gate emitter voltage of high side IGBT VBS_thON: bootstrap turn-on undervoltage threshold (maximum value, see datasheet) ma x)sat(CE)on(RDSFCCCBOOT VVVVV −−−= max)sat(CE(min )GE)on(RDSFCCCBOOT VVVVVV −−−−=Δ thON_BS(min)CBOOT VV >
Considering the factors contributing to VCBOOT decreasing, the total charge supplied by the bootstrap capacitor (during high side on phase) is: Equation 13 where: QGATE: total IGBT gate charge ILKGE: IGBT gate emitter leakage current IQBO: bootstrap circuit quiescent current ILK: bootstrap circuit leakage current ILKDiode: bootstrap diode leakage current ILKCap: bootstrap capacitor leakage current (relevant when using an electrolytic capacitor but can be ignored if other types of capacitors are used) tHon: high side on time QLS: charge required by the internal level shifters Finally, the minimum size of the bootstrap capacitor is: Equation 14 For an easier selection of bootstrap capacitor, Figure 24 shows the behavior of CBOOT (calculated) versus switching frequency (f sw), with different values of ΔVCBOOT, corresponding to Equation 14 for a continuous sinusoidal modulation and for STGIPS20K60 and STGIPL20K60 (worst case) and a duty cycle δ = 50%. For all the other devices the bootstrap capacitor can be calculated using the same curve. () LSHonapLKCLKDiodeLKQBOLKGEGATETOT QtIIIIIQQ +⋅+++++= CBOOT TOTBOOT V QC Δ=
directly on the SLLIMM pins is strictly recommended.
2.3.14 Initial bootstrap capacitor charging
- t1: the bootstrap capacitor starts to charge through the low side IGBT (LVG)
- t2: the voltage across the bootstrap capacitor (VCBOOT) reaches its turn-on undervoltage threshold VBS_thON.
- t3: the bootstrap capacitor is fully charged, this enables the high side IGBT and the CBOOT capacitor starts to discharge in order to provide the right IGBT gate charge. The bootstrap capacitor recharges during the on state of low side IGBT (LVG).
Figure 24. Bootstrap capacitor vs. switching frequency
three times longer than the calculated value. For safety reasons, the initial charging time must be at least 12 ms. Figure 25. Initial bootstrap charging time
3 Package
thermal performance, and great electrical isolation (> 2500 V RMS). SLLIMM family due to the improved thermal and electrical conductivity. stability in thermal cycling, small size with optimum cost-effectiveness, and quality level.
3.1 DBC substrate
Figure 26. Direct bonded copper substrates have management of high power semiconductor modules. Figure 26. DCB structure
- Excellent electrical isolation
- Very good thermal conductivity
- The thermal expansion coefficient is close to that of silicon, so no interface layers are required
- Good heat spreading
- May be structured just like printed circuit boards or “IMS substrates”
- Environmentally clean
3.2 PCB
electrically connect those using conductive pathways. Figure 27 shows the internal PCB detail.
3.3 Package structure
Figure 27. PCB structure
Figure 28. Images and internal view of SDIP-25L package
Figure 29. Images and internal view of SDIP-38L package
3.4 Package outline and dimensions
Figure 30. Outline drawing of SDIP-25L package
Table 9. SDIP-25L mechanical data
Figure 31. Outline drawing of SDIP-38L package
3.5 Input and output pins description
description and layout suggestions, please consult the relevant sections. Table 10. SDIP-38L mechanical data
Figure 32. Pinout of SDIP-25L package (bottom view) Table 11. Input and output pins of SDIP-25L package
8 GND Ground
10 HIN V High side logic input for V phase
11 OUT W High side reference output for W phase
12 V bootW Bootstrap voltage for W phase
13 LIN W LINW
14 HIN W High side logic input for W phase
15 T 1 SD / OD NTC thermistor terminal 1 SD logic input (active low) /
16 T 2 CIN NTC thermistor terminal 2 Comparator input
17 N W Negative DC input for W phase
18 W W phase output
19 P Positive DC input
21 V V phase output
22 P Positive DC input
23 N U Negative DC input for U phase
24 U U phase output
25 P Positive DC input
Table 11. Input and output pins of SDIP-25L package (continued) Figure 33. Pinout of SDIP-38L package (bottom view) Table 12. Input and output pins of SDIP-38L package
10 V bootV Bootstrap voltage for V phase
11 LIN V Low side logic input for V phase (active low)
12 HIN V High side logic input for V phase
13 OP -V Op amp inverting input for V phase
14 OP OUTV Op amp output for V phase
15 OP +V Op amp non inverting input for V phase
16 CIN V Comparator input for V phase
17 OUT W High side reference output for W phase
18 V bootW Bootstrap voltage for W phase
19 LIN W Low side logic input for W phase (active low)
20 HIN W High side logic input for W phase
21 OP -W Op amp inverting input for W phase
22 OP OUTW Op amp output for W phase
23 OP +W Op amp non inverting input for W phase
24 CIN W Comparator input for W phase
25 V CC Low voltage power supply
26 SD / OD Shutdown logic input (active low) / open drain (comparator output)
27 GND Ground
28 T 2 NTC thermistor terminal 2
29 T 1 NTC thermistor terminal 1
30 N W Negative DC input for W phase
31 W W phase output
32 P Positive DC input
34 V V phase output
35 P Positive DC input
37 U U phase output
38 P Positive DC input
Table 12. Input and output pins of SDIP-38L package (continued)
High-Side bias voltage pins /high-side bias voltage reference Pins: VbootU-OUTU, VbootV-OUTV, VbootW-OUTW
- The bootstrap section is designed to realize a simple and efficient floating power supply, in order to provide the gate voltage signal to the high-side IGBTs.
- The SLLIMM family integrates the bootstrap diodes. This helps customer to save cost, board space, and number of components.
- The advantage of the ability to bootstrap the circuit scheme is that no external power supplies are required for the high-side IGBTs.
- Each bootstrap capacitor is charged from the V CC supply during the on-state of the corresponding low side IGBT.
- To prevent malfunctions caused by noise and ripple in supply voltage, a good quality (low ESR, low ESL) filter capacitor should be mounted close to these pins.
- The value of bootstrap capacitors is strictly related to the application conditions. Please consult Section 2.3.12: Bootstrap circuit. Gate driver bias voltage Pin: VCC
- Control supply pin for the built-in ICs.
- To prevent malfunctions caused by noise and ripple in the supply voltage, a good quality (low ESR, low ESL) filter capacitor should be mounted close to this pin. Gate drive supply ground Pin: GND
- Ground reference pin for the built-in ICs.
- To avoid noise influences, the main power circuit current should not be allowed to flow through this pin (see Section 5.1: Layout suggestions). Signal input Pins: HINU, HINV, HINW; LINU, LINV, LINW; LINU, LINV, LINW
- These pins control the operation of the built-in IGBTs.
- The signal logic of HINU, HINV, HINW, LINU, LINV, and LINW pins is active high. The IGBT associated with each of these pins is turned on when a sufficient logic (higher than a specific threshold) voltage is applied to these pins.
- The signal logic of LIN U, LINV, LINW pins is active low. The IGBT associated with each of these pins is turned on when a logic voltage (lower than a specific threshold voltage) is applied to these pins.
- The wiring of each input should be as short as possible to protect the SLLIMM against noise influences.
Internal comparator non-inverting Pins: CINU, CINV, CINW
- The current sensing shunt resistor, connected on each phase leg, could be used by the internal comparator (pins CINU, CINV and CINW) to detect short-circuit current.
- The shunt resistor should be selected to meet the detection levels matched for the specific application.
- An RC filter (typically ~ 1 µs) should be connected to the CIN U, CINV, CINW pins to eliminate noise.
- The connection length between the shunt resistor and CIN U, CINV, CINW pins should be minimized.
- If a voltage signal, higher than the specified VREF (see datasheet), is applied to this pin, the SLLIMM automatically shuts down and the SD / OD pin is pulled down (to inform the microcontroller). Shutdown / open drain Pin: SD / OD
- The SD / OD pin works as an enable/disable pin.
- The signal logic of the SD / OD pin is active low. The SLLIMM shuts down if a voltage lower than a specific threshold is applied to this pin, leading each half bridge in tri-state.
- The SD / OD status is connected also to the internal comparator status ( Section 2.3.6: Short-circuit protection and smart shutdown function). When the comparator triggers, the SD / OD pin is pulled down acting as a FAULT pin.
- The SD / OD, when pulled down by the comparator, is open drain configured. The SD / OD voltage should be pulled up to the 3.3 V or 5 V logic power supply through a pull-up resistor. Thermistor Pins: T1, T2
- A co-packaged NTC is available for temperature monitor purposes.
- A simple voltage divider (as shown in Section 2.3.10: Overtemperature protection) can be realized with an external resistor in order to realize a temperature dependent voltage signal.
- The NTC is not able to sense IGBT junction temperature fast variation (due to its slow dynamic). Integrated operational amplifier (only for STGIPL14K60 and STGIPL20K60) Pins: OP-U, OP-V, OP-W; OPOUTU, OPOUTV, OPOUTW; OPU, OPV, OPW
- The op amps are completely uncommitted.
- The op amps performances are optimized for advanced control technique (FOC).
- Thanks to the integrated op amps it is possible to realize compact and efficient board layout, minimizing the required BOM list.
Pin: P
- These are three DC-link positive power supply pins of the inverter, which offer designers more flexibility in their approach. They are internally connected to the collectors of the high-side IGBTs.
- To suppress the surge voltage caused by the DC-link wiring or PCB pattern inductance, connect decoupling capacitors close to this pin and power ground (typically, high frequency, high voltage, non-inductive capacitors of about 0.1 or 0.22 μF are used). Negative DC-link Pins: NU, NV, NW
- These are the DC-link negative power supply pins (power ground) of the inverter.
- These pins are connected to the low side IGBT emitters of each phase.
- The power ground of the application should be separated from the logic ground of the system and they should be reconnected at one specific point (star connection). Inverter power output Pins: U, V, W
- Inverter output pins for connecting to the inverter load (e.g. motor).
4 Power losses and dissipation
the blocking voltage and leakage current, can be neglected. motor drive, where the major sources of power losses are specified.
4.1 Conduction power losses
Figure 34. Typical IGBT power losses
where T is the fundamental period. Figure 35. IGBT and diode approximation of the output characteristics
AN3338 Power losses and dissipation Assuming that: 1. the application is a variable voltage variable frequency (VVVF) inverter based on sinusoidal PWM technique 2. the switching frequency is high and therefore the output currents are sinusoidal 3. the load is ideal inductive. Under these conditions, the output inverter current is given by: Equation 22 where Î is the current peak, θ stands for ωt and φ is the phase angle between output voltage and current. The conduction power losses can be obtained as: Equation 23 Equation 24 where ξ is the duty cycle for this PWM technique and is given by: Equation 25 and ma is the PWM amplitude modulation index. Finally, solving Equation 23 and Equation 24, we have: Equation 26 Equation 27 () φ= -θcos Iˆi () () θφθξπ ⋅+θφθξπ ⋅= φ+π φ+π− φ+π φ+π− d-cos 2 IˆRd-cos 2 IˆVP CETOcond_IGBT ()() () () φ+π φ+π− φ+π φ+π− θφθξ−π+θφθξ−π= d-cos 12 IˆRd-cos 12 IˆVP 22 AKFOcond_Diode cosm1 a θ⋅+=ξ Pcond_IGBT VTO Î 1 RCE Î2 1 8--- ma φcos⋅ ⋅+⋅= Pcond_Diode VFO Î 1 RAK Î2 1 8--- ma φcos⋅ ⋅+⋅=
Power losses and dissipation AN3338 56/72 Doc ID 18441 Rev 4 and therefore, the conduction power losses of one device (IGBT and diode) are: Equation 28 Of course, the total conduction losses per inverter are six times this value.
4.2 Switching power losses
The switching loss is the power consumption during the turn-on and turn-off transients. As already shown in Figure 34, it is given by the pulse of power dissipated during the turn-on (ton) and turn-off (toff). Experimentally, it can be calculated by the time integral of product of the collector current and collector-emitter voltage for the switching period. Anyway, the dynamic performances are strictly related to many parameters such as voltage and current, temperature, so it is necessary to use the same assumptions of conduction power losses Section 4.1: Conduction power losses) to simplify the calculations. Under these conditions, the switching energy losses are given by: Equation 29 Equation 30 where Êon and Êoff are the maximum values taken at Tjmax and Îc, θ stands for ωt and φ is the phase angle between output voltage and current. Finally, the switching power losses per device depend on the switching frequency (f sw) and are calculated as follows: Equation 31 where EIGBT and EDiode are the total switching energy for IGBT and freewheeling diode, respectively. Also in this case, the total switching losses per inverter are six times this value. Figure 36 shows the real turn-on and turn-off waveforms of STGIPL14K60 under the following conditions:
- VPN = 300 V, IC = 7 A, Tj = 25 °C with inductive load on full bridge topology, taken on the high side IGBT. The red plots represent instantaneous power as a result of I C (in blue) and VCE (in green) waveforms multiplication, during the switching transitions. The areas under these plots are the switching energies computed by graphic integration thanks to the digital oscilloscope. cond_Diodecond_IGBTcond PPP += () φ=θ -θcos Eˆ)(E onon () φ=θ -θcos Eˆ)(E offoff φ+π φ+π π ⋅+=θ⋅+π= swDiodeIGBTswDiodeIGBTsw f)EE(df)EE(2
Eon and Eoff are the areas under the red plots.
4.3 Thermal impedance overview
away from the power chips and into the environment using an adequate cooling system. and its thermal resistance play a fundamental role. Figure 36. Typical switching waveforms of STGIPL14K60
4.4 Power losses calculation example
- V PN = 300 V, ma = 0.8, cos = 0.6, Tj = 150 °C, Tc = 100 °C, fSINE = 60 Hz, max. value of Rth(j-c), typical VCE(sat) and Etot values.
Table 13. RC Cauer thermal network elements by device
Figure 40. Maximum IC(RMS) current vs. fsw simulated curves
Design and mounting guidelines AN3338 62/72 Doc ID 18441 Rev 4
5 Design and mounting guidelines
In this section the main layout suggestions for an optimized design and major mounting recommendations, to appropriately handle and assemble the SLLIMM family, are introduced.
5.1 Layout suggestions
Optimization of PCB layout for high voltage, high current and high switching frequency applications is a critical point. PCB layout is a complex matter as it includes several aspects, such as length and width of track and circuit areas, but also the proper routing of the traces and the optimized reciprocal arrangement of the various system elements in the PCB area. A good layout can help the application to properly function and achieve expected performance. On the other hand, PCB without a careful layout can generate EMI issues (both induced and perceived by the application), can provide overvoltage spikes due to parasitic inductances along the PCB traces, and can produce higher power loss and even malfunction in the control and sensing stages. The compactness of the SLLIMM solution, which offers optimized gate driving network and reduced parasitic elements, allows designers to focus only on some specific issues, such as the ground issue or noise filter. Anyhow, in order to avoid all the aforementioned conditions, the following general guidelines and suggestions must be followed in PCB layout for 3- phase applications.
5.1.1 General suggestions
- PCB traces should be designed to be as short as possible and the area of the circuit (power or signal) should be minimized to avoid the sensitivity of such structures to surrounding noise.
- Ensure a good distance between switching lines with high voltage transitions and the signal line sensitive to electrical noise. Specifically, the tracks of each OUT phase, bringing significant currents and high voltages, should be separated from the logic lines and analog sensing circuit of op amps and comparators.
- Place the R SENSE resistors as close as possible to the low side pins of the SLLIMM (NU, NV and NW). Parasitic inductance can be minimized by connecting the ground line (also called driver ground) of the SLLIMM directly to the cold terminal of sense resistors. Use of a low inductance type resistor, such as an SMD resistor instead of long-lead type resistors, can help to further decrease the parasitic inductance.
- Avoid any ground loop. Only a single path must connect two different ground nodes.
- Place each RC filter as close as possible to the SLLIMM pins in order to increase their efficiency.
- In order to prevent surge destruction, the wiring between the decoupling capacitor and the P pin and power ground should be as short as possible. The use of a high
- Fixed voltage tracks, such as GND or HV lines, can be used to shield the logic and analog lines from the electrical noise produced by the switching lines (e.g. OUT U, OUTV and OUTW).
- Generally it is recommended to connect each half bridge ground in a star configuration and the three RSENSE very close to each other and to the power ground. In Figure 41 and Figure 42 the general suggestions for all SLLIMM products are summarized.
Figure 41. General suggestions 1
common PCB mistakes are shown. Figure 42. General suggestions 2 close as possi ble the op am p pins.
Figure 43. Example 1 of a possible wrong layout field concentration at the inner edge.
5.2 Mounting instructions
isolation of both SDIP-25L and SDIP-38L packages when mounting on a heatsink. For further details please refer to the TN0107 technical note.
5.2.1 Heatsink mounting
is essential to ensure an optimal contact between the SLLIMM and the heatsink. Figure 45. Be Figure 44. Example 2 of a possible wrong layout
5.2.2 Mounting torque
specified torque value using a torque wrench. Figure 47 shows the screw fastening order. Figure 45. Recommended silicon grease thickness and positioning Table 14. Mounting torque and heatsink flatness
5.2.3 General handling precaution and storage notices
Figure 46. Measurement point of Cu heatsink flatness Figure 47. Recommended fastening order of mounting screws
AN3338 Design and mounting guidelines The SLLIMM is an ESD sensitive device, it may be damaged in the case of ESD shocks. All equipment used to handle power modules must comply with ESD standards including transportation, storage, and assembly. Transportation Be careful when handling the SLLIMM and packaging material. Ensure that the module is not subjected to mechanical vibration or s hock during transport. Do not toss or drop to ensure the SLLIMM is correctly functioning before boarding. Wet conditions are dangerous and moisture can also adversely affect the packaging. Hold the package avoiding touching the leads during mounting. Put package boxes upside down, leaning them or giving them uneven stress may cause the terminals to be deformed or the resin to be damaged. Throwing or dropping the packaging boxes may cause the modules to be damaged. Wetting the packaging boxes may cause the breakdown of modules when operating. Pay particular care when transporting in wet conditions. Storage
- Do not force or load the external pressure to the modules while they are in storage
- Humidity should be kept within the range of 40% to 75%, the temperature should not go over 35 °C or below 5 °C
- Lead solder ability is degraded by lead oxidation or corrosion. So using storage areas where there is minimal temperature fluctuation is highly recommended
- The presence of harmful gases or dusty conditions is not acceptable for storage.
- Use antistatic containers Electrical shock and thermal injury
- Do not touch either module or heatsink when SLLIMM is operating to avoid sustaining an electrical shock and/or a burn injury.
6 References
- STGIPS10K60A datasheet 2. STGIPS14K60 datasheet 3. STGIPL14K60 datasheet 4. STGIPS20K60 datasheet 5. STGIPL20K60 datasheet 6. AN2738 application note 7. UM0969 user manual 8. UM0900 user manual 9. UM1036 user manual 10. Minimum-Loss Strategy for Three-Phase PWM Rectifier, IEEE, JUNE 1999 11. TN0107 technical note. Note: SLLIMM™ and PowerMESH™ are trademarks of STMicroelectronics.
7 Revision history
Table 15. Document revision history 21-Mar-2011 1 Initial release. Heatsink flatness max. value Table 14 on page 67. page 63, Figure 42 on page 64 and Figure 43 on page 65.