AN3232 STMICROELECTRONICS | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1 Epoxy sealed, non-herme tic RF power packages
- 2 Exceptional thermal per formance potential of the STAC package
- 3 Heatsink selection
- 4 Core preparation
- 5 Mounting base surface conditions
- 6 Thermal interface material
- 7 Seating plane
- 8 Printed circuit board (PCB) cons iderations
- 9 Package attachment to core by means of boltdown method
- 9.1 Required hardware
- 9.2 Considerations
- 9.3 Procedure summary
- 10 Package attachment to thermal base by means of soldering
- 10.1 Hardware
- 10.2 Solder reflow equipment and methods
- 11 Electrical connection
- 12 Conclusion
- 13 Revision history
mechanical stress and thermal and electrical resistance within the application environment. VDMOS and LDMOS technology products. data please refer to the relevant product datasheet. is a registered trademarks of STMicroelectronics. Figure 1. STAC boltdown packages
1 Epoxy sealed, non-hermetic RF power packages
maximum ratings. Refer to Figure 2 for recommended baking conditions. Figure 2. Drying times materials upon which STAC packages are realized.
Epoxy sealed, non-hermetic RF power packages AN3232 6/26 Doc ID 17594 Rev 3 Power RF packages typically require a reliable, low thermal resistance attachment to a heatsink. In this respect, nothing out-performs a direct attachment of the device flange, or thermal base, to the heatsink by means of soldering. This can be accomplished using any of the PbSn or Pb-free soldering methods used throughout the electronic industry. The final soldering step may be preceded by a hot-solder dip of the package base and/or leads, as required for situations that require attention to Au content of the solder joint. Alternatively, the packages may be inserted into an amplifier using a pick-and-place methodology, so that complete soldering is accomplished in a single reflow. Some amplifier assemblies require a manual approach for device positioning on a PCB while soldering bases to copper core heatsinks. In such manual operations STAC boltdown style packages have the unique possibility of serving as a built-in clamp to accomplish both tasks expeditiously. These manual efforts are rewarded by an extremely low thermal resistance, achieved by an ultra-thin solder joint case-to-heatsink, referred to as the Rth HS. At the same time, the need to allocate valuable amplifier real estate to specialized clamping fixtures is eliminated. The approaches to soldering RF transistors in amplifier housings are as numerous as the quantity of RF package outlines. While the traditional demand for high levels of ruggedness in RF devices assures an intrinsic high tolerance to a wide variety of assembly methods, the high-stress nature of any soldering operation requires careful consideration. Users ultimately assume responsibility for developing and qualifying their soldering processes, and therefore it is strongly recommended to fully evaluate temperature profiles at all steps in the soldering procedure to avoid excessive peak temperatures and ramp rates. When amplifier assemblies require cleaning after soldering operations, the use of a non- reactive cleaning agent is recommended. All residue from reactive flux should be removed according to the flux supplier's recommendations. If a non-aqueous cleaning method is employed, it must be followed by cleaning with DI water to remove all ionic contamination. It is recommended to periodically check the conductivity of the DI rinse to insure that levels of ionic contamination are as low as possible. In cases where heavy ionic contamination is present, multiple DI rinses in isolated baths should be used. Proceed from the most to the least contaminated rinsing system to maximize cleaning effectiveness. In general it is recommended to minimize the use of flux, to use no-clean flux, or to adopt fluxless soldering techniques. When there is doubt as to the behavior of residual flux or flux levels, consider a two-step solder approach. Since the PCB and other components may involve flux, an initial soldering step of the majority of non-critical components can be done, followed by a thorough cleaning. The second solder step, with greatly reduced flux content, can be planned for more critical components such as epoxy sealed RF transistors. An added benefit of a two-step operation is that non-solder thermal interface materials (TIMs), such as thermal compounds, are not influenced by aggressive flux cleaning. Following DI rinsing operations, the entire assembly should be baked, as determined by user experimentation, before power is applied. It is suggested to perform this drying at 125 °C for 24 hrs, if all components are rated for this condition. A longer bake time is recommended at lower temperatures. Refer to Figure 2 for some suggestions. OEM equipment operating conditions should be specified for operation only in a “non- condensating” environment. If there is a question of humidity in ambient conditions in power cycling, a heating/drying cycle is recommended before power is applied.
2 Exceptional thermal performance potential of the
approaches those frequently encountered in the realm of high-energy physics. thermal flux from the active regions of semiconductor chips to the external environment. Figure 3. Infrared imaging of a STAC package
Exceptional thermal performance potential of the STAC package concept AN3232 8/26 Doc ID 17594 Rev 3 approximately 30 % lower than it's ceramic package cousin, the ubiquitous GEMINI package. This situation affords amplifier designers extreme flexibility in terms of trade-offs between power dissipated, output power, power density, and MTTF . For example, higher power can be dissipated for a target junction temperature, or, on the other hand, increased MTTF can be achieved for a target case temperature with equivalent power density. While such flexibility often shifts the burden of cooling to system level, this decision is often the more cost effective solution or easier to manage. Alternatively, such a solution could translate into the ability to move an amplifier system from ground level to pole top. In the end analysis, the choice of heatsinking system depends on the specific device and application needs.
3 Heatsink selection
assembly and greatly influences system performance and cost. amplification or backed-off linear power amplifiers. applications and operating conditions. first, affording a means of transferring heat very quickly to a more convenient location. thickness range for the core layer is listed in Table 1. control spreading of the heat. Table 1. Preferred copper core thickness
4 Core preparation
By design, the STAC package family does not require complex core preparation, such as channels, pockets, cavities, etc., assuming a typical PCB thickness is selected for the application. However, because of the intended use of these packages, some aspects of core preparation are appropriate. Holes for screws, solder wells, etc., should be slightly countersunk and/or de-burred to achieve the best performance. In soft materials such as copper, the tapping operation can lift material above the mounting surfaces. This may occur on either side of the core layer, so both sides should be inspected. It is sometimes helpful to fully thread test screws in the holes and tighten, to observe if the core material is pushed or pulled above the mounting surfaces. If such a mushroom effect is observed, it is an indication that additional countersinking of the tapped holes is warranted. It is advised to drill and tap through the entire core layer, whenever possible. In the case of boltdown mounting of STAC packages, the minimum tapped hole depth should be 0.12 in (3.0 mm). Depending on the process used to fabricate the core layer, it is common industry practice to recommend stress relieving the core material, such as an annealing step before (and sometimes after) the heavy machining steps. This should be considered whenever there are a large number of cuts, holes, and other machined features in the core layer. The flatness of the core layer should be inspected after all machining steps to insure that a buildup of stress has not caused it to become warped or otherwise deformed.
5 Mounting base surface conditions
surface conditions are shown in Table 2. values reduce both electrical and thermal resistance. Table 2. Surface conditions
6 Thermal interface material
should be removed using standard practices. of approximately 0.003 in(0.08 mm), and apply it to the core layer or heatsink. Table 3. Common TIMs
7 Seating plane
into this calculation are shown in Figure 4. Figure 4. Pocket depth consideration (mm) be factored into the PCB thickness. Figure 5. Lead bending
Figure 6, are effective methods to reduce shear stress. In applications where there is doubt concerning lead stress, users can consult STMicroelectronics or it's resellers for analysis and advice.
8 Printed circuit board (PCB) considerations
outside dimensions of the package body. Figure 6. Package cut and pads layout technique is useful for situations in which the dimensions of the slot offset are constrained. good solder fillet along three sides of each transistor lead.
9 Package attachment to core by means of boltdown
9.1 Required hardware
The recommended fastener system consists of:
- Printed circuit or wiring board (PCB or PWB)
- Core layer, normally copper
- Boltdown STAC package
- Choice of TIM
- 2 each of 4-40 UNC-2A (or M3) TORX, HEX, or PHILLIPS cap screws (one for each end of the package body)
- Means of measuring torque
9.2 Considerations
The ideal screw-center spacing for STAC244B and STAC265B packages is 1.1 inch (27.94 mm). This dimension is the same as recommended for legacy "GEMINI" package outlines such as M244, M252, M265 as well as other familiar equivalents in the industry. Regardless of the spacing, the key objective is to insure that long and short centerlines of the package body are centered along and between the screws, respectively. This alignment procedure insures that the clamping forces are correctly balanced, such that the STAC clamping design directs pressure down and towards the center of the package body.
Figure 7. Ideal screw-center spacing
Figure 8. First boltdown mounting steps should be adjusted within the range listed in Table 4. complete hardware system insure that pressure is maintained uniformly over time. Table 4. Recommended screw torque
9.3 Procedure summary
- Tighten both fastener systems to each end of the package body to a “finger-tight” condition, approximately 0.4 in-lb (0.05 N-m, 0.5 kg-cm). 2. Use a torque driver or equivalent means to tighten both screws to the recommended torque of 5 in-lbs (0.6 N-m, 5.8 kg-cm).
10.1 Hardware
- Printed circuit or wiring board (PCB or PWB)
- Solderable core layer, normally copper
- STAC package (can be flangeless or boltdown version)
- Pb or Pb-free Solder preform or similar solder paste
- Solder reflow equipment, such as an oven
- Optional mechanical hardware to locate the package
10.2 Solder reflow equipment and methods
Figure 9. SEHO FDS “MAXIPOWER” reflow oven
STAC package and copper core layer. survive such stressful conditions. Figure 10. Component level temperature profile Table 5. Pb-free process - package classification reflow temperatures (1)
- Tolerance: the device manufacture r/supplier assures process compatibility up to and including the stated
Note: The profiling tolerance is + 0 °C, -X °C (based on the machine variation capability) regardless of what is required to control the profile process, but at no time does it exceed -5 °C. The producer assures process compatibility at the peak reflow temperatures. Package volume excludes external terminals (balls, bumps, lands, leads) and/or non- integral heatsinks. The maximum component temperature reached during reflow depends on package thickness and volume. The use of convection reflow processes reduces the thermal gradients between packages. However, thermal gradients due to differences on thermal mass of SMD packages may still exist. Ultimately, the most stressful aspect of soldering for packaging consisting of plastic or epoxy layers is related to rapid transition between process steps. For this reason, it is recommended to never exceed the ramping rates recommended in J-STD-020D at the package level.
Leads and/or flanges should be attached to the PCB and/or copper heatsinks using typical Sn63Pb37 or Pb-free solders, in accordance with the supplier's recommendations. However, the following guidelines with respect to the package should be considered:
- Avoid, as much as possible, the use of flux or flux solutions as it is a potential source of contamination to the device.
- The leads of the transistor may be tinned prior to assembly on the PCB. This practice is used in situations when it is undesirable to introduce even a small amount of gold into the solder composition, forestalling the possibility of solder embrittlement issues. The source of Au stems from the lead and/or backside surfaces, which are plated with 40 to 100 µin (1 to 2.5 µm) of Au.
- The amount of solder to be used depends on the type of solder and the amount of allowable Au in the final solder composition. It is desirable to increase the amount of solder when Au content is a concern, such as in Pb-free soldering applications.
- It is recommended to use either a solder preform or solder paste having a thickness of
- Adjustment of the solder preform or paste thickness may be used advantageously to account for thickness variations in the PCB manufacturing process.
- In cases where the backside of the flange is soldered to a copper core or heatsink, the package design and previously discussed mechanical mounting procedure provide sufficient downward pressure on the solder preform, resulting in a thin, high-quality bondline after a typical solder reflow procedure. In such cases, solder-wells or a solder- moat around the perimeter of the flange should be considered, to provide a region for excess solder to flow.
- A solder preform or other metallic foil may be used as both a TIM and electrical interface between the backside of the package (source) and amplifier ground (normally the core layer or the heatsink) even without soldering.
- Electrically insulative thermal pastes must be applied sufficiently thin, such that the downward pressure is high enough to force metal-to-metal contact over a significant area of the surfaces between the package (source) and amplifier ground.
12 Conclusion
This application note provides a set of guidelines to be considered for the proper attachment of STAC packages. While these recommendations are intended to address the majority of user applications, the flexibility afforded by this new generation of package technology enables new approaches for amplifier assembly as well as novel system architectures. In the search for constant improvement, ST continues to address customer needs by improving the robustness of the STAC package line and by releasing additional outlines with more functionality and versatility. For these reasons, it is expected that these guidelines are to be revisited and updated over time. At present, these recommendations are expected to result in reliable mechanical, electrical, and thermal performance. Regarding the thermal expectations of STAC packages, this application note demonstrates the exceptional performance that can be attained when utilizing the solder-down mounting method; this can be viewed as the limiting case for lowest achievable thermal resistance. While the STAC package concept embodies highly customizable thermal solutions by means of chip carrier material substitution, the importance of an exceptionally low thermal resistance between the transistor case and the heatsink (R thC-HS) cannot be overstated. In the case presented, this interface accounts for only 0.025 °C/W, roughly half of what is achievable with industry standard flanged packages. In this regard, STAC packages afford intrinsic flatness and the highest available thermal conductivity materials, further enhancing cooling efficiency. Even without soldering, judicious selection of TIMS and respect to this set of guidelines results in R thC-HS values on the order of 0.05 °C/W.
Table 6. Document revision history 03-Aug-2010 1 Initial release. 31-Aug-2011 3 Introduction on cover page has been updated.