AN3206

AN3206 STMICROELECTRONICS | Alldatasheet

Document overview

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• PDF pages: 14

Technical content

Datasheet sections

• 1 Introduction
• 2 Reference design
• 2.1 RF design guidelines
• 2.1.1 STM32W108 RF ports
• 2.1.2 Optimizing for TX (Boost mode)
• 2.1.3 Matching network circuit design
• 2.1.4 Harmonic filter design
• 2.1.5 Band-pass filter
• 2.1.6 Antenna matching circuit
• 2.2 RF layout guidelines
• 2.2.1 PCB tolerance
• 2.3 Other design considerations
• 3 Non-RF design considerations
• 3.1 High-frequency (24-MHz) crystal reference (X1, C5, and C6)
• 3.2 Optional Low-frequency crystal reference (X2, C27 and C26)
• 3.7 RF test connector
• 4 Revision history

March 2011 Doc ID 17406 Rev 3 1/14 AN3206 Application note PCB design guidelines for the STM32W108 platform

1 Introduction

STMicroelectronics provides a IEEE 802.15.4 product design engineer with a number of paths towards the successful design of a IEEE 802.15.4-compliant solution based on the STMicroelectronics STM32W108 family of system-on-chip (SoC) platforms. The STM32W108xx kits contain software, hardware, and documentation designed for developers to create applications efficiently on a tested and controlled platform. Once the design team is familiar with ST's STM32W108xx products and the available IEEE 802.15.4 software libraries and stacks, the next step in the design path involves designing application- specific hardware to meet product requirements. This application note is intended to accompany the reference designs and provide detailed information regarding the design decisions employed within STMicroelectronics designs. In addition, it details the design guidelines for developing an application-specific IEEE 802.15.4 design using an STM32W108xx device. After reading this document, developers should be able to successfully implement a design with an STM32W108xx device. For further information, visit the STMicroelectronics web site at www.st.com/stm32w. Due to the application-specific nature of STMicroelectronics reference designs, ST recommends that hardware designers familiarize themselves with the most recent reference design available. This document is applicable to the following STM32W108xx kits:

• STM32W108xx starter kit (part number: STM32W-SK)
• STM32W108xx extension kit (part number: STM32W-EXT)
• STM32W108xx low-cost RF control kit (part number: STM32W-RFCKIT) Note: The STM32W108 Reference Design is built on a 4-layer, FR-4 epoxy PCB. The STM32W108-based Reference Design includes the following elements: ■ Schematics (in PDF format) ■ Bill of materials (BOM) ■ Gerber files While the Reference Design includes most of the information required to start an application-specific design, if additional items needed, please contact STMicroelectronics Customer Support on the STMicroelectronics web site www.st.com/stm32w.

2 Reference design

Figure 1 shows a block diagram of the reference design. Figure 1. Block diagram of STM32W108 reference design (48-pin package) section describes the design decisions behind each of the items shown in Figure 1.

2.1 RF design guidelines

2.1.1 STM32W108 RF ports

the shared port without the need for a conventional T/R switch. off-chip matching component values.

2.1.2 Optimizing for TX (Boost mode)

Figure 2. Simulated Boost output power with PA load resistance

would yield higher signal voltage swings at the LNA input, making the input referred noise less significant and thereby improving sensitivity. However, this also increases the source resistance, thereby increasing the source noise voltage. In practice at the 700Ω level, the improvement gradient is very small and the transmit output power exhibits far greater sensitivity to load variation than receiver sensitivity. The main objective for receive sensitivity is to minimize network loss, which is a common objective when transmitting. The optimum load presented to the pins of the STM32W108 device must take into consideration not only the optimum PA load but also on-chip parasitic capacitance and package bond-wire inductance. It is estimated that the optimum load presented to the pins is 27 + j95Ω (series impedance). This is equivalent to a parallel resistance of 368Ω combined with a parallel inductance of 6.6 nH.

2.1.3 Matching network circuit design

The term “matching” typically implies conjugate power matching. It is important to understand that the STM32W PA is not power matched according to the traditional definition. The term is used in this document to describe the design of an optimal PA impedance. The best way to understand ST's approach towards optimizing the STM32W “matching” is to plot on the Smith chart the impedance of the ideal 700Ω PA load transformed by the chip/package parasitic elements. The combination of the ideal load with the parasitic elements is the conjugate of the ideal load presented to the package pins. Knowing the combined load and its conjugate allows the designer to approach matching in a more traditional sense, namely, “How do we get to 50Ω?” It is also necessary at some point in the network to include a balanced-to-unbalanced (balun) conversion. Use of a ‘proper’ balun has performance benefits related to common- mode suppression both on transmit and receive sides. There are a variety of balun architectures and solutions available. The primary objective of any of ST's reference designs is to minimize design complexity and maximize time to market. Therefore, ST decided to implement its primary reference design with a ceramic balun. The cost of ceramic baluns is low, and they are available from a number of vendors. Ceramic baluns are available in 1:1 (50 to 50Ω), 2:1 (100 to 50Ω), and 4:1 ratios (200 to 50Ω). The magnitude of the reflection coefficient, | ⎡ L |, in these three cases is:

• 1:1 (50Ω) → 0.8
• 4:1 (200Ω) → 0.8 This implies that a 2:1 ceramic balun should offer the lowest network loss, assuming identical balun loss because it requires the least transformation. Investigation into ceramic balun performance from various vendors reveals that 1:1 and 2:1 ratio baluns often have an approximate 0.3 dB insertion loss advantage over a 4:1 ratio. Thus the use of a 2:1 ceramic balun is preferred. Optimal Load for STM32W (series impedance) 27 + j95 Ohms

To minimize network loss, the matching topology should try to keep Smith chart loci towards the center of the Smith chart. To do that, the following impedance transformation options are available:

• Series inductance followed by Shunt capacitance – This option favors lower balun ratios. – It leads to comparatively large inductance values. – It requires either long PCB traces or tw o discrete inductors (balanced network) which means inductor Q becomes an issue.
• Series inductance followed by Shunt inductance – Similar to auto-transformer action. – Sweet-spot for 100 Ω balun if series inductance fabricated from PCB traces since neither too long nor too short.
• Shunt inductance followed by series capacitance – Not allowed because DC feed to PA is required from balun centre-tap.
• Shunt inductance followed by Series inductance – Favors lower balun ratios, but even at 1:1 the required series inductance is comparatively large. – It requires either long PCB traces or tw o discrete inductors (balanced network) which means inductor Q becomes an issue. PCB parasitic elements play a part in the impedance transformation and even with the tightest of layouts, traces between the matching elements will add significant reactance at 2.4 GHz. In particular, there will be some series inductance between the package pins and the first matching element. This is significant when that element is shunted because it cannot be absorbed into that reactance. Since this effect cannot be avoided, it is best to take advantage of it. The option with the lowest loss and least complex arrangement is series inductance followed by shunt inductance. To make use of the PCB traces, it must be recognized that they operate more like transmission lines which travel slightly differently on the Smith chart compared with real inductors and this affects the shunt inductance value. Traces of 100Ω which equate to 150um wide on a 0.4mm thick FR-4 substrate should be used. In ST's simple single-ended representation in the Smith chart, the balanced pair must be modeled as a single 200Ω transmission line. Figure 3 illustrates the impedance transformation.

updated to a three-element match, generally making it more difficult to simulate. style at these sorts of component values. So a small price is paid on design centering. connection. Its value is chosen to be series resonant with its parasitic inductance at 2.4GHz.

2.1.4 Harmonic filter design

Pro, the relaxation is 6.9 dB. 2nd, 3rd, and 5th harmonics, but not the 4th harmonic. 1GHz~24GHz, so this becomes the default limit for the 4th harmonic. ETSI requirements, so frequencies above the 5th harmonic are not considered here. The overall requirement is shown in Table 1.

2.1.5 Band-pass filter

the antenna matching circuitry.

2.1.6 Antenna matching circuit

Table 1. Harmonic power limits

(C8) and inductor (L1) have been selected. Figure 5. Antenna matching circuit

2.2 RF layout guidelines

2.2.1 PCB tolerance

• Dissipation Factor, DF (also known as loss tangent, tanδ)
• Dielectric Constant, DK (also known as relative permittivity, εr) Generally, materials are split into 'standard loss' and 'low loss' categories, with a corresponding cost penalty. Other product considerations such as flammability rating and lead-free assembly will narrow these choices. These are beyond the scope of this document. Modern PCB manufacturing achieves very accurate etching and so this is not considered as a performance variable. Z-axis expansion depends on the FR-4 material and does not alter much between vendors' material.

2.3 Other design considerations

Please refer to Section 3 for the non-RF requirements of the STM32W-based design.

3 Non-RF design considerations

test point as well as an InSight Port connector.

3.1 High-frequency (24-MHz) crys tal reference (X1, C5, and C6)

proper STM32W clock distribution and IEEE 802.15.4 timing (see Figure 6). Figure 6. 24MHz high-frequency crystal A manufacturing token within the STM32W device stores the crystal bias register setting. NodeTest or MFG Library software is used, and it is dependent upon the selected crystal. according to the crystal manufacturer's requirements.

3.2 Optional Low-frequency crystal reference (X2, C27 and C26)

sleep timing accuracy will decide if a 32-kHz crystal is required. Figure 7. 32-kHz low-frequency crystal OSC32B (GPIO23) can be used as a general-purpose IO. Table 2. High frequency crystal requirements

Figure 9. Digital VDD filter The lower current consumption also allows for a reduction in the digital 1.8V Domain noise. This means the RX sensitivity improves by 2dB when using the 10-Ohm resistor.

3.7 RF test connector

having the possibility to solder an UF .L type RF connector such as those from Hirose. please contact STMicroelectronics support at http://www.st.com/stm32w.

4 Revision history

Table 3. Document revision history 29-Apr-2010 1 Initial release. 08-Dec-2010 2 Updated Section 3.4: 1.2V regulator loading on page 12.