AN3202 STMICROELECTRONICS | Alldatasheet

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Technical content

Datasheet sections

  • 1 General purpose timers (GPTs) in SPEAr600
  • 2 Reading a free-running timer counter
  • 3 Scenario with slow CNT_Clk and fast READ_Clk
  • 4 How to configure CNT_Clk and READ_Clk to be synchronous
  • 5 Summary
  • 6 Revision history

May 2010 Doc ID 17399 Rev 1 1/11 AN3202 Application note How to configure the SPEAr600 general purpose timers (GPTs) Introduction This application note provides information about how to configure the general purpose timers (GPTs) integrated in the SPEAr600 embedded MPU family. General purpose timers (GPTs) play an important role in any system as they provide a means of calculating time for controlling the execution of various operations. In case of an operating system, they are used for the system tick generation, usually every 10 ms; in other applications they can be used to get a finer granularity for controlling the timing of events. The purpose of this application note is to explain how to read the free running timer counter and configure the clock source of the various GPTs that are integrated in the SPEAr600 architecture.

1 General purpose timers (GPTs) in SPEAr600

Table 1. GPTs in SPEAr600 can be selected by the user from a list of clock sources.

  • READ_Clk (PCLK): When SPEAr600 is in normal mode, it takes the input from PLL1 divided by a programmable prescaler, whose reset values impose the ratio 1:2:4 to the core_clk, HCLK and PCLK clocks. When SPEAr600 is in slow mode, it takes directly the input from the OSCI signal.
  • CNT_Clk: The clock source can be selected as either a fixed 48 MHz or the PLL1 itself divided by a programmable prescaler, which is defined in the PRSC1_CLK_CFG register (0xFCA8_0044) for GPT1/GPT2/GPT3, PRSC2_CLK_CFG register (0xFCA8_0048) for GPT4 and PRSC3_CLK_CFG register (0xFCA8_004C) for GPT5. The CNT_Clk may then be further divided by a GPT internal 4-bit prescaler able to divide up to 256 times (‘/256’).

Figure 1. GPT clock sources The following table describes the clock selectors (Clock_Sel) for each GPT.

input clock is asynchronous (or not in phase). Table 2. GPTx clock source selector

2 Reading a free-running timer counter

READ_Clk for synchronizing the READ accesses of the bus the timer is connected to. Figure 2. Simplified timer completely asynchronous, for example coming from two different sources. the real value in the register. in a transitioning, unstable phase. Figure 3. Sampling a counter bit in an unstable state

Reading a free-running timer counter AN3202 6/11 Doc ID 17399 Rev 1 Let’s take as an example a counting down 16-bit counter transitioning from the value 1000_0000_0000_0000 (0x8000) to 0111_1111_1111_1111 (0x7FFF). Since the transition time of the 16 bits can be slightly different between each other, then the 16-bit counter value could be read by the CPU randomly as 0x0000 or 0xFFFF leading to a big difference from its real value. A similar scenario may also occur in case the two clocks are synchronous, but not in phase. In this case, in fact, the READ_Clk may sample the bit during its unstable state period. So, the two clocks must be synchronous and in phase.

3 Scenario with slow CNT_Clk and fast READ_Clk

CNT_Clk cycle. Or, in other words, CNT_Clk is about 60 times slower than READ_Clk. Figure 4. CNT_Clk at low frequency should be disabled during the reads. this method might be used for GPT1, GPT2 and GPT3. on the way the reads are implemented, so they should be carefully evaluated. to happen every 3 READ_Clk cycles.

How to configure CNT_Clk and READ_Clk to be synchronous AN3202 8/11 Doc ID 17399 Rev 1

4 How to configure CNT_Clk and READ_Clk to be

This method, which is very simple to implement, is nevertheless guaranteed to work for GPT4 and GPT5 only. The most common configuration is when SPEAr600 is in normal mode with system clocks fed by PLL1. In case the system is set in this mode, you can just select PLL1 as CNT_Clk to guarantee the synchronicity between CNT_Clk and READ_Clk. To set the input clock source of GPTx to PLL1 you need to use PRPH_CLK_CFG register (0xFCA8_0028). There are five different bits, one for each GPT block.

  • For GPT4: PRPH_CLK_CFG [11] = 1
  • For GPT5: PRPH_CLK_CFG [12] = 1 In case SPEAr600 enters the slow mode, for example to save power after detecting a period of inactivity, the HCLK/PCLK system clocks are directly fed from the OSCI at 30 MHz. In this mode READ_Clk (OSCI) and CNT_Clk (PLL1) become asynchronous again.

5 Summary

derived from PLL1 in normal mode (PCLK) and from the 30 MHz OSCI in slow mode. the need for reconfiguring the GPT registers if the system clock frequency is slowed down. timer value, due to the non-synchronous operation of the two clocks. Table 3. Summary of the solutions

6 Revision history

Table 4. Document revision history 03-May-2010 1 Initial release.