AN3161 STMICROELECTRONICS | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 14
Technical content
Datasheet sections
- 1 Saturation voltage impact on pa rallel
- 1.1 PT, NPT and trench field stop
- 2 General guidelines on paralleling
- 2.1 Thermal system impact
- 2.2 Layout considerations
- 3 New advanced planar PT ST GW35HF60WD
- 3.1 Notes on technology and V CE(sat) grouping
- 3.2 E OFF impact on parallel
- 4 The STGW35HF60WD on the test bench
- 5 Conclusion
- 6 Revision history
May 2010 Doc ID 17151 Rev 1 1/14 AN3161 Application note Using the STGW35HF60WD advanced PT IGBT in parallel Introduction When two or more IGBTs are connected in parallel to improve the total efficiency in high output power systems, special care is required to ensure that current sharing between the devices is as equal as possible. Current sharing is mainly influenced by differences in IGBT static parameters, circuitry layout (both driving and power) and thermal imbalances. All of these elements must be considered, especially when PT (punch-through) IGBTs work in parallel, due to their negative V CE(sat) coefficient. In order to provide the most efficient IGBT to the market while supporting reliable and easier paralleling for higher power level applications, ST offers the STGW35HF60WD 35 A, 600 V ultra fast IGBT with V CE(sat) selection. This device is explained in greater detail in Section 3: New advanced planar PT STGW35HF60WD.
1 Saturation voltage impact on parallel
1.1 PT, NPT and trench field stop
the static current difference established at the beginning. Figure 1. ∆IC (@TJ = 25 °C) of two paralleled IGBT
Figure 2. ∆IC (@TJ > 25 °C) of two paralleled IGBT without negative feedback IGBTs; this guarantees an intrinsic balancing mechanism, preventing thermal runaway.
General guidelines on paralleling AN3161 6/14 Doc ID 17151 Rev 1
2 General guidelines on paralleling
2.1 Thermal system impact
In order to guarantee the satisfactory performance of paralleled devices, regardless of the IGBT technology used, it is recommended to place them on the same heatsink, very close together. If the IGBTs are sufficiently close, the one with the higher T J will heat its neighbor, improving temperature and current sharing. PT IGBTs in particular benefit from the common heatsink, as it balances the negative V CE(sat) coefficient, which prevents thermal runway. If the thermal system impact is considered on paralleling, the mutual thermal resistance between the two junctions is the most important factor impacting on the dynamic ∆I C at high temperatures. If a thin layer of silicon grease is used between the IGBT case and the heatsink, power sharing greatly improves, leading to a significant ∆IC reduction at operating temperatures. This occurs because the silicon grease significantly decreases the thermal resistance between the relative junctions.
2.2 Layout considerations
General rules during the design phase should be adopted to minimize unavoidable asymmetries occurring under transient conditions (turn-on and turn-off). First, it is recommended to make the gate drive circuit as symmetrical as possible, and to use individual gate resistors. Individual driving stages provide two advantages:
- They avoid imbalances during the turn-on and turn-off phase. They mainly occur when the two IGBTs have different V plateau values and the same forced VGE due to the common gate. As a consequence, one of the two IGBTs turns on before the other, and turns off later.
- They damp oscillations during the transient state, caused by the cross-capacitive coupling of the paralleled devices with the driving loop inductances. If parasitic oscillations are still present due to layout inductances, ferrite beads added to each gate wire can help to drastically reduce the oscillations. Additionally, voltage overshoot can appear across the devices due to the di/dt and to stray inductances in the power circuit. It is suggested to make these loop inductances as short as possible in order not to exceed the absolute maximum rating of the IGBT voltage, rather than make them symmetrical. If not perfectly matched, the collector and emitter inductances can cause different current slopes during switch-off. Any IGBT technology can benefit from this layout optimization.
3 New advanced planar PT STGW35HF60WD
3.1 Notes on technology and V CE(sat) grouping
- The innovative double-drift process which changed the doping profile
- The advanced planar strip layout
changes in relation to the absolute VCE(sat) value, as shown in Figure 3. Figure 3. Static V CE(sat)(@20 A,15 V) derating for STGW35HF60WD
the same group work in parallel.
3.2 E OFF impact on parallel
derating (∼ 80%), which is clearly illustrated in Figure 4. Figure 4. E OFF vs. VCE(sat) for the STGW35HF60WD explains why the selected groups have different widths.
4 The STGW35HF60WD on the test bench
STGW35HF60WD IGBTs working in parallel. Figure 5. DC-DC boost scheme population (as illustrated in Figure 6) and three sets of tests are reported in this document. Figure 6. V CE(sat)(@20 A, 25 °C, 15 V) grouping for the STGW35HF60WD
consideration applies for couple n.3.
- Couple n.1 – device n.1: V CE(sat) = 1.75 V (@20 A, 25 °C,15 V) – device n.2: V CE(sat)t = 2.02 V (@20 A, 25 °C, 15 V) ∆VCE(sat) = 270 mV
- Couple n.2 – device n.1: V CE(sat) = 1.84 V (@20 A, 25 °C,15 V) – device n.2: V CE(sat) = 2.09 V (@20 A, 25 °C, 15 V) ∆VCE(sat) = 250 mV
- Couple n.3 – device n.1: V CE(sat) = 1.94 V (@20 A, 25 °C,15 V) – device n.2: V CE(sat) = 2.34 V (@20 A, 25 °C, 15 V) ∆VCE(sat) = 400 mV The goal of the on-board tests was to evaluate how the dynamic ∆IC of each group moves from board startup (TC = 25 °C) to a steady-state condition in terms of thermal sharing (TC = 100 °C). After board startup, the two paralleled devices share the total power, taking advantage of the common heatsink and layout optimization (as suggested in Section 2.1 and Section 2.2). Thanks to the negative thermal feedback introduced by the common heatsink, the dynamic ∆I C decreases despite of its initial value of TC = 25 °C, and remains stable even at high TJ temperatures. Couple n.1
Figure 7. ∆IC at TC = 25 °C (board startup) Figure 8. ∆IC at TC = 100 °C
5 Conclusion
CE(sat) selection of the total IGBT population. without risk of thermal runaway. Table 2. Suggested V CE(sat) (@20 A, 25 °C, 15 V) selection as per datasheet (1)
- The V CE(sat) grouping reported above is slightly different from the one in Figure 6, in order to meet the
6 Revision history
Table 3. Document revision history 05-May-2010 1 Initial release.