AN3118 STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 31
Technical content
Datasheet sections
- 1 Main characteristics and cir cuit description
- 2 Electrical diagram
- 3 Bill of material
- 4 Test results and signifi cant waveforms
- 4.1 Harmonic content measurement
- 4.2 MOSFET current, TM signals, and L6563H THD optimizer
- 4.3 Voltage feed-forward and brown-out function
- 4.4 Startup operation
- 4.5 PFC_OK pin and feedback failure (open-loop) protection
- 4.6 Power management and housekeeping functions
- 5 Layout hints
- 6 Thermal map
- 7 EMI filtering and co nducted EMI pre-compliance measurements
- 8 References
- 9 Revision history
250 W transition-mode PFC pre-regulator with the new L6563H
implementing an internal high voltage startup circuitry. Figure 1. EVL6563H-250W: L6563H 250 W TM PFC demonstration board
Main characteristics and circuit description AN3118 4/31 Doc ID 16847 Rev 2
1 Main characteristics and circuit description
The main characteristics of the SMPS are listed below:
- Line voltage range: 90 to 265 Vac
- Line frequency (fL): 47 to 63 Hz
- Regulated output voltage: 400 V
- Rated output power: 250 W
- Maximum 2fL output voltage ripple: 22 V pk-pk
- Hold-up time: 10 ms (VDROP after hold-up time: 300 V)
- Minimum switching frequency: 46 kHz
- Minimum estimated efficiency: 93 % (@ Vin=90 Vac, Pout=250 W)
- Maximum ambient temperature: 50 °C
- PCB type and size: single side, 35 µm, CEM-1, 88 x 116 mm This demonstration board implements a power factor correction (PFC) pre-regulator, 250 W continuous power, delivering a regulated 400 V rail from a wide range mains voltage and providing for the reduction of the mains harmonics, therefore meeting the European EN61000-3-2 or the Japanese JEITA-MITI standard. The regulated output voltage is typically the input for the cascaded isolated DC-DC converter that will provide the output rails required by the load. The power stage of the PFC is a conventional boost converter, connected to the output of the D1 rectifier bridge. It is completed by the L2 coil, the D3 diode, and the C5 capacitor. The boost switch is represented by the power Q1 and Q2 MOSFETs, connected in parallel. The NTC R1 limits the inrush current at switch on. It is connected on the DC rail, in series to the output electrolytic capacitor, in order to improve the efficiency during low line operation. In fact the RMS current flowing into the output stage is lower than current flowing into the input stage at the same input voltage. The board is equipped with an input EMI filter necessary to filter the switching noise coming from the boost stage. At startup the L6563H (U1) is powered by the Vcc electrolytic capacitor C9 which is charged via High Voltage Start up (HVS) pin #9. The HVS pin, able to withstand 700V, is connected directly to the rectified mains voltage. A 0.85 mA (typ.) internal current source charges the C9 capacitor connected between Vcc pin #16 and GND pin #14 until the voltage on the Vcc pin reaches the startup threshold. The L2 secondary winding and the charge pump circuit (C6, R2, D4 and D5) generate the Vcc voltage, powering the L6563H during normal operations. The L2 secondary winding is also connected to the L6563H pin #13 (ZCD) through the R14 resistor. Its purpose is to supply the information which L2 has demagnetized, needed by the internal logic to trigger a new switching cycle. The divider R4, R8, R12 and R15 provides to the L6563H multiplier the information of the instantaneous mains voltage that is used to modulate the peak current of the boost. The R3, R6, R7 with R9 and R10 resistors are dedicated to sensing the output voltage and feed to the L6563H the feedback information necessary to regulate the output voltage. The C7, R13, and C10 components are the error amplifier compensation network necessary to get the required loop stability. The peak current is sensed by R23 and R24 resistors in series to the MOSFET and the signal is fed into pin #4 (CS) of the L6563H via the filter by R20 and C14.
AN3118 Main characteristics and circuit description Doc ID 16847 Rev 2 5/31 C12, R27 and R28 are connected to pin # 5 (VFF), they complete an internal peak-holding circuit which obtains the information on the RMS mains voltage. The voltage signal at this pin, a DC level equal to the peak voltage on pin #3 (MULT), is fed to a second input to the multiplier for 1/V 2 function necessary to compensate the control loop gain dependence on the mains voltage. Additionally, pin #12 (RUN) is connected to pin# 5 (VFF) through the R27 and R28 resistor divider providing a voltage level for brown-out (AC mains under voltage) protection. A voltage on the RUN pin below 0.8V shuts down (not latched) the IC and brings its consumption to a considerably lower level. The L6563H restarts as the voltage at the pin rises above 0.88 V. The R21, R25, R26 and R33 dividers provide the information regarding the output voltage level to the L6563H pin #7 (PFC_OK). It is required by the L6563H output voltage monitoring and disable functions used for PFC protection purposes. If the voltage on pin #7 exceeds 2.5 V the IC stops switching and restarts as the voltage on the pin falls below 2.4 V, realizing the so called dynamic OVP , preventing the output voltage from becoming excessive in case of transient, due to the slow response of the error amplifier. However, if contemporaneously the voltage of the INV pin falls below 1.66 V (typ.), a feedback failure is assumed. In this case the device is latched off. Normal operation can be resumed only by cycling Vcc, bringing its value lower than 6 V before moving up to turn- on threshold. Additionally, if the voltage on pin #7 (PFC_OK) is tied below 0.23V, the L6563H is shut down. To restart the L6563H operation the voltage on pin #7 (PFC_OK) must increase above 0.27 V. This function can be used as a remote on/off control input. To allow the interfacing of the board with a D2D converter the J3 connector allows the powering of the L6563H with an external Vcc. It also gives the opportunity to manage failure or abnormal conditions via the PWM_LATCH (#8) and PWM_STOP (#11) pins. The L6563H operation can be also disabled or enabled to properly manage light load or failure conditions by the D2D via the PFC_OK pin (#7), still available at pin #5 of J3 (ON/OFF). For further details please see Section 4.6.
2 Electrical diagram
Figure 2. EVL6563H-250W: demonstration board TM PFC electrical schematic
3 Bill of material
Table 1. EVL6563H-250W TM PFC bill of material
Table 1. EVL6563H-250W TM PFC bill of material (continued)
4 Test results and significant waveforms
4.1 Harmonic content measurement
distortion, decreasing the harmonic contents below the limits of the relevant regulations. power limit at which the harmonics have to be limited according to the mentioned standards. Measurements are given in Figure 3 to 6. Figure 3. EVL6563H-250W TM PFC Figure 4. EVL6563H-250W TM PFC Figure 5. EVL6563H-250W TM PFC Figure 6. EVL6563H-250W TM PFC
distortion as confirmed by the low THD in all line and load conditions. Figure 7. EVL6563H-250W TM PFC input
250 W load
Figure 8. EVL6563H-250W TM PFC input Figure 9. EVL6563H-250W TM PFC input
70 W load
Figure 10. EVL6563H-250W TM PFC input
Figure 15. EVL6563H-250W TM PFC: static Vout regulation vs. output power The measured output voltage at different line and load conditions is reported in Figure 15. As shown, the voltage is very stable over all the input voltage and output load range.
4.2 MOSFET current, TM signal s, and L6563H THD optimizer
smaller and cheaper MOSFETs instead of one bigger one.
AN3118 Test results and significant waveforms Doc ID 16847 Rev 2 15/31
4.3 Voltage feed-forward and brown-out function
The power stage gain of PFC pre-regulators varies with the square of the RMS input voltage. As does the crossover frequency fc of the overall open-loop gain because the gain has a single pole characteristic. This leads to large trade-offs in the design. For example, setting the gain of the error amplifier to get fc = 20 Hz @ 264 Vac means having fc 4 Hz @ 88 Vac, resulting in sluggish control dynamics. Additionally, the slow control loop causes large transient current flow during rapid line or load changes that are limited by the dynamics of the multiplier output. This limit is considered when selecting the sense resistor to let the full load power pass under minimum line voltage conditions, with some margin. But a fixed current limit allows excessive power input at high line, whereas a fixed power limit requires the current limit to vary inversely with the line voltage. Voltage feed-forward can compensate for the gain variation with the line voltage and overcome all of the above mentioned issues. It consists of deriving a voltage proportional to the input RMS voltage, feeding this voltage into a squarer/divider circuit (1/V 2 corrector) and providing the resulting signal to the multiplier that generates the current reference for the inner current control loop. In this way a change of the line voltage will cause an inversely proportional change of the half-sine amplitude at the output of the multiplier (if the line voltage doubles the amplitude of the multiplier, output is halved and vice versa) so that the current reference is adapted to the new operating conditions with (ideally) no need for invoking the slow dynamics of the error amplifier. Additionally, the loop gain will be constant throughout the input voltage range, which improves dynamic behavior at low line significantly and simplifies loop design. Actually, with another PFC embedding the voltage feed-forward, deriving a voltage proportional to the RMS line voltage implies a form of integration, which has its own time constant. If it is too small the voltage generated is affected by a considerable amount of ripple at twice the mains frequency that causes distortion of the current reference (resulting in high THD and poor PF); if it is too large there is a considerable delay in setting the right amount of feed-forward, resulting in excessive overshoot and undershoot of the pre- regulator's output voltage in response to large line voltage changes. Clearly a trade off was required. The L6563H realizes an innovative voltage feed-forward which, with a technique that overcomes this time constant trade off issue whichever voltage change occurs on the mains, both surges and drops. A C FF (C12) capacitor and a RFF (R27 + R28) resistor, both connected to the VFF pin (#5), complete an internal peak-holding circuit that provides a DC voltage equal to the peak of the rectified sinewave applied on the MULT pin (#3). In this way, in case of sudden line voltage rise, C FF is rapidly charged through the low impedance of the internal diode; in case of line voltage drop, an internal “mains drop” detector enables a low impedance switch which suddenly discharges C FF, avoiding a long settling time before reaching the new voltage level. Consequently an acceptably low steady-state ripple and low current distortion can be achieved without any considerable undershoot or overshoot on the pre-regulator's output, like in systems with no feed-forward compensation. In Figure 21 the behavior of the EVL6563H-250W demonstration board, in case of an input voltage surge from 90 to 140 Vac, is shown; in the image it is evident that the V FF function provides for the stability of the output voltage which is not affected by the input voltage surge. In fact, thanks to the VFF function, the compensation of the input voltage variation is very fast and the output voltage remains stable at its nominal value. The opposite is confirmed in Figure 20; the behavior of a PFC using the L6562A and delivering the same output power is shown; in case of a mains surge the controller cannot compensate it and the output voltage stability is guaranteed by the feedback loop only. Unfortunately, as previously stated, its bandwidth is narrow and therefore the output voltage has a significant deviation
140 Vac to 90 Vac the output voltage variation is not very different but the output voltage
forward fast discharging is much more emphasized. Figure 20. L6562A input mains surge 90 Vac to
140 Vac - no V
Figure 21. EVL6563H-250W TM PFC input Figure 22. L6562A: input mains dip 140 Vac to
90 Vac - no VFF input
Figure 23. EVL6563H-250W TM PFC input
4.4 Startup operation
wake-up time is almost independent to the input mains voltage. without any large overshoot. Figure 29. EVL6563H-250W TM PFC: startup at
90 Vac - 60 Hz - full load
Figure 30. EVL6563H-250W TM PFC: startup at
265 Vac - 50 Hz - full load
4.5 PFC_OK pin and feedback failure (open-loop) protection
Figure 2. This divider is selected so that the voltage at the pin reaches 2.5 V if the output expected, including also worst-case load/line transients. the error amplifier and PFC_OK comparator. The OVP function described above is able to handle “normal” over voltage conditions, i.e. a PFC_OK pin floating, results in shutting down the IC and stopping the pre-regulator. the voltage at the pin go above 0.27 V.
4.6 Power management and housekeeping functions
properly handled. The L6563H provides some pins to do that. PWM controller of the cascaded DC-DC converter. consumption of the power supply. Examples of intefacing some ST half-bridges controllers are shown in Figure 34. Figure 34. L6563H on/off control by a cascaded converter controller via PFC_OK or by connecting it to the cascaded converter via the R30, R31, R32 series resistors. resistor, please connect it close to the cascaded PWM for better noise immunity.
5 Layout hints
layout needs smaller EMI filters or less filter stages and so it allows a consistent cost saving. working either in transition mode or with a fixed off-time control.
- Keep power and signal RTN separated. Connect the return pins of components
converter will have to be connected to this return point.
- Minimize the length of the traces relevant to the boost inductor, MOSFET drain, boost
rectifier and output capacitor.
- Keep signal components as close as possibl e to each L6563H relevant pin. to specify,
in its high impedance status.
- Please connect heat sinks to power GND
- Add an external copper shield around the boost inductor and connect it to power GND.
- Please connect the RTN of the signal components including the feedback, PFC_OK
- Connect a ceramic capacitor (100÷470 nF) to pin #16 (Vcc) and pin #14 (GND), close
to the L6563H. Connect this point to the RTN star point (see 1). Figure 37. EVL6563H-250W TM PFC: PCB layout (SMT side view)
6 Thermal map
temperatures depending on the input mains. Figure 38. Thermal map at 115 Vac - 60 Hz - full load - PCB top side Figure 39. Thermal map at 230 Vac - 50 Hz - full load - PCB top side
Table 2. Thermal maps reference points - PCB top side
7 EMI filtering and conducted EMI pre-compliance
measurements must be done in the same conditions. by the current, decreasing the differential mode consequently limits the second one. detection to evaluate the benefit of the jittering effect of the TM control. Figure 40. EVL6563H-250W CE AVG Figure 41. EVL6563H-250W CE AVG
8 References
- L6563H datasheet 2. AN3027 “How to design a TM PFC pre-regulator with L6563S and L6563H”
9 Revision history
Table 3. Document revision history 29-Jun-2010 1 Initial release. 26-Nov-2010 2 Update Chapter 1 on page 4, Chapter 4.5 on page 20.