AN3117 STMICROELECTRONICS | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1 DMA controller description
- 1.1 DMA main features
- 1.2 Peripherals supported by DMA
- 2 Performance considerations
- 2.1 DMA latency
- 2.2 Data bus bandwidth
- 3 Programming the DMA using the standard peripheral library
- 3.1 Configuring the DMA peripheral to transfer data
- 3.1.1 Configuring the DMA channels
- 3.1.2 Selecting the channel request source
- 3.1.3 Enabling the DMA transfers
- 3.1.4 Configuring the arbitration delay
- 3.2 Supervising the DMA transfer
- 3.2.1 Method 1: Current data counter
- 3.2.2 Method 2: Flags/interrupts
- 4 DMA programming examples
- 4.1 Memory to peripheral transfer example: transferring
- 4.2 Peripheral to memory transfer example 1: transferring data
- 4.3 Peripheral to memory transfer example 2: transferring data
- 4.4 DMA transfer examples in low power mode
- 4.4.1 DMA transfer example in Wait for event (WFE) mode
- 4.4.2 DMA transfer example in Wait for interrupt (WFI) mode
- 4.5 DMA transfer example with TIM1 in Burst mode
- 4.6 DMA channel priority transfer example
- 4.6.1 Transfer example case 1: hardware priority configuration of DMA
- 4.6.2 Transfer example case 2: software priority configuration 1 of the DMA
STM8 products covered by this application note. data bandwidth and to develop very low latency response time software. correct response times for different peripherals and subsystems. examples shown in this document. Table 1. Applicable products
4.6.3 Transfer example case 3: software priority configuration 2 of the DMA
Table 2. Peripherals served by DMA and channel a llocations (medium+ and high density devices). 7
DMA controller description AN3117 6/28 Doc ID 16846 Rev 4
1 DMA controller description
The STM8L05xxx/15xxx, STM8L162xx, STM8AL31xx/3Lxx DMA controller is a system peripheral used for transferring data between the local memory and the main memory without the intervention of the central processor unit (CPU). Once the DMA registers have been configured, large blocks of data can be transferred at high speed between peripherals and a memory, or from one memory location to another. Moving data with the DMA keeps CPU resources free for other operations and allows computation and data transfer concurrency. This is especially useful in real-time computing applications where not stalling the CPU during concurrent operations is critical, and when data processing and transfer must be performed in parallel to achieve sufficient throughput.
1.1 DMA main features
- Four DMA channels shared among several peripherals
- Three transfer directions – Peripheral to memory – Memory to peripheral – Memory to memory
- Hardware and software channel priorities which allow arbitration
- Programmable number of “data to be transferred” (up to 255 data blocks)
- Capability to increment and decrement memory addressing mode
- Optional interrupt on half transactions and end of transactions
- Two transfer block sizes (8-bit and 16-bit data) which are programmable by software.
- Circular buffer management (auto-reload mode)
- Capability to suspend and to resume DMA transfers
- Capability to operate in Low power modes (Wait for interrupt or Wait for event) Each channel is assigned to a unique peripheral (data channel) at a given time. Peripherals connected to the same DMA channel (see Table 3) cannot be used simultaneously when the DMA controller is active. The DMA controller performs direct memory transfers by sharing the address and data bus with the STM8 core. The DMA request may stop CPU access to the bus for some bus cycles, for example, when the CPU and DMA are targeting the same destination (memory or peripheral). The arbitration between DMA and CPU is performed inside the STM8 core. Refer to the STM8 core description for further information.
1.2 Peripherals supported by DMA
peripherals served by the DMA and the bus system structure are represented in Figure 1. chapter in the RM0031 reference manual). The default mapping is Channel 0.
2 TIM4 can be mapped on each of the four channels: depending on the
chapter in the RM0031 reference manual). The default mapping is Channel 3. 3 DAC is not present in STM8L05xxx devices. Table 2. Peripherals served by DMA and channel allocations (medium+ and high
chapter in the RM0031 reference manual). The default mapping is Channel 0. chapter in the RM0031 reference manual). The default mapping is Channel 3. Table 3. Peripherals served by DMA and channel allocations (medium density
Figure 1. Bus system and peripherals supporting DMA
- Peripherals available on medium + and high density devices only. AES available on STM8L162xx only.
- Not available on STM8L05xxx devices.
The DMA is able to transfer data from the memory to a peripheral.
- For regular DMA channels (0, 1 and 2), data transfer can be from (or to) a part of the RAM memory (see note1).
- For memory DMA channel (channel 3), 2 cases are available: a) When a peripheral-to-memory or memory-to-peripheral transfer is performed, the memory areas can be all addressable areas (see note 2). b) When a memory-to-memory transfer is performed, the source memory areas are all addressable areas (see note 2), while the destination memory areas are the first 8 Kbytes (see note 3). Note: 1 For medium and medium+ density devices, 2-Kbyte RAM memory is accessible (between 0x0000 and 0x07FF). For high density devices, 4-Kbyte RAM memory is accessible (between 0x0000 and 0x0FFF).
2 Source memory addressable areas are comprised between 0x0000 and 0xFFFF for
medium density devices and between 0x0000 and 0x17FFF for high density devices.
3 Destination memory addressable areas are comprised between 0x0000 and 0x1FFF , which
corresponds to the RAM and the Data EEPROM.
Performance considerations AN3117 10/28 Doc ID 16846 Rev 4
2 Performance considerations
The DMA controller performs direct memory transfers by sharing the address and data bus with the STM8™ core. DMA requests may stop CPU accesses to the bus during some bus cycles, when the CPU and the DMA are both targeting memory and peripheral. The arbitration is performed inside the STM8 core. In addition, the DMA controller can signal to the STM8 core that the current access must h ave priority over the CPU. There are two ways to do this:
- The application specifies the timeout duration (number of wait cycles starting from the latest request) by configuring TO[5:0] bits in the DMA_GCSR register. The DMA then waits until this timeout has elapsed before requesting from the core a high priority access to the bus.
- The application configures a channel so that it always takes priority over the CPU. Refer to Section 4.6: DMA channel priority transfer example for more details.
2.1 DMA latency
Three operations are required to perform a DMA data transfer from peripheral to RAM (for example SPI reception): 1. DMA request arbitration and address computation 2. Reading data from the peripheral (DMA source) 3. Writing loaded data in RAM (DMA dest ination) When transferring data from RAM to peripheral (for example SPI transmission), the o perations are performed in the opposite order: 1. DMA request arbitration and address computation 2. Reading data from RAM memory (DMA source) 3. Writing data to the peripheral The service time per channel for 8-bit data transfer, tS, is given by the equation below: tS tA tACC tRAM++= where:
- tA is the arbitration and address computation time tA = 1 system clock cycle
- tACC is the peripheral access time tACC = 1 system clock cycle
- tRAM is the RAM read or write access time tRAM = 1 system clock cycle As a result, the total latency for 8-bit data transfer is 3 system clock cycles.
AN3117 Performance considerations Doc ID 16846 Rev 4 11/28 The service time per channel for 16-bit data transfer, tS, is given by the equation below: tS tA tACC16 tRAM16++= where:
- tA is the arbitration and address computation time tA = 1 system clock cycle
- tACC16 is the peripheral access time tACC16 = 2 system clock cycles
- tRAM16 is the RAM read or write access time tRAM16 = 2 system clock cycles As a result, the total latency for 16-bit data transfer is 5 system clock cycles. When the DMA is idle, it compares the priorities of all pending DMA requests (software and ha rdware priorities, in this order). The highest priority channel is served and the DMA jumps to execute the second operation. While a channel is being served (operation 2 or 3 ongoing), no other channel can be served whatever its priority. As a result, when a DMA transfer is on going, the DMA latency for the highest priority cha nnel is the sum of the ongoing transfer time (without the arbitration phase) and the transfer time for the next DMA channel to be served (highest pending priority).
2.2 Data bus bandwidth
When the DMA has priority over the CPU, the maximum data transfer rate is obtained with 16-bit data transfers at 16 MHz. Two bytes are transferred in 5 clock cycles, which makes a t ransfer rate of 6.4 Mbytes/s. For 8-bit data transfers, the maximum rate is 1 byte in 3 clock cycles, that is transfer rate of a 3 Mbytes/s. The data rate is reduced when the CPU takes prior ity over the DMA for RAM and peripheral accesses.
3 Programming the DMA using the standard peripheral
from the STMicroelectronics website: http://www.st.com/mcu/familiesdocs-120.html. driver provides the user with an easy way to configure and supervise the DMA peripheral.
3.1 Configuring the DMA peripheral to transfer data
Figure 2. The user can adapt these steps to suit his application. Figure 2. Configuring the DMA peripheral to transfer data
3.1.1 Configuring the DMA channels
Table 4. DMA_lnit parameters
3.1.2 Selecting the channel request source
request sources: one for transmission (TX) and one for reception (RX). DMA channel allocation for the appropriate communication peripheral. Table 5. DMA request configuration functions from the communication peripheral 2)TX or RX requests are selected independently. and RX requests are selected. Table 6. Communication peripheral DMA channel allocations
(using the ADC_DMACmd() function). DMA, informing it that data are ready to be transferred. SYSCFG_REMAPDMAChannelConfig() function and its parameters. control feature (using the TIMx_DMACmd() functions where x =1, 2, 3 or 4). Table 7 describes the timer DMA request sources and channel allocations. driver TIM1_DMAConfig() function. using the system configuration driver SYSCFG_REMAPDMAChannelConfig() function. SYSCFG_REMAPDMAChannelConfig() function and its parameters. Table 7. Timer DMA request sources and channel allocations
Programming the DMA using the standard peripheral library AN3117 16/28 Doc ID 16846 Rev 4
3.1.3 Enabling the DMA transfers
After configuring the DMA channels, the user should do the following: 1. Enable the corresponding DMA channel transfer (using the DMA_Cmd() function). DMA_Cmd(DMA_Channelx, ENABLE); 2. Enable the global DMA channel transfers (using the DMA_GmobalCmd() function). DMA_GlobalCmd(ENABLE); Once the DMA request is enabled, the DMA transfer starts.
3.1.4 Configuring the arbitration delay
Arbitration between the DMA and CPU is performed inside the STM8 core. The DMA controller can inform the STM8 core that the current access should have priority over the CPU. The DMA waits until the configured timeout (using the DMA_SetTimeOut() function) has elapsed before requesting from the core a high priority access to the system bus. One timeout duration is equal to one CPU cycle. When the timeout delay is programmed to 0, it means there is no timeout. Once a request is served, the DMA immediately asks the CPU for a high priority access to the system bus.
3.2 Supervising the DMA transfer
3.2.1 Method 1: Cu rrent data counter
A DMA transfer consists of a single read/write operation from/to a data block. It cannot be interrupted. A DMA transaction consists of a complete DMA read and write operation of a given number of data blocks. They can be divided into single transfers. A data block consists of either 8-bits or 16-bits of data depending on the size of the block that has been programmed. The number of transfers is indicated by the DMA_BufferSize parameter that the user chooses during DMA channel initialization (using the DMA_Init() function). The DMA driver provides a function which returns the current data counter. By reading the current data counter, using the DMA_GetCurrDataCounter() function, the user learns the number of remaining transfers.
3.2.2 Method 2: Flags/interrupts
The DMA peripheral provides two flags for each channel which are shown in Table 8. DMA_ClearFlag() / DMA_ClearITPendingBit() functions). Table 8. DMA flags
4 DMA programming examples
associated with this application note.
4.1 Memory to peripheral tr ansfer example: transferring
buffer) using DMA memory to peripheral mode. Figure 3. Transferring data from Flash memory to DAC Since the DMA is configured in circular mode, the DAC is triggered periodically by TIM4. The DMA transfer from the Flash memory buffer to the DAC is repeated indefinitely. STM8AL3Lx standard peripheral library package.
4.2 Peripheral to memory transf er example 1: transferring data
Figure 4. Transferring data from the ADC to the RAM via multi channel acquisition transfer of the ADC data register values to the RAM buffer (position 02). mode, ADC acquisition and transfer to the RAM are repeated indefinitely. STM8AL3Lx standard peripheral library package.
4.3 Peripheral to memory transf er example 2: transferring data
a specific RAM buffer using the DMA. Figure 5. Transferring data from the USART to the RAM The DMA event is provided by the USART_RX. STM8AL3Lx standard peripheral library package.
4.4 DMA transfer examples in low power mode
4.4.1 DMA transfer example in Wait for event (WFE) mode
transferred to a specific RAM buffer using the DMA. Figure 6. DMA transfer example in WFE mode The DMA event is provided by the USARTx_RX. data register to a RAM buffer, the MCU enters WFE mode. RX is configured in circular mode, the same procedure is repeated indefinitely. STM8AL3Lx standard peripheral library package.
4.4.2 DMA transfer example in Wait for interrupt (WFI) mode
returning to the main program. STM8AL3Lx standard peripheral library package.
4.5 DMA transfer example with TIM1 in Burst mode
Figure 7. DMA transfer example with TIM1 in Burst mode frequency and duty cycle when an EXTI event triggered by the key button occurs. STM8AL3Lx standard peripheral library package.
4.6 DMA channel priority transfer example
transfers. All transfers are 8 bits in size and have a length of 1.
- DMA channel 0: Transfer A: from RAM buffer 2 to TIM3 register
- DMA channel 1: Transfer B: from RAM buffer 1 to TIM2 register
- DMA channel 2: Transfer C: from TIM1 register to RAM buffer 1
- DMA channel 3: Transfer D: from TIM4 register to RAM buffer 2 Before starting any transfer, the RAM buffers and timer registers are initialized as shown in Table 9.
4.6.1 Transfer example case 1: hardwar e priority configuration of DMA
hardware priority acts and the software priority stays the same for all channels. Figure 8. Example case 1: DMA channel data transfers as a function of time Table 9. RAM buffers and timer registers at t = t0 Table 10. Example case1: priority configuration of the DMA channels
Transfer results are shown in Table 11.
4.6.2 Transfer example case 2: software priority configuration 1 of the DMA
In this example, the software priority of the channels is updated as shown in Table 12. Figure 9. Example case 2: DMA channel data transfers as a function of time Table 11. Results of example case 1 Table 12. Example case 2: priority configuration of the DMA channels
Transfer results are shown in Table 13.
4.6.3 Transfer example case 3: software priority configuration 2 of the DMA
Figure 10. Example case 3: DMA channel data transfers as a function of time Table 13. Results of example case 2 Table 14. Example case 3: priority configuration of the DMA channels
Transfer results are shown in Table 15. STM8AL3Lx standard peripheral library package. Table 15. Results of example case 3
5 Revision history
Table 16. Document revision history 21-Sep-2012 3 Added STM8L05xx products. Added Table 1: Applicable products. 21-Nov-2012 4 Added STM8AL31xx and STM8AL3Lxx products.