AN3112

AN3112 STMICROELECTRONICS | Alldatasheet

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Technical content

Datasheet sections

1 Introduction to FOT control
2 Operation of an FOT- controlled PFC pre-regu lator
3 Implementing the line-modulat ed fixed-off-time
4 Designing a fixed-off- time PFC
4.1 Input specification
4.2 Operating condition
4.3 Power section design
4.3.1 Bridge rectifier
4.3.2 Input capacitor
4.3.3 Output capacitor
4.3.4 Boost inductor
4.3.5 Power MOSFET selection and power dissipation calculation
4.3.6 Boost diode selection
4.3.7 L6564 biasing circuitry
5 Design example using the L6564-FOT PFC Excel® spreadsheet
6 Reference
7 Revision history

1 Introduction to FOT control

mode control can still be used. passive parts and no significant extra cost, is all that is needed. Figure 3. Basic waveforms for fixed Figure 4. Basic waveforms for fixed-off-time

2 Operation of an FOT- controlled PFC pre-regulator

resets the PWM latch, and M, supposedly already on, is switched off. Figure 5. Block diagram of an FOT-controlled PFC pre-regulator externally the operation of the standard TM PFC controller so that the off-time of M is fixed. the fixed off-time technique and in particular the line modulated FOT, please refer to [5].

3 Implementing the line-modulated fixed-off-time

Figure 6. During the on-time of the MOSFET the gate voltage VGD = 15 V is high, diode D is Figure 6. Circuit implementing FOT control with the L6564

Implementing the line-modulated fixed-off-time AN3112 8/36 Doc ID 16820 Rev 3 It is easy to see that TOFF is now a function of the instantaneous line voltage. We refer to this technique as line-modulated fixed-off-time (LM-FOT) [5]. This modification, although simple, introduces profound changes in the timing relationships, with a positive influence on the energetic relationships. From the control point of view, modulating T OFF is a feed-forward term that modifies the gain but does not change its characteristics. Consequently, all of the properties of the standard FOT control are maintained. Due to the highly non-linear nature of the TOFF modulation introduced by T1 and R0, its effects are discussed only qualitatively and the quantitative aspects are provided graphically for a specific case in [5]. As a practical rule, it is convenient to first select a capacitor and then to calculate the resistor needed to achieve the desired TOFF (see Section 4.3.7 on page 19). As the gate voltage VGD rises, the Rs resistor charges the C timing capacitor as quickly as possible up to VZCDclamp, without exceeding the clamp rating (IZCDx =10 mA). Then it must fulfill the following inequalities: Equation 6 where VGD (assume VGD = 10 V) is the voltage delivered by the gate driver, VGDx = 15 V its maximum value, and VF the forward drop on D. When working at high line/light load the on-time of the power switch becomes very short and the Rs resistor alone is no longer able to charge C up to VZCDclamp. The speed-up capacitor Cs is then used in parallel to Rs. This capacitor causes an almost instantaneous charge of C up to a certain level, after that, Rs completes the charge up to VZCDclamp. It is important that the steep edge caused by Cs does not reach the clamp level, otherwise the internal clamp of the L6564 undergoes uncontrolled current spikes (limited only by the dynamic resistance of the 1N4148 and the ESR of Cs) that could overstress the IC. Cs must then be: Equation 7 ZCDclamp FZCDclampGD ZCDclamp ZCDx FZCDclampGDx V VVVRRs R VI FZCDclampGDx ZCDclamp VVV VCCs −−<

AN3112 Designing a fixed-off-time PFC Doc ID 16820 Rev 3 9/36

4 Designing a fixed-off-time PFC

4.1 Input specification

The following is a possible design procedure for a fixed-off-time mode PFC using the L6564. This first part is a detailed specification of the operating conditions of the circuit that is needed for the calculations in Section 4.2 on page 11. In this example a 400 W, wide-input range mains PFC circuit is considered. Some design criteria are also given. Because the PFC is a boost topology the regulated output voltage depends strongly on the maximum AC input voltage. In fact, for correct boost operation the output voltage must always be higher than the input and therefore, as Vin max is V pk, the output has been set at 400 Vdc as the typical value. In cases where the maximum AC input voltage VACmax is higher than 265 V, as typical in ballast applications, the output voltage must be set higher accordingly. As a rule of thumb the output voltage must be set 6/7% higher than the maximum input voltage peak. The target efficiency and PF are set here at minimum input voltage and maximum load. They are used for the following operating condition calculation of the PFC. Of course at high input voltage there is higher efficiency. Because of the narrow loop voltage bandwidth, the PFC output may experience overvoltages at startup or in the case of load transients. To protect from excessive output voltages that can overstress the output components and the load, in the L6564, a device pin (PFC_OK, pin #6) has been dedicated to monitor the output voltage with a separate resistor divider, selected so that the voltage at the pin reaches 2.5 V if the output voltage exceeds a preset value (Vovp) larger than the maximum Vout that can be expected, also including worst-case load/line transients.

Mains voltage range (Vac rms): (1)
Minimum mains frequency: (2)
Rated output power (W): (3)
Regulated DC output voltage (Vdc) (4)
Expected efficiency (%): (5)
Expected power factor: (6) Vac90VACmin = Vac265VACmax = Hz47fl = W400Pout = V400Vout = %90P P in out ==η 99.0PF =

Designing a fixed-off-time PFC AN3112 10/36 Doc ID 16820 Rev 3 The mains frequency generates a 2fL voltage ripple on the output voltage at full load. The ripple amplitude determines the current flowing into the output capacitor and the ESR. Additionally, a certain hold-up capability in case of mains dips can be requested from the PFC in which case the output capacitor must also be dimensioned, taking into account the required minimum voltage value (Vout min) after the elapsed hold-up time (tHold). The PFC minimum switching frequency is one of the main parameters used to dimension the boost inductor. Here we consider the switching frequency at low mains on top of the sinusoid and at full load conditions. As a rule of thumb, it must be higher than the audio bandwidth in order to avoid audible noise and additionally it must not interfere with the L6564 minimum internal starter period, as given in the datasheet. Alternatively, if the minimum frequency is set too high the circuit shows excessive losses at higher input voltage and probably operates skipping switching cycles not only at light load. The typical minimum frequency range is 55÷95 kHz for wide range operation. The design is done on the basis of a ripple factor (the ratio of the maximum current ripple amplitude to the inductor peak current at minimum line voltage) kr=0.34. In order to properly select the power components of the PFC and dimension the heat sinks in case they are needed, the maximum operating ambient temperature around the PFC circuit must be known. Please note that this is not the maximum external operating temperature of the entire equipment, but it is the local temperature at which the PFC components are working.

Maximum. output voltage (Vdc): (7)
Maximum output low frequency ripple: (8)
Minimum output voltage after line drop (Vdc): (9)
Hold-up capability (ms): (10)
Minimum switching frequency (kHz) (11)
Ripple factor (12)
Maximum ambient temperature (°C): (13) V430VOVP = V10Vout =∆ V300V minout = ms20tHold = kHz80f minsw = 34.0kr = C50Tambx °=

AN3112 Designing a fixed-off-time PFC Doc ID 16820 Rev 3 11/36

4.2 Operating condition

The first step is to define the main parameters of the circuit, using the specification points given in Section 4.1 on page 9: Rated DC output current: Equation 8 Maximum input power: Equation 9 Referring to the main currents shown in Figure 1, the following formula expresses the maximum value of current circulating in the boost cell which means at minimum line voltage of the selected range: RMS input current: Equation 10 It is important to define the following ratios in order to continue describing the energetic relationships in the PFC: Equation 11 Equation 12 From Equation 11 and Equation 12: Line peak current: Equation 13 Inductor Ripple-∆ILpk: out out out V PI = A00.1V400 W400Iout == η= out in PP W44.44410090 W400Pin =⋅= PFVAC PI min out in ⋅= A99.499.0Vac90 W400Iin =⋅= out min min V VAC2k = 32.0V400 Vac902kmin == out max max V VAC2k = 94.0V400 Vac2652kmax == outmin in maxPK Vk P2I ⋅ ⋅= A98.6V40032.0 W44.4442I maxPK =⋅

Designing a fixed-off-time PFC AN3112 12/36 Doc ID 16820 Rev 3 Equation 14 Inductor peak current: Equation 15 It is also possible to calculate the RMS current flowing into the switch and into the diode, needed to calculate the losses of these two elements. RMS switch current: Equation 16 RMS diode current: Equation 17 It is worth remembering that the accuracy of the approximate energetic relationships described here is quite good at maximum load for low values of parameter k, that is, at low line voltage, but worsens at high line and as the power throughput is reduced. Since, in the design phase, current stress is calculated at maximum load and minimum line voltage, their accuracy is acceptable for design purposes.

4.3 Power section design

4.3.1 Bridge rectifier

The input rectifier bridge can use standard slow recovery, low-cost devices. Typically a 600 V device is selected in order to obtain a good margin against mains surges. An NTC resistor, limiting the current at turn-on, is required to avoid overstress to the diode bridge. The rectifier bridge power dissipation can be calculated using equations Equation 18,Equation 19,Equation 20. The threshold voltage (Vth) and dynamic resistance (Rdiode) of a single diode bridge can be found in the component datasheet. maxPK r r pk Ik38 k6IL ⋅⋅− 34.06ILpk =⋅⋅− ⋅=∆ maxPK r maxpk Ik38 8IL maxpk =⋅⋅−= π ⋅−⋅⋅= 3 k162Vk PISW min outmin in rms A22.43 32.0162V40032.0 W400ISWrms =π ⋅−⋅⋅= π⋅⋅= 3 k16 Vk PID min outmin in rms A57.23 32.016 V40032.0 W400IDrms =π ⋅⋅⋅=

AN3112 Designing a fixed-off-time PFC Doc ID 16820 Rev 3 13/36 Equation 18 Equation 19 The power dissipated on a D15XB60 bridge may be: Equation 20

4.3.2 Input capacitor

The input filter capacitor (Cin) is placed across the diode bridge output. This capacitor must smooth the high-frequency ripple and must sustain the maximum instantaneous input voltage. In a typical application an EMI filter is placed between the mains and the PFC circuit. In this application the EMI filter is reinforced by a differential mode Pi-filter after the bridge to reject the differential noise coming from the whole switching circuit. The design of the EMI filter (common mode and differential mode) is not described here. The value of the input filter capacitor can be calculated as follows, simply considering the output power that the PFC should deliver at full load: Equation 21 The maximum value of this capacitor is limited to avoid line current distortion. The value chosen for this design is 1 µF .

4.3.3 Output capacitor

The output bulk capacitor (Co) selection depends on the DC output voltage (4), the allowed maximum voltage (7) and the converter output power (3). The 100/120 Hz (twice the mains frequency) voltage ripple (Vout = peak-to-peak ripple value) (8) is a function of the capacitor impedance and the peak capacitor current: Equation 22 With a low ESR capacitor the capacitive reactance is dominant, therefore: A53.32 A99.42 I2I in inrms =⋅=⋅= A25.2A99.42I2I in avg_in =π ⋅=π avg_inthinrms2 diodebridge IV4IR4P ⋅⋅+⋅⋅= bridge =⋅⋅+⋅Ω⋅= out in P105.2C ⋅⋅= − F1W400105.2C 3 in µ=⋅⋅= − Ol outout ESR )Cf22( 1I2V + ⋅⋅π ⋅⋅=∆

Designing a fixed-off-time PFC AN3112 14/36 Doc ID 16820 Rev 3 Equation 23 Vout is usually selected in the range of 1.5% of the output voltage. Although ESR does not usually affect the output ripple, it should be taken into account for power loss calculations. The total RMS capacitor ripple current, including mains frequency and switching frequency components, is: Equation 24 If the PFC stage must guarantee a specified hold-up time, the selection criterion of the capacitance is different. Co has to deliver the output power for a certain time (t Hold) with a specified maximum dropout voltage (Vout min) that is the minimum output voltage value (which takes load regulation and output ripple into account). Vout min is the minimum output operating voltage before the 'power fail' detection and consequent stopping by the downstream system supplied by the PFC. Equation 25 A 20% tolerance on the electrolytic capacitors must be taken into account for correct dimensioning. Following the previous relationships, after selecting the commercial value of 330 µF the actual hold-up capability and ripple voltage are recalculated. In detail: Equation 26 Equation 27

4.3.4 Boost inductor

In the continuous mode approach, the acceptable current ripple factor, Kr, is typically fixed in the range between 10% to 35%. For this design, the maximum specified current ripple factor is 34%. outoutl out outl out O VVf2 P Vf2 W400CO µ=⋅⋅⋅π≥ outrms2 Crms IIDI −= () ( ) A36.2A0.1A56.2I 22 Crms =−= () 2 minout outout Holdout O VVV tP2C −∆− ⋅⋅= () ( ) F3.242 V300V10V400 ms20W4002C 22O µ= ⋅⋅= out minout outoutO hold P2 VVVC t ⋅ V300V10V400F330t hold =⋅ −−⋅µ= Ol out out Cf2 IV ⋅⋅π⋅=∆ V2.10F330Hz472 A0.1Vout =µ⋅⋅π⋅=∆

Figure 9. The effect of fixing off-time - boundary between DCM and CCM the system works in discontinuous conduction mode and in transition mode at the boundary. voltage and sense resistor value. maximum temperature rise of the inductor.

4.3.5 Power MOSFET selection and power dissipation calculation

(4) adding some margin (20%) to guarantee reliable operation. The MOSFET's power dissipation depends on conduction, switching and capacitive losses.

AN3112 Designing a fixed-off-time PFC Doc ID 16820 Rev 3 17/36 temperature), a factor of 1.75 to 2 should be taken into account. The exact factor can be found on the device datasheet. Now, combining equations Equation 29 and Equation 16, the conduction losses referred to a 1 ΩRDS(on), at ambient temperature as a function of Pin and VAC can be calculated: Equation 30 The generic switching losses due to the MOSFET commutation occurring at turn-on and turn-off can be basically expressed by: Equation 31 Because the switching frequency depends on the input line voltage and phase angle on the sinusoidal waveform, it can be demonstrated that from Equation 31 the switching losses per 1 µs of current, rise and fall-time can be written as: Equation 32 From the STP12NM50FP datasheet trise = tfall = 0.01 µs is the crossover time at turn-on and off. At turn-on the losses are due to the discharge of the total drain capacitance inside the MOSFET itself. In general, the capacitive losses are given by: Equation 33 Where Cd is the total drain capacitance including the MOSFET and the other parasitic capacitances such as inductor etc. At the drain node, V MOS is the drain voltage at MOSFET turn-on. Taking into account the frequency variation with the input line voltage and the phase angle, the capacitive losses per 1 nF of total drain capacitance can be calculated as: Equation 34 The total drain capacitance (Cd) of the two parallel MOSFETs is 0.36 nF , not including the other component contributions, Vout is the drain voltage at MOSFET turn-on. out in2 rmscond 3 )VAC(k162V)VAC(k P2))VAC(ISW(2)VAC(P ⎟⎟ π )VAC(f2 ttIV)VAC(P sw fallrise MOSMOSswitch ⋅⎟ ⎛ +⋅⋅= ()∫ π sw 2pk maxpkoutswitch d),VAC(fsin1 ILILV)VAC(P )VAC(fVC2 1)VAC(P swMOS2 dcap ⋅⋅⋅= () ϑ⋅ϑπ⋅=′ ∫ π d),VAC(fV1 1)VAC(P sw outcap

MOSFET datasheet for the selected device package, a heat sink must be used. Figure 10. Conduction losses and total losses in the STP12NM50FP MOSFET two selected STP12NM50FP MOSFETs.

4.3.6 Boost diode selection

Following a similar criterion to that of the MOSFET, the output rectifier can also be selected. 125°C the device has been correctly selected, otherwise a bigger device must be selected.

calculation of the rectifier losses.

4.3.7 L6564 biasing circuitry

Figure 11. For more detail on the internal functions please refer to the datasheet. Figure 11. L6564 internal schematic

Designing a fixed-off-time PFC AN3112 20/36 Doc ID 16820 Rev 3 Pin 1 (INV) is connected both to the inverting input of the E/A and to the OVP circuitry. A resistive divider is connected between the boost regulated output voltage and this pin. The internal reference on the non-inverting input of the E/A is 2.5 V (typ.), the output voltage (Vout) of the PFC pre-regulator is set at its nominal value, by the resistors ratio of the feedback output divider. RoutH and RoutL are then selected considering the desired nominal output voltage and the desired output power dissipated on the output divider. For example for a 50 mW output divider dissipation: Equation 39 With the commercial value selected RoutH = 3 MΩ: Equation 40 Equation 41 RoutL = 62 kΩ in parallel to a 27 kΩ can be selected. Please note that for RoutH a resistor with a suitable voltage rating (>400 V) is needed, or more resistors in series must be used. Pin 6 (PFC_OK - feedback failure protection): The PFC_OK pin is dedicated to monitoring the output voltage with a separate resistor divider. This divider is selected so that the voltage at the pin reaches 2.5 V if the output voltage exceeds a preset value (Vovp), usually larger than the maximum Vout that can be expected, also including worst-case load/line transients. For a maximum output voltage Vout max of 430 V and selecting a 50 µA current flowing into the divider: Equation 42 By selecting a commercial value of 51kΩ: Equation 43 Connecting in series, two 3.3 MΩ resistors and one 2.2 MΩ resistor, a total value of 8.8 MΩ can be obtained. Note that both feedback dividers connected to the L6564 pin #1 (INV) and pin #6 (PFC_OK) can be selected without any constraints. The unique criterion is that both dividers must sink mW50 )V5.2V(R OUT outH −= Ω=−= M160.3mW50 )V5.2V400(R outH 1V5.2 V R R out outL outH −= 1591V5.2 V400 R R outL outH =−= 159 RR outH outL = Ω=Ω= k8.18159 M3RoutL divider OK_PFC_REF L I VR = Ω=µ= k50A50 V5.2RL −⋅= 1V VRR OK_PFC_REF MAX_OUT LH Ω=⎟ ⎛ −⋅Ω= M721.81V5.2 V430k51RH

AN3112 Designing a fixed-off-time PFC Doc ID 16820 Rev 3 21/36 a current from the output bus which needs to be significantly higher than the current biasing the error amplifier and PFC_OK comparator. The OVP function described above can handle "normal" over-voltage conditions, that is, those resulting from an abrupt load/line change or occurring at start-up. If the over-voltage is generated by a feedback disconnection for instance, when one of the upper resistors of the output divider fails to open, an additional circuitry detects the voltage drop of pin INV. If the voltage on pin INV is lower than 1.66V (Typ.) and at same time the OVP is active, a feedback failure is assumed. Therefore, the gate drive activity is immediately stopped, the device is shut down, its quiescent consumption is reduced to below 180 µA and the condition is latched as long as the supply voltage of the IC is above the UVLO threshold. To restart the system it is necessary to recycle the input power, so that the Vcc voltage of the L6564 goes below 6 V and that one of the PWM controllers goes below its UVLO threshold. Note that this function offers complete protection against feedback loop failures or erroneous settings, and also against the failure of the protection itself. Either resistor of the PFC_OK divider failing short or open or a PFC_OK pin floating may result in shutting down the IC and stopping the pre- regulator. In addition, the PFC_OK pin doubles its function as a not-latched IC disable: a voltage below 0.23 V shuts down the IC, reducing its consumption below 2 mA. To restart the IC, simply let the voltage at the pin go above 0.27 V. Pin 2 (COMP): This pin is the output of the E/A that is fed into one of the two inputs of the multiplier. A feedback compensation network is placed between this pin and the INV pin (pin#1). It must be designed with a narrow bandwidth in order to avoid the system rejecting the output voltage ripple (100 Hz) that would cause high distortion of the input current waveform. A theoretical criterion to define the compensation network value is to set the E/A bandwidth (BW) from 20 to 30 Hz. For a more complex way of compensating the FOT PFC please refer to [ 1], [2], [3]. A compensated two-pole feedback network for this 400 W FOT PFC can be obtained with the following values: to which the following open-loop transfer function and its phase function correspond. nF100CcompP = F1CcompS µ= Ω= k56RcompS (14)

Designing a fixed-off-time PFC AN3112 24/36 Doc ID 16820 Rev 3 Equation 48 The voltage on the MULT pin is also used to derive the information from the RMS mains voltage for the VFF compensation. Before describing the correct operating point of the multiplier for the brownout function the voltage feed forward pin and its enable-disable property is here described: Pin 5 (voltage feed forward): The power stage gain of PFC pre-regulators varies with the square of the RMS input voltage. As does the crossover frequency (fc) of the overall open- loop gain because the gain has a single pole characteristic. This leads to large trade-offs in the design. For example, setting the gain of the error amplifier to get fc = 20 Hz @ 264 Vac means having fc about 4 Hz @ 88 Vac, resulting in sluggish control dynamics. Additionally, the slow control loop causes large transient current flow during rapid line or load changes that are limited by the dynamics of the multiplier output. This limit is considered when selecting the sense resistor to let the full load power pass under minimum line voltage conditions, with some margin. But a fixed current limit allows excessive power input at high line, whereas a fixed power limit requires the current limit to vary inversely with the line voltage. Voltage feed-forward can compensate for the gain variation with the line voltage and allow the overcoming of all of the above-mentioned issues. It consists of deriving a voltage proportional to the input RMS voltage, feeding this voltage into a squarer/divider circuit (1/V corrector) and providing the resulting signal to the multiplier which generates the current reference for the inner current control loop. In this way, a change of the line voltage causes an inversely proportional change of the half- sine amplitude at the output of the multiplier (if the line voltage doubles the amplitude of the multiplier, output is halved and vice versa), so that the current reference is adapted to the new operating conditions with (ideally) no need for invoking the slow dynamics of the error amplifier. Additionally, the loop gain is constant throughout the input voltage range, which significantly improves the dynamic behavior at low line and simplifies loop design. Actually, with another PFC embedding the voltage feed-forward, deriving a voltage proportional to the RMS line voltage implies a form of integration, which has its own time constant. If it is too small the voltage generated may be affected by a considerable amount of ripple at twice the mains frequency which causes distortion to the current reference (resulting in high THD and poor PF); if it is too large there may be a considerable delay in setting the right amount of feed-forward, resulting in excessive overshoot and undershoot of the pre-regulator's output voltage in response to large line voltage changes. Clearly a trade- off was required. The L6564 produces an innovative voltage feed-forward which, with a technique that makes use of just two external parts, overcomes this time constant trade-off issue regardless of which voltage change occurs on the mains, both surges and drops. A capacitor CFF and a resistor RFF , both connected from the VFF pin (pin #5) to ground, complete an internal peak-holding circuit that provides a DC voltage equal to the peak of the rectified sine-wave applied on the MULT pin (pin #3). In this case the following value has been selected: (15) V V66.1dV dV MULT CS = F1CFF µ= Ω= M1RFF

AN3112 Designing a fixed-off-time PFC Doc ID 16820 Rev 3 25/36 In this way, in the case of a sudden line voltage rise, CFF is rapidly charged through the low impedance of the internal diode; in case of line voltage drop, an internal mains drop detector enables a low impedance switch which suddenly discharges CFF , avoiding long settling time before reaching the new voltage level. Consequently an acceptably low steady-state ripple and low current distortion can be achieved without any considerable undershoot or overshoot on the pre-regulator's output, like in systems with no feed-forward compensation This pin is internally connected to a comparator in order to provide the brownout (AC mains undervoltage) protection. A voltage below 0.8 V shuts down (not latched) the IC and brings its consumption to a considerably lower level. The IC restarts when the voltage at the pin rises above 0.88 V. These details must be taken into account during the MULT divider selection. The suggested procedure to properly set the operating point of the multiplier is now described. First, the maximum peak value for V MULT, VMULTmax is selected. This value, which occurs at maximum mains voltage, should be 3 V or thereabouts in wide range mains and less in single mains. The sense resistor selected is Rs = 0.12 Ω and it is described in the pin 4 section. According to the L6564 datasheet and to the linearity setting of the pin, the maximum voltage on the multiplier input is: From (16) the maximum required divider ratio is calculated as: Equation 49 Supposing a 60 µA current flowing into the multiplier divider the lower resistor value can be calculated: Equation 50 A commercial value of 51 kΩ for the lower resistor is selected. The upper resistor value can now be calculated: Equation 51 In this example a RmultH = 6.9 MΩ and a RmultL = 51 kΩ can be selected. For RmultH a resistor with a suitable voltage rating (>400 V) is needed, or more resistors in series must be used. The voltage on the multiplier pin with the selected component values re-calculated at minimum line voltage is 0.93 V and at maximum line voltage is 2.74 V. So the multiplier works correctly within its linear region. (16) V3VMULTmax = max maxMULT p 108 Vac2652 V00.3 VAC2 Vk −⋅= Ω=µ=µ= k50A60 V00.3 A60 VR maxMULT multL Ω=Ω ⋅−=−= − M319.6k51 108 1081Rk k1R 3 multL p p multH

Designing a fixed-off-time PFC AN3112 26/36 Doc ID 16820 Rev 3 Because the MULT divider also determines the mains input voltage at which the PFC starts and stops (brownout function), these values are calculated using the actual divider ratio: Equation 52 And also the stop voltage: Equation 53 Start and stop PFC mains voltage are compatible with the input mains voltage range (1). In order to obtain the required startup and shutdown voltage, a reiteration may be required, by selecting MULT resistors and checking the actual PFC start and stop mains voltage. Pin 7 (ZCD): This is the input of the zero current detector circuit. In FOT mode, it is connected to the line-modulated fixed-off-time circuit seen in Figure 6. Taking into account the information in Section 3: Implementing the line-modulated fixed-off-time, the starting point for the design of that circuit is the pair of the desired values for TOFF on the top of the line voltage sinusoid at minimum (TOFF @VACmin) and maximum line (TOFF @VACmax) obtained by setting the switching frequency on the peak of the sinusoid at low mains and considering the minimum on-time of the L6564: Equation 54 Equation 55 Where Fswmin is the switching frequency on top of the sinusoid of the input voltage at VACmin = 90 Vac (Figure 16) and 220 ns is a corrector factor in order to consider the delay between the ZCD and GD signal. Considering the ratio between Equation 55, Equation 54, we have: Equation 56 In the formula, Equation 55 and Equation 54, the delay between the ZCD signal and the gate drive signal is taken into account in order to increase the accuracy of the mathematical model. multL multLmultH START R RR k51M9.6 V88.0VSTART =Ω Ω+Ω⋅= multL multLmultH STOP R RR k51M9.6 V80.0VSTOP =Ω Ω+Ω⋅= minsw min minOFF f k)VAC(T = s76.3ns220kHz80 32.0)VAC(T minOFF µ=−= max maxminON maxOFF k1 kT)VAC(T − ⋅= s1.6ns22094.01 94.0ns450)VAC(T maxOFF µ=−− )VAC(T )VAC(T minOFF maxOFF x =ρ 63.1s76.3 s1.6 x =µ µ=ρ

in order to avoid line distortion [5]. Figure 16. Switching frequency function on the peak of the sinusoid input voltage discharging time constant of the capacitor C.

Designing a fixed-off-time PFC AN3112 28/36 Doc ID 16820 Rev 3 Equation 59 Equation 60 From Equation 56 and Equation 59, solving the following equation: Equation 61 And then substituting K1 value into the Equation 60 expression, the k2 parameters are obtained: Equation 62 From the values of K1 and K2 it is possible to calculate the time constant τ =(R1//R2) C necessary to achieve the desired TOFF@90 Vac: Equation 63 Now, by selecting a capacitor C in the hundred picofarad range or a few nanofarads, for example a C =220 pF , it is possible to determine the required equivalent resistance value: Equation 64 From Equation 57 R and R0 are found: [][] ⎥ ⋅+− −⋅+ ⎡ +⋅− −⋅⎥⎦ ⎡ +⋅ Fminmult ZCDtrigger 1FminmultZCDclamp 1Fminmult F min max minmult ZCDtrigger min max minmultZCDclamp min max minmult 1minmult VV Vln)k(VVV )k1(VVln VVAC VACV Vln )k(VVAC VACVV )k1(VVAC VACV ln )k,V( [] ⎥ ⋅+− −⋅+⋅− Fminmult ZCDtrigger 1FminmultZCDclamp 1Fminmult 1minmult2 VV V lnkVVV )k1(VVlnk1 1)k,V(k 0)k,V( x1minmult =ρ−ρ 903.0K1 = )k,V(kK 1minmult22 = 17.11K2 = minOFF K )VAC(T=τ ns35.33617.11 s76.3 =µ=τ CReq τ= Ω== k53.1pF220 ns35.336Req

Designing a fixed-off-time PFC AN3112 30/36 Doc ID 16820 Rev 3 Equation 69 Equation 70 For example, a commercial value of the limiting resistor of 1 kΩ and a speed-up capacitor of 100 pF can be selected for this application. Pin 8 (GND) acts as the current return both for the signal internal circuitry and for the gate drive current. When laying out the printed circuit board, these two paths should run separately. Pin 9 (GD) is the output of the driver. The pin is able to drive an external MOSFET with 600 mA source and 800 mA sink capability. The high-level voltage of this pin is clamped at about 12 V to avoid excessive gate voltages if the pin is supplied with a high Vcc. To avoid undesired switch-on of the external MOSFET because of some leakage current when the supply of the L6564 is below the UVLO threshold, an internal pull-down circuit holds the pin low. The circuit guarantees 1.1 V maximum on the pin (@ Isink = 2 mA), with VCC > VCC_ON. This allows the omitting of the bleeder-resistor connected between the gate and the source of the external MOSFET used to this purpose. Pin 10 (Vcc) is the supply of the device which is externally connected to the start-up circuit (usually, one resistor connected to the rectified mains) and to the self-supply circuit. Whatever the configuration of the self-supply system, a capacitor is connected between this pin and ground. To start the L6564, the voltage must exceed the start-up threshold (12 V typ.). Below this value the device does not and consumes less than 90 µA (typ.) from Vcc. This allows the use of high value start-up resistors (in the hundreds kΩ), which reduces power consumption and optimizes system efficiency at low load, especially in wide range mains applications. When operating, the current consumption (of the device only, not considering the gate drive current) rises to a value depending on the operating conditions but never exceeding 6 mA. The device continues to work as long as the supply voltage is over the UVLO threshold (13 V max). If the Vcc voltage exceeds 22.5 V an internal zener diode, 20 mA rated, is activated in order to clamp the voltage. Please remember that during normal operation the internal zener doesn’t have to clamp the voltage, because in this case the power consumption of the device increases considerably and its junction temperature also increases. The suggested operating condition, for safe operation of the device, is below the minimum clamping voltage of the pin. Ω<<Ω k1Rs726 pF144Cs <

5 Design example using the L6564-FOT PFC Excel ®

pre-regulator using the STMicroelectronics L6564 controller, operating in fixed-off-time. Designing a fixed-off-time PFC. Figure 19. Excel spreadsheet design specification input table Figure 20. Other design data Figure 21, including the power dissipation calculation of the main components.

Figure 21. Excel spreadsheet FOT PFC schematic The bill of material in Figure 21 is automatically compiled by the Excel spreadsheet. It summarizes all the selected components and some salient data.

Figure 22. Excel spreadsheet BOM

400 W FOT PFC BASED ON L6564

6 Reference

A new continuous-time model for current-mode control with constant frequency, constant on-time and constant off-time, in CCM and DCM”, IEEE power electronics specialists conference record, San Antonio, Texas, pp. 382-389, 1990 2. “Current mode control”, venable technical paper #5, www.venableind.com 3. “Fixed-off-time control of PFC pre-regu lators”, 10th European conference on power electronics and applications, EPE2003, Toulouse, France, paper 382 4. “L6564, transition-mode PFC controller”, datasheet, www.st.com 5. “Design fixed-off-time-controlled PFC pre-regulators with the L6562”, AN1792 6. “400W FOT -controlled PFC pre-regulator with the L6563”, AN2485 7. “A systematic approach to frequency comp ensation of the voltage loop in boost PFC pre-regulator”, abstract

7 Revision history

Table 1. Document revision history 03-May-2010 1 Initial release. 02-Dec-2010 2 Updated: Section 4.3.7 on page 19. 09-Feb-2011 3 Updated: Figure 11 on page 19.

Summary

Solution for designing a fixed off-time controlled PFC pre-regulator 09-Feb-2011

Description