AN3100 STMICROELECTRONICS | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 24
Technical content
Datasheet sections
- 1 SPEAr3xx memory controller over view
- 2 DDR overview
- 2.1.1 Package differences
- 2.1.2 Power supply differences
- 2.1.3 Other feature differences
- 2.2 Addressing
- 2.3 DDR mobile overview
- 3 DDR programming in SPEAr3xx
- 4 Configuring SPEAr MPMC for a specific DDR memory part
- 5 DDR controller delay lines tuni ng
- 5.1 Reading from DRAM
- 5.2 Writing to DRAM
- 5.2.1 Example using these parameters
- 6 PCB layout recommendations
- 7 Pad descriptions and configurations
- 7.1 DDR_PAD register configuration
March 2012 Doc ID 16606 Rev 2 1/24 AN3100 Application note Configuring the SPEAr3xx multi-port memory controller (MPMC) for external DDR SDRAM Introduction The SPEAr3xx embedded MPU family features a multi-port memory controller for interfacing with external DDR or DDR2 memory devices. This application note describes how to configure the MPMC to use different types of DDR and DDR2 memories and tune the parameters in accordance with JEDEC requirements and the flexibility available in the application.
1 SPEAr3xx memory controller overview
the system elements/blocks and external memory. can read or write to the memory. This can be handled by the MPMC’s multi-port capablity. data ports (M0,..,M4) and the various subsystems of the design. Figure 1. SPEAr3xx architecture SPEAr3xx and the corresponding memory controller AHB slave data port.
32 KI/32 KD
85 Multilayer bus interconnection matrix
to connect masters to the external DDR. the selected DDR memory part, DDR frequency, CAS latency etc. Table 1. Memory controller AHB data ports
2 DDR overview
(double data rate) SDRAM (synchronous DRAM), which is a variant of dynamic RAM. performance. However, SRAMs are much more expensive than DRAMs. and the processor. SDRAM transfers one bit (per data line) of data per clock cycle. interface’s clock speed remains constant, but the data bus effectively doubles in frequency. The figure below shows a simple DDR1 SDRAM architecture example. Figure 2. DDR1 SDRAM architecture as part of other control signals to form commands rather than simple strobes.
precharging a row (deactivating a row, often in preparation for activating a new row). automatically precharge the activated row after the requested transaction completes. Table 2. Basic SDRAM command set
Being a 2nd generation DDR, the most important improvement found in DDR2 memory is its transfer data rate or bandwidth. As in the case of DDR SDRAM vs. SDRAM, the bandwidth of DDR2 memory can double the bandwidth of DDR. DDR already operates on both the rising and the falling edge of the clock, so DDR2 can achieve twice the bandwidth by doubling the I/O buffer frequency. DDR2 utilizes a “4-bit prefetch” architecture: this means that 4 bits of data are moved from the memory array to the I/O buffer per data line for each core clock cycle. The core clock cycle refers to the cycle time of the memory array, and the frequency of the memory array is half of the I/O buffers and ¼ of the data rates. The table below compares the main features of DDR1 and DDR2. Section 2.1.1 and Section 2.1.2 give more details on the package and power supply differences. Table 3. DDR1 and DDR2 at a glance
Features
Data rate 200/266/333/400 Mbps 400/533/667 Mbps Bus frequency 100/133/166/200 MHz 200/266/333 MHz DRAM core frequency 100/133/166/200 MHz 100/133/166 MHz Prefetch size 2 bit 4 bit Burst length 2/4/8 4/8 Data strobe Single DQS Differential Strobe: DQS, /DQS CAS latency 1.5, 2, 2.5 3, 4, 5 Write latency 1T Read latency-1 Power Specs Core voltage (VDD) 2.5 V 1.8 V I/O voltage (VDDQ) SSSTL_2(2.5 V) SSSTL_1.8(1.8 V) Format Packaging TSOP(II), TBGA FBGA Compatibility with DDR1 Command Set Same as DDR1 Parameters Same as DDR1 Bus Utilization and Signal Integrity New features ODT OCD calibration Posted CAS Additive latency
2.1.1 Package differences
DDR2 memories have smaller size packages with less electrical noise, thus resulting in improved integrity at higher operating frequencies.
2.1.2 Power supply differences
DDR2 operates at 1.8 V. This is a 28% reduction compared to DDR1, which combined with power saving features such as smaller page sizes and an active power down mode results in power consumption advantages.
2.1.3 Other feature differences
DDR2 has also some other new features like on die termination (ODT). Around the memory slots on a DDR1-supporting motherboard, there can be termination resistors, which are used to eliminate excessive signal noise. For DDR2 modules, the termination resistors are built into the chip, which are far closer to the source of the noise. This ODT feature can reduce interference within the chip, thus guaranteeing the stability and reliability of DDR2 memory when working under high frequencies. There are other features such as Posted CAS and Additive latency, which work together to prevent data collisions and utilize the data bus more efficiently, as well as the off-chip driver calibration (OCD), which increases signal integrity and system timing margin as well.
2.2 Addressing
Once configured, you do not need to to worry about the DDR protocol; you can access the DDR by directly accessing the memory address. In SPEAr3xx, DDR is mapped from 0x0000_0000 to 0x3FFF_FFFF: that means that an addressable space of 1 GB is dedicated to the external DRAM. In this way you can address, using all the 30 address bits, up to 2 x 4 Gb memory chips. Only 256 Mb x 16 cuts are possible because of the presence of only 14 address lines, DDR_MEM_ADDR [14:0]. In this case, the use of the bits is divided in the following way:
- 10 bits for column address
- 3 bits for bank address
- 15 bits for row address In the user address, bit 0 is used to select the width of the datapath. It is fixed to ‘0’ if the datapath is 16 bit and if the datapath is 8 bit, it is fixed to ‘1’. So in this case:
- User_address [0] = datapath;
- User_address [10:1] = column address;
- User_address [13:11] = bank address;
- User_address [28:14] = row address;
- User_address [29] = chip select; Regardless of the memory cut selected, the CPU always sees a contiguous addressable space. For this reason, the memory controller always shifts the memory address parts (row, bank and column) in the user address according to the physical memory cut attached and its configuration.
For example, the situation for the cut 128 Mb x 8 in eight and four bank mode is shown below:
- 128 Mb x 8 (eight bank mode, all 3 bank address bits are used) – User_address [0] = datapath; – User_address [10:1] = column address; – User_address [13:11] = bank address; – User_address [27:12] = row address; – User_address [28] = chip select;
- 128 Mb x 8 (four bank mode, only 2 bits are used for the bank address) – User_address [0] = datapath; – User_address [10:1] = column address; – User_address [12:11] = bank address; – User_address [26:13] = row address; – User_address [27] = chip select; SPEAr3xx supports DDR mobile and DDR2 devices. The memory controller needs to be configured once at system startup depending on the memory type, size, and vendor and on the frequency you want to work with.
2.3 DDR mobile overview
In addition to DDR2, SPEAr3xx also supports DDR mobile for low power consumption applications, such as battery powered devices. Of course, the clock frequency and hence the bandwidth of DDR mobile is reduced comared to DDR2. DDR mobile has the following special features:
- Temperature-compensated self refresh (TCSR) This is an on-chip temperature sensor that controls the refresh interval based on the device temperature.
- Partial-array self refresh (PASR) For power savings, the PASR feature enables the controllers to select the amount of memory that will be refreshed during the self refresh.
- Deep power-down (DPD) Deep power-down mode effectively cuts the power to the array and decreases leakage current. Applications that do not require data retention can use the DPD feature while the system power is maintained. Data is not retained after the device enters DPD mode.
- Clock stop mode Clock stop mode can be used to save power in the application by reducing the number of transitions in the clock path. Power savings can be achieved by selecting either of the following methods: – Change the clock frequency when the data transfers require a different rate of speed – Hold CKE HIGH, with CK LOW and CK# HIGH for the full duration of clock stop mode Both methods are specific to the application and its requirements, and both methods enable power savings by reducing the number of transitions in the clock path.
DDR programming in SPEAr3xx AN3100 10/24 Doc ID 16606 Rev 2
3 DDR programming in SPEAr3xx
In the SPEAr3xx LSP (Linux support package), the memory controller is programmed in a small piece of firmware executed just after boot ROM code and named “Xloader”. The standard Xloader provided by STMicroelectronics is coded for the DDR2 device installed on the ST SPEAr3xx evaluation boards. The memory part available on ST’s evaluation board is either an mt47H64M16_3 1-Gbit or an mt47H32M16 viz. 512-Mbit capacity DDR2 device. Y ou need to:
- Change the setting of the memory controller in case of different vendor /different memory sizes. Refer to Section 4: Configuring SPEAr MPMC for a specific DDR memory part for the procedure to follow.
- Fine tune the DLL to find the best settings of the MPMC in the your application board, as explained in Section 5: DDR controller delay lines tuning. The objective of the next two sections is to provide all the information you need to customize the “general purpose” MPMC settings provided by ST, modifying them to match your application requirements.
4 Configuring SPEAr MPMC for a specific DDR memory
address of MPMC: this requires careful study. SPEAr devices and for each selected DDR part.
- Product name, for example SPEAr600 or SPEAr300
- CAS latency supported by the selected DDR part at the selected frequency
- Required burst length (f ixed to 4 in case of DDR2)
The figure below shows a snapshot of the page of the Web tool. Figure 3. ST SPEAr600 configuration manager
Configuring SPEAr MPMC for a specific DDR memory part AN3100 12/24 Doc ID 16606 Rev 2 This tool allows you to select memories and request the configuration values. A progress page is displayed while the script runs, and the file can be downloaded when the script completes. Once the configuration values for SPEAr3xx are obtained from the Web tool for the selected DDR part, these values should be updated in the Xloader code. In the Xloader code, there are separate DDR configuration files for SPEAr3xx in a folder named “DDR”. Y ou need to create another similar DDR configuration file for the memory part in use with the values received from the Web tool. Moreover, it is necessary to make sure that the PLL of the SPEAr system used to clock DDR is programmed for the selected DDR frequency. Refer to the miscellaneous block chapter of the SPEAr3xx user manual for details.
AN3100 DDR controller delay lines tuning Doc ID 16606 Rev 2 13/24
5 DDR controller delay lines tuning
There are certain JEDEC timing requirements for DDR signals on the memory part side for writes and at the controller side for reads. All DRAM and memory controller manufacturers follow these timing specifications for reliable data read/write. Because of PCB properties (for example, track lengths, impedance, device Substrate, memory loading, etc), it is necessary to tune these signals/parameters in order to be in accordance with the specifications and maximize the specifications margin for the signals at DRAM and memory controller side. This tuning can be done by delaying/shifting the signals (DQS and data) with respect to each other and the core clock.
5.1 Reading from DRAM
DDR (dual data rate) memories send a data strobe (DQS) signal coincident with the read data so that the read data can be reliably captured by the memory controller. The edges of this strobe are aligned with the data output by the DRAM devices. The paths for the data and the associated data strobe signals should be routed with the same length between the capture logic and the DRAM devices, allowing the rising and falling edges of the data strobe to arrive at the capture logic at the same time the data is in transition. However, the raw data strobe signal cannot be used as a clock to capture the data, since the data will not be stable when the data strobe edges are rising and falling. Instead, a delayed version of the data strobe signal must be used to capture the data. The delay added to the data strobe signals should be such that the margin to capture the read data is maximized. Because the frequency of the data strobe signal is matched to the system clock, the delay is a relative number based on the period of the system clock. On SPEAr devices, this delay is managed by dll_dqs_delay_1 and dll_dqs_delay_0 parameters (MPMC_Register_39, at offset 0x9C from base address of MPMC) respectively for upper 8 bits and lower 8 bits of the memory datapath.
5.2 Writing to DRAM
DDR memories require that the DQS data strobe arrives at the DDR within a certain window around the clock. This value (tdqss) is specified in fractions of a clock cycle. Most DRAM devices specify this value between +/- 0.25 and 0.2 of a clock cycle. This translates to a valid window of between 0.5 and 0.4 of a clock cycle. The DRAM devices expect the data strobe signal to be shifted by the memory controller in order to allow the DRAM the maximum margin for capturing the data with the data strobe signal sent to the DRAM devices from the memory controller. The DLL maintains two delay lines for sending write data and the write data strobe. The first delay line delays the main clock so that the write data strobe transition reaches the DRAM as synchronously as possible with the clock edge under typical operating conditions. The second delay line adjusts the clock that is used to output the write data. This clock should be adjusted to maximize the setup and hold requirements around the write strobe. Both the DQS (for write) and Data (DQ) signals from the SPEAr device are controlled by the programmable parameters dqs_out_shift (MPMC_Register_40, at offset 0xA0 from base address of MPMC) and wr_dqs_shift (MPMC_Register 41, at offset 0xA4 from base address of MPMC). These two parameters for writes are valid for both bytes that constitute the
DDR controller delay lines tuning AN3100 14/24 Doc ID 16606 Rev 2 memory data path, in contrast to the read parameters dll_dqs_delay_x. These parameters allow these two clocks to be delayed by a fixed percentage of the core clock. In short, for writing to DDR you need to: 1. Align DQS signal with respect to the clock 2. Adjust DQ signals to the specs (1/4 cycle) relative to DQS. This can be done by programming the following registers:
- MPMC_CTL_40: to align DQS (write) to the clock signal
- MPMC_CTL_41: to adjust DQ signal to within 1/4 clock cycle of DQS. There is only one register, mentioned previously, to center the read DQS signal in the clock signal: MPMC_CTL_39: to activate the DQS signal in the middle of the data valid signal The delay introduced by these parameters can be determined based on the following equation, Where param is one of the following parameters:
- wr_dqs_shift
- dqs_out_shift
- dll_dqs_delay_X The value “delays in one cycle” is automatically generated by the memory controller DCC (delay compensation circuit) master delay line that calculates the number of delay elements that constitute a complete cycle in an adaptive way (according to PVT variations).
5.2.1 Example using these parameters
At DDR frequency of 333 MHz (666 MT/sec): One cycle time = 3 ns If Write DQS generated by the memory controller is in phase with the clock on the controller side and also at the DRAM end (effects of PCB tracks, substrate track length are compensated), then DQS can be aligned to the clock by two values of wr_dqs_shift parameter which are 0 or 0x7F . Equation 1 Delay = 3 ns x 0 = 0 or = 3 ns x 128/128 = 3 ns In both cases either the delay between write DQS and clock is zero or 3 ns (one clock cycle), so the two signals which are Data strobe/DQS and clock would be aligned. But in actual scenarios, the write DQS generated by the memory controller is slightly shifted. At higher frequencies like 333 MHz, clock cycle time is very small (3 ns) and a deviation of more than ¼ clock cycle time is not accepted. So we need to change this parameter value from its ideal value of 0x0 or 0x7F . Just for reference, the value for this parameter in the SPEAr300 evaluation board is 0x7F .
AN3100 DDR controller delay lines tuning Doc ID 16606 Rev 2 15/24 Similarly to make the DQ signal within ¼ clock time of DQS, according to Equation 1 the value 0x5F would be in an ideal scenario. Off course we need to tune this parameter because of the same above mentioned reason. Just for reference, the value for this parameter for in the SPEAr300 evaluation board is 0x5F . During reading from DRAM, memories send the data strobe (DQS) signal coincident with the read data. In ideal scenarios, to center DQS signal in the data valid window, we need to delay the DQS signal by ¼ of clock cycle as data is read on both rising and falling edges. So the value of the dll_dqs_delay_X parameter should be 0x1F according to Equation 1. In practice, you need to tune this value as per the board and device. The value used in the SPEAr300 evaluation board for this parameter is 0x1d for both dll_dqs_delay_X parameters.
PCB layout recommendations AN3100 16/24 Doc ID 16606 Rev 2
6 PCB layout recommendations
Layout and PCB parameters play a very important role for DDR, especially when the system runs at high frequencies like 333 MHz (667 MT/sec). AN2674 PCB layout guidelines for SPEAr3xx provides recommendations for DDR signal routing, track lengths and impedances. Please strictly follow these guidelines. This application note also provides the required data to balance the length of the data/control tracks going to the DDR chips. PCB simulation is also strongly suggested to make sure that PCB does not introduce signal reflection and to determine violations in the communication between MPMC and DDR. The IBIS model of the DDR interface of SPEAr3xx is available to run these simulations. Refer to AN3099 IBIS models for signal integrity simulation of SPEAr3xx applications. The schematics and layouts of the SPEAr3xx evaluation boards are available and can be used as reference design and starting point for your application design.
7 Pad descriptions and configurations
configure the various pads that interface the DDR memory. Table 4. SPEAr3xx memory controller pads
- Data cell (BDPROGDDRSCARUDQP_VDDE_1V8_2V5_SF_TF_2ROWS , BDPROGDDRSCARUDQP_GNDE_1V8_2V5_SF_TF_2ROWS )
- Clock cell (BDCLKRESDDRSCARUDQP_INPUT_DQS_1V8_2V5_SF_TF_2ROWS ) The figures below show the data cell and the clock cell architecture.
Figure 4. Data cell architecture
Figure 5. Clock cell SPEAr3xx user manual for further details.
7.1 DDR_PAD register configuration
DDR2_EN to configure the pads in hardware or software mode.
- Bits [18:15] = 0000: hardware configuration mode. In this mode, the input level of the DDR2_EN pin selects the configuration (DDR2_EN =1 = configuration for DDR2) and DDR_PAD register [0] is don’t care.
- Bits [18:15] = 0110: software configuration mode. In this mode, the value of DDR_PAD register [0] selects the configuration] (1 = configuration for DDR2) and pin DDR2_EN is don’t care. All other combinations are not allowed. Bit [14] is a status bit and reflects the status of the pin DDR2_EN. All these settings establish the value for the pin DDR2V5 of pad data and clock cells and configure them to operate properly on the basis of the memory type attached. Bit [13] establishes the nature of the common reference for all SSTL pads. 0 = internal reference and 1 = external reference. It is recommended to use an external reference to improve the stability. Bit [12] Controls GATE_OPEN_MODE. It should be set to 1 in normal operating conditions. Bit [11] is reserved. Bit [10] Controls the pad ENZI signal (input buffer enable). It should be 0 in normal operating conditions. Bits [9: 8] respectively control the pull-up and the pull-down of pins PDNCLK2V5 and PUPCLK2V5 of the pad clock cells for the DDR_MEM_DQS[1:0] pads.See Table 5 for the settings. Bits [7: 6] respectively control the pull-up and the pull-down of pins PDNCLK2V5 and PDNCLKB2V5 of the pad clock cell for the DDR_MEM_CLKP/N pads.See Table 5 for the settings. Bits [5: 4] control the pull-up and the pull-down of the pins PU2V5 and PDN2V5 of all pad data cells.See Table 5 for the settings. Bits [3: 1] respectively control the pins ZPROGOUTA2V5, PROGA2V5, PROGB2V5 for all pad data and clock cells.
Table 5. Pull-up and pull down settings
AN3100 Pad descriptions and configurations Doc ID 16606 Rev 2 21/24 The following notes apply to these three bits:
- They are independent, but not completly uncorrelated. All 8 combinations are valid, but are partially overlapping.
- They are board dependent, and must be determined during the tuning phase for every PCB type.
- They depend on the PCB characteristic impedance and the frequency of the DDR signals. Bit [3], the drive mode bit, changes the output impedance of the pad and must be set in accordance with the PCB load. It must be set to 0 (strong mode) when the characteristic impedance of the PCB is up to 50 Ohm. It must be set to 1 (weak mode) when the characteristic impedance of the PCB is from 50 to 70 Ohm. Bits [2] and [1 ), prog_a and prog_b, set the “way” the internal transistors of the pad are loaded as well as the resulting effect on the slope of the signal. These 2 bits define 4 increments of increasing capability: from 00 (slower slope) to 11 (higher slope). All intermediate values are valid. When you deal with high frequency signals, you should configure higher slopes to increase the data valid window, keeping in mind that the higher the slope, the more the signal reflection.
Table 6. Acronyms used in this document
Revision history
Table 7. Document revision history 08-Jan-2010 1 Initial release. 12-Mar-2012 2 Modified in troduction referring to SPEAr3xx family.