AN3029

AN3029 STMICROELECTRONICS | Alldatasheet

Document overview

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• PDF pages: 42

Technical content

Datasheet sections

• 1 Hardware requirements summary
• 2 Power supply
• 2.1 Power supply overview
• 2.2 Main operating voltages
• 2.3 Power-on/power-down reset (POR/PDR)
• 3 Analog-to-digital converter (ADC)
• 3.1 Analog power
• 3.2 Analog input
• 4 Clock management
• 4.1 Clock management overview
• 4.2 Internal clocks
• 4.3 External clock
• 4.3.1 HSE clock
• 4.3.2 LSE clock
• 5 Reset control
• 5.1 Reset management overview
• 5.1.1 Output characteristics
• 5.1.2 Input characteristics
• 5.2 Hardware reset implementation
• 6 Recommendations
• 6.1 Printed circuit board
• 6.2 Component position
• 6.3 Ground and power supply (V
• 6.4 Decoupling
• 6.5 Other signals
• 6.6 Unused I/Os and features
• 6.7 User options
• 6.8 Bootloader

application around an STM8L or STM8AL 8-bit microcontroller device. list of relevant documentation and online support resources. Table 1. Applicable products

Hardware requirements summary AN3029

1 Hardware requirements summary

To build an application around an STM8L or STM8AL device, the application board should provide the following features:

• Power supply (mandatory)
• Clock management (optional)
• Reset management (optional)
• Debugging tool support: Single wire interface module (SWIM) connector (optional)

2 Power supply

2.1 Power supply overview

The STM8L or STM8AL can be supplied through a 1.65 V to 3.6 V external source (1.8 V to 3.6 V for STM8L05xxx). For medium density STM8L15xxx, medium density STM8AL31xx/STM8AL3Lxx, and high density STM8L15xxx/STM8L162xx with BOR, the power supply must be above 1.8 V at power-on and can go down to 1.65 V at power-down. An on-chip power management system provides the constant digital supply to the core logic, both in normal and low power modes. This guarantees that the logic consumes a constant current over the voltage range. It is also capable of detecting voltage drops and generate reset to avoid heratic behavior. The STM8L and STM8AL devices provide:

• Depending on packages, one pair of pads (VDD/VSS), or several pairs of pads (VDDx/VSSx) from 1.65 V or 1.8 V to 3.6 V. All VDDx and VSSx must be at the same potential respectively. The VDDx pins must be connected to VDD with external decoupling capacitors: one 100 nF Ceramic capacitor for each VDDx pin and one single 1 µF Tantalum or Ceramic capacitor. The STM8L15xxx, STM8AL31xx, and STM8L162xx devices also provide in some packages:
• One pair of pads, VDDA/VSSA, dedicated to analog functions. VDDA and VSSA must be at the same potential respectively as VDD and VSS. Refer to Section 3: Analog-to-digital converter (ADC) for more details. The VDDA pin must be connected to two external decoupling capacitors (one 100 nF Ceramic capacitor and one single 1 µF Tantalum or Ceramic capacitor). Additional precautions can be taken to filter analog noise: V DDA can be connected to VDD through a ferrite bead. STM8L152xx, STM8AL3Lxx and STM8L162xx devices manage the supply voltage needed by the LCD in three different ways (see Figure 1): 1. If the LCD feature is not used, connect the VLCD pin to V DD. 2. Apply to VLCD the voltage to be applied to the LCD. 3. Leave the STM8L152xx/STM8L162xx/STM8AL3Lxx to provide the correct voltage, via its programmable LCD booster, by connecting the VLCD pin to a 1µF capacitor.

Figure 1. Power supply

1. Optional: if a separate, external reference voltage is connected on V REF+, the two capacitors (100 nF and 1

µF) must be connected. VREF+ is either connected to VDDA or VREF.

1. N is the number of V DD and VSS inputs.

Note: The capacitors must be connected as close as possible to the device supplies. ground must be connected as close as possible to VSS.

2.2 Main operating voltages

STM8AL devices have an internal regulator with a nominal target output of 1.8 V.

2.3 Power-on/power-down reset (POR/PDR)

down reset circuit. The monitoring voltage begins at 0.7 V. respected, as the internal reset provided for supply stabilization is maintained for ~1 ms. reset release is defined in the electrical characteristics section of the product datasheets. A hysteresis is implemented (POR > PDR) to ensure clean detection of voltage rise and fall. threshold (isolated and repetitive events). Correct device reset during power-on sequence is guaranteed when tVDD[max] is respected. (PVD) for an earlier detection of voltage drop. but exact values depend on the application needs. Figure 2. Typical layout of VDD/VSS pair

3 Analog-to-digital converter (ADC)

This section does not apply to STM8L101xx devices.

3.1 Analog power

chosen according to the frequencies to be filtered.

• The VREF+ pin can be connected to the VDDA external power supply. If a separate, external reference voltage is applied on VREF+, a 100 nF and a 1 µF capacitor must be connected on this pin. To compensate for peak consumption on VREF, the 1 µF capacitor may be increased to 10 µF when the sampling speed is low. In all cases, VREF+ must be kept between 2.4 V and VDDA. If VDDA is below 2.4, VREF+ must be equal to VDDA. This input is internally bonded to VDDA in the devices that have no internal VREF+ pin.
• VREF- (input, analog reference negative): The lower/negative reference voltage is internally bonded to VSSA.

3.2 Analog input

multiplexed with an I/O, which are converted by the ADC one at a time. at maximum speed (1 MHz) if RAIN is less than 0.5 kΩ. Figure 3. Analog input interface Please refer to the applicable datasheets and reference manuals for more details.

4 Clock management

The STM8L101xx devices have no external clock, so no precautionary measures are needed.

4.1 Clock management overview

STM8L05xxx, STM8L15xxx, STM8L162xx, STM8AL31xx and STM8AL3Lxx devices offer a flexible way of selecting the core and peripheral clocks (ADC, memory, and digital peripherals). The devices have internal and external clock source inputs, both of which have a high speed and a low speed version. Any of those four clocks can be use for the CPU and most of the peripherals through a programmable prescaler. An I/O can be programmed as output clock (CCO) to reflect one of the four clocks (with or without prescaling). The signal which leaves the I/O represents an output clock (CCO) divided by a division factor.

4.2 Internal clocks

STM8L and STM8AL devices have two kinds of internal clock: A high speed internal clock (HSI) running at 16 MHz and a low speed internal clock (LSI) running at 38 kHz. After reset, the CPU starts with the internal RC (HSI clock signal) divided by 8, i.e. 2 MHz.

4.3 External clock

STM8L05xx, STM8L15xxx, STM8L162xx, STM8AL31xx, and STM8AL3Lxx devices have two kinds of external clock: A high speed external clock (HSE) running at up to 16 MHz and a low speed external clock (LSE) running at 32.768 kHz.

4.3.1 HSE clock

STM8L05xx, STM8L15xxx, STM8L162xx, STM8AL31xx, and STM8AL3Lxx devices can connect to an external crystal or an external oscillator. Note: When no external clock is used, OSCIN and OSCOUT can be used as general purpose I/Os. Figure 4 describes the external clock connections. External clock

• Frequency: 0 kHz … 16 MHz
• Input hysteresis: 100 mV Caution: Without prescaler, a duty cycle of 45/55 % maximum must be respected at high speed

• Frequency range: 1 to 16 MHz
• Stabilization time: Programmable from 1 to 4096 cycles
• Oscillation mode: Preferred fundamental
• Output duty cycle: Max 55/45%
• I/Os: Standard I/O pins multiplexed with OSCIN and OSCOUT
• Cload: 10 to 20 pF
• Drive level maximum: at least 100 µW The values of the load capacitors CL1 and CL2 are heavily dependent on the crystal type and frequency. Refer to the datasheet of the crystal manufacturer to select the capacitances. For best oscillation stability, CL1 and CL2 normally have the same value. Typical values are in the range from below 20 pF up to 40 pF (cload: 10 to 20 pF). The parasitic capacitance of the board layout also needs to be considered and typically adds a few pF to the component values (refer to AN2867). A clock security system prevents any CPU fatal error from a HSE failure, as it safely switches to HSI.

Figure 4. HSE clock sources

1. The value of R EXT depends on the crystal characteristics. A 0 Ω resistor works well with most oscillators

REXT value, refer to AN2867 (Oscillator design guide for ST microcontrollers).

PCB area around the oscillation circuit using suitable shielding.

4.3.2 LSE clock

• LSE external crystal/ceramic resonator (see Figure 6)
• LSE user external clock (see Figure 6) External source (LSE bypass) In this mode, an external clock source must be provided. It must have a frequency of 32.768 kHz. The external clock signal (square, sine or triangle) with a duty cycle of about 50% has to drive the OSC32_IN pin while the OSC32_OUT pin must be left high impedance (see Figure 5 and Figure 6).

Figure 5. External clock

1. OSC32_IN and OSC32_OUT pins can be used also as GPIO but, it is recommended not to use them as

both RTC and GPIO pins in the same application. peripheral (RTC) for clock/calendar or other timing functions. capacitance values must be adjusted according to the selected oscillator.

Figure 6. Crystal/ceramic resonators

1. To avoid exceeding the maximum value of C L1 and CL2 (15 pF), it is strongly recommended to use a

AN2867 (Oscillator design guide for ST microcontrollers).

1. OSC32_IN and OSC32_OUT pins can be used also as GPIO, but it is recommended not to use them as

both RTC and GPIO pins in the same application.

1. The value of R EXT depends on the crystal characteristics. A 0 Ω resistor works with most oscillators. A

5 Reset control

5.1 Reset management overview

be used as a general purpose I/O.

• External reset through the NRST pin
• Power-on reset (POR) and brown-out reset (BOR): During power-on, the POR keeps the device under reset until the supply voltage (VDD and VDDx) reach the voltage level at which level the BOR starts to function. STM8L101xx devices have only a POR.
• Independent watchdog reset (IWDG)
• Window watchdog reset (WWDG), featuring also software reset: only for STM8L05xx, STM8L15xxx, STM8L162xx, STM8AL31xx, and STM8AL3Lxx.
• SWIM reset: An external device connected to the SWIM interface can request the SWIM block to generate a microcontroller reset.
• Illegal opcode reset: If a code to be executed does not correspond to any opcode or prebyte value, a reset is generated. Figure 7 shows a simplified functional I/O reset schematic.

Figure 7. Reset management

5.1.1 Output characteristics

• A valid pulse on the pin is guaranteed with a ≥ 20 ns pulse duration on the internal output buffer.
• After a valid pulse is recognized, a pulse on the pin of at least 20 µs is guaranteed starting from the falling edge of A.

Figure 8. Output characteristics

5.1.2 Input characteristics

• All pulses with a duration less than 50 ns are filtered
• All train/burst spikes with a ratio of 1/10 must be filtered. This means that a negative spike of up to 50 ns is always filtered, when a 5 ns interval between spikes occurs (ratio 1/10).
• All pulses with duration more than 300 ns are recognized as valid pulses

Figure 9. Input characteristics

5.2 Hardware reset implementation

The STM8L and STM8AL do not require an external reset circuit to power-up correctly. Only a pull-down capacitor is recommended (see Figure 7). However, charging/discharging the pull-down capacitor through an internal resistor has a negative influence on the device power consumption. Therefore, the recommended capacitor value of 100 nF can be reduced down to 10 nF to limit such power consumption. The STM8L101xx reset state is released 1 ms after the POR value (1.35 V to 1.65 V) is reached. At this time, V DD should be in the 1.65 V to 3.6 V range. For medium density devices and medium+ and high density devices operating from 1.8 V at power-on: the reset state is released 1 ms after the BOR minimum value (~1.75 V) is reached.

6 Recommendations

6.1 Printed circuit board

For technical reasons, it is best to use a multi-layer PCB with a separate layer dedicated to the VSS and another layer to the VDD supply. This results in a good decoupling, as well as a good shielding effect. For many applications, economical requirements prohibit the use of this type of board. In this case, the most important feature is to ensure a good structure for the VSS and power supply.

6.2 Component position

A preliminary layout of the PCB must separate the different circuits according to their electromagnetic interference (EMI) contribution. This reduces cross-coupling on the PCB, for instance, noisy, high-current circuits, low voltage circuits, and digital components.

6.3 Ground and power supply (V SS, VDD)

The VSS should be distributed individually to every block (noisy, low level sensitive, and digital) with a single point for gathering all ground returns. Loops must be avoided or have a minimum surface. The power supply should be implemented close to the ground line to minimize the surface of the supply loop. This is due to the fact that the supply loop acts as an antenna, and is therefore the main emitter and receiver of EMI. All component-free surfaces of the PCB must be filled with additional grounding to create a kind of shield (especially when using single-layer PCBs).

6.4 Decoupling

The standard decoupler for the external power is a 1 µF pool capacitor. Supplementary 100 nF capacitors must be placed as close as possible to the VSS/VDD pins of the microcontroller to reduce the area of the current loop. As a general rule, decoupling all sensitive or noisy signals improves electromagnetic compatibility (EMC) performances. There are two types of decouplers:

• Capacitors close to components. Inductive characteristics, which apply to all capacitors beyond a certain frequency, must be taken into account. If possible, parallel capacitors
• Inductors. Although often ignored, ferrite beads, for example, are excellent inductors due to their good dissipation of EMI energy and there is no loss of DC voltage (which is not the case when simple resistors are used).

6.5 Other signals

When designing an application, the following areas should be closely studied to improve EMC performances:

• Noisy signals (clock)
• Sensitive signals (high impedance)
• Signals for which a temporary disturbance permanently affects operation of the application, for example, interrupts and handshaking strobe signals (but not LED commands). A surrounding VSS trace for such signals increases EMC performances, as does a shorter length or absence of noisy and sensitive traces (crosstalk effect). For digital signals, the best possible electrical margin must be reached for the two logical states. Slow Schmitt triggers are recommended for eliminating parasitic states.

6.6 Unused I/Os and features

Microcontrollers are designed for a variety of applications, where often a particular application does not use 100 % of the microcontroller resources. To avoid unnecessary power consumption (especially important for battery powered applications) and also to improve EMC performance, unused clocks, counters, or I/Os, should not be left free, I/Os should be forced externally (pull-up or pull-down to the unused I/O pins), and unused functions should be ‘frozen’ or disabled. Alternatively, unused I/Os can be programmed as push-pull ‘low’ to keep them at a defined level without using external components. However in this case, the I/O is not driven during the power up phase, until the I/O is configured. This can add a little extra power consumption, and may be undesirable in very power sensitive applications.

6.7 User options

STM8L and STM8AL devices have user option features that can be used for remapping or enabling/disabling an automatic reset or low speed watchdog. For more details, please refer to the product datasheets.

6.8 Bootloader

STM8L05xx, STM8L15xxx, STM8L162xx, STM8AL31xx, and STM8AL3Lxx devices have a bootloader embedded in a ROM memory. Through this firmware the device memory can be re-programmed via:

• USART communication interface for medium density devices
• USART1, USART2, USART3, SPI1, and SPI2 communication interfaces for medium+ and high density devices.

7 Reference design

7.1 Component references

Table 2. Component list

1 Microcontroller STM8L, STM8AL 1

3 Capacitor 1 µF n Decoupling capacitor

4 Capacitor 100 nF n Ceramic capacitor (decoupling capacitor)

5 Capacitor 10 µF 1 Ceramic capacitor (decoupling capacitor)

6 Crystal 1 to 16 MHz 1 -

7 Capacitor 20 to 40 pF 2 Used for crystal

8 Capacitor 5 to 20 pF 2 Used for crystal

9 SWIM connector 4 pins 1 -

7.2 Schematics

Figure 10. Reference design

1. If these components are removed, they hav e to be replaced by a short connection.
2. Optional: if a separate, external reference voltage is connected on VREF+, the two capacitors (100 nF and 1 µF) must be

connected. VREF+ is either connected to VDDA or VREF.

1. One 100 nF Ceramic capacitor for each VDDx pin and one single 1 µF Tantalum or Ceramic capacitor.

0 Ohm

8 STM8 development tools

• STVD for integrated development environment
• STM8 C compiler (from Cosmic, Raisonance, or IAR)
• ST toolset and STM8 firmware library from STMicroelectronics STM8L101xx standard peripheral library, STM8L05x/STM8L15x/STM8L16x/STM8AL31x/STM8AL3Lx standard peripheral library
• STM8 evaluation board from STMicroelectronics (STM8L101-EVAL for STM8L101xx, STM8L1526-EVAL for medium density STM8L15xxx and STM8AL31xx/STM8AL3Lxx, and STM8L1528-EVAL for high density STM8L15xxx/STM8L162xx)
• If you use STM8L101-EVAL, you also need the HW SWIM debug interface "Rlink" from Raisonance and ST-Link or STice-SWIM. The debug interface ST-LINK is included in STM8L1526-EVAL and STM8L1528-EVAL.
• STM8L-DISCOVERY

8.1 Single wire interface module (SWIM)

8.1.1 SWIM overview

powerful and close in performance to a full-featured emulator. and debug module user manual (UM0470) for more SWIM protocol details. Figure 11. Debug system block diagram

100 KHz Osc

8.1.2 SWIM connector pins

The SWIM connector pins consist of four pins as described in Table 3.

8.1.3 Hardware connection

Figure 12. Hardware connection device, as this minimizes any possible signal degradation caused by long PCB tracks. Table 3. SWIM connector pins

8.2 STice emulator

8.2.1 STice overview

interface, and to the application board in place of the target microcontroller.

• Emulation mode
• In-circuit mode It can also be used instead of RLink for SWIM connection.

Figure 13. Connection description

• Emulator box
• Cables for USB, power supply, trigger, and analyzer input Connection flex
• 60-pin or 120-pin cable for connection to the application board Connection adapter
• Links the connection flex to the footprint of the STM8L/STM8AL microcontroller Adapter socket
• Package-specific socket for connection adapter and STM8L/STM8AL microcontroller

8.2.2 STice in emulation configuration

application board in place of the target microcontroller being used.

• Connection flex: Flexible cable (60-pin or 120-pin depending on the target microcontroller) that relays signals from the STice to the application board.
• Connection adapter: Links the connection flex to the footprint of the target microcontroller on the users application board.
• Adapter socket: Socket that solders to the application board in place of the microcontroller and receives the connection adapter. The above accessories are not included with the STice system. To determine exactly what is required for any supported microcontroller, refer to the online product selector on www.st.com.

Figure 14. STice in emulation configuration

8.2.3 In-circuit pr ogramming and debugging

Figure 15. In-circuit programming and debugging

8.3 RLink and STLink

debugging and programming. See Section 10.3.3: Connecting the hardware on page 34.

9 STM8 software toolchain

• Integrated development environment
• Compiler
• Firmware library (optional, used to ease the startup)

Figure 16. STM8 software toolchain

AN3029 STM8 software toolchain

9.1 Integrated deve lopment environment

The integrated development environment ST Visual Develop (STVD) provides an easy-to- use, efficient environment for start-to-finish control of application development, from building and debugging the application code to programming the microcontroller. STVD is delivered as part of the free ST toolset, which also includes the ST Visual Programmer (STVP) programming interface and ST Assembler-Linker. To build applications, STVD provides seamless integration of C and assembly tool chains for ST including the Cosmic and Raisonance C compilers and ST Assembler-Linker. When debugging, STVD provides an integrated simulator (software) and supports a complete range of hardware tools including the low-cost RLink in-circuit debugger/programmer, the high-end STice emulator, and the low-cost ST-LINK tool. To program applications to an STM8L/STM8AL, the STVD also provides an interface for reading from the microcontroller memories, writing to them and verifying them. This interface is based on the ST Visual Programmer (STVP), and supports all the target devices and programming tools supported by STVP . The free ST toolset for STM8 is available from STMicroelectronics homepage (see www.st.com).

9.2 Compiler

STM8L/STM8AL devices can be programmed by a free assembler toolchain which is included in the ST toolset. As the core is designed for optimized high-level-language support, use of a C compiler is recommended! C compilers for STM8 are offered by the third party companies Cosmic, Raisonance, and IAR. A free version of the C compiler with up to 32 Kbytes of generated code is available at:

9.3 Firmware library

The STM8 firmware library is a complete set of source code examples for each STM8 peripheral. It is written in strict ANSI-C and it is fully MISRA C 2004 compliant. All examples can be used with four workspace and project definition files, one for STVD and Cosmic C compiler, one for STVD and raisonance Compiler, one for Raisonance integrated debugging environment and compiler (RIDE7 IDE), and one for IAR embedded workbench for STM8 (EWSTM8). This enables the user to load and compile them easily into their preferred development environment. The examples run on the STMicroelectronics STM8L evaluation board and can be tailored easily to other types of hardware. For additional information and download of the STM8L/STM8AL firmware library connect to www.st.com/mcu.

Setting up the STM8 development environment AN3029

10 Setting up the STM8 development environment

10.1 Installing the tools

All software tools are delivered with a setup wizard which guides the user through the installation process. It is recommended to install the tools in the following order: 1. C compiler 2. ST toolset 3. STM8 firmware library ST-LINK does not need any dedicated software installation in the STM8 development environment because the necessary drivers are delivered with the ST toolset. The R-link drivers must be launched separately as follows: Start/Programs/STtoolset/Setup/Install Rlink driver.

10.2 Using the tools

development environment can be launched. an existing project from the STM8 firmware library. template to configure all the compiler options. Enter your own code after main(). STVD\\Cosmic, STVD\\Raisonance, RIDE, or EWSTM8. Figure 17. STVD open example workspace

10.2.1 Project editing

All project source files are visible and can be edited (see Figure 18). Figure 18. STVD MCU edit mode

10.2.2 Online help

to help the user understand the structure of the STM8 firmware library. Figure 19. STM8 firmware library online help manual

10.3 Running the de monstration software

• Go to www.st.com/mcu and search for STM8L/STM8AL products
• Choose STM8L1x-EVAL, STM8L1526-EVAL, or STM8L1528-EVAL firmware
• Open the desired project workspace within the chosen demonstration firmware package. To run the demonstration software on the STM8 evaluation board, the project has to be compiled and the correct HW tool must be selected before the debug session can be started.

10.3.1 Compiling the project

The project can be compiled using the ‘Build’ function in the ‘Build’ menu (see Figure 20). Figure 20. STVD: Building the project

10.3.2 Selecting the correct debug instrument

the on-board debug module of the STM8. Instrument Settings’ dialog (see Figure 21). Figure 21. STVD: Selecting the debug instrument

10.3.3 Connecting the hardware

please read the evaluation board user manuals to select power and debug support jumpers. EVAL, evaluation board is powered by an external 5 V supply (see Figure 22). Figure 22. Connecting the debug instrument to the STM8L101-EVAL evaluation board

Figure 23. Connecting the debug instrument to the STM8L152x-EVAL evaluation

10.3.4 Starting the debug session

Debug mode can be entered by the command ‘Debug Start Debugging’ (see Figure 24). Figure 24. STVD: Starting the debug session

10.3.5 Running the software

‘Debug Run’ (see Figure 25). Figure 25. STVD: Run the software

Figure 26. STM8 evaluation board

10.3.6 Follow up

from the initial debug session described above. memory), are delivered in the STM8L1x firmware library.

AN3029 Documentation and online support

11 Documentation and online support

Documentation resources related to tool usage includes: Application

• STM8L/STM8AL datasheets
• How to program STM8L Flash program memory and data EEPROM (PM0054)
• STM8 CPU programming manual (PM0044)
• STM8L05xx, STM8L15xx, STM8L162x, STM8AL31xx and STM8AL3Lxx microcontroller family (RM0031)
• STM8L101xx microcontroller family (RM0013) Tools
• STM8L/STM8AL firmware library and release note (detailed descriptions of the library are included as help files)
• STice advanced emulation system for ST microcontrollers data briefing
• STice user manual
• Cosmic, Raisonance, or IAR C compiler user manual
• STM8L101-EVAL, STM8L1526-EVAL, or STM8L1528-EVAL evaluation board user manual.
• STM8L1x-EVAL, STM8L1526-EVAL, or STM8L1528-EVAL firmware
• ST Visual Develop tutorial (included as help files in the ST-toolchain)
• ST Visual Develop (STVD) user manual
• STM8 SWIM communication protocol and debug module user manual (UM0470) The microcontroller discussion forum on www.st.com can be used by developers to exchange ideas. It is the best place to find different application ideas. In addition, the website has a knowledge base of FAQs for microcontrollers, which provide answers to many queries and solutions to many problems.

Table 4. Document revision history density and high density devices. Replaced VDDIO and VSSIO by VDDx and VSSx respectively. Replaced 48-pin package by “some packages”. Section 2.1: Power supply overview: updated text. Figure 1: added note 2; removed the + sign on the VLCD cappa. Crystal/ceramic resonator: added reference to AN2867. Section 3.2: Analog input: updated text. Section 4.3.2: LSE clock: re-arranged section. Figure 7: removed EMS reset; added external reset circuit. number 2 (battery); added ID number 5 (ceramic capacitor). Figure 10: added external reset circuit and note 1. and project definition files. Section 10.2: Using the tools: added EWSTM8. Figure 1: updated figure content and footnotes. Section 2.1: Power supply overview: updated bullet points. Figure 10: updated figure content and footnotes. cost ST-Link tool in the list of hardware tools supported by STVD.

Document updated to include the STM8AL products. Added Table 1: Applicable products. Added note (1) to Table 2: Component list. Updated references in Section 8: STM8 development tools. Table 4. Document revision history (continued)