AN3027

AN3027 STMICROELECTRONICS | Alldatasheet

Document overview

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Technical content

Datasheet sections

• 1 Introduction to power fa ctor correction
• 2 TM PFC operation (boost topolog y)
• 3 Designing a TM PFC
• 3.1 Input specifications
• 3.2 Operating conditions
• 3.3 Power section design
• 3.3.1 Bridge rectifier
• 3.3.2 Input capacitor
• 3.3.3 Output capacitor
• 3.3.4 Boost inductor
• 3.3.5 Power MOSFET selection and dissipation
• 3.3.6 Boost diode selection
• 3.4 L6563S biasing circuitry
• 4 L6563H: high-voltage startup transition-m ode PFC
• 5 Design example using the L6563S-TM PFC Excel spreadsheet
• 6 EVL6563S-100W and EVL6563H-100W dem onstration boards
• 7 References
• 8 Revision history

applications that may require a low-cost power factor correction. as the L6563S with the addition of a high-voltage startup power source. master stage without an auxiliary SMPS. Figure 1. Typical system block diagram

Introduction to power factor correction AN3027 4/41 Doc ID 16134 Rev 4

1 Introduction to power factor correction

The front-end stage of conventional offline converters, typically consisting of a full-wave rectifier bridge with a capacitor filter, has an unregulated DC bus from the AC mains. The filter capacitor must be large enough to have a relatively low ripple superimposed on the DC level. This means that the instantaneous line voltage is below the voltage on the capacitor most of the time, thus the rectifiers conduct only for a small portion of each line half-cycle. The current drawn from the mains is a series of narrow pulses whose amplitude is 5-10 times higher than the resulting DC value. Many drawbacks result, such as a much higher peak and RMS current down from the line, distortion of the AC line voltage, overcurrents in the neutral line of the three-phase systems and, consequently, a poor utilization of the power system's energy capability. This can be measured in terms of either total harmonic distortion (THD), as norms provide for, or power factor (PF), intended as the ratio between the real power (the one transferred to the output) and the apparent power (RMS line voltage multiplied by the RMS line current) drawn from the mains, which is more immediate. A traditional input stage with capacitive filter has a low PF (0.5-0.7) and a high THD (>100%). By using switching techniques, a power factor corrector (PFC) preregulator, located between the rectifier bridge and the filter capacitor, allows drawing a quasi-sinusoidal current from the mains, in phase with the line voltage. The PF becomes very close to 1 (more than 0.99 is possible) and the previously mentioned drawbacks are eliminated. Theoretically, any switching topology can be used to achieve a high PF but, in practice, the boost topology has become the most popular thanks to the advantages it offers:

• Primarily because the circuit requires the fewest external parts (low-cost solution)
• The boost inductor located between the bridge and the switch causes the input di/dt to be low, thus minimizing the noise generated at the input and, therefore, the requirements on the input EMI filter
• The switch is source-grounded, therefore easy to drive However, boost topology requires the DC output voltage to be higher than the maximum expected line peak voltage (400 VDC is a typical value for 230 V or wide-range mains applications). In addition, there is no insulation between the input and output, thus any line voltage surge is passed on to the output. Two methods of controlling a PFC pre-regulator are currently widely used: the fixed-frequency, average current mode PWM (FF PWM) and the transition mode (TM) PWM (fixed on-time, variable frequency). The first method needs complex control that requires a sophisticated controller IC (ST's L4981, with the variant of the frequency modulation offered by the L4981) and a considerable component count. The second one requires a simpler control (implemented by ST's L6563S), much fewer external parts and is therefore much more economical. With the first method the boost inductor works in continuous conduction mode, while TM makes the inductor work on the boundary between continuous and discontinuous mode, by definition. For a given throughput power, TM operation involves higher peak currents. This, also consistent with cost considerations, implies its use in a lower power range (typically up to 250 W), while the former is recommended for higher power levels. To conclude, FF PWM is not the only alternative when CCM operation is desired. FF PWM modulates both switch-on and switch-off times (their sum is constant by definition), and a given converter operates in either CCM or DCM depending on the input voltage and the load conditions. Exactly the same result can be achieved if the on-time only is modulated and the off-time is kept constant, in which case, however, the switching frequency is no longer fixed. This is referred to as “fixed-off-time” (FOT) control. Peak-current-mode control can still be used. In this application note transition mode is studied in depth.

2 TM PFC operation (boost topology)

regulated DC output voltage (Vo). voltage. To do this, the L6563S uses the transition mode technique. Figure 2. Boost converter circuit value over a given half-cycle. mains peak voltage and the value of the error signal. MOSFET on again and another conversion cycle starts. total drain capacitance energy that is dissipated inside the MOSFET.

Figure 3. Inductor current waveform and MOSFET timing and discontinuous current mode and that is why this system is called a transition mode PFC. PFC to lower power range applications.

3 Designing a TM PFC

The following section describes a design flowchart of a 100 W transition mode PFC, using the L6563S. The same design procedure and formulas proposed can also be applied for dimensioning a similar 100 W transition mode PFC, using the L6563H.

3.1 Input specifications

This section details the specifications of the operating conditions of the circuit that are needed for the calculations given in Section 3.2. In this example an L6563S, wide input range mains PFC circuit has been considered. Some design criteria are also given. Because the PFC is a boost topology, the regulated output voltage depends mainly on the maximum AC input voltage. In fact, for correct operation the output voltage must be always higher than the input and thus, because V in max is 265·1.414 = 374.7 Vpk, the output has been set at 400 Vdc as typical value. If the input voltage is higher, as is typical in ballast applications, the output voltage must be set higher accordingly. As a rule of thumb, the output voltage must be set 6/7% higher than the maximum input voltage peak. The target efficiency and PF are set here at minimum input voltage and maximum load. They are used for the calculations of the operating conditions of the PFC in Section 3.2. Of course at high input voltage, the efficiency is higher. Because of the narrow loop voltage bandwidth, the PFC output can face overvoltages at startup or in the case of load transients. To prevent excessive output voltage that can overstress the output components and the load, in the L6563S a pin of the device (PFC_OK, pin #7) has been dedicated to monitor the output voltage with a separate resistor divider, selected so that the voltage at the pin reaches 2.5 V if the output voltage exceeds a preset

• Mains voltage range (Vac rms): (1)
• Minimum mains frequency (2)
• Rated output power (W): (3)
• Regulated DC output voltage (Vdc): (4)
• Expected efficiency (%): (5)
• Expected power factor: (6) Vac90VACmin = Vac265VACmax = Hz47fMAINS = W100Pout = V400Vout = %94=η 99.0PF =

value (VOVP), usually larger than the maximum Vout that can be expected, also including worst-case load/line transients. The mains frequency generates a 2fMAINS voltage ripple on the output voltage at full load. The ripple amplitude determines the current flowing into the output capacitor and the ESR. Additionally, a request for a certain hold-up capability can be sent to the PFC if mains dips occur in which case the output capacitor also must be dimensioned, taking into account the required minimum voltage value (V out min) after the hold-up time (tHold) has elapsed. The PFC minimum switching frequency is the one of the main parameters used to dimension the boost inductor. Here we consider the switching frequency at low mains on the top of the sinusoid and at full load conditions. As a rule of thumb, it must be higher than the audio bandwidth in order to avoid audible noise and additionally it must not interfere with the L6563S minimum internal startup period, given in the datasheet. On the other hand, if the minimum frequency is set too high, the circuit shows excessive losses at a higher input voltage and probably skips switching cycles not only at light load. The typical minimum frequency range is 20 - 50 kHz for wide range operation. In order to properly select the power components of the PFC and dimension the heatsinks in case they are needed, the maximum operating ambient temperature around the PFC circuitry must be known. Please note that this is not the maximum external operating temperature of the entire system, but it is the local temperature at which the PFC components are working.

• Maximum output voltage (Vdc): (7)
• Maximum output low-frequency ripple: (8)
• Minimum output voltage after line drop (Vdc): (9)
• Hold-up capability (ms): (10)
• Minimum switching frequency (kHz): (11)
• Maximum ambient temperature (°C): (12) V430VOVP = V20Vout =∆ V300V minout = ms10tHold = kHz40f minsw = C50Tambx °=

3.2 Operating conditions

The first step is to define the main parameters of the circuit, using the specifications given in Section 3.1.

• Rated DC output current: Equation 1
• Maximum input power: Equation 2
• RMS input current: Equation 3
• Peak inductor current: Equation 4 As shown in Figure 3, the inductor current is a triangle shape at the switching frequency, and the peak of the triangle is twice its average value. The average value of the inductor current is exactly the peak of the input sine wave current, and therefore it can be easily calculated as its RMS value can be obtained from Equation 3. In order to provide a complete inductor specification for the inductor manufacturer, we must also provide the RMS and the AC current that can be calculated using Equation 5 and Equation 6.
• RMS inductor current: Equation 5
• AC inductor current: Equation 6 The current flowing in the inductor can be split in two parts, depending on the conduction instant. During the on-time, the current increases from zero up the peak value and circulates into the switch, while during the following off-time the current decreases from its peak down to zero and circulates into the diode. Therefore these two components have a current with a triangular wave, with the same peak value equal to that of the inductor. Thus, it is also possible to calculate the RMS current flowing into the switch and into the diode, needed to calculate the losses of these two elements. out out out V PI = A25.0V400 W100Iout == η= out in PP W38.10610094 W100Pin =⋅= PFVAC PI min in in ⋅= A19.199.0Vac90 W38.106Iin =⋅= inpk I22IL ⋅⋅= A38.3A19.122ILpk =⋅⋅= inrms I 2IL ⋅= A38.1A19.1 2ILrms =⋅= in rmsac IILIL −= () ( ) A69.0A19.138.1IL 22 ac =−=

• RMS switch current: Equation 7
• RMS diode current: Equation 8

3.3 Power section design

3.3.1 Bridge rectifier

The input rectifier bridge can use standard slow recovery, low-cost devices. Typically a 600 V device is selected in order to have good margin against mains surges. An NTC resistor limiting the current at turn-on is required to avoid excessive stress to the diode bridge. The rectifier bridge power dissipation can be calculated using Equation 9, Equation 10, Equation 11. The threshold voltage and dynamic resistance of a single diode of the bridge can be found in the datasheet of the device. Equation 9 Equation 10 The power dissipated on the bridge GBU4J is: Equation 11 out min pkrms V VAC 1ILISW ⋅π ⋅−⋅= A18.1V400 Vac90 1A38.3ISWrms =⋅π ⋅−⋅= out min pkrms V VAC 24ILID ⋅π ⋅⋅= A72.0V400 Vac90 24A38.3IDrms =⋅π ⋅⋅= A84.02 A19.12 I2I in inrms =⋅=⋅= A54.0A19.12I2I in avg_in =π ⋅=π avg_inthinrms2 diodebridge IV4IR4P ⋅⋅+⋅⋅= bridge =⋅⋅+⋅Ω⋅=

3.3.2 Input capacitor

The input high-frequency filter capacitor (Cin) has to attenuate the switching noise due to the high-frequency inductor current ripple (twice the average line current, Figure 3). The worst conditions occur on the peak of the minimum rated input voltage. The maximum high-frequency voltage ripple across Cin is usually imposed between 5% and 20% of the minimum rated input voltage. This is expressed by a coefficient r (= 0.05, 0.2) as an input design parameter: Equation 12 In real conditions the input capacitance is designed to take the EMI filter into account and to have a tolerance on the component of about 5% -10% (typ. for polyester capacitors). A commercial capacitor of Cin = 0.47 µF has been selected. Of course a bigger capacitor benefits the EMI but hurts the THD, especially at high mains. Therefore a compromise must be found between these two parameters. A good quality film capacitor for this component must be selected in order to have an effective filter.

3.3.3 Output capacitor

The selection of the output bulk capacitor (Co) depends on the DC output voltage (4), the allowed maximum output voltage (7) and the converter output power (3). The 100/120 Hz (twice the mains frequency) voltage ripple (∆Vout = peak-to-peak ripple value) is a function of the capacitor impedance and the peak capacitor current: Equation 13 With a low ESR capacitor the capacitive reactance is dominant, therefore: Equation 14 ∆Vout is usually selected in the range of 1.5% of the output voltage. Although ESR usually does not affect the output ripple, it should be taken into account for calculating the power losses. The total RMS capacitor ripple current, including mains frequency and switching frequency components, is: Equation 15

• Ripple voltage coefficient (%): (13)15.0r = minminsw in in VACrf2 IC ⋅⋅⋅π= F359.0Vac9015.0kHz402 A19.1Cin µ=⋅⋅⋅π= Ol outout ESR )Cf22( 1I2V + ⋅⋅π ⋅⋅=∆ outoutMAINS out outl out O VVf2 P Vf2 W100CO µ=⋅⋅⋅π≥ outrms2 Crms IIDI −= () () A67.0A25.0A72.0I 22 Crms =−=

If the PFC stage has to guarantee a specified hold-up time, the selection criterion of the capacitance changes. Co has to deliver the output power for a certain time (tHold) with a specified maximum dropout voltage (Vout min) that is the minimum output voltage value (which takes load regulation and output ripple into account). It is also the minimum output operating voltage threshold before triggering the “power fail” detection and consequent stopping of the downstream system supplied by the PFC. Equation 16 A 20% tolerance on the electrolytic capacitors has to be taken into account for the right dimensioning. As shown in Equation 14, for this application a capacitor CO = 47 µF (450 V) has been selected in order to maintain a hold-up capability of 14 ms. The actual output voltage ripple with this capacitor is also calculated. In detail: Equation 17 As expected the ripple variation on the output is: Equation 18

3.3.4 Boost inductor

The boost inductor determines the operating frequency of the converter, thus it is usually calculated so that the minimum switching frequency is greater than the maximum frequency of the L6563S internal startup (150 µs typ.), to ensure correct TM operation. Assuming unity PF: Equation 19 Equation 19 demonstrates that the on-time doesn't depend on the mains phase angle, but it is constant over the entire mains cycle. Equation 20 ton and toff represent respectively the on-time and the off-time of the power MOSFET. ILpk is the maximum peak inductor current in a line cycle and θ is the instantaneous line phase of the interval [0,Π]). Note that the on-time is constant over a line cycle. () 2 minout outout Holdout O VVV tP2C −∆− ⋅⋅= () ( ) F7.36 V300V20V400 ms10W1002C 22O µ= ⋅⋅= out minout outoutO hold P2 VVVC t ⋅ V300V20V400F47t hold =⋅ −−⋅µ= Ol out out Cf2 IV ⋅⋅π⋅=∆ V02.18F47Hz472 A25.0Vout =µ⋅⋅π⋅=∆ VAC2 ILL )sin(VAC2 )sin(ILL),VAC(t pkpk on ϑ⋅⋅ ϑ⋅⋅=ϑ )sin(VAC2V )sin(ILL),VAC(t out pk off ϑ⋅⋅− ϑ⋅⋅=ϑ

maximum at the zero crossings of the line voltage (θ = 1 or Π ==> sin θ =0), where toff =0. inductance value for the PFC dimensioning. For this application a 0.52 mH boost inductance has been selected. Figure 4. Switching frequency, fixing the line voltage

values. The minimum switching frequency can be recalculated for the selected inductance value, inverting the formula in Equation 22 to the following: Equation 24 From the comparison of fswmin(VACmin) and fswmin(VACmax) with L = 0.52 mH as the actual, the calculated minimum switching frequency is 40.13 kHz, as expected. The core size is determined, assuming a peak flux density Bx ≅ 0.25T (depending on the ferrite grade selected and relevant specific losses) and calculating the maximum current according to Equation 45 as a function of the maximum clamping voltage of the current sense pin and sense resistor value. DC and AC copper losses and ferrite losses must also be calculated to determine the maximum temperature rise of the inductor.

3.3.5 Power MOSFET selection and dissipation

The selection of the MOSFET concerns mainly its RDS(on), which depends on the output power (3), since the breakdown voltage is fixed just by the output voltage (4), plus the overvoltage admitted (7) and a safety margin (20%). Thus, a voltage rating of 500 V (1.2 · Vout = 480 V) is selected. Regarding its current rating as a rule of thumb, we can select a device having ~ 3 times the RMS switch current (see Equation 7), but the power dissipation calculation gives the final confirmation that the selected device is the right one for the circuit. The heatsink dimensions must also be considered. In this L6563S TM PFC application, an STF7NM50 MOSFET has been selected. The MOSFET' s power dissipation depends on conduction, switching and capacitive losses. The conduction losses at maximum load and minimum input voltage are calculated by: Equation 25 Because normally in datasheets the RDS(on) is given at ambient temperature (25 °C) to calculate correctly the conduction losses at 100°C (typical MOSFET junction operating temperature) a factor of 1.75 to 2 should be taken into account. The correct factor can be found in the device datasheet. Now, the conduction losses referred to a 1 Ω R DS(on) at ambient temperature as a function of Pin and VAC can be calculated, combining Equation 25 and Equation 7: Equation 26 The switching losses in the MOSFET occur only at turn-off because of TM operation and can be basically expressed by: Equation 27 outin out minsw VPL2 )VAC2V(VAC)VAC(f ⋅⋅⋅ ⋅−⋅= () 2 rms)on(DScond )VAC(ISWR)VAC(P ⋅= out in2 rmscond V VAC2 162 PFVAC2 P2))VAC(ISW(2)VAC(P ⎟ ⋅=⋅=′ )VAC(ftIV)VAC(P swfallMOSMOSswitch ⋅⋅⋅=

Equation 27 represents the crossing between the MOSFET current that decreases linearly during the fall time and the voltage on the MOSFET drain that increases. In fact during the fall time, the current of the boost inductor flows into the parasitic capacitance of the MOSFET, charging it. For this reason, switching losses depend also on the total drain capacitance. Because the switching frequency depends on the input line voltage and the phase angle on the sinusoidal waveform, it can be demonstrated that from Equation 27 the switching losses per 1 µs of current fall time and 1 nF of total drain capacitance can be written as: Equation 28 On the power MOSFET datasheet tfall at turn-off can be found. At turn-on the losses are due to the discharge of the total drain capacitance inside the power MOSFET itself. In general, the capacitive losses are given by: Equation 29 Where Cd is the total drain capacitance including the MOSFET and the other parasitic capacitances like inductor etc. at the drain node. VMOS is the drain voltage at MOSFET turn- on. Taking into account the frequency variation with the input line voltage and the phase angle similar to Equation 29, a detailed description of the capacitive losses per 1 nF of total drain capacitance can be calculated as: Equation 30 θ1 and θ2 depend on the input voltage and they are defined below. Equation 31 Equation 32 ()∫ π sw outpkswitch d),VAC(fsin1VIL)VAC(P )VAC(fVC2 1)VAC(P swMOS2 dcap ⋅⋅⋅= ϑ ϑ d),VAC(fVVAC221 1)VAC(P sw outcap ⎛=ϑ VAC22 Varcsin out 12 ϑ−π=ϑ

Figure 7. Conduction losses and total losses in the STF7NM50N MOSFET for the MOSFET datasheet for the selected device package, a heatsink must be used.

3.3.6 Boost diode selection

In this 100 W application an STTH2L06, (600 V, 2 A) has been selected. calculating the rectifier losses. From the STTH2L06 datasheet, Vth is 0.89 V, Rd is 0.08 Ω.

ambient, a heatsink is not needed to properly dissipate the heat.

3.4 L6563S biasing circuitry

Figure 8. For more details on the internal functions please refer to the datasheet. Figure 8. L6563S internal schematic

the desired output power dissipated on the output divider. For example, considering a power dissipation of 50 mW: Equation 37 With the commercial resistor selected, RoutH = 3 MΩ. Equation 38 Equation 39 The RoutL = 62 kΩ resistor in parallel to 27 kΩ has been selected for giving a total resistance close to the calculated value. Please note that for RoutH a resistor with a suitable voltage rating (>400 V) is needed, or more resistors in series have to be used. Please note also that the maximum value of the resistor divider is limited by the L6563S INV pin input bias current given in the datasheet. To guarantee correct output voltage regulation, the current flowing in the resistor divider must be significantly higher than the current flowing into the pin. Pin 7 (PFC_OK - feedback failure protection): the PFC_OK pin has been dedicated to monitor the output voltage with a separate resistor divider. This divider is selected so that the voltage at the pin reaches 2.5 V if the output voltage exceeds a preset value V OVP (7), usually larger than the maximum Vout that can be expected, also including worst-case load/line transients. For a maximum output voltage Vout max of 430 V and imaging a 50 µA current flowing into the divider: Equation 40 By selecting a commercial resistor of 51 kΩ: Equation 41 Using two 3.3 MΩ resistors and one 2.2 MΩ resistor, a total output PFC_OK high resistor of 8.8 MΩ has been obtained. Notice that both feedback dividers connected to L6563S pin #1 (INV) and pin #7 (PFC_OK) can be selected without any constraints. The unique criterion is that both dividers have to sink a current from the output bus which needs to be significantly higher than the current biasing the error amplifier and PFC_OK comparator. The OVP function described above is able to handle “normal” overvoltage conditions, i.e. those resulting from an abrupt load/line change or occurring at startup. In case the mW50 )V5.2V(R OUT outH −= Ω=−= M160.3mW50 )V5.2V400(R outH 1V5.2 V R R out outL outH −= 1591V5.2 V400 R R outL outH =−= 159 RR outH outL = Ω=Ω= k8.18159 M3RoutL divider OK_PFC_REF L I VR = Ω=µ= k50A50 V5.2RL −⋅= 1V VRR OK_PFC_REF MAX_OUT LH Ω=⎟⎟ ⎛ −⋅Ω= M721.81V5.2 V430k51RH

overvoltage is generated by a feedback disconnection, for instance, when one of the upper resistors of the output divider fails open, an additional circuitry detects the voltage drop of pin INV. If the voltage on pin INV is lower than 1.66 V (Typ.) and at same time the OVP is active, a feedback failure is assumed. Thus, the gate drive activity is immediately stopped, the device is shut down, its quiescent consumption is reduced below 180 µA and the condition is latched as long as the supply voltage of the IC is above the UVLO threshold. To restart the system it is necessary to recycle the input power, so that the Vcc voltage of the L6563S goes below 6 V and that one of the PWM controller goes below its UVLO threshold. Note that this function offers a complete protection against not only feedback loop failures or erroneous settings, but also against a failure of the protection itself. Either resistor of the PFC_OK divider failing short or open or a floating PFC_OK pin results in shutting down of the IC and stopping the pre-regulator. Moreover, the pin PFC_OK doubles its function as a non-latched IC disable. A voltage below 0.23 V shuts down the IC, reducing its consumption below 2 mA. To restart the IC simply let the voltage at the pin go above 0.27 V. Pin 2 (COMP): This pin is the output of the E/A that is fed to one of the two inputs of the multiplier. A feedback compensation network is placed between this pin and INV (pin #1). It has to be designed with a narrow bandwidth in order to avoid that the system rejects the output voltage ripple (100 Hz) that would lead to a high distortion of the input current waveform. A simple criterion to define the capacitance value is to set the bandwidth (BW) from 20 to 30 Hz. The compensation network can be just a capacitor, providing a low-frequency pole as well as a high DC gain. A more complex network, typically a type-II CRC network providing 2 poles and a zero, is more suitable for constant power loads like a downstream converter. In case a single capacitor is used, it can be dimensioned using the following formulas: Equation 42 Equation 43 For a more complex compensation network calculation, please refer to [2], [3]. For this 100 W TM PFC, a CRC network providing two poles and a zero has been implemented here, using the following values: The relevant open loop transfer function and its phase function are shown in Figure 9 and Figure 10. (14) () onCompensatioutLoutH CR//R2 1BW ⋅⋅π= () BWR//R2 outLoutH onCompensati ⋅⋅π= nF68CcompP = nF680CcompS = Ω= k82RcompS

distortion introduced by the E/A 100 Hz residual ripple is below 3%. equipped with 150 ns leading-edge blanking for improved noise immunity.

• ILpk is the maximum peak current in the inductor, calculated as described in Equation 4
• Vcsmin = 1.0 V, and is the minimum voltage admitted on the L6563S current sense (in the datasheet) Because the internal current sense clamping sets the maximum current that can flow in the inductor, the maximum peak of the inductor current is calculated considering the maximum voltage Vcsmax admitted on the L6563S (in the datasheet): Equation 45 The calculated ILpkx is the threshold value after which the boost inductor saturates and it is used for calculating the inductor number of turns and air gap length. In case of boost inductor saturation, a second comparison level at 1.7 V detects the abnormal currents and, on this occurrence, activates a safety procedure that temporarily stops the converter and limits the stress of the power components.

Figure 9. Open loop tran. function bode plot Figure 10. Phase function

within the range 0 to 3 V of VMULT and the range 0 to 1.16 V (typ.) of VCS, while the minimum guaranteed value of the maximum slope of the characteristics family (typ.) is: Equation 48 The voltage on the MULT pin is also used to derive the information from the RMS mains voltage for the VFF compensation. We suggest the following procedure to properly set the operating point of the multiplier. First, the maximum peak value for VMULT, VMULTmax is selected. This value, which occurs at maximum mains voltage, should be 3 V or nearly so in wide-range mains and less in case of single mains. The sense resistor selected is R s = 0.27 Ω as given in Equation 44. According to the L6563S datasheet and to the linearity setting of the pin, the maximum voltage accepted on the multiplier input is: where ILpk and Rs have been already calculated, 1.66 is the multiplier maximum slope given in the datasheet. From (15) the maximum required divider ratio is calculated as: Equation 49 Supposing a 60 µA current flowing into the multiplier divider, the lower resistor value can be calculated: Equation 50 A commercial resistor of 51 kΩ for the lower resistor is selected. The upper resistor value can now be calculated as: Equation 51 In this application example RmultH = 6.6 MΩ and RmultL = 51 kΩ have been selected. Please note that for RmultH a resistor with a suitable voltage rating (>400 V) is needed, or more resistors in series must be used. The voltage on the multiplier pin with the selected component values is re-calculated at minimum line voltage (0.93 V) and at maximum line voltage (2.74 V). So the multiplier works correctly within its linear region. Pin 5 (voltage feed-forward): The power stage gain of PFC pre-regulators varies with the square of the RMS input voltage as well as the crossover frequency fc of the overall open- loop gain because the gain has a single pole characteristic. This leads to large trade-offs in (15) V V66.1dV dV MULT CS = V3VMULTmax = max maxMULT p 108 Vac2652 V00.3 VAC2 Vk −⋅= Ω=µ=µ= k50A60 V00.3 A60 VR maxMULT multL Ω=Ω ⋅−=−= − M319.6k51 108 1081Rk k1R 3 multL p p multH

preregulator's output like in systems with no feed-forward compensation. low. The IC restarts as the voltage at the pin goes above 0.88 V. FF pin as shown in the Figure 14. Figure 14. Brownout function in L6563S and L6563H input mains voltage VACmin (in this design 90Vac) as specified in (1). ∆V is the voltage drop between the VFF and MULT pins.

Setting up RFF_L = 1 MΩ, RFF_H can be calculated from Equation 53. Equation 54 The result of Equation 54 is based on typical values and doesn't take into account the VRUN_EN threshold and the resistor tolerances. In order to have the startup at minimum mains voltage as set in (1) and guarantee against variation of parameters, the mentioned tolerances should be taken into account, making calculations to consider the worst cases. In this case, taking into account the resistors and threshold tolerances, 1 MΩ and 56 kΩ have been calculated, thus the actual divider ratio is 0.946. Then the following check can be done: Equation 55 Equation 56 Equation 57 Equation 58 Pin 11 (ZCD): The pin #11 is the input of the zero-current detector circuit. In transition-mode PFC the ZCD pin is connected, through a limiting resistor, to the auxiliary winding of the boost inductor. The ZCD circuit is negative-going edge triggered. When the voltage on the pin falls below 0.7 V, it sets the PWM latch and thus the MOSFET is turned on. To do so the circuit must first be armed. Prior to falling below 0.7 V, the voltage on pin #5 must experience a positive-going edge exceeding 1.4 V (due to the MOSFET's turn-off). The maximum main- to-auxiliary winding turn ratio, nmax, has to ensure that the voltage delivered to the pin 904.0RR R V V H_FFL_FF L_FF V@FF EN_RUN START =+= L_FF EN_RUN V@FF H_FF R1V V R START ⋅⎟⎟ −= Ω=Ω⋅⎟⎟ ⎛ −= k105M11V88.0 V973.0R H_FF L_FF H_FFL_FF EN_RUNENABLE_FF R RRVV +⋅= V923.0M1 k56M1V88.0V ENABLE_FF =Ω Ω+Ω⋅= multL multLmultHEN_FF START_in R RR mV20VV +⋅⎟⎟ ⎛ += Vac87k51 k51M6.6 mV20V923.0V START_in =Ω Ω+Ω⋅⎟⎟ ⎛ += L_FF H_FFL_FF DIS_RUNDISABLE_FF R RRVV +⋅= V844.0M1 k56M1V80.0V DISABLE_FF =Ω Ω+Ω⋅= multL multLmultHDIS_FF STOP_in R RR mV20VV +⋅⎟⎟ ⎛ += Vac9.79k51 k51M6.6 mV20V844.0V STOP_in =Ω Ω+Ω⋅⎟⎟ ⎛ +=

schematic of Figure 28, Figure 29 can be used. VZCDH = 5.7 V and VZCDL = 0 V are the upper and lower ZCD clamp voltages of the L6563S. selected as the limiting resistor. run out of energy, (Figure 15).This minimizes the power dissipation at turn-on. Figure 15. Optimum MOSFET turn-on

With this IC the function can be implemented by connecting a resistor (RT) between the TBO pin and ground. The TBO pin presents a DC level equal to the peak of the MULT pin voltage and is then representative of the mains RMS voltage. The resistor defines a current, equal to V(TBO)/R T, that is internally 1:1 mirrored and sunk from pin INV (pin #1) input of the error amplifier. In this way, when the mains voltage increases, the voltage at TBO pin increases as well which increases the current flowing through the resistor connected between TBO and GND. Then a larger current is sunk by the INV pin and the output voltage of the PFC preregulator is forced to go higher. Obviously, the output voltage moves in the opposite direction if the input voltage decreases. To avoid undesired output voltage rise should the mains voltage exceed the maximum specified value, the voltage at the TBO pin is clamped at 3 V. By properly selecting the multiplier bias it is possible to set the maximum input voltage above which input-to-output tracking ends and the output voltage becomes constant. If this function is not used, leave the pin open: the device regulates a fixed output voltage. Starting from the following data: To set the output voltage at the desired values use the following design procedure: 1. Determine the input RMS voltage V inCLAMP that produces Vo = Vox: Equation 62 and choose a value Vinx such that Vin2 = Vinx < VinCLAMP. This results in a limitation of the output voltage range below Vox (it equals Vox if one chooses Vinx = VinCLAMP) 2. Determine the divider ratio of the MULT pin (pin #3) bias:

• Minimum specified input RMS voltage (18)
• Maximum specified input RMS voltage (19)
• Regulated output voltage at Vin = Vin1 (20)
• Regulated output voltage at Vin = Vin2 (21)
• Absolute maximum limit for the regulated output voltage (22)
• Maximum output voltage (Vdc) - (7) (23) Vin1 Vin2 Vo1 Vo2 Vox VOVP 1in 1O2O 2OOX 2in 1O2O 1OOX inCLAMP VVV VVVVV VVV ⋅− −−⋅−

1. Determine R outH, the upper resistor of the output divider, for instance 3 MΩ.
2. Calculate the lower resistor R outL of the output divider and the adjustment resistor RT:
3. Check that the maximum current sourced by the TBO pin (pin #6) does not exceed the

Figure 16. Tracking boost block diagram

Note that in this design example of the 100 W board PFC, the tracking boost function has not been used because the PFC has to supply a stable 400 V output voltage over the entire input mains. Pin 8 (PWM_LATCH): Output pin for fault signaling. During normal operation this pin features high impedance. If a feedback failure is detected (PFC_OK > 2.5 V and INV+40 mV < PFC_OK) the pin is asserted high. Normally, this pin is used to stop the operation of the DC-DC converter supplied by the PFC pre-regulator by invoking a latched disable of its PWM controller. If not used, the pin is left floating. Pin 9 (PWM_STOP): Output pin for fault signaling. During normal operation this pin features high impedance. If the IC is disabled by a voltage below 0.8 V on pin RUN (#10), the voltage on the pin is pulled to ground. Normally, this pin is used to temporarily stop the operation of the DC-DC converter supplied by the PFC pre-regulator by disabling its PWM controller. A typical usage of this function is brownout protection in systems where the PFC pre-regulator is the master stage. If not used, the pin is left floating. Pin 12 (GND): This pin acts as the current return both for the signal internal circuitry and for the gate drive current. When laying out the printed circuit board, these two paths should run separately. Pin 13 (GD): is the output of the driver. The pin is able to drive an external MOSFET with 600 mA source and 800 mA sink capability. The high-level voltage of this pin is clamped at about 12 V to avoid excessive gate voltages in case the pin is supplied with a high Vcc. To avoid undesired switch-on of the external MOSFET because of some leakage current when the supply of the L6563S is below the UVLO threshold, an internal pull-down circuit holds the pin low. The circuit guarantees 1.1 V maximum on the pin (at I sink = 2 mA), with Vcc > VCC_ON. This allows omitting the “bleeder” resistor connected between the gate and the source of the external MOSFET used for this purpose. Pin 14 (Vcc): is the supply of the device. This pin is externally connected to the startup circuit (usually, one resistor connected to the rectified mains) and to the self-supply circuit. Whatever the configuration of the self-supply system, a capacitor is connected between this pin and ground. To start the L6563S, the voltage must exceed the startup threshold (12 V typ.). Below this value the device does not work and consumes less than 90 µA (typ.) from Vcc. This allows the use of high value startup resistors (in the hundreds of kΩ), which reduces power consumption and optimizes system efficiency at low load, especially in wide-range mains applications. When operating, the current consumption (of the device only, not considering the gate drive current) rises to a value depending on the operating conditions but never exceeding 6 mA. The device keeps working as long as the supply voltage is over the UVLO threshold (13 V max). If the Vcc voltage exceeds 22.5 V, an internal Zener diode, 20 mA rated, is activated in order to clamp the voltage. Please remember that during normal operation the internal Zener does not have to clamp the voltage, because in that case the power consumption of the device increases considerably and its junction temperature increases too. The suggested operating condition for safe operation of the device is below the minimum clamping voltage of the pin.

4 L6563H: high-voltage startup transition-mode PFC

embeds the same features existing in the L6563S with the addition of a high-voltage startup. Figure 18. The pin function is the same, in this paragraph a detailed description of the HV temperature-compensated current generator connected to its source. Figure 19. High-voltage startup generator: internal schematic Figure 17. L6563H - SO16 Figure 18. L6563S - SO14

Vcc to ground and makes its voltage rise almost linearly. Figure 20. Timing diagram: normal power-up and power-down sequences

5 Design example using the L6563S-TM PFC Excel

most functionalities are the same and therefore they can be calculated in the same way. Figure 23. Excel spreadsheet design specification input table Figure 24. Other design data calculation of the main components.

Figure 27. Excel spreadsheet BOM - 100 W TM PFC based on L6563S/H

6 EVL6563S-100W and EVL6563H-100W demonstration

has been dimensioned using the Excel tool presented in Section 5. Figure 28. Wide-range 100 W demonstration board electrical circuit (EVL6564-100W)

L6563H shown in Figure 29 has been dimensioned too. Figure 29. Wide-range 100 W demonstration board electrical circuit (EVL6563H-100W)

7 References

1. L6563S datasheet 2. L6563H datasheet 3. “A systematic approach to frequency compensation of the voltage loop in boost PFC preregulator”, abstract 4. AN1089 5. AN3063 6. AN3065

8 Revision history

Table 1. Document revision history 28-Apr-2010 1 Initial release.