AN3010 MA-COM | Alldatasheet

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Technical content

figure, a high power and low loss limiter is required. integrated Schottky diode limiter and high power load.

  • single chip, no extra components and assembly, low cost solution
  • balanced configuration, built-in couplers
  • high-power termination resistor on the chip
  • limiter parasitic capacitance part of the LNA’s input match, improved noise figure with respect to discrete solutions
  • high-output, third-order intercept point
  • uses standard, reliable and high performance MSAG MESFET technology. A block diagram of the high power limiter/LNA MMIC is shown in Figure 1. Figure 2 shows the photograph of the two- stage balanced limiter/LNA. The chip measures 4.6 ×3.1 mm. The design of integrated high power limiter/LNA has been described in [2]. Test Methodology The limiter recovery time was measured by pulsing the input RF signal from a small signal level to a high power state Jim Looney, David Conway, and Inder Bahl (inderb@tycoelectronics.com) are with M/A-COM, Inc., 5310 Valley Park Drive, Roanoke, V A 24019. USA An Examination of Recovery Time of an Integrated Limiter/LNA ■ Jim Looney, David Conway, and Inder Bahl

Figure 1. A balanced three-stage LNA with limiter.

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time as the RF level drops back to normal operating levels. Figure 2. MA01502D, a commercially available C/X-band integrated LNA/Limiter. Figure 3. A LNA/limiter recovery time test set-up.

8 GHz

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loscope. Refer to Figure 3 for the test set-up block diagram. and goes low, as shown in Figure 4. recovery time decreased by approximately 50%. leads to “noise” in the recovery time measurement. different units of the same type) to get the best signal. [1] Microwave MMIC Products, M/A-COM, Roanoke, VA. Figure 5. A LNA small-signal recovery time plot of F1 tone used to trigger F2 source and oscilloscope. Figure 6. An LNA small-signal recovery time plot of F1 tone Figure 4. Ar epresentational plot of relationship between F1 (CW, small-signal) and F2 (pulsed, large-signal) tones.