AN3008 STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 14
Technical content
Datasheet sections
- 1 High voltage power supply base d on STOD2540
- 1.1 STOD2540 function description
- 1.2 Load disconnect
- 1.3 Output adjust
- 1.4 Inductor selection
- 1.6 Diode selection
- 1.7 Single inductor circuit based on STOD2540 derives 35 V / 70 V
- 2 Test results
- 2.1 Start-up
- 2.2 Output voltage ripple
- 2.3 Efficiency
- 2.4 Line regulation 70 V / 35 V
- 2.5 Load regulation
- 3 Layout
- 3.1 Input / output connections
- 4 Application schematic and bill of materials
- 5 Revision history
in Figure 1 generates a 70 V output from a 3.7 V input voltage. up to 35 V from a 3.0 to 5.5 V input voltage. order to keep the output voltage regulated. disconnected from the input and the quiescent current is less than 3 µA. Figure 1. High voltage power supply based on STOD2540
AN3008 High voltage power supply based on STOD2540 Doc ID 16021 Rev 2 3/14
1 High voltage power supply based on STOD2540
1.1 STOD2540 function description
The STOD2540 uses a PFM control scheme to reach high efficiency in low load conditions. The DC-DC has a current mode control scheme that uses a minimum OFF time and a maximum ON time. The converter monitors the output voltage through the resistor dividers R1 and R2 by comparing the feedback voltage with the internal reference voltage of 1.24 V. The integrated main power switch is turned on as soon as the feedback voltage falls below the internal reference. The switch stays on until the inductor current reaches the peak current limit or for a maximum ON time equal to 5.5 µsec. The peak current limit value is adjustable through an external resistor connected between the RSET pin and GND. The main switch stays off for at least a minimum OFF time (300 ns typical) and remains in the off state for as long as the feedback voltage remains above the internal reference voltage. During the ON time, the load current is only supplied by the charge stored in the output capacitor until the feedback voltage drops below the reference voltage again. PFM regulation is particularly useful when output currents are low and the part is prevalently in the OFF state.
1.2 Load disconnect
When the device is in shutdown mode, a DC current path exists between the power source and the load. A high-side switch LDS isolates the load from the source when the device is disabled.
1.3 Output adjust
Choose the R4 value in the range of 10 to 200 kΩ. The value of R3 can be calculated from the following equation. Equation 1 Where RU is the upper resistor of the voltage divider. RL is the lower resistor of the voltage divider. 1% tolerance resistors should be chosen for a more accurate VOUT. The STOD2540 shows a pulses burst behavior that causes a high output voltage ripple. To decrease the output ripple it is possible to insert a capacitor across the upper feedback resistor. The following formula can be used to obtain a first estimation of the value of the capacitor. ⎛ −×= 1V VRR FB OUT LU
High voltage power supply based on STOD2540 AN3008 4/14 Doc ID 16021 Rev 2 Equation 2 Where RU is the upper resistor of the voltage divider. FSW is the switching frequency. The following equation gives the switching frequency at the nominal load current. Equation 3 The CF capacitor increases the amplitude of the voltage ripple on the FB pin, causing a deterioration of the line regulation; therefore, the value of CF should be as small as possible.
1.4 Inductor selection
Since the hysteretic control scheme is inherently stable, the inductor value does not affect the stability of the regulator. Using the PFM peak current control scheme, the converter operates in discontinuous conduction mode (DCM). The inductance value must be calculated so as to ensure that the inductor current reaches the current limit before the maximum ON time expires. The following equation can be used to calculate the maximum value of the inductance. Equation 4 Where IPK is the controlled inductor peak current. In this case the maximum value of the load current is given by Equation 5. Equation 5
1.5 C OUT selection
The output voltage ripple very much depends on the application conditions. The output capacitor has a significant effect on the output voltage ripple magnitude because it supplies the load current through the charge stored during the ON state. The output voltage ripple consists of two parts: the first is caused by the ESR, the second by the charging and discharging process of the output capacitor. U SW R20 1CF ××π× PK INOUTLOAD LOADSW IL )VV(I2)I(F −××= MAX_ON PK MIN_IN TI VL ×≤ MIN IN PK INOUT PK MAX_LOAD toffV LI)VVdV(2 LII
The output ripple can be approximately given by the following equation. present. For the best output voltage filtering, a low ESR output capacitor is recommended.
1.6 Diode selection
The output diode in a boost converter conducts current only when the power switch is off.
- a small forward voltage drop.
- a rated current larger than the peak inductor current.
- a reverse voltage larger than the output voltage.
- a small reverse leakage current.
1.7 Single inductor circuit ba sed on STOD2540 derives 35 V/70 V
(C1 and C2) allows delivering output voltages of over 70 V. biased and the load current is supplied only by the output capacitor COUT. Figure 2. External charge pump - T ON state
D1 into C2. Therefore, the voltage at node SW is equal to the voltage on C2 (35 V). is reverse-biased during this time period. like the 70 V output voltage and varies with the current drawn from the 70 V. 35 V output and an unregulated 70 V output. ratings for the diodes must be greater than half the peak switch current of the STOD2540. rated for the full output voltage. Figure 3. External charge pump - T OFF state
2 Test results
2.1 Start-up
evaluation module in the following conditions.
- VIN = 3.7 V
- VOUT = 73 V
- ILOAD = 5 mA
2.2 Output voltage ripple
different input voltages and ILOAD equal to 10 mA. Figure 4. Start-up/V OUT Figure 5. Start-up/inductor current Figure 6. 70 V output voltage ripple vs. V IN Figure 7. 70 V output voltage ripple vs. I LOAD
2.3 Efficiency
2.4 Line regulation 70 V / 35 V
Figure 8. Output efficiency for the 70 V output Figure 9. 70 V line regulation Figure 10. 35 V line regulation
2.5 Load regulation
and the FB pin is closed on 70 V. Figure 11. 70 V output load regulation Figure 12. 35 V output changes when load Figure 13. 35 V unregulated output
3 Layout
- The GND connections of the COUT, CIN capacitors and STOD2540 PGND should be placed as close as possible to each other.
- The connection from the IC pins (VIN, SW) and the inductor must be kept short.
- CIN should be placed close to the VIN pin of the chip.
- The ground area should be as large as possible. If a two-layer PCB is used, one layer should be assigned as the ground layer and a good connectivity between both layers should be observed.
Figure 14. Assembly layer Figure 15. Top layer
3.1 Input / output connections
Figure 16. Bottom layer Table 1. Input / output connections JP1 VIN/GND VIN: positive connection to the input power supply. GND: return connection to the input power supply. HV: high voltage – 70 V. Positive connection for the load. MV: medium voltage – 35 V. Positive connection for the load.
4 Application schematic and bill of materials
Figure 17. Demonstration board schematic Table 2. Bill of materials
1 U1 DC-DC converter STOD2540PMR QFN8 3 x 3 mm
1 C1 Capacitor, ceramic, 100 nF , 50 V, X5R 0805
2 COUT Capacitor, ceramic, 1 µF , 100 V, X5R GRM31CR72A105KA01L 0805
1 CF Capacitor, ceramic, 47 pF 0603
3 D1, D2, D3 Diode, Schottky 2 A 30 V STPS2L40AF SMAflat
1 R1 Resistor, 1 k Ω, 1/16 W, 1% 0603
1 R2 Resistor, 1/16 W, 1% 0603
1 R3 Resistor, 680 k Ω, 1/16 W, 1% 0603
1 R4 Resistor, 10 k Ω, 1/16 W, 1% 0603
1 R5 Potentiometer, 100 k Ω
2 JP1, JP2 Header, 2-pin, 100-mil spacing
1 JP3 Header, 3-pin, 100-mil spacing
5 Revision history
Table 3. Document revision history 10-Nov-2009 1 Initial release. page 11, Figure 17 and Table 2 on page 12.