AN3001 STMICROELECTRONICS | Alldatasheet

Document overview

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Technical content

STMicroelectronics’ TS4657 device. ■ a brief description of the TS4657 device. ■ a description of the demonstration board and all of its components. ■ the layout of the demonstration board. Figure 1. TS4657 demonstration board

1 About the TS4657

The TS4657 is a stereo digital-to analog-converter (DAC) that integrates a high- performance audio line driver capable of generating a 2.2 Vrms output level from a single 3.0 to 5.5 V supply. One single supply is sufficient for the digital and analog parts of the circuit, thus eliminating the need for external regulators. The TS4657 is a low-power consumption device. It features only 22 mW power dissipation at a 3.0 V power supply in full operation. A 16-bit multi-bit sigma delta DAC is used, operating at 256xFs with oversampling digital interpolation filters. The digital audio data can be 16- to 24-bit long and sample rates from 32 to 48 kHz are supported. The output stage signal is ground-referenced by using an internal self-generated negative power supply, and as such external bulky output coupling capacitors are not necessary. The TS4657 features the following.

  • Power supply range: 3.0 V to 5.5 V.
  • Audio line output: 2.2 Vrms for all VCC range.
  • 16- to 24-bit audio data format stereo DAC, 32 to 48 kHz sample rate.
  • I²S, right- or left-justified compatible digital audio interface.
  • 95 dB SNR A-weighted at 48 kHz, VCC =5V .
  • Low current consumption of 7.4 mA at V CC = 3.0 V, full operation.
  • Internal negative power supply to ensure ground-referenced, capless outputs.
  • No necessity for an external capacitor for negative power supply generation.
  • Integrated structure to suppress pop and click noise
  • Standby mode active low.
  • Q F N 2 0 p a c k a g e , 4m mx4m m , 5 0 0µ m p i t c h . Refer to the datasheet entitled "Single supply stereo digital audio line driver with 2.2 Vrms capless outputs" for complete information on the TS4657.

2 Description of the demonstration board

device is soldered on a two-layer PCB. on the demonstration board (Table 1). Table 1. Demonstration board connectors input format (see section 4.1.2 Digital audio input format in the TS4657 datasheet). input format (see section 4.1.2 Digital audio input format in the TS4657 datasheet). Controls the chip standby (JP1:1-2 = circuit activated, 2-3 = circuit in standby mode). see Section 3.3: Output filters on page 6). Section 3.3: Output filters on page 6). Section 3.3: Output filters on page 6). Section 3.3: Output filters on page 6).

Figure 2. Schematic diagram Table 2. Component list for the demonstration board

3 Configuring the demonstration board

3.1 Serial data input configuration

FORMAT2 as detailed in Table 3. The level on both of these pins should be fixed before waking-up the chip.

3.2 Sample rate capability

integer, as shown in Table 4. Table 3. Digital audio data formats supported by the TS4657

00 Right-justified, 16-bit data

01 Right-justified, 24-bit data

10 Left-Justified, 16-bit up to 24-bit data

11 I²S, 16-bit up to 24-bit data

Table 4. Audio data sampling rates

3.3 Output filters

with R = R5 =R 7 in ohms, C in farads and C = C6 =C 7. Figure 3. Output stage without output filters Figure 4. Output stage with output filters

AN3001 Configuring the demonstration board Doc ID 15911 Rev 1 7/12

3.4 Optional measurement loads

As shown in Figure 2 on page 4, there are two resistors (R6 and R8) that are not connected on the demonstration board. These resistors are used to measure the performances of the TS4657 with different loads. After the test, it is best to remove them and load the TS4657 with the application only. The load on both outputs should be higher or equal to 5 k. Generally, the standard load for the audio line is 10 k (10 K/1 %, 0.063 W, SMD resistors, 0603).

3.5 Specific considerations

The TS4657 utilizes a power management unit to supply its internal structures. A self-generated negative supply allows the drivers to be powered from positive and negative supplies, thus increasing the output signal amplitude. This internal negative supply switches at a higher frequency than traditional architectures, derived from the master clock MCLK. This structure uses an original design that allows suppressing the flying or floating capacitors. Therefore, only four small 1 µF decoupling capacitors are necessary for VCCA/VCCD and VREGA/VREGD. Furthermore, the self-generated negative supply allows the amplifier outputs to be centered around zero, thus the bulky output coupling capacitors can be removed. As mentioned previously, the MCLK is used internally to supply some blocks. It is therefore not recommended to switch off the MCLK during normal operation. To properly power-down the device, MCLK, BCLK and LRCLK should be switched off after the STDBY signal. The power-down time is very short and can be considered as zero.

4 Demonstration board layout

The following figures show the layers and top and bottom views of the demonstration board. Figure 5. PCB top overlay Figure 6. PCB top layer Figure 7. PCB bottom overlay Figure 8. PCB bottom layer

5 Conclusion

To order the board online, go to http://www.st.com/stonline/domains/buy/buy_dev.htm, and use the order code STEVAL-CCA018V1.

6 Revision history

Table 5. Document revision history 03-Jul-2009 1 Initial release.