AN2344

AN2344 STMICROELECTRONICS | Alldatasheet

Document overview

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• PDF pages: 27

Technical content

Datasheet sections

• 1 MOSFET fundamentals
• 1.1 Failure modes descriptions
• 2 Testing avalanche ruggedness
• 3 Datasheet avalanche ratings
• 3.1 Avalanche operation maximum current (IAR)
• 3.2 Energy during avalanche for single pulse (EAS)
• 3.3 Avalanche rating example
• 3.3.1 EAR (Energy during avalanche for repetitive pulse)
• 4 Conclusion
• 5 Revision history

Power MOSFET avalanche characteristics and ratings Introduction Back in the mid-80s, power MOSFET manufacturers started to claim a new outstanding feature: Avalanche Ruggedness. Suddenly, new families of devices evolved, all with this “new” feature. The implementation was quite simple: the vertical MOSFET structure has an integral body drain diode which cannot be eliminated. By changing some process and layout parameters, it is possible to guarantee the use of the clamping capability of this diode for withstanding accidental voltage/power surges beyond the nominal drain source voltage. Rating ‘ruggedness’ in a datasheet was very difficult because of the great confusion regarding the meaning of this feature, as well as poor theoretical knowledge of it. Nonetheless, all of the Power MOSFET manufacturers started to produce avalanche-rated devices and propose datasheet ratings (although imperfect), to protect themselves and the end users from this incomplete knowledge. Now, knowledge about a device’s behavior during avalanche conditions is greatly enhanced by a number of application notes and papers issued, which provide different explanations of avalanche ratings and behavior. This application note briefly reviews the MOSFET physics on avalanche behavior and supplies designers with tools and suggestions for dealing with avalanche issues.

1 MOSFET fundamentals

Figure 1. shows a basic, simplified MOSFET structure. The actual MOSFET is an infinite Sources are linked by the top metal layer. various older technologies (e.g. cellular) as well. reverse bias, and a very small current (leakage) flows through the junction. actual drain-source breakdown voltage. sufficient heat sinking is provided. Figure 1. MOSFET vertical structure and parasitic elements

MOSFET fundamentals AN2344

1.1 Failure modes descriptions

The integral diode of a MOSFET is the collector-base junction of the parasitic transistor. If the current flows laterally through region P , the increase in the voltage drop across the emitter base resistance causes the BJT to turn ON. The initial avalanche current is concentrated mainly in the diode localized in the deep zone of P+; as soon as the current grows, it begins to interest the more lightly doped P regions. Since, by design, the lateral resistance RP value is higher than that of the heavy doped P region vertical resistance, and the current is concentrated in the region P+, the BJT should not turn ON. As soon as the current begins to stimulate the P region, causing a sufficient drop of voltage to equal the BJT base-emitter voltage (VBE), the base current (IB), in conjunction with the transistor β will cause the BJT to turn ON. The VBE has a negative temperature coefficient, consequently leading to thermal runaway and finally, the destruction of the device due to the secondary breakdown of the parasitic BJT. The adoption of a heavily doped P + region, thereby determining the reduction of the transistor gain and base resistance has been the first step for MOSFET improvement, followed by other, more subtle optimizations. The power that is dissipated in the MOSFET causes an increase in junction temperature. If the temperature increases to a critical value set by the siliconfs property, the failure, without the contribution of the parasitic bipolar, occurs because of the creation of thermally generated carriers in the epitaxial/bulk region, which in turn, create the hot spots. The critical temperature to have phenomenon is beyond the maximum junction temperature of the devices, and is related to the intrinsic temperature of doped silicon, to which the concentration of the bulk is equal to that of the thermally generated carriers. The temperature increase that occurs during avalanche phenomena, due to the silicon thermal capacitance, is not instantaneous. Therefore, this type of failure should be distinguished from that caused by current as the device holds the breakdown voltage for a finite time before its destruction.

2 Testing avalanche ruggedness

1. At zero time, the device switches ON, closing the circuit.
2. The current increases following an exponential law as a function of the L/R
3. As soon as the device is switched OFF , the dI/dt causes an overvoltage on the drain of

Figure 2. UIS reference diagram Figure 3. Typical UIS waveforms

Table 1. UIS circuit equations

Datasheet avalanche ratings AN2344

3 Datasheet avalanche ratings

When the device is classified as gAvalanche Ratedh, the datasheet provides the end-user some useful parameters which define the ratings of the device during avalanche:

• Avalanche operation maximum current (IAR)
• Energy during Avalanche for Single pulse (EAS)

3.1 Avalanche operation maximum current (I AR)

This is the maximum current that can flow through the device during avalanche operations without the BJT latching. This Maximum limit must be considered as an absolute maximum rating. Even if the critical current to bring the device to failure is higher than the IAR, the producer guarantees the operation of the device below this limit. This test is usually conducted for several microseconds. All of ST's High Voltage Power MOSFETs are tested according to the I AR. All the avalanche operations (single event or repetitive) below this current value can be considered safe unless there are power dissipation issues. Note: For MOSFETs connected in parallel, the current that is switched during the avalanche phenomenon is not shared, which is different than operations in the conduction state. In fact, at turn-off, only the device with the lower breakdown and/or with the faster switch will go into avalanche, withstanding the total current that is shared with the other MOSFETs in parallel during the ON state. If such current is more than the I AR, the device can fail. Even if the energy associated with that event is very low, failure would be due to the activation of the MOSFET's parasitic bipolar.

3.2 Energy during avalanche for single pulse (EAS)

This is the maximum energy that can be dissipated by the device during a single pulse avalanche operation (at the same circuit conditions described in testing avalanche ruggedness. From the I AR and starting junction temperature of 25°C, the junction temperature is brought up to the maximum that is stated in the absolute maximum ratings. The EAS value decreases as the starting junction temperature increases. In most datasheets, this energy derating curve (see Figure 6.) is referred to as “Avalanche Energy vs. Starting TJ”. In the case of Figure 6., all of the single event avalanche operations below the EAS value are considered safe for the device, if the junction starting temperature is 25°C, then the drain current is switched to less than or equal to I AR. If TJ > 25°C, the user can refer to this curve to obtain the correct energy dissipation derating.

Figure 6. EAS vs temperature STP9NK80Z

3.3 Avalanche rating example

In this example, a user wants to use an STP9NK80Z as a DC/DC converter main switch.

• EAS = 350mJ,
• IAR = 7.5A, and
• TJ(max) = 150°C. According to the board analysis, the device used for such power supply condition can experience a single pulse avalanche operation. The measurements have shown that the average junction temperature is 100°C, the peak drain current switched during the avalanche is 4A, and the energy that is dissipated during that single avalanche operation is 0.24mJ. To understand if the device is working within the datasheet ratings, the switched current needs to be checked by comparing it to the I AR; because the ID peak value is 4A and below the IAR, this rating is satisfied. To confirm that TJ is below TJ(max), it is assumed that TJ before the avalanche is average (100°C). Figure 6. shows that the energy it takes to bring TJ to the maximum rating (starting from 100°C) is approximately 50mJ. Since the energy measured is below 50mJ, the TJ reached during the avalanche will be less than TJ(max). Considering that both of the bonds, the current below IAR and the TJ value below the TJ(max) are well satisfied, one can safely state that the device (under that single avalanche event) is working within the datasheet ratings. Each MOSFET manufacturer (including ST) presents their own approaches to measuring EAS values, as well as their findings. These values are not simple to state because it is very difficult to look at T J during an avalanche operation. In order to provide as clear an explanation as possible, some manufacturers set this value by using the thermal impedance stated in the datasheet. This could be an interesting approach, but some concerns would Starting TJ=100°C

Datasheet avalanche ratings AN2344 have to be taken into consideration. These are mainly systemic in nature because the datasheet thermal impedance is the response of the userfs system to a rectangular power pulse, while maintaining the package case temperature at 25°C. This response can be expressed as follows: Equation 1 where, JC= Change in junction-case temperature ZthJC= Rectangular pulse derived from triangular pulse t= Triangular and Rectangular response time, and P= Power dissipated The application of Equation 1, without any modification cannot give precise information. In fact, a comparison between a rectangular and a triangular power pulse (both with the same peak), indicates that the peak temperature between them is quite different (see Figure 7.). To use the Zth, the triangular pulse can be approximated as rectangular pulse, with scaled amplitude and width. Another important concern about the use of thermal impedance is that usually it is experimentally and theoretically calculated according to the ON state of the device, so the normal power distribution within the device may be different from the one that occurs during the avalanche state. ST's approach to an EAS statement starts from a theoretical thermal model of the die with some experimental verifications. The T J(max) during an avalanche may be sterting from: Equation 2 where: tAV = Avalanche time (s), A = die area (m2), P0 = peak power (W), and K= the silicon‘s thermal constant (Wm-2 s1/2 K-1) This solution is derived from the general heat transmission equation (Fourier equation) for the special case where an infinite media (mono-dimensional case) is subordinated to a short rectangular power source pulse and uniformly distributed over a die area. Equation 2, when it is applied to a triangular power pulse, is a simple and good approximation to use for the temperature increase calculation within the device during the avalanche operation, if the pulse is of short duration. ∆Tjc Zth jc t() P= Tj

Figure 9. V DS/ID shapes with the Coil during the UIS

3.3.1 EAR (Energy during av alanche for repetitive pulse)

duty cycle and the nominal power rating of the device (see Equation 3).

AN2344 Datasheet avalanche ratings The total power includes the power conduction (PCOND) and switching (PSW) losses: Equation 6 The STW9NK80Z is used again as an example (see section 3.3 ), however, in this case, the avalanche is not a single event, but is repetitive, with a frequency, f=50kHz. For the single event example, when the current is below IAR and the TJ is below 150°C, the device works in a safe operating mode. When the device is subjected to repetitive avalanche events, it needs to be checked to see if it maintains the T J below 150°C. Since power dissipation for each avalanche pulse is 0.24mJ, the average avalanche power dissipation is expressed as: Equation 7 If the device has a junction-to-ambient thermal resistance (R thJA), Equation 8 and the average switching and conduction losses equal to 2W, Equation 9 then the average temperature is calculated as follows: Equation 10 Given that the average temperature and peak temperature during the avalanche should be higher, it is clear that the avalanche phenomenon is generating power so high that the system thermal behavior cannot dissipate in order to maintain the T J below TJ(max). The only solution is to reduce the thermal resistance of the system by changing the heat sink or redesigning the application to avoid the avalanche failure. In order to obtain a more accurate computation, the only way to evaluate the maximum temperature during repetitive avalanche is to calculate it by the Zth of the system. Despite all the concerns already discussed about adopting the published Zth for the avalanche (see Equation 1), the computation results for repetitive avalanche as given by manufacturers are sufficiently guardbanded for real world applications. Several methods can be used to find the steady-state maximum temperature during a steady-state or after a finite number of avalanche occurrences. The most frequently and sufficiently conservative equation used in order to find the maximum temperature for periodic rectangular power pulses at steady-state is: Equation 11 PTOT PCOND PSW PAV++= PAV Ef• 0.24mJ 50kHz• 12W=== RthJA RthJC RthCS RthSA 10° CW⁄=++= PTOT PCOND PSW PAV 2W 12W 14W=+=++= TJ PTOT R• thJA TA 140° CT A+=+= TJC max() P0 tp T----RthJC 1 tp T----–  Zth JC tp()+ =∆

• First pulse Equation 13
• Second pulse Equation 14
• Third pulse Equation 15

Figure 12. Thermal response comparison waveforms detailing the avalanche phenomenon. Table 2. Rectangular approximation of special power curves

0.7 P 1• Zth JC t1 tD1 t2+–() Zth JC tD1 t2+()–[]•+

0.7 P 1• Zth JC t1 tD1 t2 t3 tD3+++–() Zth JC tD1 t2 t3 tD3+++()–[]•+ * * +

0.89 P 2• Zth JC t2 t3 tD3++() Zth JC t3 tD3+()–• * * *+

• T= 12µs
• TCASE=70°C
• TON=40ns;
• TOFF=60ns
• tCOND=2.4µs
• tAV=86ns For the peak power calculation over the conduction state, it is assumed that the worst case RDS(ON) is: and, where, 2.4 is the derating factor found in the STP11NM60FP datasheet, in the plot showing the “normalized RDS(ON) vs. temperature".

Figure 13. Steady-state STP11NM60FP switching

Figure 16. Normalized STP11NM60FP impedante By using Equation 15, a more accurate TJ value at avalanche onset can be calculated.

• Pulse 1 (turn ON) Equation 22
• Pulse 2 (conduction) Equation 23
• Pulse 3 (turn OFF) Equation 24
• Pulse 4 (avalanche) Equation 25 Tj P AVE RthJC 0.7PPEAK AV() Zth JC 0.71tAV() TCASE++= Zth JC 61ns() 3.57 K• 61ns() 0.00125° CW⁄=≈ TJm a x() 45 2448 0.7 0.00125 70 117 ° C≈+••+= t1 40ns 0.71 28.4ns=•= td1 5.8ns= P1 0.7 256W 179W=•=** t3 60ns 0.71 43ns=•= td3 58ns= P3 0.7 672W 470W=•=* * t4 86ns 0.71 61ns=•= td4 12.5ns= P4 0.7 2448W 1714W=•=* *

Figure 17. STP11NM60FP rectangular pulse switching approximation absolute maximum ratings and consequently risk the Power MOSFET’s failure.

4 Conclusion

Here are a few reminders:

• The required verifications for single and repetitive avalanche is that TJ(max) and IAR must always be below the absolute maximum ratings in the DUT datasheet.
• Any high frequency repetitive avalanche may result in device failures, depending on the actual consistency of the heat sink used.
• All manufacturers' production testing is performed only for some milliseconds and that a “pass” is simply defined as a device that has survived without destructive damage.
• Stresses of highly localized peak temperatures and currents at the “microscopic” levels on the MOSFET are impossible to identify. All manufacturing processes are intended to produce uniform and consistent test results (e.g. Rb and Beta). but this does not mean that any single device amongst these, up to several thousands from a single wafer are perfect, even if it survives the short production test.
• The reliance on data sheet avalanche ratings, even if the in-circuit stresses are not carefully calculated or characterized, is motivated by a potentially significant circuit cost saving. The apparent respect of the ratings at certain standard “in lab” conditions cannot be easily and safely generalized to all normal or abnormal events that can happen in the real world application environment. Accepting and tolerating - at least as worst case - the use of the avalanche characteristics of the Power MOSFET in applications where such behavior is not strictly required, must take into account the risk of a reduced guard-band for withstanding events and any other variations that can be correlated with the application failure.

• Stout, R.P ., Billings, D.T. How to Extend the Thermal RC Network Model to Respond to an Arbitrary Fast Input. 14th IEEE SEMI-THERM, 1998.
• Sze, S.M. Physics of Semiconductor Devices. 2nd ed. Canada: John Wiley & Sons, Inc., 1981.
• Stoltenburg, R.R. gBoundary of Power MOS UIS Avalanche Current Capability.h IEEE Applied Power Electronics Conference Proceedings 359-64: (Mar 1989).
• McGloin, J., Sdrulla, D. Estimating the Temperature Rise of Power MOSFETs During the UIS Test. IEEE, 1992.
• Blackburn, David L. Power MOSFET Failure Revisited. PESC, 1988.

5 Revision history

Table 3. Revision history 02-Aug-2006 1 Initial release.