AN2208 STMICROELECTRONICS | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1 High-side driver description
- 2 VN808 reference design board
- 2.1 Circuit description
- 2.2 Surge suppression
- 2.3 Isolation recommendations
- 2.4 Heatsink recommendations
- 2.5 Schematic diagrams
- 3 VN340SP reference design board
- 3.1 Circuit description
- 3.2 Schematic diagrams
- 4 Load switching tests
- 5 Thermal stress test s
- 6 Electromagnetic compatibility (EMC) tests
- 6.1 Terminology
- 6.2 List of EMC test equipment
- 6.3 Requested test levels
- 6.3.1 IEC 61000-4-4
- 6.3.2 IEC 61000-4-5
- 6.3.3 IEC 61000-4-6
- 6.4 IEC 61000-4-4 EFT test setup
- 6.4.1 Power supply tests
- 6.4.2 Input port tests
- 6.4.3 Output port tests
- 6.5 IEC 61000-4-5 surge test setup
- 6.5.1 Power supply tests
- 6.5.2 Output port tests
- 6.6 IEC 61000-4-6 conducted immunity
- 6.6.1 Power supply tests
VN808/VN340SP high-side drivers are tested mounted on their respective reference design board (RDB). included in Section Appendix C: L5970D DC/DC converter on page 46. Figure 1. VN808 and VN340SP reference design boards
1 High-side driver description
threshold. The system oscillates depending on the thermal impedance of the application. Table 1. VN808 and VN340SP main characteristics
1 High-side driver description AN2208
Figure 2. VN808 block diagram Figure 3. VN340SP block diagram
2 VN808 reference design board
for an industrial environment.
2.1 Circuit description
VN808 reference design board. The VN808 reference design board uses multi-channel TLP281-4 and TLP181 optocouplers. Datasheet available at www.st.com. about designing boards to improve EMC immunity and performance in industrial environments.
2.2 Surge suppression
Figure 4. VN808 reference design board
2 VN808 reference design board AN2208
pulse power dissipation of 1500 W, stand-off voltage of 36 V and breakdown voltage of 37.8 V. An electrolytic capacitor (C1) must be placed immediately after the surge suppression block. easier with ST's high-side drivers.
2.3 Isolation recommendations
Industrial environments require good isolation between digital and power supply parts. solution. Figure 6 shows a schematic diagram with optocouplers connected to ground. respect to the other side as shown in Figure 7. optocouplers) as shown in Figure 52: VN808 RDB PCB layout (top and bottom). Figure 5. Surge Suppression Block
2.4 Heatsink recommendations
temperature during inductive switching, acts as a thermal capacitor. Figure 6. Typical input/status isolation by optocouplers Figure 7. Burst pulse affecting one input
sink area is 6 cm²). The recommended layout for Power SO packages is shown in Figure 8.
2.5 Schematic diagrams
Figure 8. Recommended layout for High Power Dissipation capability Figure 9. DC/DC part of the application circuit Figure 10. Current and voltage conventions
Figure 11. Complete application circuit with VN808 and L5970D devices
Figure 12. Switching part of the application circuit
3 VN340SP reference design board
applications for an industrial environment.
3.1 Circuit description
Transil diodes are the same as those used in the VN808 reference design board. Figure 13. VN340SP reference design board
3 VN340SP reference design board AN2208
3.2 Schematic diagrams
Figure 14. Switching part of the application circuit
Figure 15. Complete application circuit with VN340SP and L5970D devices
4 Load switching tests AN2208
4 Load switching tests
specifications are generally considered as the worst case. CC supply condition is between 18.5V and 28.5V DC. switch off the circuit, the bigger | VCLAMP | compared with | VCC | has to be. Note: Typical VCLAMP value for VN808 is 52V. structure, an integrated solution for fast switch-off of inductive loads. can be used only if thermal behavior and load conditions are well known to designers. mandatory to prevent improper utilization of the IPSs. Figure 16. Description of the switching inductor loads
Note: For more information about switching inductor loads, see Application Note AN1351. Figure 17. IPS simplified structure
5 Thermal stress tests AN2208
5 Thermal stress tests
Figure 18. RthJC and RthCA represent the junction-to-case and the case-to-ambient thermal Note: Case thermal time constant of 48 ms without external cooling. impedance, in order to minimize the chip temperature jump-up. 8 channels active, 4 channels working at the same time. Figure 18. Simplified thermal models
AN2208 5 Thermal stress tests If the PSO36 is on FR4, RthCA = 50°C/W tOFF = 1.6 ms << 48 ms (constant time of the PSO36) TC = TA + Pmean* RthCA TJMax during tOFF = 94 + (1.1 + (1.9/4))*52 = 175°C
6 Electromagnetic compatibility (EMC) tests AN2208
6 Electromagnetic compatibility (EMC) tests
specific product datasheet for electrostatic discharge (ESD) characteristics).
6.1 Terminology
Table 2. EMC industrial compliance Table 3. Abbreviations
6.2 List of EMC test equipment
6.3 Requested test levels
6.3.1 IEC 61000-4-4
- Polarity: positive/negative
- Test voltage: Level 4 (4 kV)
- Burst duration: 15 ms±20% at 5 kHz
- Burst period: 300 ms±20%
- Duration time: 60 seconds (min.)
- Applied to: Input/Output ports and Supply lines
6.3.2 IEC 61000-4-5
- Polarity: positive/negative
- Test voltage: Level 3 (2 kV)
- Number of Discharges: 5
- Repetition Rate: 1 per min.
- Applied to: Output ports and Supply lines (all combinations)
Table 4. Equipment list for EMC tests
6.3.3 IEC 61000-4-6
- Test voltage: Level 3 (10 V)
- Frequency range: 150 kHz to 80MHz
- Modulation: 80% depth by AM 1 kHz
- Frequency step: 1%
- Dwell Time 100 ms
- Applied to: Input/Output ports and Supply lines
6.4 IEC 61000-4-4 EFT test setup
6.4.1 Power supply tests
supply against the test voltage.
6.4.2 Input port tests
Maximum test voltage must not exceed 4 kV. Figure 19. Power supply tests (IEC 61000-4-4)
6.4.3 Output port tests
performed while the HSD output port is switched On/Off at 1 Hz. Maximum test voltage must not exceed 4 kV. Figure 20. Switch diagram Figure 21. Test on input ports (IEC 61000-4-4)
6.5 IEC 61000-4-5 surge test setup
on the power supply lines and output port.
6.5.1 Power supply tests
- Line-to-line coupling mode with source impedance 42Ω (meaning VCC 24V and GND_Power on the board, both polarities)
- Line-to-PE coupling mode with source impedance 42Ω (meaning VCC 24V/GND_Power to GND_earth on the board, both polarities)
- Output to GND_Power with source impedance 42Ω
- Output to VCC 24V with source impedance 42Ω
- Output to Protect Earth with source impedance 42Ω
Figure 22. Output port tests (IEC 61000-4-4)
at 1Hz. The maximum length of the cables between the EUT and CDN is 2 meters.
6.5.2 Output port tests
switched On/Off with both polarities. The output lines are tested between VCC /GND and PE.
6.6 IEC 61000-4-6 conducted immunity
same signal. The EUT clearance from all metallic objects must be at least 0.5 meters. Figure 23. Power supply tests (IEC 61000-4-5) Figure 24. Test on Output Ports (IEC 61000-4-5)
6.6.1 Power supply tests
must be placed on the wood isolation.
6.6.2 Input port tests
test is performed while the HSD input port is switched On/Off at 1Hz.
6.6.3 Output port tests
Figure 25. Power supply tests (IEC 61000-4-6) Figure 26. Input port tests (IEC 61000-4-6)
Figure 27. Output port tests (IEC 61000-4-6)
7 Test results AN2208
7 Test results
The following abbreviations are used in this section.
7.1 VN808 HSD test results
Table 5. Abbreviations Figure 28. VN808 Waveforms (Part 1)
7.1.1 Load switching test results
performed with different VCC values. Test Results: The VN808 HSD worked properly during the test. Figure 29. VN808 Waveforms (Part 2)
conditions: Power supply = 24V, Load = 24V /15W lamp, and HSD input = ON. If the HSD input is OFF , then the output will still switch OFF after GND_Power disconnection. Figure 30. GND_Power disconnection Figure 31. Switching lamps: VCC = 24V, f =
0.5 Hz, Wave1 = VINOPT ,
Figure 32. Waveform tOFF inductor load: VCC =
7.1.2 Thermal stress test results
- All channels shorted: fSWITCH = 0.5 Hz, VCC = 28V, duration 72 hours, TA = 25°C.
- All channels shorted: fSWITCH = 0.5 Hz, VCC = 28V, duration 8 hours, TA = 85°C.
- All channels shorted: fSWITCH = 0.5 Hz, VCC = 28V, duration 8 hours, TA = –25°C.
and 121°C with an ambient temperature of 85°C. Figure 33. Waveform switching inductive load: Figure 34. Switching with short circuit: VCC = Figure 35. Time delay between VINOPT and Figure 36. GND_Power disconnection for
HSD during the short circuit with different ambient temperature. The input is switched at 1 Hz. The thermal shutdown is active and the output channel is switched off because it is shorted. (without short circuit) as shown in Figure 39. coupler. No airflow present during the test. Figure 37. Waveform ITOT and VINOPT during Figure 38. Waveform on ITOT and VINOPT during Figure 39. Case temperature dependency vs. current ITOT (TA = 25°C and VCC = 24 V)
7.1.3 EMC test results
tests, all channels were switched. Test result: The VN808 HSD worked properly during the test. test was executed with ±2kV. only the tested channel was switched. A 4.7nF 500V capacitor was placed between the power supply and the earth protection. Table 6. EMC test IEC 61000-4-4 EFT test results (VN808 RDB) Figure 40. Burst applied on the power supply Figure 41. Burst applied on the output channel
rate was 1 discharge per minute. Test result: The VN808 HSD worked properly during the test. Level 3 (10V) compliance. Table 8 lists test results. Table 7. EMC test IEC61000-4-5 surge test results (VN808 RDB) Figure 42. Positive surge applied on power Figure 43. Negative surge applied on power
Test result: The VN808 HSD worked properly during the test.
7.2 VN340SP HSD test results
7.2.1 Load switching test results
Test result: The VN340SP HSD worked properly during the test. Figure 44 to Figure 49 show the waveforms during the load switching tests. is OFF , the output remains OFF .
7.2.2 Thermal stress test results
- All channels shorted: fSWITCH = 0.5 Hz, VCC = 28V, duration 72 hours, TA = 25°C.
- All channels shorted: fSWITCH = 0.5 Hz, VCC = 28V, duration 8 hours, TA = 85°C.
- All channels shorted: fSWITCH = 0.5 Hz, VCC = 28V, duration 8 hours, TA = –25°C.
Test result: The VN340SP HSD worked properly during the test. during the thermal stress tests. Table 8. EMC test IEC 61000-4-6 conducted immunity test results (VN808 RDB)
The input was switched at 1 Hz. The thermal shutdown is shown in the figures below. Figure 44. Switching lamps: VCC = 24V, f = Figure 45. Waveform tOFF inductor load: VCC = Figure 46. Time delay between VINOPT and Figure 47. Switching with short circuit: VCC =
7.2.3 EMC test results
output ports are tested while all other channels are active. Table 9 lists test results. Figure 48. Waveform switching inductive load: Figure 49. Switching with short circuit: VCC = Figure 50. Waveform ITOT and VSTATUSOPT Figure 51. Waveform on ITOT and VSTATUSOPT
Test result: The VN340SP HSD worked properly during the test. the test. Different combinations of channel activity were also tested. Table 10 lists test results. A 4.7nF 500V capacitor was placed between the power supply and earth protection. Test result: The VN340SP HSD worked properly during the test. The test was executed according the standard with required levels. Table 11 lists test results. Table 9. EMC test IEC 61000-4-4 EFT test results (VN340SP RDB) Table 10. EMC test IEC61000-4-5 surge test results (VN340SP RDB)
Table 11. EMC test IEC 61000-4-6 conducted immunity test results (VN340SP RDB)
The list of parts for the VN808 Reference Design Board is provided in Table 12. Table 12. VN808 RDB bill of materials
The list of parts for the VN340SP Reference Design Board is provided in Table 13. Table 13. VN340SP RDB bill of materials
in BCD5 technology and the power switching element is a P-Channel D-MOS power transistor. An internal oscillator sets the switching frequency at 250 kHz, minimizing the LC output filter. The L5970D is used for supplying optocouplers and other applications. L5970D is an attractive and simple solution. The main internal blocks are shown in Figure 56 where is reported the device block diagram.
- A voltage regulator that supplies the internal circuitry. From this regulator a 3.3V reference voltage is externally available.
- A voltage monitor circuit that checks the input and internal voltages.
- A fully integrated sawtooth oscillator whose frequency is 250 kHz ±5%, including also the voltage feed forward function and an input/output synchronization pin.
- Two embedded current limitations circuitries which control the current that flows through the power switch. The Pulse by Pulse Current Limit forces the power switch OFF cycle by cycle if the current reaches an internal threshold, while the Frequency Shifter reduces the switching frequency in order to strongly reduce the duty cycle.
- A transconductance error amplifier.
- A pulse width modulator (PWM) comparator and the relative logic circuitry necessary to drive the internal power.
- A high-side driver for the internal P-MOS switch.
- An inhibitor block for stand-by operation.
- A circuit to provide the thermal protection function.
Figure 56. L5970D block diagram
For more information and technical data about L5970D, refer to the L5970D datasheet. has to be kept short as possible. and so they should be as far as possible from the high current paths. device is connected to the ground plane directly with VIA on the bottom side of the PCB. Figure 57. L5970 DC/DC converter layout example
The DC/DC converter was tested with a constant output current with resistive load. The Waveform on coil L1 has to be clear without overshot (see Figure 61., Figure 63.). Input/output voltage ripple depends on ESR capacitor values.
- Resistive load = 12Ω.
- Input voltages VSS = 8, 12, and 24V.
- Output voltage VBSS = 5V
- Output current IOUTDC = 0.4A
- Ambient Temperature (TA) = 25°C Test results: If output current is increase up to 1.4 A, then the current limiter will be active. Output voltage ripple can be seen in Figure 62. The maximum value of ripple is 93 mV. The efficiency measurement results are shown in Figure 58.
Table 14. L5970D electrical characteristics Figure 58. Efficiency vs. output current
8 Revision history AN2208
8 Revision history
16-Sept-2005 1.0 Initial release.
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