AN2197 STMICROELECTRONICS | Alldatasheet

Document overview

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Technical content

Datasheet sections

  • 1 ST72F324 Migration: feature overview
  • 2 ST72F321 Migration: feature overview
  • 3 Feature compatibility
  • 3.1 Pinout
  • 3.2 VDD Rise time
  • 3.3 Asynchronous RESET pin
  • 3.4 Oscillator pad
  • 3.5 Clock Security System (CSS)
  • 4 Performance improvements
  • 5 New features and peripher als
  • 5.1 Clock Security System (CSS)
  • 6 Register map
  • 6.1 Register Address
  • 6.2 Register Modifications
  • 6.2.1 SICSR Register
  • 7 Limitations summary
  • 8 Revision History

microcontroller devices in applications originally designed for the ST72F324 and ST72F321 series. Note: Use ST72F325 if your application requires CSS (Clock Security System). Table 1. Migration cross-reference table

1 ST72F324 Migration: feature overview

Table 2. ST72F324 migration: feature overview Note 1: Refer to the corresponding datasheets for more information. Note 4: Go to http://www.st.com for information on third-party tools.

2 ST72F321 Migration: feature overview AN2187

2 ST72F321 Migration: feature overview

Table 3. ST72F321 Migration: feature overview Note 1: Refer to the corresponding datasheets for more information. Note 4: Go to http://www.st.com for information on third-party tools.

3 Feature compatibility

3.1 Pinout

Table 4. Addition of 8-bit PWMART and I 2C Alternate Function I/Os peripheral. N/A stands for not-available.

3.2 V DD Rise time

Table 5. VDD Rise time

3.3 Asynchronous RESET pin

respectively (see <Blue HT>Table 6). Table 6. RESET Pin Characteristics

3 Feature compatibility AN2187

3.4 Oscillator pad

The ST72F324B (32k Flash only), ST72F321B and ST72F325 devices feature a new oscillator pad which is more tolerant of the crystal type and is not disturbed if the oscillator pins are left unconnected. When migrating to these, devices the MCU needs to be validated with your existing resonator / crystal. Murata 16 MHz 3rd overtone oscillators are not recommended for ST72F324B (32k Flash), ST72F321B and ST72F325. For applications requiring a high precision f CPU at 8MHz, the preferred solution is to use 4 MHz + PLL. Note that the PLL jitter is improved compared to ST72F324 and ST72F321. Refer to the Electrical characteristics section of the datasheets.

3.5 Clock Security System (CSS)

CSS has been added in ST72F325 devices. The Clock Security System (CSS) protects the ST7 against main clock problems. To allow the integration of the security features in the applications, it is based on a clock filter control and an Internal safe oscillator. The CSS can be enabled or disabled by option byte. Please refer to the datasheet for more information.

AN2187 4 Performance improvements

4 Performance improvements

The ST72F324B, ST72F321B and ST72F325 devices feature many significant improvements such as:

  • Reduced PLL clock jitter
  • Lower power consumption
  • Improved A/D converter accuracy and negative injection on robust pins. Refer to the relevant datasheets for more details.

5 New features and peripherals AN2187

5 New features and peripherals

5.1 Clock Security System (CSS)

applications, it is based on a clock filter control and an Internal safe oscillator. Figure 1. ST72F325 Option Bytes Refer to the relevant datasheets for more details.

6 Register map

extra peripherals available in ST72F325 devices.

  • All “reserved” byte memory areas must never be “read” or “write”.
  • All “reserved” or “unused” bits must be left unchanged when accessing the byte.

6.1 Register Address

In ST72F325 devices, I2C and 8-bit PWMART are added as new features. Please, refer to the datasheet for the description of the new features. Figure 2. Register Map Modifications

6 Register map AN2187

6.2 Register Modifications

6.2.1 SICSR Register

Two bits related to CSS have been added in the SICSR (System Integrity Control/Status Register) register. Figure 3. SICSR Register Changes

0 AVDI

0 AVDIE AVDF LVDR

AN2187 7 Limitations summary

7 Limitations summary

For more details, refer to the KNOWN LIMITATIONS chapter at the end of each datasheet Note 1: refer to ELECTICAL CHARACTERISTICS chapter of the datasheet Note 2: no limitation if LVD is enabled. Note 3: Negative injection current on any of the analog input pins significantly reduces the accuracy of ADC. Note 4: When OSC1 or OSC2 is unconnected, main oscillator may overrun above the maximum frequency guaranteed. The product may then operates in unsafe / undefined state. Note 5: Vih(min) and Vil(max) on reset pin is 0.85xVdd and 0.16xVdd respectively. Note 6: ICC 39-pulse is not available for 8/16k Flash devices only Limitations ST72F324 ST72F321 ST72F324B ST72F321B ST72F325 Internal RC Oscillator Active Halt wake up by external interrupt XX ✔✔✔ Negative Injection current immunity on Analogic pins 1 XX ✔✔✔ Over frequency on OSC pad X4 X4 X4 ✔✔ CSS functionality XX X X ✔ Vih(min) / Vil(max) 0.7xVdd / 0.3xVdd on reset pin X5 X5 ✔✔✔ ICC mode entry with 39 pulses ✔✔ X6 ✔✔

8 Revision History AN2187

8 Revision History

04-Oct-2005 1 Initial release

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