AN211A

AN211A MOTOROLA | Alldatasheet

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2 MOTOROLA SEMICONDUCTOR APPLICATION INFORMATION

in long term instability and changes in device characteristics. structure is analogous to two diodes connected back to back. Figure 3. Junction FET with Single-Ended Geometry Figure 4. Development of Enhancement-Mode Freescale Semiconductor, Inc.

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*:/C0051% *:& ÍÍÍÍÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍÍÍÍÍ )!%+ *&,) ’ *,*+)+ % % % Figure 8. Channel Depletion Phenomenon. in Increased Channel Resistance.

ELECTRICAL CHARACTERISTICS

Because the basic mode of operation for field-effect devices differs greatly from that of conventional junction transistors, the terminology and specifications are necessarily different. An understanding of FET terminology and characteristics are necessary to evaluate their comparative merits from data-sheet specifications. Static Characteristics Static characteristics define the operation of an active device under the influence of applied dc operating conditions. Of primary interest are those specifications that indicate the effect of a control signal on the output current. The VGS – ID transfer characteristics curves are illustrated in Figure 9 for the three types of FETs. Figure 10 lists the data-sheet specifications normally employed to describe these curves, as well as the test circuits that yield the indicated specifications. Of additional interest is the special case of tetrode-connected devices in which the two gates are separately accessible for the application of a control signal. The pertinent specifications for a junction tetrode are those which define drain-current cutoff when one of the gates is connected to the source and the bias voltage is applied to the second gate. These are usually specified as VG1S(off), Gate 1 — source cutoff voltage (with Gate 2 connected to source), and VG2S(off), Gate 2 — source cutoff voltage (with Gate 1 connected to source). The gate voltage required for drain current cutoff with one of the gates connected to the -* - -/C0047*+ -/C0047*+ -/C0047*+ -* /C0048 /C0048 /C0048 /C0051 - %J %% +!&% % % +!&% % % -* -*C9 +!&% % % % % %+ &%#0 +!&% &%#0 +!&% % % % %+ $& /C0048 /C0048 %J %% # ",%+!&% %J %% # $&* %/C0051 %J %% # $&* %/C0051 -/C0047 -/C0047 -/C0047 =/C0047 =/C0047 !- ! =/C0047 !-! %&+ !% + !* ) Figure 9. Transfer Characteristics and Associated Scope Traces for the Three FET Types Freescale Semiconductor, Inc.

/C0078 5MOTOROLA SEMICONDUCTOR APPLICATION INFORMATION source is always higher than that for the triode-connected case where both gates are tied together. Reach-through voltage is another specification uniquely applicable to tetrode-connected devices. This defines the amount of difference voltage that may be applied to the two gates before the depletion region of one spreads into the junction of the other — causing an increase in gate current to some small specified value. Obviously, reach-through is an undesirable condition since it causes a decrease in input resistance as a result of an increased gate current, and large amounts of reach-through current can destroy the FET. Gate Leakage Current Of interest to circuit designers is the input resistance of an active component. For FETs, this characteristic is specified in the form of IGSS — the reverse-bias gate-to-source current with the drain shorted to the source (Figure 11). As might be expected, because the leakage current across a reverse-biased p-n junction (in the case of a JFET) and across a capacitor (in the case of a MOSFET) is very small, the input resistance is extremely high. At a temperature of 25°C, the JFET input resistance is hundreds of megohms while that of a MOSFET is even greater. For junction devices, however, input resistance may decrease by several orders of magnitude as temperature is raised to 150°C. Such devices, therefore, have gate-leakage current specified at two temperatures. Insulated-gate FETs are not drastically affected by temperature, and their input resistance remains extremely high even at elevated temperatures. Gate leakage current may also be specified as IGDO (leakage between gate and drain with the source open), or as IGSO (leakage between gate and source with the drain open). These usually result in lower values of leakage current and do not represent worst-case conditions. The IGSS specification, therefore, is usually preferred by the user. Voltage Breakdown A variety of specifications can be used to indicate the maximum voltage that may be applied to various elements of a FET. Among those in common use are the following: V(BR)GSS = Gate-to-source breakdown voltage V(BR)DGO = Drain-to-gate breakdown voltage V(BR)DSX = Drain-to-source breakdown voltage (normally used only for MOSFETs) In addition, there may be ratings and specifications indicating the maximum voltages that may be applied between the individual gates and the drain and source (for tetrode connected devices). Obviously, not all of these specifications are found on every data sheet since some of them provide the same information in somewhat different form. By understanding the various breakdown mechanisms, however, the reader should be able to interpret the intent of each specification and rating. For example: In junction FETs, the maximum voltage that may be applied between any two terminals is the lowest voltage that will lead to breakdown or avalanche of the gate junction. To measure V (BR)GSS (Figure 12a), an increasingly higher reverse voltage is applied between the gate and the source. Junction breakdown is indicated by an increase in gate current (beyond IGSS ) which signals the beginning of avalanche. Some reflection will reveal that for junction FETs, the V (BR)DGO specification really provides the same information as V(BR)GSS . For this measurement, an increasing voltage is applied between drain and gate. When this applied voltage becomes high enough, the drain-gate junction will go into avalanche, indicated either by a significant increase in drain current or by an increase in gate current (beyond IDGO ). For both V(BR)DGO and V (BR)GSS specifications, breakdown should normally occur at the same voltage value. From Figure 2 it is seen that avalanche occurs at a lower value of VDS when the gate is reverse biased than for the zero-bias condition. This is caused by the fact that the reverse-bias gate voltage adds to the drain voltage, thereby increasing the effective voltage across the junction. The maximum amount of drain-source voltage that may be applied VDS(max) is, therefore, equal to V(BR)DGO minus VGS , which indicates avalanche with reverse bias gate voltage applied. For MOSFETs, the breakdown mechanism is somewhat different. Consider, for example, the enhancement-mode structure of Figure 5. Here, the gate is completely insulated from the drain, source, and channel by an oxide-nitride layer. The breakdown voltage between the gate and any of the other elements, therefore, is dependent on the thickness and purity of this insulating layer, and represents the voltage that will physically puncture the layer. Consequently, the voltage must be specified separately. The drain-to-source breakdown is a different matter. For enhancement mode devices, with the gate connected to the source (the cutoff condition) and the substrate floating, there is no effective channel between drain and source and the applied drain-source voltage appears across two opposed series diodes, represented by the source-to-substrate and substrate-to-drain junctions. Drain current remains at a very low level (picoamperes) as drain voltage is increased until the drain voltage reaches a value that causes reverse (avalanche) breakdown of the diodes. This particular condition, represented by V(BR)DSS , is indicated by an increase in ID above the IDSS level, as shown in Figure 12b. For depletion/enhancement mode devices, the V(BR)DSS symbol is sometimes replaced by V(BR)DSX . Note that the principal difference between the two symbols is the replacement of the last subscript s with the subscript x. Whereas the s normally indicates that the gate is shorted to the source, the x indicates that the gate is biased to cutoff or beyond. To achieve cutoff in these devices, a depleting bias voltage must be applied to the gate, Figure 12b. An important static characteristic for switching FETs is the “on” drain-source voltage VDS(on). This characteristic for the MOSFETs is a function of VGS , and resembles the VCE(sat) versus IB characteristics of junction transistors. The curve for these characteristics can be used as a design guide to determine the minimum gate voltage necessary to achieve a specified output logic level. Dynamic Characteristics Unlike the static characteristics, the dynamic characteristics of field-effect transistors apply equally to all FETs. The conditions and presentation of the dynamic characteristics, however, depend largely upon the intended application. For example, the following table indicates the dynamic characteristics needed to adequately describe a FET for various applications. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

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Figure 10. Static Characteristics for the Three FET Types Are Defined by the Above Curves, Tables, and Test Circuits Figure 11. Test Circuit for Leakage Current Freescale Semiconductor, Inc.

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Figure 14. Forward Transfer Admittance versus Drain Figure 15. Forward Transfer Admittance versus Figure 16. yos Measurement Circuit for Depletion FETs at 1 kHz and in complex form at high frequencies. transistor registration format but can be calculated as yfs/yos. of the quality of the field-effect manufacturing process. takes the place of yis in low-frequency field-effect transistors. This is because yis is entirely capacitive at low frequencies. necessary for tetrode-connected devices. and Gate 1 tied to Gate 2 are necessary. a large voltage swing at the gate must appear across Ciss. capacitance for the chopper drive. field-effect transistors generate a certain amount of noise. designer can anticipate the noise level inherent in his design. Freescale Semiconductor, Inc.

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C d(sub) and rds are of primary interest. enough to perform adequately in the circuit of Figure 21. in turn, is set by the potentiometer in the source of the FET. higher series resistance (rds(on)) than the junction transistor. applications of FETs should broaden considerably. transistors have generally been least successful. Figure 21. RF Stage of Broadcast Auto Radio Figure 22. Line Operated Phono Amplifiers Freescale Semiconductor, Inc.

Figure 23. FET Chopper Circuits Freescale Semiconductor, Inc.

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Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Literature Distribution Centers: USA: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. EUROPE: Motorola Ltd.; European Literature Centre; 88 Tanners Drive, Blakelands, Milton Keynes, MK14 5BP, England. JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141, Japan. AN211A/D◊ Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...