AN2115 STMICROELECTRONICS | Alldatasheet

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Technical content

Datasheet sections

  • 1 Device description
  • 2 Pin function
  • 3 Block diagram
  • 4 Operation description
  • 4.1 Light load modes of operation
  • 4.2 Low consumption mode
  • 4.2.1 Low noise mode
  • 4.3 System stability
  • 4.3.1 Current loop compensation
  • 4.3.2 Voltage loop compensation
  • 4.4 Short circuit protection
  • 5 Synchronization
  • 5.1 Dropout operation
  • 5.2 PGOOD (Power good output)
  • 5.3 Adjustable output voltage
  • 5.4 OVP (overvoltage protection)
  • 5.5 Thermal shutdown
  • 6 Application information
  • 6.1 External component selection
  • 6.1.1 Input capacitor
  • 6.1.2 Output capacitor
  • 6.1.3 Inductor
  • 6.1.4 Compensation network (R1 C3)
  • 6.2 Application losses and efficiency
  • 6.2.1 Conduction losses
  • 6.2.2 Switching losses
  • 6.2.3 Gate charge losses
  • 6.2.4 Thermal consideration

This application note details the main features and application advantages of the L6928. is provided to aid in the selection of the external components and evaluation of the losses. conclusion of this document a few application ideas are provided. Figure 1. Minimum application board size

1 Device description

such as PDAs and hand-held terminals, DSCs (digital still cameras) and cellular phones. current short circuit protection, Power Good (power good output) and thermal shutdown. components, allows for very compact applications. Figure 2. Minimum size application circuit Figure 3. Pin connection Figure 4. Package

2 Pin function

Table 1. Pin description working. When high (above 1.3 V) the device is enabled. This pin must not be left floating. capacitor is sufficient to guarantee loop stability (see related section). external resistor divider from 0.6 V up to the input voltage. 5 LX Switch output node. This pin is internally c onnected to the drain of the internal switches. from 2 V to 5.5 V. An internal UVLO circuit generates a 200 mV (typ.) hysteresis.

7 SYNC

Operating mode selector input. When high (above 1.3 V) Low Consumption Mode is selected. and the device works at the same switching frequency. This pin must not be left floating.

8 PGOOD

3 Block diagram

Figure 5. Block diagram

AN2115 Operation description Doc ID 11165 Rev 5 9/33

4 Operation description

The main loop uses a constant frequency peak current mode architecture. Each cycle, the high side MOSFET is turned on, triggered by the oscillator, so that the current flowing through it (which is the same as the inductor current) increases. When this current reaches the threshold (set by the output of the error amplifier E/A, the peak current limit comparator, PEAK_CL, turns off the high side MOSFET and turns on the low side MOSFET until the next clock cycle begins, or if the current flowing through it decreases to zero (ZERO CROSSING comparator). In particular, the error amplifier output is dependent on the FB pin voltage. When the output current increases, the output capacitor is discharged and so the FB pin voltage decreases. This produces an increase in the error amplifier output, allowing a higher value for the peak inductor current. For the same reason, when the output current decreases due to a load transient, the error amplifier output goes low, thus reducing the peak inductor current to meet the new load requirements. The system includes a slope compensation signal, added to the sensed high side ramp current, which provides loop stability even in high duty cycle conditions (see related section).

4.1 Light load modes of operation

Depending on the SYNC pin value, the device can operate in LCM (low consumption mode) or LNM (low noise mode). If the SYNC pin is high (greater than 1.3 V) low consumption mode is selected while low noise mode is selected if the SYNC pin is low (less than 0.5 V).

4.2 Low consumption mode

In this mode of operation, the device operates discontinuously based on the COMP pin voltage in order to maintain very high efficiency even in light load conditions. When the device is not switching, the load discharges the output capacitor and the output voltage decreases. When the feedback voltage goes below the internal reference, the COMP pin voltage increases, and when an internal threshold is reached the device begins to switch. In this condition the peak current limit is set in the range of approximately 200 mA - 400 mA, depending on the slope compensation (see related section). Once the device starts to switch, the output capacitor is recharged. The feedback pin voltage increases and, when it reaches a value slightly higher than the reference voltage, the output of the error amplifier decreases until a clamp is activated. At this point the device stops switching. In this phase, most of the internal circuitry is off, reducing the device’s consumption down to a typical value of 25 µA.

4.2.1 Low noise mode

If for noise considerations, the very low frequencies of low consumption mode are undesirable, low noise mode can be selected. In low noise mode, efficiency is slightly lower compared to low consumption mode in very light load conditions, but for medium-high load currents the efficiency values are very similar.

4.3 System stability

after the load steps required by the application.

4.3.1 Current loop compensation

intrinsic peak current measurement which simplifies the current limit protection. from the control value, which is the E/A output voltage). implemented from a duty cycle of around 25% - 30%, as shown in Figure 8. Figure 8. Slope compensation changing the output voltage will also change the maximum output load. time. This slope, for a given duty cycle, is inversely proportional to the inductor value.

OFF time inductor current slope) is directly proportional to the input voltage. depends both on the switching frequency and input voltage. to the LC double pole (the pole splitting effect will not be present).

4.3.2 Voltage loop compensation

source), while the pole due to the output capacitor will remain within the bandwidth. Table 2. Minimum inductor value to ensure loop stability

Figure 9. Equivalent circuit for voltage loop analysis frequency based on the load value. integrator stage, the transfer function of which is shown in Equation 2. placed at half of the switching frequency.

4.4 Short circuit protection

switch is accurately sensed. cycle, the inductor current will likewise increase cycle by cycle. Figure 10. Equivalent buck converter circuit (during ON time) Figure 11. Equivalent buck converter circuit (during OFF time) negative slope on the parasitic resistances.

5 Synchronization

The device can also be synchronized with an external signal from 1 MHz up to 2 MHz through the internal PLL. When the device is locked, the external signal and the high side turn on rising edges are aligned. In this case, low noise mode is automatically selected. The device could skip some cycles in very light load conditions depending on the input/output conditions. The internal synchronization circuit is inhibited in short circuit and overvoltage conditions in order to keep the protections effective (see relative sections). The synchronization signal amplitude can range typically from 1 V to V CC and the duty factor can range typically from 20% to 80%. Occasionally, if the synchronization signal duty cycle is very similar to the application duty factor, a jittering can be detected on the LX pin. In this case some practical solutions are listed below: 1. Change the synchronization signal duty factor. 2. Decrease the synchronization signal amplitude. 3. Add a 20 pF capacitor between the COMP pin and ground. The device switches at 1.4 MHz (typ.) if no synchronization signal is applied.

5.1 Dropout operation

The Li-Ion battery voltage ranges from approximately 3 V to 4.2 V (depending on the anode material). If the regulated output voltage is from 2.5 V and 3.3 V, it is possible for the battery voltage to decrease to the regulated voltage near the end of battery life. In this case, the device stops switching and works at 100% of duty cycle, minimizing the dropout voltage and the device losses. The minimum input voltage necessary to ensure output regulation can be calculated as: Equation 8 Where R DS(on)_HS_MAX is the maximum high side resistance and RL is the series inductor resistance.

5.2 PGOOD (Power Good output)

The device also features a Power Good output signal. The VFB pin is internally connected to a comparator with a threshold set at 90% of the reference voltage (0.6 V). Since the output voltage is connected to the V FB pin by a resistor divider, when the output voltage goes lower than the regulated value, the VFB pin voltage goes lower than 90% of the internal reference value. The internal comparator is triggered and the Power Good pin is pulled down. The pin is an open drain output, so it should be connected to a pull up resistor. If the feature is not required, the pin can be left floating.

5.3 Adjustable output voltage

The output voltage can be adjusted by an external resistor divider from a minimum value of 0.6 V up to the input voltage. The output voltage value is given by: Vin MIN– Vo Io RDS on() HS– MAX– RL+()•+=

Thanks to the very low FB leakage current (25 nA), high R3 and R2 values can be chosen (hundreds of kΩ) which increase system efficiency at very low load.

5.4 OVP (overvoltage protection)

The device is equipped with an internal overvoltage protection circuit to protect the load. If the voltage at the feedback pin goes higher than an internal threshold set at 10% (typ.) higher than the reference voltage, the low side MOSFET is turned on until the feedback voltage goes lower than the reference voltage. During overvoltage circuit intervention, the zero crossing comparator is disabled so that the device is also able to sink current.

5.5 Thermal shutdown

The device also has thermal shutdown protection, which is activated when the junction temperature reaches 155 °C. In this case both the high and low side MOSFETs are turned off. Once the junction temperature goes back below 95 °C, the device resumes normal operation. Vout 0.6 1 R3 ⎛⎞•=

6 Application information

6.1 External component selection

6.1.1 Input capacitor

6.1.2 Output capacitor

The output capacitor is very important for satisfying the output voltage ripple requirement. Table 3. Recommended input capacitors

This ripple, multiplied by the ESR of the output capacitor, is the output voltage ripple. provides some capacitor manufacturers.

6.1.3 Inductor

This is particularly important when using ferrite cores because they can saturate severely. causing an abrupt increase in the current flowing through it. paragraph regarding slope compensation). value can decrease efficiency. In the following table some inductor manufacturers are listed. Table 4. Recommended output capacitors

6.1.4 Compensation network (R 1 C3)

The nearest standard E12 series value is R1 = 24 kΩ. Table 5. Recommended inductors

If the output capacitors are of the tantalum type, the ESR zero is within the system bandwidth and it can be used to stabilize the system so that the zero due to the compensation network will be rendered unnecessary.

6.2 Application los ses and efficiency

There are many losses affecting the efficiency of the application. Some of these losses are related to the device and others are related to the external components. The most important losses are described below.

6.2.1 Conduction losses

These losses are basically due to the significant resistances of the internal switches and the external inductor. Usually the current ripple across the inductor is negligible and so to estimate the conduction losses of the inductor, the average output current can be considered. The conduction losses of the switches depend also on the duty cycle of the application. The RMS current flowing through the high side MOSFET is (I o)2D, while the RMS current flowing through the low side MOSFET is (Io)2 (1-D). So, the total conduction losses of the application are: Equation 18 Where RON-HS and RON-LS are the series resistances of the high side and low side MOSFETs respectively, and RL is the series resistance of the inductor. The conduction losses due to the ESR of the input and output capacitors are usually negligible, particularly when using ceramic caps (very low ESR). In any case, when the ESR values for these caps are high, their conduction losses are: Equation 19 Where ΔI is the current ripple flowing through the choke and D the duty cycle of the application. The conduction losses are particularly important at high current cause they depend on its squared value.

6.2.2 Switching losses

The switching losses are due to the turning on and off of the internal high side MOSFET. Equation 20 where TON and TOFF are the turn on and turn off times of the internal high side switch. These are approximately in the range of 15 ns to 20 ns.This loss is important at high frequency. PMOS Io

2 RON HS– D() RON LS– 1D–() RL+•+•()•=

PCIN COUT, Io

2 D1 D –()•() ESR CIN

ΔI2 PSWITCHING Vin Io• FSW• TON TOFF+()

6.2.3 Gate charge losses

MOSFETs) are charged and discharged with the input voltage at the switching frequency. are usually negligible compared with the conduction and switching losses.

6.2.4 Thermal consideration

junction to ambient of the package and Ptot is the overall power dissipated by the device. Figure 13. Thermal perf ormance results: Vin = 3.7 V, Vout = 1.8 V, Iout = 800 mA board, which is described in the following paragraph.

2 CH CL+()• FSW•=

Figure 14. R DS(on) vs. temperature with the temperature of the MOSFET’s RDS(on), as shown in the Figure 14.

7 Application board

7.0.1 Demonstration board

The illustrations below show the layout of the demonstration board. Figure 15. Component placement Figure 16. Top side view Figure 17. Bottom side view

8 Demonstration board schematic

The very small package and high switching frequency allow for a very compact application. Figure 18. Schematic of the demonstration board Table 6. Demonstration board parts list

9 Efficiency results

Some efficiency results are shown in the figures below. Figure 19. Low noise vs. low consumption efficiency Figure 20. Efficiency vs. output current

10.1 Buck boost topology

etc. Moreover, in certain applications the output voltage requirements can also change. systems, a 3.3 V output is normally required to power the processor I/O, memory and logic. on the battery type and conditions, this would leave unused some 20 - 40% of its capacity. or more can be required to power the RF power amplifier (PA). gain in battery capacity due to the fact that it is used over the full voltage range. Figure 23. Positive buck boost applicat ion. 1 Li-Ion cell to 3.3 V@0.25 A

10.2 White LEDs

on the input source, appropriate topologies must be used.

10.2.1 Driving white LEDs: buck topology

approximately 4.5 V, which is the case, for example, with a USB bus. Figure 24. Buck LED In this case, the maximum device current (800 mA, continuous) can be delivered to the LED. Moreover, in this topology the efficiency is maximized.

10.2.2 Driving white LEDs: boost topology

NiMH battery cells) a boost topology must be implemented, as shown in Figure 25. Figure 25. Boost LED

that a path between the input and output is always present. even when the device is turned off.

10.2.3 Driving white L EDs: buck boost topology

Figure 26. Buck boost LED that when the device is turned off there is no current path between the input and the output. Figure 27. Another way to implement LED dimming is by changing the voltage of the

Table 7. Document revision history