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© Motorola, Inc., 2001 AN2104 Using Background Debug Mode for the M68HC12 Family By Timothy J. Airaudi Applications Engineering, Microcontroller Division Austin, Texas Introduction This application note describes the basic operation of the background debug mode (BDM) and some of its applications, as it relates to Motorola’s M68HC12 Family of microcontrollers (MCU). Examples of in- circuit programming of internal FLASH memory and in-circuit debugging, using P&E Microcomputer Systems’ BDM interface cable and its software, are also contained in this document. The BDM’s main purpose is to allow debugging of the actual microcontroller being used in the user’s target application. This takes the place of hardware such as an in-circuit emulator, which uses external components to attempt to duplicate operation of the MCU from outside of the target application. Instead of having this external hardware, and a variety of potential problems, the debug logic is built into the MCU’s on-chip integration module. This differs from other systems that have the debugging logic located in the central processor unit (CPU). Not having the debugging logic in the CPU allows for reading and writing of memory locations, while the CPU is executing user code, with no degradation in real-time operation. This is an example of the BDM being enabled but not active. Freescale Sem iconductor, I For More Information On This Product, Go to: www.freescale.com nc...

Figure 2. BDM Tool Connector for synchronization is allowed. per bit. The E-clock is defined as the SYSCLK divided by two.

  • Hardware
  • Firmware When using hardware commands, the BDM is enabled, but not active, and the user’s code is running. SeeTable 1. These commands allow all internal and external memory, which is accessible to the microcontroller, to be read or written. This also includes on-chip I/O (input/output) and control registers. The control logic watches the bus for any free bus cycles that it can use to execute the hardware command. By using the free bus cycles, the CPU is not disturbed. If, however, a free cycle is not found within a specified time, it will use a bus cycle, which temporarily freezes the CPU. RESET BKGD VDD GND VFP NC Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Table 1. BDM Hardware Commands BACKGROUND 90 None Enter background mode (if firmware enabled). data for even address on high byte. 1000 0000 (out)READ_BD_BYTE $FF01. BGND instruction is allowed. (waiting for single wire serial command). external access) must be aligned access. byte, data for even address on high byte. cycles if external access) must be aligned access. data for even address on high byte. write the result back to STATUS. external access) must be aligned access. data for even address on high byte. if external access) must be aligned access.

  1. STATUS command is a specific case of the READ_BD_BYTE command.
  2. ENABLE_FIRMARE is a specific case of the WRITE_BD_BYTE command.

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CPU, which executes code out of the BDM ROM. Table 2. BDM Firmware Commands Freescale Semiconductor, Inc.

data than the normal memory mapped locations for these addresses.

  • BDM status register (STATUS)
  • BDM CCR (condition code register) holding register (CCRSAV) The BDM status register can be read at any time, but must not be written to during BDM operation. SeeFigure 3 for a description of the bits. This register can be read or written by BDM commands or firmware. ENBDM — Enable BDM Bit (permit active background debug mode) 0 = BDM cannot be made active (hardware commands still allowed). 1 = BDM can be made active to allow firmware commands.

Table 3. BDM Registers Figure 3. BDM Status Register (STATUS) Freescale Semiconductor, Inc.

firmware-based instructions. from the user’s program upon entering the BDM. SeeFigure 4.

  • When the CPU gets the command to go into the BDM, the user’s return address is stored in a temporary register.
  • Next, the BDM ROM is turned on and the CPU fetches a vector that points to the beginning of the BDM firmware program. Address: $FF06 Bit 7 654321 Bit 0 Read: CCR7 CCR6 CCR5 CCR4 CCR3 CCR2 CCR1 CCR0 Write: Reset: 00000000

Figure 4. BDM CCR Holding Register (CCRSAV) Freescale Semiconductor, Inc.

  • Next the BDM firmware saves the contents of the user’s D register in another temporary register and then saves the user’s CCR register in the CCRSAV register.
  • The BDM firmware then checks the ENBDM bit in the STATUS register to see if it will be allowed to go into the active BDM. If it is, the BDM firmware enters a software loop and waits for a valid firmware command in which to execute. The user’s program counter (PC), stack pointer (SP), and X and Y registers are not changed by the BDM firmware, so the user doesn’t need to save or stack these values. During exit from the BDM, the user’s register values are restored and a value is stored in the BDM STATUS register. Then a jump command is executed to resume execution of the user’s program. M68HC12 Operating Modes The two basic modes of operation (seeTable 4) for the M68HC12 Family are:
  • Normal modes — Provide protection for control registers from being accidentally modified
  • Special modes — Allow access to these control registers for system development and special testing If any of the normal operating modes are entered (BKGD high), the BDM is available, but must be enabled and/or made active. If the special single-chip mode is selected (BKGD, MODA, and MODB all low), the BDM comes up enabled and active. Table 4also shows that the states of the BKGD, MODA, and MODB pins determine a specific mode where the port A and port B pins are configured for different functions. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

register after the part is powered up. SeeFigure 5. change can be done only once. long as the part remains in special mode. Table 4. Mode Selection

110 Reserved

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Background Debug Mode Application Examples AN2104

  • When in normal operating mode, another normal operating mode can be accessed, but this can be done only once.
  • To change to the normal operating mode, when the part is in special operating mode, a 1 (one) must be written twice to the SMODN bit in the mode register.
  • When the part comes up in special single-chip mode, the BDM is enabled and active.
  • When the part comes up in special single-chip mode, it accesses the BDM ROM, not the normal memory mapped locations at $FF00–$FFFF.
  • To perform hardware commands, the BDM does not need to be active (seeTable 1).
  • To perform firmware commands, the BDM must be enabled and active (seeTable 2).
  • The BDM does not operate in stop mode. Background Debug Mode Application Examples Two BDM application examples are given here in a step-by-step format. In-Circuit Programming of Internal FLASH This application example of the BDM explains how to perform in-circuit programming of the internal FLASH memory of an MC68HC912B32 using P&E Microcomputer Systems’ Cable12 POD and software (see Figure 1). The target board for this example is the M68EVB912B32 evaluation board. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Follow these steps in order: 1. Load P&E’s PKG12Z software. 2. Connect a parallel cable from the host PC to the Cable12 POD. 3. Connect the 6-pin BDM cable from the POD to the evaluation board making sure that pin 1 of the cable is connected to pin 1 of the POD and target. On the evaluation board, make sure that jumpers W3 and W4 are in the EVB positions and jumper W7 is in the VDD position. 4. Apply +5 Vdc to P5 of the evaluation board and +12 Vdc to W8. 5. Launch P&E’s WinIDE. 6. Open P&E’s sample code named SCI. 7. Assemble/compile this file. SeeFigure 6. 8. Launch the programmer. If the correction assistant window opens, select the correct parallel port being used. Defaults should work for the other options in this window. SeeFigure 7. 9. Select the 9b32_32k.12p programming algorithm. 10. Input $8000 for the base address when prompted. 11. Move jumper W7, on the evaluation board, to the VPP position. 12. SelectErase Module. 13. Ensure that the SCI.s19 file is in the S-record in the configuration window. If not, selectSpecify S recordand select this file. 14. SelectProgram Module. 15. After programming is complete, move jumper W7 to the VDD position. Do not leave the programming voltage on the FLASH. 16. The SCI.s19 file has now been erased and programmed into the FLASH of the MC68HC912B32 using the BDM. SelectVerify Module to verify that this programming is correct. The code also can be viewed by selectingShow Module at address $8000. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Figure 6. P&E’s WinIDE Window Freescale Semiconductor, Inc.

Figure 7. P&E’s Programmer Window example will be the M68EVB912B32 evaluation board.

  1. Load P&E’s PKG12Z software.
  2. Connect a parallel cable from the host PC to the Cable12 POD.
  3. Connect the 6-pin BDM cable from the POD to the evaluation

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Background Debug Mode Application Examples AN2104 jumpers W3 and W4 are in the EVB positions and jumper W7 is in the VDD position. 4. Apply +5 Vdc to P5 of the evaluation board. 5. Launch P&E’s WinIDE. 6. Open P&E’s sample code named SCI. 7. Assemble/compile this file. SeeFigure 6. At this point, ensure that the FLASH is programmed as in the previous application example inIn-Circuit Programming of Internal FLASH. 8. Launch the debugger. If the correction assistant window opens, select the correct parallel port being used. Defaults should work for the other options in this window. SeeFigure 8. 9. Verify that the correct S19 is loaded in the debugger by selecting theFile drop down menu and selectingLoad S19 File and the SCI.S19 file. 10. In theExecute drop down menu, selectReset Processor. 11. From this point, the code can be debugged by selectingSingle step,Multiple step, orGo . Breakpoints also can be set by selecting the line of code chosen for a breakpoint, clicking the right mouse button, and selectingToggle Breakpoint at Cursor. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Figure 8. P&E’s Debugger Window the FLASH in the target application. Freescale Semiconductor, Inc.

  • Software and Hardware Engineering: Motorola M68HC12 by Fredrick M. and James M. Sibigtroth
  • CPU12 Reference Manual, document order number CPU12RM/AD
  • M68HC12B Family Advance Information, Motorola document order number M68HC12B/D
  • MC68HC812A4 Advance Information, Motorola document order number MC68HC812A4/D
  • MC68HC912D60 Advance Information, Motorola document order number MC68HC912D60/D
  • MC68HC912DG128 Advance Information, Motorola document order number MC68HC912DG128/D Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

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NON-DISCLOSURE AGREEMENT REQUIRED Application Note Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...