AN2021

AN2021 STMICROELECTRONICS | Alldatasheet

Document overview

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• PDF pages: 39

Technical content

Datasheet sections

• 1 Modified features
• 1.1 Pinout
• 1.1.1 Pinout modification summary
• 1.1.2 Pin
• 1.1.3 Pin
• 1.1.4 Pin
• 1.1.5 Pins 143 and
• 1.2 XRAM
• 1.2.1 ST10F272B’s XRAM
• 1.2.2 ST10F272E’s XRAM
• 1.3 Flash EEPROM
• 1.3.1 Hardware impact
• 1.3.2 Software impact
• 1.4 A/D converter
• 1.4.1 Hardware / Software impact: conversion timing control
• 1.4.2 Hardware impact: electrical characteristics
• 1.4.3 Software impact
• 1.5 Real time clock
• 1.5.1 Hardware impact
• 1.5.2 Software impact
• 1.6 CAN modules
• 1.6.1 Hardware impact
• 1.6.2 Software impact
• 1.7 Port input control
• 1.7.1 Hardware impact
• 1.7.2 Software impact
• 1.8 Ports output control
• 1.8.1 Hardware impact
• 1.8.2 Software impact
• 1.9 PLL and main on-chip oscillator
• 1.9.1 Hardware impact
• 1.9.2 Software impact

Datasheet sections

• 5.1.1 Absolute maximum ratings
• 5.1.2 Overview of the DC characteristics
• 5.2 AC characteristics at 40 MHz
• 5.2.1 External memory bus timings
• 5.2.2 Hi-speed synchronous serial interface (SSC)
• 6 Referenced documents
• 7 Revision history

Porting an application from the ST10F269 to the ST10F272B/E Introduction The ST10F272B and ST10F272E are members of the STMicroelectronics ST10 family of 16-bit single-chip CMOS microcontrollers. They are functionally upward compatible with the ST10F269. The ST10F272B and the ST10F272E devices differ only in terms of XRAM memory size and XPeripherals. In this application note, the ST10F272B and ST10F272E will be referred to as ST10F272 for all aspects that are applicable to both products. For points specific to each product, the full name with the B or E extension will be used. The goal of this document is to highlight the differences between ST10F269 and ST10F272 devices. It is intended for hardware or software designers who are adapting an existing application based on the ST10F269 to the ST10F272. This document presents the ST10F272’s modified functionalities and the new ones, and goes on to describe the modified and the new registers. For each part, the differences with the ST10F269 that may have an impact when replacing the ST10F269 by the ST10F272 are stressed and some advice is given on the way they can be handled.

1 Modified features

1.1 Pinout

1.1.1 Pinout modification summary

Table 1 summarizes the modifications made to the pinout.

1.1.2 Pin 17

the pin 17 (named DC2) and the nearest VSS pin. This is no longer the case for the ST10F272 device where pin 17 is a VDD pin. Table 1. Pinout modifications

17 DC2

Internal voltage regulator decoupling.

56 DC1

Internal voltage regulator decoupling. Internal voltage regulator decoupling. according to level during reset. supply input for the standby mode. ground to avoid consumption.

1.1.3 Pin 56

On the ST10F269, a decoupling capacitor of 330nF minimum has to be connected between the pin 56 (named DC1) and the nearest VSS pin. On the ST10F272, pin 56 is named V18 and a capacitor of value between 10nF minimum and 100nF maximum must be connected between it and the nearest VSS pin. Hardware impact Change on the capacitor value. As the value is much lower, the footprint of the capacitor might be smaller and then a modification of the PCB is needed. Software impact None.

1.1.4 Pin 99

On the ST10F269, pin 99 is EA and used upon reset to select the start from the internal Flash memory or the external memory. On the ST10F272, pin 99 has the additional function of providing the 5V power supply to the device in standby mode (new power-saving mode), it is called EA-VSTBY. Hardware impact The modification depends on the previous use of the ST10F269 and on whether the Standby mode is used or not. For an application where the Standby mode is not used, no change to the PCB is required. If the new application uses the Standby mode, the EA -VSTBY pin must be separated from the common 5V and have a specific supply path. Software impact None.

1.1.5 Pins 143 and 144

These pins are VSS and VDD, respectively, in the ST10F269. On the ST10F272 they are used as XTAL3 and XTAL4 for connection to an optional 32 kHz crystal to clock the Real Time Clock during power-down. Hardware impact PCB must be redesigned. If the optional 32 kHz is not used:

• Pin 143 (XTAL3) must be linked to ground like on the ST10F269
• Pin 144 (XTAL4) must be left open. It can also be connected to ground via a capacitor to reduce the potential RF noise that might be propagated inside the device if the pin is left floating.

In case the optional 32 kHz is not used, the OFF32 bit of the RTCCON register must be set. Prior to setting the OFF32 bit in the RTCCON register, the RTC must be enabled by setting RTCEN, bit 4 of XPERCON, and XPEN, bit 2 of SYSCON.

1.2 XRAM

The ST10F272B and ST10F272E devices do not have the same size of XRAM. Each configuration is detailed hereafter.

1.2.1 ST10F272B’s XRAM

The ST10F269 and the ST10F272B have the same size of extension XRAM: 10 Kbytes. The XRAM of the ST10F269 is divided into two ranges being XRAM1 of 2 Kbytes and XRAM2 of 8 Kbytes:

• The XRAM1 address range is 00’E000h - 00’E7FFh if enabled (XPEN and XRAM1EN, bit 2 of SYSCON register and of XPERCON register, respectively, must both be set).
• The XRAM2 address range is 00’C000h - 00’DFFFh if enabled (XPEN and XRAM2EN, bit 2 of SYSCON register and bit 3 of XPERCON register, respectively, must both be set). The XRAM of the ST10F272 is divided into two ranges, XRAM1 of 2 Kbytes (compatible with the ST10F269) and XRAM2 of 8 Kbytes with a user re-programmable address range and the StandBy mode.
• The XRAM1 address range is 00’E000h - 00’E7FFh if enabled (XPEN and XRAM1EN, bit 2 of SYSCON register and bit 2 of XPERCON register must both be set).
• The XRAM2 address range is 09’0000h - 09’1FFFh, by default (mirrored every

16 Kbytes in the range 09’0000h -0F’FFFFh), if enabled (XPEN and XRAM2EN, bit 2 of

SYSCON register and bit 3 of XPERCON register, must both be set). Hardware impact None. Software impact There is no change in the enabling of the XRAM blocks: XPERCON register bits, XRAM1EN and XRAM2EN, and SYSCON register bit, XPEN, are used to enable them. The memory mapping of the application is impacted by the difference in XRAM2 location. A new register has been created in order to allow the user to remap XRAM2 (please refer to Section 4.1: XADRS3 register on page 28 for details).

1.2.2 ST10F272E’s XRAM

The ST10F269 has 10 Kbytes of extension RAM whereas the ST10F272E has 18 Kbytes.

• The XRAM1 address range is 00’E000h - 00’E7FFh if enabled.
• The XRAM2 address range is 00’C000h - 00’DFFFh if enabled. The XRAM of the ST10F272E is divided into two ranges being XRAM1 of 2 Kbytes (compatible with the ST10F269) and XRAM2 of 16 Kbytes with a user reprogrammable address range:
• The XRAM1 address range is 00’E000h - 00’E7FFh if enabled (XPEN and XRAM1EN, bit 2 of SYSCON register and bit 2 of XPERCON register, respectively, must be set).
• The XRAM2 address range is 09’0000h - 09’3FFFh, by default (mirrored every

SYSCON register and bit 3 of XPERCON register, respectively, must be set). and XRAM2EN, and SYSCON register bit, XPEN, are used to enable them. the XRAM2 (please refer to Section 4.1: XADRS3 register on page 28 for details).

1.3 Flash EEPROM

Table 2. Flash memory key characteristics

1.3.1 Hardware impact

1.3.2 Software impact

programming routines must be updated. order to prevent any use of this memory range. Table 3. Flash memory mapping

1.4 A/D converter

10-bit resolution and an on-chip sample and hold circuit.

1.4.1 Hardware / Software impact: conversion timing control

ADSTC bit fields are no longer compatible. shows the differences in sample time. Table 4. ST10F272 conversion timing table

1.4.2 Hardware impact: electrical characteristics

Table 6 lists the differences in the DC characteristics of the two devices. Table 5. ST10F272 vs ST10F269 sample time comparison table Table 6. ADC differences

1.4.3 Software impact

is complete in order to initialize the ADC module. This self-calibration is seen by the ST10F272 as a conversion and thus bit ADCIR is set. ADCEIR flags before configuring the ADC module and starting the first conversion. Table 6. ADC differences (continued) Table 7. ADCON register description New bit valid only for the ST10F272.

bit 10 of the XPERCON register, must be set to have access to the XMISC register.

1.5 Real time clock

can be made via an additional bit in the RTCCON register.

1.5.1 Hardware impact

Check the usage of pins XTAL3 and XTAL4 (pins 143 and 144, respectively).

1.5.2 Software impact

must be modified according to the new mapping. Table 8. XMISC register description

• In the ST10F272, these flags are cleared by writing them to ‘1’
• In the ST10F269, these flags are cleared by writing them to ‘0’ As these flags must be cleared by software when entering the corresponding interrupt service routine, a change in the application code is needed. ST10F272: RTCCON (F1C4h / E2h) ESFR Reset value: 0000h 15 14 13 12 11 10 9 8 7654 3 2 1 0 Reserved OFF

32 OSC RTC

Table 9. RTCCON register description 0: The bit was reset less than a Basic Clock unit ago. 1: The interrupt was triggered. 1: RTC_SecIT is enabled; it is generated every basic clock unit. 0: The bit was reset less than n Basic Clock units ago. 1: The interrupt was triggered. 1: Clock oscillator is switched off when ST10 enters Power Down mode. and registers can be written. 0: The clock oscillator used by the RTC is the main oscillator. 1: The clock oscillator used by the RTC is the low power 32 kHz oscillator.

Replace ST10F269 code: RTCCON &= 0xFFFE;// Clear RTCSIR flag by the following code for ST10F272: RTCCON |= 0x0001;// Write 1 into RTCSIR flag to clear it

1.6 CAN modules

The ST10F269 has two CAN modules of the B-CAN type. The ST10F272 has two CAN modules of the C-CAN type. These modules are functionally compatible with the modules of the ST10F269. The C-CAN cells provide additional Message Objects and new functionalities. The main difference is that the Message Objects are no longer directly accessed as memory but are available through a Message Interface. This changes the programming model of the modules.

1.6.1 Hardware impact

None.

1.6.2 Software impact

Rewrite the CAN drivers.

1.7 Port input control

In the ST10F269, the Port Input Control register PICON is used to select between TTL and CMOS-like input thresholds. The CMOS-like input thresholds are defined above the TTL levels and feature a hysteresis of 250mV to prevent the inputs from toggling while the respective input signal level is near the thresholds. This feature is available for all pins of Port 2, Port 3, Port4, Port 7 and Port 8. In the ST10F272, Port 6 has been added. Moreover, the default hysteresis is now 500mV for TTL levels and 800mV for CMOS levels. ST10F269: PICON (F1C4h / E2h) ESFR Reset value: --00h 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 Reserved P8 LIN LIN Res. P4 LIN HIN LIN HIN LIN - R/W R/W - R/W R/W R/W R/W R/W ST10F272: PICON (F1C4h / E2h) ESFR Reset value: 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved P8 LIN LIN LIN LIN HIN LIN HIN LIN - R/W R/W R/W R/W R/W R/W R/W R/W

1.7.1 Hardware impact

1.7.2 Software impact

None if the software is not writing to PICON bit 5 (P6LIN).

1.8 Ports output control

application’s requirements, and eventually, the EMI behavior of the device can be improved.

• Edge characteristic defines the rise/fall time for the respective outputs, that is, the transition time. Slow edge reduces the peak currents that are sunk/sourced when changing the voltage level of an external capacitive load.
• Driver characteristic defines either the general driving capability of the respective drivers, or if the driver strength is reduced after the target output level has been reached or not. Reducing the driver strength increases the output’s internal resistance, which attenuates noise that is imported via the output line. This feature is not available on the ST10F272.

1.8.1 Hardware impact

Some modifications might be needed depending on the usage of this functionality.

1.8.2 Software impact

Parts related to the initialization of the POCONx registers should be suppressed.

1.9 PLL and main on-chip oscillator

• PLL multiplication factors have been adapted in order to match the new frequency range.
• On-chip main oscillator input frequency range has been reshaped, reducing it to 4 to

8 MHz: This allows the power consumption to be reduced when the Real Time Clock is

Table 10. PICON register description

1.9.1 Hardware impact

Port0 configuration might be changed with regards to the new PLL factor. All configurations need a crystal (or ceramic resonator) to generate the CPU clock through the internal oscillator amplifier, except for the Direct Drive mode (oscillator amplifier disabled, so no crystal or resonator can be used). Vice versa, the clock can be forced through an external clock source only in Direct Drive mode. The components on XTAL1 and XTAL2 (crystal and capacitors, or resonator) must be changed as:

• the input frequency range is now reduced
• it is no longer possible to use a crystal or a ceramic resonator in direct drive mode
• it is no longer possible to use a PLL factor with a frequency generator
• the electrical characteristics of the main oscillator have changed (transconductance)

1.9.2 Software impact

None.

2 New features

2.1 Additional XPeripherals

are linked to additional alternate functions of some ports of the ST10F272.

• A second SSC (SSC of ST10F269 becomes SSC0, while the new one is referred to as XSSC or simply SSC1). Note that some restrictions and functional differences due to the XBus peculiarities are present between the standard SSC, and the new XSSC.
• A second ASC (ASC0 of ST10F269 remains ASC0, while the new one is referred to as XASC or simply as ASC1). Note that some restrictions and functional differences due to the XBus peculiarities are present between the standard ASC, and the new XASC.
• An I2C interface is added (see X-I2C or simply I2C interface). In addition to the previous XPeripherals, the ST10F272E also features a second PWM (PWM of ST10F269 becomes PWM0, while the new one is referred to as XPWM or simply as PWM1). Note that some restrictions and functional differences due to the XBus peculiarities are present between the standard PWM, and the new XPWM.

2.1.1 Hardware impact

None if the additional XPeripherals are not used.

2.1.2 Software impact

XPERCON and SYSCON are compatible with the ST10F269.

2.2 Programmable divider on CLKOUT

Table 12. XCLKOUTDIV register description

2.2.1 Hardware impact

2.2.2 Software impact

None if only CLKOUT is needed. default the CPU clock is output on P3.15.

2.3 New multiplexer for X-Interrupts

• Higher Byte (XIRxSEL[15:8]) Interrupt Enable bits
• Lower Byte (XIRxSEL[7:0]) Interrupt Flag bits

Figure 2. X-Interrupt basic structure

implemented inside the user application. Table 13: X-Interrupt detailed mapping gives an overview of the different settings available.

2.3.1 Hardware impact

2.3.2 Software impact

to these registers. Refer to Section 3.1: XPERCON register for more details.

• XIR0SEL = 0x0100, only the CAN1 interrupt is enabled and can generate an interrupt to the ST10 through XP0IC
• XIR1SEL = 0x0100, only the CAN2 interrupt is enabled and can generate an interrupt to the ST10 through XP1IC
• XIR2SEL = 0x0, not used
• XIR3SEL = 0x2000, only the PLL unlock interrupt is enabled and can generate an interrupt to the ST10 through XP3IC

Table 13. X-Interrupt detailed mapping

Then, in the interrupt routines associated with the XPxIC, the respective flags in the XIRxSEL registers must be cleared. Since the XIRxSEL registers are not bit addressable, a pair of registers (a pair for each XIRxSEL) is provided to set and clear the bits of XIRxSEL without risking to overwrite requests coming after reading the register and before writing it. Therefore, the following registers must be written to clear the flags:

• in the CAN1 interrupt routine, XIR0CLR (@ EB14h) = 0x0001
• in the CAN2 interrupt routine, XIR1CLR (@ EB24h) = 0x0001
• in the PLL unlock interrupt routine, XIR3CLR (@ EB44h) = 0x0020 Additional information on the X-Interrupt multiplexer structure Figure 2: X-Interrupt basic structure shows that the X-Interrupt sources are connected to the interrupt request flag of the XIRxSEL registers and to the XPxIR request flag via an AND gate with the enable bit. This AND gate is activated by a transition on the Interrupt source line and not by the latched value in the XIRxSEL register. This means that:
• A transition on the IT source line generates an interrupt to the ST10 core if the source is enabled.
• Writing to an interrupt request flag in an XIRxSEL register does not generate an interrupt to the ST10 core. Example: If XIR0SEL = 0x0100: CAN1 interrupt enabled on XP0IC interrupt To trigger by software the CAN1 interrupt routine with the XP0IC register, the following code must be used: XIR0SET = 0x0001;/* Set CAN1 interrupt request Flag in XIR0SEL */ XP0IC = XP0IC | 0x0080;/* Set XP0IR flag, generate an interrupt */ Executing only the first line only sets the flag in the XIR0SEL register but it is not seen by the AND gate and cannot set the XP0IR flag.

2.4 Additional ports input control

Ports 0, 1 and 5 via the XPICON register.

2.4.1 Hardware impact

2.4.2 Software impact

Table 14. XPICON register description

3 Modified registers

3.1 XPERCON register

In the ST10F272, new bits have been added with regards to the additional XPeripherals. and thus this peripheral is not visible and not available. Table 15. XPERCON register description

10 XMISCEN

0: Accesses to the Additional Miscellaneous Features is disabled. 1: The Additional Features are enabled and can be accessed. 0: Accesses to the on-chip XI 2 C are disabled, external access performed. 1: The on-chip XI 2 C is enabled and can be accessed.

8 XSSCEN

0: Accesses to the on-chip XSSC are disabled, external access performed. 1: The on-chip XSSC is enabled and can be accessed.

7 XASCEN

0: Accesses to the on-chip XASC are disabled, external access performed. 1: The on-chip XASC is enabled and can be accessed. 1: The on-chip XPWM module is enabled and can be accessed.

configuration registers, equivalent to the External Bus register BUSCONx and ADDRSELx. XPeripherals sharing the same pair of registers are disabled.

• CAN1, CAN2, XASC, XSSC, XI2C, XPWM, XRTC and XMISC: Accesses to the 00’E800h-00’EFFFh range are redirected to external memory only if all corresponding bits are cleared
• XRAM1: Accesses to the 00’E000h-00’E7FFh range are redirected to external memory if bit XRAM1EN is cleared
• XRAM2: Accesses the 09’0000h-0F’FFFFh range (default value in XADRS3 register, refer to Section 4.1: XADRS3 register) are redirected to external memory if bit XRAM2EN is cleared

3.1.1 Hardware impact

3.1.2 Software impact

None if the ST10F269 software is not writing to the reserved bit. 1: The on-chip Real Time Clock is enabled and can be accessed. 1: The on-chip XRAM2 is enabled and can be accessed. 1: The on-chip XRAM1 is enabled and can be accessed. 1: The CAN2 XPeripheral is enabled and can be accessed. 1: The CAN1 XPeripheral is enabled and can be accessed. Table 15. XPERCON register description (continued)

4 New registers

4.1 XADRS3 register

way the address range of the XRAM2 memory is now user-programmable.

• The address window can only be located in the first megabyte of addressable space, that is, in the 00’0000h-0F’FFFFh range
• The window start address must be aligned to a Range Size boundary

4.1.1 Hardware impact

Table 16. XADRS3 register description Defines the bits A19..A8 of the start address of the address window. Defines the size of the address window. Table 17. Definition of address area

4.1.2 Software impact for the ST10F272B

On ST10F272B, this register must be programmed by the user before accessing XRAM2 so that:

• RGSZ defines an 8 Kbyte window size. RGSZ = 0101b
• RGSAD defines bits 8 to 19 of the window start address aligned to an 8 Kbyte boundary (the least significant bits of the field are not relevant). By programming XADRS3 to 0C05h, the XRAM2 will be 8 Kbytes, mapped from 00’C000h to 00’DFFFh, exactly as in the ST10F269. Note: XADRS3 cannot be changed after executing the EINIT instruction.

4.1.3 Software imp act for the ST10F272E

On ST10F272E, this register must be programmed by the user before accessing XRAM2 so that:

• RGSZ defines a 16 Kbyte window size. RGSZ = 0110b
• RGSAD defines bits 8 to 19 of the window start address aligned to a 16-Kbyte boundary (the least significant bits of the field are not relevant). In the ST10F272E, the XRAM2 cannot be located within page 3 of segment 0. The user can either:
• map the XRAM2 from anywhere above address 09’0000h
• map the XRAM2 in the 16-Kbyte page available in segment 0 in the 00’8000h - 00’BFFFh range. The desired value should be written in XADRS3 register before enabling XRAM2 in the SYSCON and XPERCON registers. Note: XADRS3 cannot be changed after executing the EINIT instruction. Example To map the 16-Kbyte XRAM2 onto page 60 (starting address 0F’0000h, compatible with the ST10F276E), then XADRS3 must be initialized with the value F006h. To map the 16-Kbyte XRAM2 onto page 2 (starting address 00’8000h), then XADRS3 must be initialized with the value 0806h. Variables and PEC transfers For architecture reasons, the PEC destination and source pointers must be in the segment 0. Therefore, all RAM variables and arrays that are PEC-addressed must be located in RAM memory available in segment 0 (DPRAM + XRAM1, and XRAM2 if remapped onto page 2). About Toolchain memory model A change in the Toolchain configuration is needed to take into account the XRAM2’s new location. In the ST10F269, all the XRAM is in page 3 and it is then automatically addressed using DPP3 that points to page 3 (in order to access the DPRAM and the SFR/ESFR). For the ST10F272, it is necessary to dedicate a DPP to access some of XRAM2.

Example in case of Small memory model with tasking toolchain The Small memory model makes it possible to have a total code size up to 16 Mbytes, up to

64 Kbytes of fast accessible 'normal user data' in three different memory configurations and

the possibility to access far/huge data, if more than 64 Kbytes of data is needed. The three memory configurations possible for this 64 Kbytes of 'normal user data' are:

• Default The four DPP registers are assumed to contain their system startup value (0-3), providing one linear data area of 64 Kbytes in the first segment (00’0000h - 00’FFFFh).
• Addresses Linear DPP3 contains page number 3, allowing access to SYSTEM (extended) SFR registers and bit-addressable memory. DPP0 - DPP2 provide a linear data area of 48 Kbytes anywhere in memory.
• Paged DPP3 contains page number 3, allowing access to SYSTEM (extended) SFR registers and bit-addressable memory. DPP0, DPP1 and DPP2 contain the page number of a data area of 16 Kbytes anywhere in memory. Therefore, mapping the XRAM2 onto page 2 (segment 0) makes it available for PEC transfer and the default configuration of the C compiler toolchains can still be used.

4.2 XPEREMU register

This register has been added as a write-only register. The bit meaning is exactly the same as in the XPERCON register.

4.2.1 Hardware impact

None.

4.2.2 Software impact

Once the XPEN bit of the SYSCON register is set and at least one of the XPeripherals (except for memories) is activated, the XPEREMU register must be written with the same contents as the XPERCON register: This is mandatory in order to allow a correct emulation of the new set of features introduced on XBus for the new ST10 generation. The following instructions must be added inside the initialization routine: if (SYSCON.XPEN && (XPERCON & 0x07D3)) then {XPEREMU = XPERCON} ST10F272: XPEREMU (EB7Eh) XREG Reset value: XXXXh 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 Reserved XMIS CEN XI2 CEN XSS CEN XAS CEN XPW MEN Res. XRT CEN XRAM2 EN XRAM1 EN CAN2 EN CAN1 EN - W OW OW OW OW O - W OW OW OW OW O

4.3 Emulation-dedicated registers

XPEREMU, they are write-only registers. These registers are used by emulators. They have no user action on the ST10F272.

4.3.1 Hardware impact

4.3.2 Software impact

memory but is recommended to reserve this space for upward compatibility.

4.4 XMISC register

this register, the XMISCEN bit, that is, bit 10 of XPERCON, must be set. Table 18. XMISC register description

2 CANCK2

4.4.1 Hardware impact

4.4.2 Software impact

even if the CANPAR bit is set.

0 ADCMUX

Table 18. XMISC register description (continued)

5 Electrical characteristics

the symbol CC (Controller Characteristics) is included in the Symbol column.

5.1 DC characteristics

5.1.1 Absolute maximum ratings

5.1.2 Overview of the DC characteristics

therefore the characteristics are different. The user should verify the DC characteristics. Table 19 lists the parameters that might be impacted most. Table 19. DC characteristics

5.2 AC characteristics at 40 MHz

check carefully your design for possible impact.

5.2.1 External memory bus timings

become zero or negative, that in most of the cases is not acceptable or not meaningful at all. extension), tC (Memory Cycle Time wait-states) and tF (Memory tri-state time). Table 19. DC characteristics (continued)

Table 20. Multiplexed bus timings (ns) Table 21. Demultiplexed bus timings

40 MHz

5.2.2 Hi-speed synchronous serial interface (SSC)

SSCBR register (prescaler value) must not be lower than 2.

2 TCL -

Table 21. Demultiplexed bus timings (continued)

AN2021 Referenced documents

6 Referenced documents

The following documents were used to write this application note:

• ST10F269 datasheet, 16-BIT MCU WITH MAC UNIT, 256K BYTE FLASH MEMORY AND 12K BYTE RAM, revision of March 2003
• ST10F272B-E Final Data, 16-bit MCU with 256 Kbyte Flash memory and 12/20 Kbyte RAM, Rev. 1, 20 July 2006

7 Revision history

Table 22. Revision history