AN2014

AN2014 STMICROELECTRONICS | Alldatasheet

Document overview

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• PDF pages: 65

Technical content

Datasheet sections

• 1 EEPROM cell and memory array architecture
• 1.1 Floating gate operation within an EEPROM ce ll
• 1.1.1 Reading the value stored in a memory cell
• 1.1.2 Writing a new value to the memory cell
• 1.1.3 Cycling limit of EEPROM cells
• 1.2 Electrical architecture of ST serial EEPROM arrays
• 1.2.1 Memory array architecture
• 1.2.2 Decoding architecture
• 1.2.3 Intrinsic electrical stress induced by programming
• 2 Choosing a suitable EEPROM for your appl ication
• 2.1 Choosing a memory type suited to the task to be performed
• 2.2 Choosing an appropriate memory interface
• 2.3 Choosing an appropriate supply voltage and temperature range
• 3 Recommendations to improve EEPROM reli ability
• 3.1 Electrostatic discharges (ESD)
• 3.1.3 ST EEPROM ESD protection
• 3.2 Electrical overstress and latchup
• 3.2.2 How to prevent EOS and latchup events
• 3.2.3 ST EEPROM latchup protection
• 3.3 Power supply considerations
• 3.3.1 Power-up and power-on-reset sequence
• 3.3.2 Stabilized power supply voltage
• 3.3.3 Absolute maximum ratings
• 4 Hardware considerations
• 4.1 I 2C family (M24xxx devices)
• 4.1.1 Chip enable (E0, E1, E2)
• 4.1.2 Serial data (SDA)
• 4.1.3 Serial clock (SCL)

Datasheet sections

• 4.1.4 Write control (WC)
• 4.1.5 Recommended I 2C EEPROM connections
• 4.2 SPI family (M95xxx devices)
• 4.2.1 Chip Select (S )
• 4.2.2 Write Protect (W)
• 4.2.3 Serial Data input (D) and Serial Clock (C)
• 4.2.4 Hold (HOLD)
• 4.2.5 Serial Data output (Q)
• 4.2.6 Recommended SPI EEPROM connections
• 4.3 MICROWIRE ® family (M93Cxxx and M93Sxxx devices)
• 4.3.1 Chip Select (S)
• 4.3.2 Serial Data (D) and Serial Clock (C)
• 4.3.3 Organization Select (ORG)
• 4.3.4 Serial Data output (Q)
• 4.3.5 Don’t use (DU)
• 4.3.6 Recommended MICROWIRE EEPROM conne ctions
• 4.4 PCB Layout considerations
• 4.4.1 Cross coupling
• 4.4.2 Noise and disturbances on power supply lin es
• 5 Software considerations
• 5.1 EEPROM electrical parameters
• 5.2 Optimal Write control
• 5.2.1 Page mode
• 5.2.2 Data polling
• 5.3 Write protection
• 5.3.1 Software write protection
• 5.3.2 Hardware write protection
• 5.4 Data integrity
• 5.4.1 The checksum
• 5.4.2 Data redundancy
• 5.4.3 Checksum and data redundancy
• 5.4.4 Extra redundancy
• 5.5 Cycling endurance and data retention
• 5.5.1 Cycling and data retention qualification procedures
• 5.5.2 Optimal cycling with ECC

How a designer can make the most of STMicroelectronics serial EEPROMs Introduction Electrically Erasable and PROgrammable Memory (EEPROM) devices are standard products used for the non-volatile storage of data parameters, with a fine-granularity. This application note describes most of the internal architecture and related functionality of the STMicroelectronics EEPROM, such as the storage mechanism, interface circuits, optimal settings of hardware, software and data management. With these guidelines, an application designer gains a better understanding of the device’s operation and can profit from these recommendations to significantly improve the reliability of the application.

1 EEPROM cell and memory array architecture

1.1 Floating gate operation within an EEPROM cell

From the user’s point of view, this EEPROM device is a circuit for storing digital information. simple interface, however, there are a number of sensitive analog and physical processes. Figure 1. Structure of an EEPROM floating gate transistor, and circuit symbol Figure 1. shows the key component of a single EEPROM cell, the floating gate transistor present, we can assume that this is a fairly linear relationship. Figure 2. MOSFET-like operation it some of its normal electrons. This is used for the Written state of the EEPROM cell.

1.1.1 Reading the value stored in a memory cell

the memory cell can be read. Figure 5. Using the voltage on the Control Gate to determine the charge

1. A written cell draws a current I µA (where IµA > I d.ref); an erased cell does not draw any current (0 µA).

stored information as a digital signal on the output pins of the memory device.

1.1.2 Writing a new valu e to the memory cell

1, but the exact choice is manufacturer and product-type dependent). (1 million V/mm, or more) is needed to make electrons pass through the thin Tunnel Oxide. For a Tunnel Oxide thickness of 100Å, the high voltage needs to be at least 10V.

• voltage and current references to control oscillators and timings.
• a regulated charge pump that generates a stable 15 to 18V voltage, HiV, from the single external power supply.
• a ramp generator that, from the stable HiV voltage, makes the specific waveform (shown in Figure 8) that is to be applied to the cells. VPP is the high voltage that is directly applied to the FLOTOX cell, as described earlier. The precise shape of the VPP voltage waveform is critical, and has a direct effect on the reliability and endurance of the memory cells. The slope, plate time and maximum level are parameters that are very carefully controlled. Writing new data in an EEPROM array triggers an auto-erase of all the addressed bytes, resets them all to the Erased state, and then selectively programs those bits that should be set to the Written state.

Figure 8. VPP signal applied to EEPROM cells the cell (FLOTOX transistor) current to a reference.

1.1.3 Cycling limit of EEPROM cells

program the cell properly. The Erased and Written states become undifferentiated. 100% insulated, and loses its charges, and so the data retention time drops drastically. Figure 9. Accumulation of negative or positive charges in the tunnel oxide involved in cell cycling and endurance limitations.

1.2 Electrical architecture of ST serial EEPROM arrays

In the previous section, the EEPROM functionality was considered at the single bit level. overview of the architecture of an EEPROM device.

1.2.1 Memory array architecture

• Each memory cell consists of one Select transistor in series with a FLOTOX transistor and each byte is made up of eight memory cells and a Control Gate transistor with a drain that is common to the Control Gates of all eight FLOTOX transistors.
• Rows (in the horizontal direction) are made up of 16 bytes (or more, depending on the memory size (the number of bytes within each row being a function of the array size). For each row, all Select transistors and all Control Gate transistors are connected to the Row line.
• Columns are grouped by eight bit-lines plus one Cg-line. This is then repeated as many times as the number of bytes in a row.
• A bit-line is common to all the drains of the Select transistors of each memory cell located in the column. A Cg-line is common to all the sources of the Control Gate transistors of the column.

Figure 10. Architecture of the memory array (showing the grouping in bytes) Section 5.5: Cycling endurance and data retention and AN2440 for more details).

8 Select

8 FLOTOX

1.2.2 Decoding architecture

Figure 11. Decoding block diagram

1.2.3 Intrinsic electrical st ress induced by programming

a. The high voltage is required to Erase and program an EEPROM cell.

AN2014 EEPROM cell and me mory array architecture Consider, by way of example, the stress induced on the array elements when programming one single byte in a 1Kbit EEPROM, organized as 128 x8 bit. The memory array is composed of 8 pages (or rows) of 16 bytes (or columns). Erase cycle: the complete row (page) that contains the addressed byte receives the VPP signal, on the selected Row-line, as does the complete column, on the selected Cg-line:

• Control Gates of all the Select transistors in the given row: 1 row x 16 bytes x 8 bits =128
• Control Gates of all the Control Gate transistors in the given row: 1 row x 16 bytes = 16
• Drains of all the Control Gate transistors that are connected to the given Cg-line: 1 column x 8 rows = 8 The Bit-lines of the addressed bytes are floating. Write cycle: the complete row (page) that contains the addressed byte receives the VPP signal, on the selected Row-line:
• Control Gates of all the Select transistors in the given row: 1 row x 16 bytes x 8 bits =128
• Control Gates of all the Control Gate transistors in the given row: 1 row x 16 bytes = 16
• The Cg-line of the addressed byte is held at ground voltage
• The Bit-lines are left floating or receive VPP depending on data to be written. The worst case is when FFh is to be written, and all Bit-lines receive the VPP signal
• Drains of all the Select transistors sharing the same 8 Bit-lines: 1 column x 8 rows x 8 bits = 64 This example shows how one single byte, being erased or programmed, incurs a lot of High Voltage stress on elements that share the same row, column and bit-line as the one addressed. For a 1Kbit EEPROM, programming one single byte to FFh induces stress on

128 Select transistors and 24

Control Gate transistors during auto-erase, and 192 Select transistors and 16 Control Gate transistors during the write cycle, even though only 17 transistors (8 Select transistors, 8 FLOTOX transistors, 1 MOS transistor) were really being addressed for the data change. The bigger the memory array, the larger the number of additional transistors that are involved. This is why when high cycling performance is required, it is recommended to group N contiguous bytes inside one page and use the write page mode so that the overall number of write cycles remains to its lowest value.

Choosing a suitable EEPROM for your application AN2014

2 Choosing a suitable EEPROM for your application

ST EEPROM products offer a very high quality level as they are produced with a mature process and benefit from an efficient testing coverage on each single production part. Nevertheless, the reliability on EEPROM products is also closely linked to the way they are controlled in the end application. The aim of the following chapters is to provide a set of recommendations to significantly improve the reliability and robustness in the end application. In the case of automotive applications, ST strongly recommends the use of products that are classified as automotive grade, that is, devices referenced as MXXxxx-125 (previous generation) and MXXxxx-A125/A145 (new generation with improved features). These devices are designed to satisfy the most stringent quality requirements and are tested with STMicroelectronics’ High Reliability Certified Flow (described in Quality Note, QNEE9801).

2.1 Choosing a memory type suited to the task to be performed

EEPROM devices are particularly suited to the tasks of code traceability and parameter storage. The Serial protocol offers the best compromise of performance versus cost where the access time is not critical.

2.2 Choosing an approp riate memory interface

ST is specialized in Serial Access EEPROMs, which are based on three main protocols: I²C, SPI and MICROWIRE (see Table 1). Fundamental requirements such as noise immunity, ESD, latchup and cycling Endurance are basic features of each ST Serial EEPROM device (independent from the protocol used). The choice of the most appropriate Serial EEPROM depends mainly on the hardware resources of the master and on the architecture built around it. See the following:

• The I2C bus offers a 2-wire protocol working at a maximum clock rate of 1 MHz and so is preferred when the hardware resources are limited and the data rate is not a constraint at all. The multiple slave configuration requires no extra hardware and is managed by software.
• The SPI bus and MICROWIRE bus are 4-wire protocols allowing higher communication speed (speed is determined by each manufacturer design and technology). The number of slaves is unlimited but N slaves require N additional master I/Os for each chip select line. Both SPI and MICROWIRE bus can be reduced to only 3 wires providing that the D and Q pins are tied together to a bidirectional I/O. Data Write protection is different for each protocol family and is also a key factor when selecting the memory interface. I2C products offer only hardware Write protection while SPI and MICROWIRE products provide both hardware and software protection. Refer to Section 5.3: Write protection.

AN2014 Choosing a suitable EEPR OM for your application

2.3 Choosing an appropriate su pply voltage and temperature

These are essential parameters that will define the device reliability when operating in the application. The VCC values and the temperature values of the application must always stay within the limits defined in ST datasheets. Table 1. Three serial bus protocols

Features

Up to 8 devices cascadable on the same bus Hold mode (input pin) Write control for 4 blocks Block write protection defined by software for M93Sxxx family

3 Recommendations to improve EEPROM reliability

3.1 Electrostatic discharges (ESD)

drastically reduced, causing the device to fail prematurely in field service. protect against ESDs, such as Faraday shields, perimeter ground lines or ground planes.

3.1.3 ST EEPROM ESD protection

accordance with AEC-Q100-002. writing data in the EEPROM when an ESD is more likely to occur. Table 2. ESD generation(1)

1. The charge unbalance depends on many factors such as the contact area, separation speed and relative

AN2014 Recommendations to improve EEPROM reliability

3.2 Electrical over stress and latchup

Electrical overstress (EOS) and latchup are also damaging stresses that are either immediately destructive, or may create latent defects leading to premature failure. 3.2.1 What are EOS and latchup? In comparison with ESDs, EOS and latchup are lower-intensity events that last much longer (sometimes more than a few seconds). That is why the energy induced by an EOS is higher than the ESD energy. EOS and latchup induce current injections inside the EEPROM when an overvoltage stress is applied on one or more package pins. Latchup occurs when a charge injection triggers the I/O parasitic thyristors (also called SCR) thus generating a very high current between VDD and VSS. This phenomenon lasts until the VCC power supply is turned off.

3.2.2 How to prevent EOS and latchup events

Typically power supply cycling leads to EOS situations. During the power-up and power- down phases, the EEPROM I/Os interfaced with other ICs may temporary see voltages greater than VCC or lower than VSS. When outside Absolute Maximum Ratings, these biasing conditions may lead to positive and negative current injections, respectively. This kind of stress cannot always be completely prevented but it can be minimized. The switching sequence of the different interfaced ICs must be carefully determined, and if necessary protection resistor (<1KΩ) can be placed on critical pins or sometimes directly on VCC pin (<50Ω) to limit eventual latchup current. Please refer to Section 4: Hardware considerations for more details. Overshoots and undershoots may occur on external device pins when the application is running. They can be generated by radiations, power supply disturbances or even some ICs. The very first protection is provided by the semiconductor manufacturer (ST) which offers the best possible robustness against EOS and latchup. If extra protection is needed, the application designer can add small value resistors (<1kΩ) in series on all interfaced lines and (<50Ohm) in series on VCC line so that it can be compatible with the communication speed constraints and power supply range. Please refer to the Hardware considerations section for more details. Manufacturing and handling devices are also sources of EOS: all voltage levels applied to the device must be checked accurately and regularly. In addition all equipment should be constantly calibrated. During write operations, an EEPROM device is more sensitive to overvoltages on its power supply pin because the internal high voltage generator is directly fed by the voltage applied to the power supply pin.

Figure 12. Latchup mechanism and protection

1. Protection is only recommended if latchup risk is identified.

3.2.3 ST EEPROM latchup protection

Figure 13. Latchup test conditions

1. The device does not latch up within the gray areas.

3.3 Power supply considerations

stress coming from an I/O pin.

3.3.1 Power-up and power-on-reset sequence

be placed in the Standby Power mode. Figure 14. Power-up

1. Power-up is safe with a monotonous rising slope slower than 1V/µs.

Table 3. Typical POR threshold values

3.3.2 Stabilized power supply voltage

Figure 15. Local EEPROM supply filtering

1. Capacitor should be placed as close as possible to VCCand VSS pins to avoid parasitic inductive effects.
2. Resistor must never be placed betw een the decoupling capacitor and the VCC pin of the EEPROM.

3.3.3 Absolute maximum ratings

are above or below normal operating conditions.

4 Hardware considerations

design can protect the parts from uncontrolled behavior.

4.1 I 2C family (M24xxx devices)

4.1.1 Chip enable (E0, E1, E2)

like pick-up or other cross coupling effects. Figure 16. Chip Enable inputs E0, E1, E2 The input leakage current on the Ei pins depends on the input voltage value (Table 4).

4.1.2 Serial data (SDA)

and EEPROM I/O buffer characteristics. See Table 5 for calculation rules. Table 4. Connecting the Ei inputs of I²C products Table 5. Calculation rules for pull-up resistor on SDA(1)

1. The smaller R BUS, the faster the clock frequency. The higher RBUS, the lower the operating current, the

slower the transitions and the lower the electromagnetic interference.

1. Refer to the Maximum R BUS value versus bus parasitic capacitance (CBUS) for an I2C bus at maximum

frequency figure in the I2C datasheet.

Figure 17. Serial Data input/output SDA Figure 18. SDA bus conflict with push-pull buffers (NOT RECOMMENDED)

1. R S > VCC/IO with IO = min(Master IOH, EEPROM IOL). Without the RS resistor the current is limited by the

Master buffer and transistor T2 producing overstress at both Master and EEPROM side.

4.1.3 Serial clock (SCL)

appears at the end of a data byte inside a transmitted Write command. Figure 19. Serial clock input SCL

4.1.4 Write control (WC )

be maintained Low after the STOP condition ending the Write command. Input pin leakage current depends on input pin voltage. See Table 6.

Figure 20. Write control input (WC)

4.1.5 Recommended I 2C EEPROM connections

Table 6. Connecting WC inputs in I2C products

1. These pull-down values can change within the range authorized in the datasheet without previous notice.

4.2 SPI family (M95xxx devices)

4.2.1 Chip Select (S )

the voltage on the S pin always remains above VIH = 0.7VCC during power-up. protection circuit, does not offer any open path to the VSS or VCC. following two conditions are met: S falling edge and S remains low. Figure 23. Chip Select, Clock, Data, Hold input pins

4.2.2 Write Protect (W )

preventing the potential execution of an ongoing write command. density above 8 Kbits, the /W protects the Write in the Status Register. protection circuit, does not offer any open path to VSS or VCC.

Figure 24. Write Protect input W

4.2.3 Serial Data input (D) and Serial Clock (C)

trigger input buffer and should be controlled by push-pull buffers (from the SPI master bus). the signal control and the device standby current. before the Clock signal crosses the input buffer trigger point (around VCC/2).

4.2.4 Hold (HOLD )

not sink a current even if a voltage higher than VCC is applied to it. Select, Clock, Data, Hold input pins).

4.2.5 Serial Data output (Q)

Figure 25. Output pin tri-state buffer reverse diode to VCC, therefore the voltage applied on Q must never be higher than VCC.

4.2.6 Recommended SPI EEPROM connections

1. The decoupling capacitor (10 nF min) mu st be placed as close as possible to the
2. S input is pulled high with RPU and C input is pulled low with RPD. In doing so, if the SPI

together, that is tCHSH=0, out of a specification event).

1. If unused, the Hold and W pins must be directly connected to VCC, as a CMOS input

must never be left floating.

4.3 MICROWIRE ® family (M93Cxxx and M93Sxxx devices)

4.3.1 Chip Select (S)

controls the Chip select (S) with a push-pull buffer. power-up, power-down and the reset phase of the Master. Figure 28. Chip Select, Clock, Data input pins

4.3.2 Serial Data (D) and Serial Clock (C)

pull-down resistor on Serial Data Input (D) will optimize signal control and standby current. weaker) than the pull-down value on Chip Select (S).

4.3.3 Organization Select (ORG)

organization and switch from Single data byte management to word data management. Figure 29. Organization input ORG

1. The pull-up resistor is only active fo r a short period of time (right after the device selection) to latch the level

read on the ORG pin when it’s left floating.

4.3.4 Serial Data output (Q)

4.3.5 Don’t use (DU)

recommended for the lowest standby power consumption mode.

4.3.6 Recommended MICROW IRE EEPROM connections

Recommended MICROWIRE EEPROM connections are shown in Figure 30 and Figure 31.

1. A decoupling capacitor (10 nF min) must be placed as close as possible to the package
2. A 50 Ohm resistor can be connected to V CC if extra filtering on VCC is needed or if an

identified latchup risk is to be minimized. Figure 30. Recommended MICROWIRE connections - safe design Figure 31. Recommended MICROWIRE connections - robust design Table 8. Calculating external pull-up and pull-down resistors in MICROWIRE products

4.4 PCB Layout considerations

communication speed, noise due to interference and all EMC constraints.

4.4.1 Cross coupling

and antenna-like pick-up. All unused pins should be tied correctly (in general to VCC or VSS).

4.4.2 Noise and disturbanc es on power supply lines

of 10nF to 100nF are usually preferred. Figure 32. PCB decoupling

AN2014 Software considerations

5 Software considerations

The purpose of the suggestions presented below is to help the application designers make the most of ST’s EEPROM products, and to help to improve the system robustness and compatibility with future EEPROM devices.

5.1 EEPROM electrical parameters

Low-level drivers (hardware dependent) must follow the EEPROM electrical parameters for correct communication. EEPROM samples are not absolute references for software validation as they are not representative of production variations. The EEPROM timings given in the device datasheets are unique reference characteristics. They correspond to minimum and maximum timing values to be taken into account for hardware and software calibration. Typical errors to be avoided in applications are:

• Input voltage levels not compatible with the specifications, VIL<0.3VCC and VIH > 0.7VCC.
• Excessive current requested from EEPROM data output buffer (output CMOS levels are no more guaranteed).
• Write time not completed (tW = 5 ms) before issuing a new command.
• Data setup time in applications using high clock rate or very smooth waveforms with slow transitions (as a general recommendation, signal rise and fall time must be less than 10% of the clock period).
• Out of specification (too short) pulses on the Clock signal, Chip select signal or on Start/Stop conditions. The behavior of EEPROM devices operating “out of specification” can never be guaranteed and is not always predictable. Moreover, major compatibility issues may arise when switching to a new device version or using a compatible device from another supplier. When using a double source supplier for EEPROMs, the worst value of each single timing should be used as a reference for direct compatibility.

5.2 Optimal Write control

EEPROM devices are simple products with few operating modes and instructions. It is nevertheless worth focusing on the features that can be used to improve performance and application robustness.

5.2.1 Page mode

The memory array is divided into pages. The size of a page is given on the first page of the product datasheet (it can be 8, 16, 32, 64, 128 or 256 bytes).

Software considerations AN2014 The Write Page mode is used to write a block of data bytes in a single shot. The Write Page mode sequence consists of a write instruction with the start address and one or more data bytes directly followed by the internal execution of the operation (tW).

• The maximum number of bytes programmed during a Write Page is limited by the page length of the product.
• A data block can be programmed starting at any offset inside the page.
• The address of the first data byte to program is given in the instruction, other data bytes are programmed in consecutive addresses.
• If the last location in a page is reached when shifting in the data bytes during a Write command, the internal address pointer rolls over to the first byte inside the same page. It is therefore not possible to store data in two different pages with a single Write Page instruction.
• If more data bytes than the page length (for instance 32) are shifted in, only the last received data bytes (last 32 bytes) are programmed in the page (The 33 rd data byte shifted in will replace the 1st data byte shifted in and so on). To write to the EEPROM, it is recommended to use the Page mode instead of the byte mode whenever possible. The programming time (tW) is independent of the number of bytes to program and the Page mode has two main advantages: 1. It speeds up the application when storing or updating data. 2. It minimizes the high-voltage programming stress and naturally extends the cycling endurance.

5.2.2 Data polling

Data polling is a very safe and optimal way of managing the EEPROM Write time (tW). The aim is to check the EEPROM status before sending the next instruction, so as to prevent bad master-slave communications. Data polling is a software loop used to optimize the write wait time and control the correct operation of the device. Moreover, software which has data polling will be able to adapt to different devices regardless of the specified write time. This data polling algorithm must be coupled to a time-out counter to limit the data polling time and avoid some endless polling. The timeout limit should be higher than the maximum write time of all devices used (typically 15 ms should be enough). I2C products In I2C products, the device does not respond (NoAck) when a programming operation is in progress. Data polling thus consists in sending a Device Code in a loop mode and tracking the EEPROM acknowledgement. It is recommended to poll the device with a Write instruction.

Figure 33. I2C data polling algorithm

1. Using the READ Device code (R/W = 1) is hazardous due to I 2C protocol constraints.

Figure 34. SPI data polling algorithm

1. Although ST EEPROM allow continuous read of the stat us register it is, for compatibility reasons,

recommended to send each time the full RDSR command. start to decode incoming bits.

Figure 35. MICROWIRE data polling algorithm

1. There is no difference in the data polling process if chip is deselected between 2 ready/busy checks.
2. It is strongly recommended not to operate the Clock during the data polling sequence because as soon as

the chip is ready, the logic will start to decode incoming bits.

5.3 Write protection

5.3.1 Software write protection

• I²C products have no software write protection.
• In SPI products, 2 non-volatile Status Register bits (BP0, BP1) are dedicated to the software write protection. The upper quarter, the upper half or the whole memory array can be set as Read-Only.
• In 1 Kbit to 4 Kbit M93Sxxx MICROWIRE products the amount of data to protect is directly set by a user instruction. The selected area becomes a Read-Only memory. Data items like trace codes, identification codes, manufacturing configurations, default parameters and all sensitive data in general, can be software protected against corruption during field service. Software protection bits are non volatile bits and therefore offer the same cycling and data retention performances than the EEPROM memory bits. Ai11081 Write in Progress Select (S=1)Deselect (S=0) Ready/Busy on Q pin Q level Deselect (S=0) Ready for new command Low (1) High (2)

5.3.2 Hardware write protection

instructions transiting on the interface bus. operation (Refer to the Hardware considerations).

• The WC pin in I²C products protects the entire array.
• The W pin protects the entire array by resetting the Write Enable Latch (WEL) bit in 1 Kbit to 4 Kbit SPI products whereas it protects the non-volatile bits of the Status Register in 8 Kbit to 2 Mbit SPI products. It is recommended to change the state of the Write Protect pin only if no data transfer or program cycle is in progress. The Write Protect and Write Control pins should be controlled with very conservative timings:
• 1 clock cycle time clearance (with no data transfer) before the select (or start) event.
• 1 clock cycle time clearance (with no data transfer) after the deselect (or stop) event.
• Wait for the write cycle (tW) completion before changing the protection. This conservative sequence will not affect the communication speed but will ensure the safe operation of the products (see Figure 36 and Figure 37). The Write Protect signal (W for SPI, WC for I²C) is glitch sensitive and a short (parasitic) pulse could cause a write request to be aborted. This feature can also be of great help in emergency situations like power loss or Master reset. See the Power supply loss and application reset section for details.

Figure 36. .Recommended use of the WC pin in I²C products Figure 37. Recommended use of the W pin in SPI products

1 Clock Period

5.4 Data integrity

5.4.1 The checksum

the secure communication of parameters that are often read and updated. Correction can also be used to correct detected errors.

5.4.2 Data redundancy

redundancy is more particularly adapted to the read-only data stored in the EEPROM.

• The redundant data should not be located in the same page as the reference data page.
• The address of the duplicated data should differ from original address by at least 1 bit in the column address and 1 bit in the page address (see Table 9: Column and page address bits according to page length). Note: More detailed information on memory arra y, data scrambling and address decoding are available on request.

Table 9. Column and page address bits according to page length

Figure 38. Example of how to duplicate data safely

1. N = Page length (number of bytes defining a page);

5.4.3 Checksum and data redundancy

Combining checksums and data redundancy is the best strategy.

5.4.4 Extra redundancy

AN2014 Software considerations

5.5 Cycling endurance and data retention

Even if EEPROM devices are able to withstand a very high number of write cycles, the EEPROM should not be used in replacement for a non-volatile RAM buffer. The cycling budget during application life has to be considered.

5.5.1 Cycling and data rete ntion qualification procedures

During the cycling qualification, ST EEPROM devices are cycled with a dedicated test program which allows to program in one single write cycle the whole memory array with the same byte value. ST can thus guarantee that, for each write operation performed with this test program:

• each memory array cell is cycled once;
• the logic and the associated internal voltages that control the write cycles are cycled once. Therefore, in a device specified as 4 Mcycles, the qualification results allow to consider that each byte can be cycled 4 million times. Data retention qualification The data retention qualification tests check that the data written to the EEPROM remain available with a correct programming level after a bake at 150 °C during 1000 hours (high temperature significantly accelerates the data retention drift).

5.5.2 Optimal cycling with ECC

Some ST EEPROM devices embed an internal ECC (error correction code) logic which improves data retention performance. This ECC logic must be taken into account when defining the application cycling budget. For devices embedding the ECCx4, the ECCx4 logic compares each group of 4 bytes with 6 additional EEPROM ECC bits associated with each group of 4 bytes. As a result, if a single bit out of 4 bytes of data happens to be erroneous during a read operation, the ECC detects it and corrects it with the correct value in the output stream of data (read data). The EEPROM cell read reliability is therefore improved by using this feature. However even if a single byte has to be written, 4 bytes are internally modified (plus the ECC bits), that is, the addressed byte is cycled together with the three other bytes making up the group. For example:

• Writing one byte at address 0000h internally programs this byte plus the 3 following bytes and ECC bits.
• Writing the next byte at address 0001h internally programs this byte plus the 3 contiguous bytes (address 0000h, 0002h, 0003h), and the ECC bits.
• Writing the next byte at address 0002h internally programs this byte plus the 3 contiguous bytes (address 0000h, 0001h, 0003h), and the ECC bits.
• Wring the next byte at address 0003h, internally programs this byte plus the 3 contiguous bytes (address 0000h, 0001h, 0002h), and the ECC bits.

more details concerning the ECC. improved by using this feature.

5.5.3 Cycling and temperature dependence

Section 1.1.3: Cycling limit of EEPROM cells. this safe operating area is not recommended. Figure 39. Write cycling versus temperature

higher than the safe conditions suggested in Figure 39.

5.5.4 Defining the appl ication cycling strategy

temperature profile of the write cycles performed by the EEPROM.

• Define the main temperature stages at which the EEPROM is operating in the end application.
• For each temperature, estimate the number of write cycles executed for each data block.
• For each data block (with different cycling profiles), calculate the cumulated cycling effect using Table 10. If the total percentage of cumulated cycles (last row in Table 10) is lower than 100%, the data stored in the EEPROM are safely cycled. If the total percentage of cumulated cycles is above 100%, the intrinsic safe margin for cycling is exceeded and a data relocation strategy must be defined. Cycling on each EEPROM cell is not infinite (as shown in Figure 39), it is therefore wise to define a data relocation strategy by distributing the total number of cycles over several memory locations. To do this:
• Define a cycling limit for each data block according to the application needs and product performance (see Table 10).
• Count the numbers of cycles executed on each data block (counter value can be stored in the EEPROM).
• When the counter exceeds the defined limit, the cycled data block must be relocated to another physically independent memory address. The software developer should not move it to a location in the same page (when possible, not in the same column either) as the reference column/page. This means that the 2 addresses should differ by at b. Intrinsic = belonging to the essential na ture or constitution of the EEPROM die (extrinsic = originating from a random event).

Table 10. Application cycling profile evaluation(1)

1. The table can be adapted according to the temperature profile by taking care of putting down the maximum

cycling for each temperature (using Figure 39).

1. w, x, y and z are the forecast number of cycles for a specific data block.

Table 9. for page and column address bits. The counter is then reset and must also

• define data groups or classes (located in the same page) where data with similar update rates are gathered together. This will optimize the use of the Page mode instead of the byte mode.
• the area containing the read-only parameters and the cycled items should be separated and made independent as much as possible. Two types of data should not share the same pages and, where possible, not the same columns. Following the above rules, in laboratory environment, ST EEPROM devices have demonstrated to reach hundreds of millions of cycles, safely.

5.5.5 Overall numbe r of write cycles

The safe value of the overall number of cycling is 10 Million cycles for any ST EEPROM.

AN2014 Power supply loss and application reset

6 Power supply loss and application reset

6.1 Application reset

During the application runtime, the Master may be reset by some external reset condition like a watchdog timer, a power supply monitor, or an ESD. In such case, the serial bus is not controlled (it is left floating) while the power supply stays stable at its nominal value. When this occurs, the challenge is to either control the completion of the ongoing write cycle or to stop the communication with the EEPROM. When the Master is reset, the EEPROM can be:

• deselected in Standby mode. This is the best and safest case. The EEPROM was in the Idle state and will keep this state if the hardware connections are correct. The EEPROM will be ready to accept any new command when the Master is restarted.
• deselected while performing an internal write cycle. It is not a problem as at the end of the self-timed internal write process, the device returns to the standby state. Note that if the Master restarts while the EEPROM is still programming, the Master has to check that the EEPROM is ready by issuing a write cycle polling sequence.
• selected while receiving a command or answering to a Read command. This case has to be handled specifically according to the EEPROM protocol family. The solutions discussed hereafter concern only the case where an EEPROM is selected. The aim of these recommendations is to properly stop the communication with the device in order to avoid further potential disturbances.

6.1.1 I 2C family

The basic principle to protect an I2C transaction is to avoid issuing a Stop condition when a reset occurs. This is because a Stop condition can be decoded as the trigger of an undesired write cycle if the command was a Write and if this Stop condition occurs right at the end of a data byte. On the other hand, the Start condition is a safe event as it resets the internal state machine and as the Start is decoded by a specific logic block that is always active. Smart connections on the I2C bus lines help to avoid erroneous Stop conditions when the Master is reset (I2C bus in high impedance), as described in Figure 40: I2C bus enters the high impedance state (Master reset).

Figure 40. I2C bus enters the high impedance state (Master reset) also detailed in Section 4.1.5.

• Master must first send a re-synchronization sequence to the EEPROM. It consists of 9 START conditions + 1 STOP condition to re-initialize the internal state machine and deselect the device safely. Refer to AN1471 for any help to implement this sequence.
• Master must check that EEPROM is ready (no write cycle in progress) by sending a data polling sequence. Refer to Section 5.2.2: Data polling. Note: For the first read access to the EEPROM, it is recommended to define the internal address pointer with a Random Read instruction as a current Address Read does not change/define the address pointer value. These recommendations allow to maximize the control on the EEPROM in case of inadvertent Master reset. DL F 6&/ 6'$ 6'$ 55/ 6&/ &DVHD 0LJKWEHGHFRGHG DVD6WRSFRQGLWLRQ &DVHE 'HFRGHGDVD 6WRSFRQGLWLRQ 6DIH 6DIH 6&/ 6'$ 6'$ 6&/ &DVH 3XOOXSSXOOXSUHVLVWRUV &DVH 3XOOXSSXOOGRZQUHVLVWRUV &DVHD 'RQ W&DUH VDIH &DVHE $V55/6&/UHDFKHVEHIRUH 6'$ULVLQJHGJH 'RQ¶W&DUH VDIH 6'$ 6&/ 6'$ 6&/

6.1.2 SPI family

• Smart connections of EEPROM pins help to avoid deselect timing violation (tCHSL and tCHSH) when Master releases SPI bus. Refer to Section 4: Hardware considerations section for safe recommendations. At deselect, EEPROM will go into the standby state (see Figure 41: SPI bus enters the high impedance state (Master reset)).
• However, a write cycle may be triggered if the EEPROM is deselected between two data bytes of a write instruction. On 4-Kbit or lower-density SPI device, setting the W pin to Low before deselecting the memory will prevent the write cycle execution.
• When the Master restarts, it must run a data polling sequence to check that the EEPROM is ready (and that no write cycle is in progress). Refer to Section 5.2: Optimal Write control.
• As soon as the SPI device is ready, a WRDI instruction must be issued if the WEL bit in the Status Register is still set to 1. In so doing, the device is protected against any parasitic write instruction. These recommendations will maximize the control on the EEPROM in case of inadvertent Master reset. Recommendations for Master restart can also be the default sequence each time Master comes out of the reset state like after Power up.

Figure 41. SPI bus enters the high impedance state (Master reset)

1. A pull-down resistor on C prevents any t SHCH timing violation (as a pull-up resistor on C causes C and S to

rise at the same time, inducing tSHCH = 0).

6.1.3 MICROWIRE family

Main recommendation for MICROWIRE products is to deselect the device in a safe way.

• Smart connections of EEPROM pins help to avoid deselect critical configurations when Master releases MICROWIRE bus. Refer to Section 4: Hardware considerations section for safe connections. At deselect, EEPROM will go into the standby state (see Figure 42: MICROWIRE bus enters the high impedance state (Master reset)).
• However when deselecting the EEPROM, a write cycle may be triggered if the EEPROM is deselected between two data bytes of a write instruction.
• When Master restarts, it must run a data polling sequence to check that EEPROM is ready (no write cycle in progress).
• As soon as device is ready, an Erase/Write Disable (EWDS) instruction must be issued to disable any WRITE instruction. In this way, the device is protected against any parasitic WRITE instruction. These recommendations will maximize the control on the EEPROM in case of inadvertent Master reset. Recommendations for Master restart can also be the default sequence each time Master comes out of the reset state like after Power up.

Figure 42. MICROWIRE bus enters the high impedance state (Master reset)

1. A pull-down resistor on C prevents any t SLCH timing violation (as a pull-up resistor on C causes C to rise at

the same time as S goes low, inducing tSLCH = 0).

AN2014 Power supply loss and application reset

6.2 Power supply loss

Non-volatile memory data integrity of is a key condition as applications rely on these stored values, mainly at system start up Power loss is critical for an EEPROM device when a Write instruction is being issued or executed. In this event, the on-going write request or the internal write process in the EEPROM may not have been completed, leading to data corruption and data inconsistency.

6.2.1 Hardware recommendations

Application designer will find below some guidelines and recommendations to handle in the best conditions power supply loss on systems designed with STMicroelectronics EEPROM memories. The power supply must designed in such a way that power loss is detected and backup supply is supplied for a time allowing safe emergency ending of the system operations. The list below gives some useful elements to build a robust power management system:

• use voltage regulators including an output voltage sensor. It gives power loss information to the Master before the supply is too low for system operation.
• use available MCU features such as the Auxiliary Voltage Detector and External Voltage Detector pin to create a delay between the detection of the low voltage and the system reset.
• use diodes, bipolar transistors or analog switches to create specific areas with backup power capacitors. The extra delay time gained should be used either to allow the EEPROM to complete any on-going write process or to allow the Master to finish or interrupt safely the current communication with the EEPROM. In a running application it is not possible to distinguish these two possibilities, therefore the below recommendations must be considered all together.

6.2.2 Supply voltage energy tank capacitor

In case of inadvertent power loss, applications are very often faced with the situation where the EEPROM is operating while power supply is falling down. It is not recommended to operate the device and in particular to initiate write operations when the device is undergoing steady VCC transitions. ST EEPROM devices can however handle write cycles during smooth power supply transitions. A power supply transition is considered smooth when it allows a complete write cycle to be completed while VCC is continuously falling or rising within the authorized VCC range. Taking advantage of this possibility, a power backup capacitor can be designed to allow for the EEPROM to complete its on-going self-timed write operation in case of inadvertent power loss. The capacitor value is calculated so as to allow for the full write cycle to be executed:

• l is the EEPROM supply current (ICC max)
• t is the EEPROM write time (tW)
• U is the voltage drop from the nominal value to VCC min of the EEPROM Q = C × U = I × t => C = (l × t) / U For instance: C = (3 mA × 5 ms) / 2 V = 7.5 µF

Figure 43. EEPROM power backup capacitor

1. Sometimes filtering capacitors placed after voltage regulators, are big enough to allow the EEPROM

device to finish the write operation. In this case, backup capacitors are no longer necessary. will discharge the backup capacitor through the MCU connection.

• take into consideration the long discharge time to allow the EEPROM VCC supply to reach ground level (0 V) before setting the application supply voltage active, or
• add a discharge path to ground to accelerate the discharge if the system may or must be re-started after a short time When applying this recommendation, please read also Section 3.3.1: Power-up and power- on-reset sequence.

6.2.3 Interruption of an EEPROM request

• Drive the WC pin High. One SCL clock pulse will inhibit the current write request.
• Send a START condition followed by a STOP condition (a START condition resets the device and a STOP condition sets it in standby mode). The re-synchronization sequence described in AN1471 can also be used. See Figure 44: Emergency sequence I2C products. DLE ((3520 9&& 966

Figure 44. Emergency sequence I2C products Note: This emergency sequence is detailed in the AN1471. an eventual engaged write cycle to end correctly (tW = 5 ms).

• Drive the W pin Low while the device is selected. One clock pulse will reset the WEL bit in the Status Register (any current write request will be ignored).
• Deselect the EEPROM by driving the S pin High. Warning: If the SPI device is deselected between two data bytes of a write request and W has not been driven Low, a write cycle may be triggered. SPI products (8 Kbit and larger) Emergency procedure to interrupt a SPI request:
• drive W pin low while device is selected. Only the WRSR instruction will be ignored, the execution of a Write (to memory) is not discarded by the W pin for 8 Kbit products and larger.
• Deselect the EEPROM driving S pin High. Warning: If the chip is deselected between two data bytes of a write request, a write cycle may be triggered. DL F FORFNSHULRG 67$57 «67$57 6723 a—VDW)F N+] W Z PV 2EWDLQLQJSRZHU ORVVLQIRUPDWLRQ (IIHFWLYHSRZHUORVV

Figure 45. Emergency sequence SPI products eventual write cycle to complete correctly.

• drive W pin low for M93Sxx(c) devices. One clock pulse will discard the current write request.
• deselect the EEPROM by driving the S pin Low. Warning: If the chip is deselected between two data bytes of a write request and W has not been driven Low, a write cycle may be triggered (see Figure 46: Emergency sequence MICROWIRE products) DL F FORFNSHULRG WZ PVa—VDW)F 0+] (IIHFWLYHSRZHUORVV2EWDLQLQJSRZHU ORVVLQIRUPDWLRQ c. W pin is available on M 93Sxx products (not available on M93Cxx products).

Figure 46. Emergency sequence MICROWIRE products eventual write cycle to complete correctly.

Power supply loss and application reset AN2014

6.3 Robust software an d default operating mode

In sensitive applications such as automotive, safety or medical applications, it is not acceptable for a system to enter a locked state or an endless loop, because of bad EEPROM communications. In many cases, simple software rules can help to secure operation of the application.

• WRITE: It is recommended to add a time-out counter to the Write data polling loop to prevent the application from being locked if, for some unknown reason, the application software cannot exit from an endless Write data polling loop. After each write cycle, the software should always verify that data has been correctly programmed by reading back the data.
• READ: When reading data from the EEPROM, the application software should check whether the data value is within an acceptable range and, if not, switch to a default value allowing continuity in the application operation.
• As recommended, data in the EEPROM can be duplicated and associated with a checksum and an Error Code Correction mechanism. In particular default parameters can be stored in a protected part of the memory array (Read-Only array, the write-lock being defined by software) or in another available non-volatile memory. The MCU should then be able to access an external memory in order to copy the missing parameters back to the EEPROM.
• Moreover, it is safer to have a default operating mode that can run with a reduced set of default parameters. Refer also to Section 5.3: Write protection and Section 5.4: Data integrity.

AN2014 Operating conditions

7 Operating conditions

There are many other operating conditions, imposed by the final application environment, that may also have an adverse affect on the EEPROM device (shortened lifetime or unreliable operation). They should be studied, and solutions must be found to minimize them.

7.1 Temperature

The temperature should be kept as low as possible, since high temperatures accelerate wear-out. At high temperatures, cycling endurance and data retention capability are reduced because of charge trapping in the thin oxide of the memory cells. When applications are designed to run in hot environments with high cycling requirements, it is strongly recommended to establish a temperature profile and discuss it with the ST EEPROM quality support (refer to Section 5.5: Cycling endurance and data retention).

7.2 Humidity and chemical vapors

Boards should always operate in a clean and dry environment. Humidity and dirt of any kind can cause corrosion and short circuits between package pins and tracks.

7.3 Mechanical stress

EEPROM packages cannot withstand excessive weight, local pressure or strong shocks.

8 Conclusions

Electrically Erasable and PROgrammable Memory (EEPROM) devices are standard products, used for the non-volatile storage of parameters, with fine-granularity data. There is no single memory technology (SRAM, DRAM, EEPROM, Flash Memory, EPROM, ROM) that meets all application needs perfectly. In the case of an EEPROM, an application designer needs to know the particular strengths and weaknesses of the device technology and device architecture in order to define an optimal control of parameters for his application. In doing so, the application will remain within the specification, with the best performances and reliability level.

9 References

• AN1471, What happens to the M24xxx I²C EEPROM If the I²C bus communication is stopped?
• AN2440, Embedded ECC in F8H process automotive EEPROM: device architecture and related application guidelines.

Table 11. Document revision history 28-Oct-2005 1 Initial release. modified. Small text changes. up resistor on SDA and Note 1 modified. Note modified below Figure 22. Section 5.4: Data integrity modified. and content transferred to Section 3.3.1 on page 21. Serial Clock (C) (MICROWIRE). Figure 31: Recommended MICROWIRE connections - robust design. Maximum C2 value modified in Figure 32: PCB decoupling. Recommended I2C EEPROM connections clarified. Section 4.4.3: Communication lines removed. the high impedance state (Master reset) modified. an appropriate memory interface. Updated POR threshold in Table 3: Typical POR threshold values. dependence. Added Section 5.5.2: Optimal cycling with ECC.

Updated Figure 2: MOSFET-like operation. Updated Section 1.1.2: Writing a new value to the memory cell. Updated Section 1.1.3: Cycling limit of EEPROM cells. Updated Section 1.2.1: Memory array architecture. Updated Table 1: Three serial bus protocols. Recommended I2C EEPROM connections. Updated Section 6.1: Application reset. Table 11. Document revision history (continued)

Modified Introduction and Conclusions. Updated clock rate data in Table 1. Changed Figure 39: Write cycling versus temperature. Added specific values relating to process letter K. protection and Section 5.5.4: Defining the application cycling strategy. Updated Note below Figure 10 and Footnote 1 of Figure 29. Other text updates throughout the document, without any context change.