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TEA19361T GreenChip SMPS control IC Rev. 1.1 — 5 October 2017 Application note Document information Information Content Keywords TEA19361T, Discontinuous Conduction Mode (DCM) flyback converter, high efficiency, burst mode operation, Quasi-Resonant (QR) mode operation, low audible noise, low power consumption, multiple-output voltage applications Abstract The TEA19361T is a high-featured low-cost DCM and QR mode flyback converter controller. It provides high efficiency at all power levels and very low no-load power consumption at nominal output voltage in burst mode operation. To minimize the risk of audible noise, the TEA19361T includes an enhanced burst mode. The TEA19361T is designed to support multiple-output-voltage applications like USB PD (Type C) power supplies. Typical applications include notebooks and tablet adapters, fast charging, and direct charging adapters.
Table 1. Revision history Modifications: • Section 2.4 Features and applications - Applications has been updated.
- Section 3 Functional description has been updated.
- Section 6 Secondary side implementations - various options has been updated. v.1 20170908 first issue
NXP Semiconductors AN11879 TEA19361T GreenChip SMPS control IC Application note Rev. 1.1 — 5 October 2017
1 Introduction
This application note describes the implementation of TEA19361T functions in practical applications. Information is provided on a practical converter design. The TEA19361T operates in DCM mode and QR mode with valley switching for optimal efficiency. The burst mode is optimized for minimal audible noise. It is suited for applications using touch screens with standard Common Mode Noise requirements. Additional family members are TEA19362T, TEA19363T, TEA19363LT, and TEA1938T. The TEA19362T only operates in Fixed Frequency (FF) DCM mode. It is intended for mobile applications using touch screens requiring high spectral purity from the supply to prevent disturbance of the touchscreen operation. The TEA19363 operation can be compared with the TEA19361T operation, but it also includes active X-capacitor discharge. Furthermore, the TEA19363 comes in a latched (TEA19363LT) and a non-latched version (TEA19363T). When an OVP or OTP exception occurs, the latched version halts operation. The non-latched version initially halts and then resumes operation via a safe restart strategy. The higher Common Mode Noise due to the X-capacitor discharge function makes it less suitable for applications with touchscreen. The TEA1938T is comparable to the TEA19361T. It contains a different burst mode, which is optimized for minimum ripple. The HV pin and VCCH pin have an ESD rating of 2 kV (for the TEA1936x, the level is 1 kV). It is suited for applications using touch screens with standard Common Mode Noise requirements. Each section can be read as a standalone description with few cross-references to other parts of the application note or the data sheet. Unless stated otherwise, typical values are given to enhance the readability.
2 Features and applications
2.1 General features
- Switched-Mode Power Supply (SMPS) controller IC supporting smart-charging applications and multiple-output-voltage applications
- Wide output range (5 V to 20 V in Constant Voltage (CV) mode, 3 V to 20 V in Constant Current (CC) mode, and 3 V to 6.5 V for direct charging)
- A combination of operating modes (burst mode, Frequency Reduction (FR) mode, DCM mode, and QR mode) enables enhanced efficiency
- Small SO10 package
- Adaptive dual supply for highest efficiency over the entire output voltage range
- Integrated high-voltage start-up
- Continuous VCC regulation during start-up and protection via the HV pin, allowing minimum values for the buffer capacitors that are connected to the VCCL and VCCH pins
- Reduced optocoupler current enabling low no-load power (20 mW at 5 V output)
- Fast transient response from zero to full load
- Minimal audible noise and output voltage ripple in all operating modes
- Integrated soft start
NXP Semiconductors AN11879 TEA19361T GreenChip SMPS control IC Application note Rev. 1.1 — 5 October 2017
2.2 Green features
Enables high efficiency operation over a wide power range via:
- Low supply current during normal operation (0.6 mA without load)
- Low supply current during non-switching state in burst mode (0.2 mA)
- Valley switching to minimize switching losses
- Frequency reduction with fixed minimum peak current to maintain high efficiency at low output power levels
- QR controller can be used in combination with NXP Semiconductors Synchronous Rectification (SR) controllers for optimal efficiency performance
2.3 Protection features
- Mains voltage compensated OverPower Protection (OPP)
- OverTemperature Protection (OTP)
- Integrated overpower timeout
- Integrated restart timer for system fault conditions
- Continuous mode protection using demagnetization detection
- Accurate OverVoltage Protection (OVP)
- General-purpose input for safe restart protection; used with system OverTemperature Protection (OTP)
- Driver maximum on-time protection
- Brownin and brownout protection
- The TEA19361T OVP and OTP protections are safe restart protections
2.4 Applications
- Supports multiple-output-voltage applications
- Easy implementation of a USB-PD (type C) application together with the NXP Semiconductors TEA1903 or TEA1905 secondary side controllers
- Allows easy implementation of a direct charge application using Constant Voltage (CV) and Constant Current (CC) mode
- Notebook, netbook, and tablet adapters and chargers
NXP Semiconductors AN11879 TEA19361T GreenChip SMPS control IC Application note Rev. 1.1 — 5 October 2017
3 Functional description
This section describes the functional behavior of the TEA19361T IC on the primary side of an SMPS application. The TEA19361T can operate with various implementations of the secondary side of the SMPS:
- Single fixed voltage SMPS, e.g. a single 19.5 V output voltage (for notebooks)
- Multiple fixed voltages SMPS, e.g. simultaneous 12 V and 5 V output voltages
- Single variable voltages SMPS, e.g. 5 V, 9 V, 12 V, or 19.5 V switchable or autoswitchable output voltage (for USB-PD) that typically uses a TEA1903 or TEA1905 secondary controller
3.1 Application - primary side
The general behavior of the primary side of the applications that use the TEA19361T is explained using the elementary circuit diagram shown in Figure 1.
250 V (AC)
Figure 1. Typical TEA19361T application diagram – primary side only
3.2 Pinning
3.2.1 Pin configuration
Figure 2. TEA19361T pin configuration (SOT1437-1)
3.2.2 Pin descriptions
Table 2. Pin descriptions
1 VCCH High IC supply voltage input
transformer with a higher voltage than the auxiliary winding uses for the VCCL pin. makes the TEA19361T operate on the VCCH voltage. VCCH and VCCL is switched off. The supply current is taken from the VCCL voltage. excessively high voltage. The latter causes unnecessary power loss.
2 GND Ground connection; reference for other pins
3 VCCL Low IC supply voltage input and source for the internal HV start-up output
All internal circuits, except the high-voltage circuit, are supplied from this pin.
- Internal High-Voltage (HV) start-up source (start-up and protection). The capacitance on the VCCH pin is also charged via an internal diode between the VCCH and VCCL pins. It can be used as energy reservoir during start-up before the auxiliary supply takes over.
- Auxiliary winding from the flyback transformer (when switching)
- External DC supply When the voltage on the VCCL pin reaches 14.9 V, IC operation is enabled. In burst mode, when the voltage on the VCCL drops to below 11 V, additional switching cycles are generated. The switching cycles prevent that the VCCL voltage drops to below the stop operation level. This voltage drop can occur when no energy is required on the secondary side for a prolonged time after a load step from maximum to no load. When the voltage on the VCCL pin drops to below 9.9 V, the IC halts operation. Shutdown reset is activated at 8.65 V.
NXP Semiconductors AN11879 TEA19361T GreenChip SMPS control IC Application note Rev. 1.1 — 5 October 2017 Pin Pin name Functional description summary
4 ISENSE Current sense input
This pin senses the primary current through the MOSFET switch via an external resistor.
- Soft start A soft-start procedure is used to limit stress and audible noise during start-up. The Ipk level, measured over the sense resistor, is gradually increased to the regulated level in 15 steps. The soft-start time constant is 4 ms.
- Burst mode In this mode, the peak current is kept constant. When a fixed level of 145 mV is reached on the ISENSE pin, the drive switches off. Controlling the number of strokes per burst cycle regulates the output voltage and output power.
- FR mode In this mode, the peak current is also kept constant using a fixed switch-off level of 145 mV at the ISENSE pin. The output voltage and output power are regulated by controlling the switching frequency.
- DCM mode In this mode, the switching frequency is kept more or less constant. The increase or decrease of the peak current regulates the output voltage and output power. The voltage level for switch-off is regulated from 145 mV upward to the level that the controller can no longer operate at the fixed frequency. The reason is that the primary and secondary strokes become too long. At that moment, the controller switches to QR mode.
- QR mode In this mode, the peak current is increased to regulate the output voltage and output power. The operating frequency is reduced because the system relies on the discontinuous conversion principle. The voltage level for switch-off is regulated between 145 mV and 510 mV.
- Leading-edge blanking During the first 325 ns of each switching cycle, the ISENSE input is internally blanked. The blanking of the ISENSE input prevents that the spike caused by parasitic capacitance triggers the peak current comparator prematurely.
- Propagation delay There is a delay between the moment the ISENSE comparator is triggered and the MOSFET is switched off. During this time, the primary current continues to increase. How much it increases, depends on the dI/dt slope, and so, on the mains voltage. So, the resulting peak current not only depends on the level set by control, but also on the mains voltage.
- Overpower protection counter When the voltage on the ISENSE pin exceeds the overpower protection level (510 mV), the overpower counter is started. When the overpower timer reaches 200 ms (40 ms during start-up), a safe restart is initiated.
- Overpower compensation for mains voltage by AUX sensing current To compensate the output power level for dependency on the input voltage, an overpower compensation circuit regulates protection level based on the input voltage sensed on the AUX pin.
5 DRIVER MOSFET gate driver output
NXP Semiconductors AN11879 TEA19361T GreenChip SMPS control IC Application note Rev. 1.1 — 5 October 2017 Pin Pin name Functional description summary
6 AUX Auxiliary winding input
A resistor divider on the AUX pin applies the voltage from an auxiliary winding of the flyback transformer. The voltage on this pin is used for four functions in four different time slots:
- Demagnetization detection When the AUX voltage drops to below 40 mV, demagnetization is detected. Only when demagnetization is detected, the driver can be switched on to start the next power conversion cycle.
- Valley detection After demagnetization, an internal dV/dt detector circuit detects a valley. Depending on the operating condition, the MOSFET switches on at the first valley or one of the subsequent valleys.
- Input voltage sensing for OPP compensation When the external MOSFET is switched on, the voltage at the auxiliary winding reflects the input voltage. During this period, the AUX pin is clamped to −0.7 V. The measured input current is used to calculate the maximum allowed voltage on the ISENSE pin. Changing the value of the series resistor between the auxiliary winding and the AUX pin adjusts the measured current.
- Output voltage sensing for OVP The resistor for input voltage sensing and a resistor from the AUX pin to ground make up a voltage divider. During secondary stroke, the divider voltage reflects the output voltage. The internal level for OVP detection is 3 V. The divider must be dimensioned for a 3 V level during secondary stroke at the desired OVP level on the secondary side.
7 CTRL Control input
In DCM, the control current flowing out of the CTRL pin is regulated to an 80 μA fixed value for all modes. The regulation of the control current is achieved by generating an internal offset which regulates the power level via the internal control curve. In burst mode, the control current level varies between 100 μA and 200 μA. The internal voltage of the CTRL pin is 3 V with a 1.5 kΩ series resistance to the pin.
8 PROTECT Protection
When the voltage level on the PROTECT pin drops to below 0.5 V, a safe restart is initiated after 2 ms to 4 ms. When the pin voltage is lower than 1.45 V, an internal current source delivers −74 μA out of the pin. When the pin voltage reaches 1.45 V, the internal current source is automatically pinched off. Connecting a suitable NTC from the PROTECT pin to GND can realize an external OTP for the system. 9 n.c. Not connected This pin has no internal connection. It is used as high-voltage spacer.
NXP Semiconductors AN11879 TEA19361T GreenChip SMPS control IC Application note Rev. 1.1 — 5 October 2017 Pin Pin name Functional description summary
10 HV High-voltage start-up
The HV pin combines two functions:
- High-voltage current source At start-up, the 1.1 mA HV current source is used to charge the VCCL capacitor (and via a diode also the VCCH capacitor). In this way, IC operation can start. Until VCCL reaches the start-up level (14.9 V), the IC current consumption is limited to 40 μA. When all conditions (VCCL start-up level, PROTECT pin level, and CTRL pin level) are met, start-up commences.
- Mains voltage sensing Sampling the HV input current value every 1 ms senses the mains voltage during operation. Pulling the HV input to 2.9 V for 20 μs measures the HV input current. The series resistance of the HV pin to the bulk electrolytic capacitor determines this current value. It reflects the mains voltage value. The value of the external series resistors between bulk electrolytic capacitor and HV pin can set the start and stop levels. When the current exceeds 663 μA, start-up is enabled (brownin). When the current drops to below 587 μA for more than 30 ms, the operation is stopped (brownout). The 30 ms period is required to avoid that the system stops switching due to the zero crossings of the mains or during a short mains interruption. During operation, conditional sensing control reduces the sampling frequency. When a mains voltage is detected, mains voltage sensing is halted for 7 ms (104 ms during burst mode) to improve efficiency.
3.3 Operating modes
cooperation enables optimal efficiency. typical voltage and current waveforms when the converter operates in DCM (or BCM). Figure 3. Flyback converter in DCM
the MOSFET drain node during tdead. The next cycle can then start. Figure 4. Practical effects of parasitics
- QR mode (high power level)
- DCM at near-fixed frequency (medium-high power level)
- DCM with frequency reduction (medium-low power level)): FR DCM
- Burst mode (low power level) Depending on the required output power, the system switches between operating modes. The goal is to provide the best performance for each power level. The switching frequency is kept constant in DCM and in burst mode. The best performance is based on the highest efficiency and the lowest losses. During operation, the switching frequency of the SMPS application varies with the required output power level and with the supplied input voltage.
Figure 5. TEA19361T flyback operating modes
3.3.1 Flyback operating modes control
current mode control. Figure 6 shows the principle. Figure 6. Current mode control
3.3.1.1 CTRL pin during FR DCM, FF DCM, and QR modes
increases and so the optocoupler current increases until ICTRL becomes 80 μA again. power, which ensures stable operation at all output power levels.
3.3.1.2 CTRL pin during burst mode
burst mode. The burst mode and related ICTRL waveforms are discussed in Section 3.3.5. In burst mode, when ICTRL < 80 μA for a longer period, the IC enters normal mode again.
3.3.1.3 CTRL pin provisions load steps
- When the burst-on time is longer than 1.5 times the minimum burst period (600 μs) during a burst period, the IC changes to normal mode immediately.
- In burst mode, when ICTRL remains below 100 μA due to increased load, the IC keeps on switching at 25.5 kHz with a minimum Ipk level (145 mV).
- When ICTRL drops to below 60 μA due to increased load, the gain is increased and the time constant is reduced. To counteract the voltage drop at the output, the IC moves quickly to maximum power.
- When the load suddenly decreases to very low values and ICTRL increases to exceed 200 μA, switching stops immediately to prevent a high output voltage overshoot.
3.3.2 Quasi-Resonant (QR) mode
Figure 7. MOSFET drain voltage showing ZVS and LVS valley switching situations voltage and the output voltage. Table 3. ZVS and LVS valley switching situations for Vin and Vout
- Situation 1: Vin < n × Vout The drain voltage tends to become negative. However, the internal body diode of the MOSFET starts conducting. The voltage is clamped at the negative voltage drop of this diode. The controller also detects this situation as a valley. At the moment of detection, the MOSFET is switched on again.
- Situation 2: Vin = n × Vout The minimum drain voltage is zero. When the controller detects that the minimum drain voltage is zero, the MOSFET is switched on again. Calculations are frequently based on this condition. In situation 1 and 2, the switch-on losses are zero. In a high-efficiency
- Situation 3: Vin > n × Vout When the controller detects this valley, the minimum drain voltage remains > 0. Nevertheless, switch-on losses are minimized in this situation. The QR flyback converter operates on the border of Discontinuous Conduction Mode (DCM) and Continuous Conduction Mode (CCM). It is called Boundary Conduction Mode (BCM). Sometimes, it is also called Critical Conduction Mode (CrCM). The result is lower peak and RMS currents in the circuit (compared to FF DCM flyback) and lower switching losses (compared to CCM flyback). The combination contributes to more efficient power conversion. When operating in QRM, the TEA19361T switches on in the first valley after demagnetization. The results are minimal switching losses and a short dead time. The Ipk increases for higher power levels. This increase also causes the switch-on time and the secondary stroke time to become longer. The longer times reduce the switching frequency (see Figure 5).
3.3.3 Fixed-Frequency Discontinuous Conduction Mode (FF DCM)
the increase of dead time (tdead). example of the primary MOSFET drain voltage where switch-on occurs in distinct valleys. Figure 8. MOSFET drain voltage for Fixed Frequency DCM with valley skipping
3.3.4 Frequency Reduction Discontinuous Conduction Mode (FR DCM)
transfer. In all circumstances, the TEA19361T controller switches on in a valley. capacitive components in the application. Figure 9. MOSFET drain voltage for FR DCM with constant peak current
3.3.5 Burst mode
Burst mode operation is used to minimize power loss during low output power conditions. switching, conversion losses are zero. than half the nominal supply current during switching. Figure 10. Principle of burst mode operation and associated Vout ripple
Figure 12. Burst mode operation for different loads in burst related to ICTRL 100 μA. Only when the ICTRL drops again to below 100 μA, the next stroke is made. the behavior remains the same. to 80 μA. The internal offset takes over the regulation.
Figure 13. Burst mode frequency as a function of the number of strokes per burst
3.3.6 Loop gain and burst period
200 μA) determines the switching behavior (see Figure 14).
Figure 14. Burst period when ICTRL surpasses 200 μA Figure 14(b) shows that the burst period reduces when ICTRL exceeds the 200 μA level. The dashed ICTRL line indicates the intended (precalculated) behavior. The loop gain can be optimized to balance load step behavior and burst mode behavior.
3.4 TEA19361T start-up and supply
switching, the auxiliary winding takes over the supply of the VCCH and VCCL pins.
3.4.1 Start-up with the HV current source
- High-voltage current source for charging the capacitors at the VCCH and VCCL pins before start-up
- Mains voltage sensing input for detecting brownin and brownout The HV pin can be connected to the high voltage in two ways:
- With a diode/capacitor/resistor network before the mains rectifier bridge
- With a resistor network after the mains rectifier bridge Figure 15 shows both configurations.
NXP Semiconductors AN11879 TEA19361T GreenChip SMPS control IC Application note Rev. 1.1 — 5 October 2017 The main supply pin, which is directly connected to the internal IC supply is the VCCL pin. The VCCH pin is connected to the VCCL pin via an internal regulator. If the supply voltage via the AUX low is lower than 12.5 V, the internal regulator regulates the VCCL to 12.5 V. When the supply voltage via the AUX low pin exceeds 12.5 V, the regulator is turned off. The supply is taken from the VCCL pin. In this way, the lowest voltage that is high enough to supply the IC is always selected to save power. The IC consumes power from the supply as a current source. So, the supply dissipation increases almost linearly with the IC supply voltage. To charge the capacitors on the VCCL pin and, via the diode, also the capacitors on the VCCH pin, an internal 1.1 mA current source is enabled at start-up. The internal current source is taken from the high-voltage mains connected to the HV pin. Charging these capacitors enables the use of the full capacitance available on both pins as an energy reservoir at start-up. If the capacitance value at the VCCH pin is high enough, it offers the possibility to use a lower capacitance value on the VCCL pin than is required for start-up. As long as VCCL is below system start-up level (14.9 V), the current consumption of the internal IC circuits is limited to 40 μA. When the HV pin is connected before the bridge rectifier, the voltage on the pin may become close to 0 V. The current source is then temporarily unable to generate the 1.1 mA (typical) current required. A discontinuous increase of the VCC voltage can be observed. Depending on the applied input voltage, the series resistance between the HV pin and the mains voltage can also limit the current. When VCCL reaches the start-up level (14.9 V) during charging, the internal circuits are activated. From this moment, the start-up sequence is activated. The IC current consumption increases (600 μA for the internal IC circuits, the current for the MOSFET drive, and the CTRL function). First, all protections are checked. Further start-up is halted until the brownin condition is met and the protect pin voltage exceeds 0.55 V. Then, switching is enabled. Switching commences with a soft start. During the soft start, the peak current increases to its maximum level in 15 steps. This current increase is achieved by increasing the voltage level for switch-off of the ISENSE pin from 0 mV to 510 mV. The current source of the HV pin remains active. However, it cannot provide all the energy required. So, the VCC voltage decreases until the auxiliary high or auxiliary low winding take over the supply. When the output voltage reaches the regulation level, the HV current source is switched off. The CTRL pin detects when the output voltage has reached the regulation level. For a reliable implementation of a VCC supply at start-up and during burst operation under all conditions, use a 10 μF VCC capacitor. When space and/or cost are critical, it is possible to apply 10 μF on the VCCH pin and 1 μF on the VCCL pin. The only drawback to this configuration is that there is a slightly higher no-load power consumption. The higher power consumption occurs when a higher output voltage can be generated with the IC operating on the auxiliary low winding during normal (medium or high power level) operation. However, it must switch to auxiliary high during long non-switching periods (e.g. low power or no load). The value of the capacitor chosen for the VCCH pin must be equal or higher than the value of the capacitor on the VCCL pin. The reason is that during burst the VCC capacitors are only charged at a very low repetition rate during a very short time. The peak charging current can easily surpass 1 A. When the auxiliary high provides the supply under this condition, the series impedance of the series regulator is too high to allow proper charging of a high-value capacitor on the VCCL pin.
3.4.2 Supply protection
11 V (Vrestart)VCCL
Figure 17. Keeping the VCCL voltage up during long non-switching periods
- Load drops from maximum to zero
- The VCCL voltage has decreased to the Vrestart level (11 V)
voltage drops again. When it reaches 11 V again, the sequence is repeated.
- Vout decreases slowly over time, causing ICTRL to decrease also.
to below the saturation level. As long as Vout keeps decreasing, ICTRL keeps dropping.
- When ICTRL has dropped to 100 μA, normal burst switching is resumed.
The VCCL voltage increases to the normal level in burst mode.
- The system is in normal burst mode again.
All voltages and currents are at the normal level.
3.5 Mains voltage detection
the sampling period, a voltage of 2.9 V can be observed on the HV pin. Figure 18 shows the measuring setup of the mains sensing. Figure 18. Mains voltage sensing circuit
NXP Semiconductors AN11879 TEA19361T GreenChip SMPS control IC Application note Rev. 1.1 — 5 October 2017 When the mains sense switch closes, the current is measured. The value of the resistors between the HV pin and the rectified mains determine the current for lower input voltages. For higher input voltages, the current source in series limits the current to 1.1 mA.
3.5.1 Brownin
When the VCCL pin is charged to the start level, mains sensing is activated to generate one of the required conditions for starting the converter. The rectified mains voltage is sensed in the normal sequence of three pulses and a wait time of 7 ms. When one pulse shows a value that exceeds the brownin value (663 μA), converter start-up is enabled (as far as meeting the brownin requirements is concerned). Sensing continues after start-up. The brownin level can be calculated with Equation 1: (1) Example:
- Ibi(HV) = 663 μA
- Vmeas(HV) = 2.9 V
- Vmains(RMS) = 86.0 V; The required brownin level If the brownin level is not met when the VCCL voltage has reached Vstart, the HV current source regulates the VCCL voltage on 14.9 V. In this way, when the brownin level is reached, the IC can start immediately.
3.5.2 Brownout
If the mains voltage remains below the brownout level for at least 30 ms, a brownout is detected. The system stops switching. This delay period is built in to ensure that the system does not stop switching during a short mains interruption. The brownout level can be calculated with Equation 2: (2) Example:
- Ibo(HV) = 587 μA
- Vmeas(HV) = 2.9 V
- Vmains(RMS) = 76.5 V; The required brownout level
Figure 19. Brownin and brownout levels as a function of the HV series resistor value
3.6 TEA1936T MOSFET driver
internal source supplying the driver stage. Figure 20. Simplified model of the MOSFET driver the external MOSFET is switched on by charging the gate to a high voltage.
- The supply voltage for the internal driver (10.5 V) at switch-on
- The characteristics of the internal driver MOSFETs (RDSon)
- The value of the gate capacitance of the external MOSFET
- The switch-on/switch-off gate threshold voltage of the external MOSFET The TEA1936x data sheets provide the characteristics of the internal drivers.
Table 4. MOSFET driver characteristics
3.7 Auxiliary windings
- Supply voltage for the TEA19361T on the VCCL and the VCCH pins
- Sensing signal on the AUX pin In a transformer with separate auxiliary windings for the VCCL and VCCH pins, one of the two windings must be used to feed a signal to the AUX pin. In practice, it is the easiest to use the VCCL auxiliary winding because its voltage is lower and it saves some dissipation. The signal from the auxiliary winding is used to sense several variables that are used for control and protection:
- Demagnetization detection
- Valley detection
- Input voltage sensing for maximum output power compensations
- Output voltage sensing for indirect OVP The voltage from an auxiliary winding of the flyback transformer is connected to the AUX pin using a resistive divider. Figure 21 shows the circuit. aaa-024480 AUX VCCH VCCL Raux2 Raux1 CVCCH auxiliary high auxiliary lowCVCCL
Figure 21. AUX pin circuit configuration provided the values of the resistors are adapted for the higher voltages.
the AUX pin. It enables adjusting the position of the valley switching more accurately. Each detection function has its own time slot in the repetitive AUX signal. Figure 22. The AUX pin is used for demagnetization, input voltage, and output voltage
3.7.1 Demagnetization detection
When the signal on the AUX pin drops to below 40 mV, demagnetization is detected. transformer to the output has become zero.
3.7.2 Valley detection
effect on the efficiency of the converter.
3.7.3 Input voltage sensing for compensation
Figure 23. Compensation of the overpower levels (using VISENSE) for input voltage (using The compensation is optimized for use in QR mode.
- Lp is the primary inductance
- Ipk is the peak current value
- fsw is the switching frequency
- η is the converter efficiency Working out the formula further for QR: (4) Where:
- tperiod is the duration of one switching cycle
- tprim is the duration of the primary stroke
- tsec is the duration of secondary stroke
- tringing is the duration of one period of ringing after ending the secondary stroke; 0.25tringing is the time from the end of the secondary stroke to the first valley.
NXP Semiconductors AN11879 TEA19361T GreenChip SMPS control IC Application note Rev. 1.1 — 5 October 2017 (5) Where:
- Vbulk is the voltage of the mains electrolytic capacitor (6) Where:
- n is the primary winding to secondary winding transformer ratio
- Vout is the output voltage For ease of understanding 0.25tringing is neglected. Filling in and working out the formula for Pout we get: (7) So the maximum Pout in QR mode is proportional to the value of Ipk. However, it also depends on the level of Vbulk. To keep the maximum power constant when Vbulk varies due to the AC input voltage range, the value of Ipk must be adapted according to the value of the input voltage. The maximum switch-off voltage level on the ISENSE pin at which the OPP counter is triggered determines the maximum Ipk level. This level is 510 mV without input voltage compensation. To keep the maximum output power constant over the mains voltage range, Ipk can be lowered to 298 mV for higher input voltages using input voltage compensation. The main relationship between the input voltage for the flyback converter and the current measured at the AUX pin can be calculated with Equation 8: (8) Because the AUX input combines the input voltage compensation with the OVP protection, a resistor Raux2 to GND is also connected. An additional small current flows through the Raux2 resistor to GND. At low mains voltage, a significant amount of current is added to the total current from the AUX pin (depending on the circuit values; e.g. 10 %). (9) (10)
NXP Semiconductors AN11879 TEA19361T GreenChip SMPS control IC Application note Rev. 1.1 — 5 October 2017 The overpower functions use the compensation from the measured AUX current (see Section 3.8.1).
3.7.4 Output voltage sensing for OverVoltage Protection (OVP)
During the secondary stroke, the voltage on the AUX pin is proportional to the output voltage, which is used for an OVP protection for the secondary voltage. To avoid a wrong level detection due to voltage ringing effects, output voltage sensing is enabled 2.4 μs after the primary MOSFET is switched off (see Figure 21 and Figure 22). Together with the resistor for input voltage sensing (Raux1), a voltage divider can be made using a resistor from the AUX pin to ground (Raux2). The value of this resistor provides a conditioned signal at which an OVP can be detected. The preset internal level for OVP is 3 V. For a reliable protection function, the voltage on the AUX pin must reflect the output voltage accurately. The basic relationship (neglecting the output voltage drop via the output rectifier and output cable) between the auxiliary voltage and the output voltage is the transformer turns ratio: (11) The value of Raux1 must be determined for the overpower function. The value for Raux2 can be chosen to provide the correct protection level for the OVP. (12) (13) Example:
- Naux = NO
- Raux1 = 47 kΩ
- VO(ovp) = 25 V
- VAUX(ovp) = 3 V Solving the equation above for Raux2:
3.8 Primary current sensing
measured provides information about the power level. by the ISENSE pin) determines the maximum power level. MOSFET. It is also used to detect the various states of conversion.
3.8.1 Soft start
Figure 24 shows an example of the Ipk behavior during start-up. Figure 24. Ipk during soft start
3.8.2 OverPower Protection (OPP) counter
the AUX pin (see Section 3.7.3), the protection level can be lower for higher voltages.
to variations of the ISENSE voltage over time, the counter can sometimes be reset.
3.8.3 OPP and UnderVoltage LockOut (UVLO) on the VCC pin
3.8.4 ISENSE pin accuracy
MOSFET switch-off value and when the MOSFET is switched off (tPD(sense) = 120 ns). delay period depends on the di/dt slope. The di/dt slope depends on the mains voltage. Figure 25. Leading-edge blanking and a higher peak current due to delay saturation conditions must be avoided because the converter operation is unpredictable.
3.8.5 ISENSE pin reference levels modulated by input voltage
converter has an impact on the compensation function of the AUX and ISENSE pins.
3.9 Protections
the circuit when errors occur, every protection triggers a safe restart sequence. To avoid false triggering, some protections have a built-in delay. current source on the HV pin keeps the VCCL level above the critical level. Table 5. Protections overview
3.9.1 Safe restart sequence
system continues as in the normal start-up sequence.
NXP Semiconductors AN11879 TEA19361T GreenChip SMPS control IC Application note Rev. 1.1 — 5 October 2017
3.9.2 Brownout
Brownout is discussed in Section 3.5.2.
3.9.3 Maximum on-time
To prevent extreme power under fault conditions, the controller limits the driver on- time for the external MOSFET to 55 μs. When the on-time exceeds 55 μs, the IC stops switching and enters a safe restart cycle. Normally, the on-time is never reached unless there is a fault condition.
3.9.4 OverTemperature Protection (OTP)
3.9.4.1 Internal OTP
When the internal temperature of the IC exceeds 140 °C, a safe restart is initiated. The temperature has to drop at least 10 °C before a restart is allowed.
3.9.4.2 OTP via the PROTECT pin
To provide overtemperature protection, an external temperature sensor can be connected to the PROTECT pin. Normally, an NTC resistor with a large value is used for good accuracy. During normal operation, the PROTECT pin delivers a current of 74 μA flowing out of the pin. When the voltage on the pin drops below 0.50 V, the protection is triggered. It forces a safe restart. To allow a restart, the voltage level on the PROTECT pin must exceed 0.55 V. When the voltage on the PROTECT pin exceeds 1.45 V, the internal current source is pinched off. When not used, connecting a capacitor on the PROTECT pin ensures that the capacitor is charged to 1.45 V. It is kept on that voltage, which disables the protection. A value of 10 nF works fine for this purpose.
3.9.5 OverVoltage Protection (OVP)
3.9.5.1 OVP on the VCCL pin
The VCCL pin can withstand a continuous 45 V. When the voltage on the VCCL pin exceeds 48 V, switching is stopped to protect the pin. To prevent erroneous triggering of the protection, the overvoltage must be present for 4 switching cycles.
3.9.5.2 OVP via the AUX pin
The OVP via the AUX pin is described in Section 3.7.4.
3.9.6 OverPower Protection (OPP)
compensation is described in Section 3.7.3.
4 Circuit design aspects
maximum output current is 2.1 A for all output voltages. Figure 26 shows the schematic. Figure 26. Primary part direct charge demo board
NXP Semiconductors AN11879 TEA19361T GreenChip SMPS control IC Application note Rev. 1.1 — 5 October 2017
4.1 Input section
A fuse (F1) prevents fire hazards that can be associated with unintended failure of components on the primary side of the application. A simple common-mode choke (L1) provides elementary filtering of unwanted EMI. The common-mode choke is preferably constructed in such a way that it includes some (controlled) leakage inductance. The leakage inductance can serve as a differential mode filter component without adding extra ohmic losses to the filtering circuit. Using the layout and the component placement, make sure that L1 does not pick up too much magnetic stray field of the transformer. The filter can be extended with a small X-capacitor (≤ 100 nF) between pins 2 and 3 of the common-mode choke. An additional differential mode filter (PI-filter) is found after the rectifier bridge. It consists of capacitors C1, C2, C3, C16, inductor L3, resistor R39, and ferrite bead FB2. FB2 is a small ferrite bead that plays a role in high-frequency noise suppression. Capacitors C1, C2, and C3 also operate as the buffer capacitors for the bus voltage (Vbus). The HV pin of the TEA19361T IC is supplied from the rectified DC voltage after the diode bridge. Two resistors, R36 and R38, set the brownin and brownout levels. Two resistors in series are used to withstand the maximum DC voltage (375 V). For these resistors, 1206 SMD types with a voltage rating of 200 V can be used.
4.2 VCC supply voltage
Two auxiliary windings on the transformer provide the supply voltage for the internal operation of the TEA19361T. For optimal efficiency and lowest standby power, design the VCCH auxiliary winding voltage to keep VCCL above 12.5 V in a no-load condition at Vout = 5 V (default start-up condition for USB-PD). Check this requirement for all AC input voltages. It is important to keep the voltage on the VCCL pin well above Vrestart (11 V) in a no-load condition. When the voltage on the VCCL pin drops to below Vrestart, additional strokes are made to increase it to 11 V. These additional strokes increase the output voltage. The increasing output voltage increases the optocurrent on the secondary side and the control current on primary side. The increasing optocurrent and control current increases the input power during no load with several mW. When lower output voltages (e.g. 3 V) are also permitted for charging in current mode, check that VCCH is high enough to keep VCCL above 12.5 V under all required operating conditions at that output voltage. Simply calculating the number of turns from the auxiliary windings cannot determine the voltage levels of the VCCH and VCCL pins (see Figure 27).
Figure 27. Peak rectification increases the VCCH/L voltage mode (no load) and full load is not uncommon. conducts longer in reversed operation, the VCCH/VCCL capacitor damps the ringing. are suited for this purpose. pin. Only one auxiliary winding is required for the supply. capacitance on the VCCL pin can achieve a slightly better no-load performance. decoupling capacitor close to the pins.
4.3 Ipk current sensing
C19, as close to the ISENSE pin as possible.
NXP Semiconductors AN11879 TEA19361T GreenChip SMPS control IC Application note Rev. 1.1 — 5 October 2017
4.4 MOSFET driver
The driver must be optimized for the used MOSFET. Driving the MOSFET too hard or too softly causes efficiency loss. For a flyback in DCM, switch-on must not be too fast. However, switch-off must be fast. Switch-on behavior is tuned using resistors R28 and R29. Their series resistance and the gate capacitance determine the speed of switch-on. The value of resistor R29 is chosen to balance efficiency and EMI. Resistor R28 mainly determines the switch-off speed, which is optimized for efficiency. Do not connect the driver directly to the MOSFET gate.
4.5 AUX pin
A resistive divider is connected to the AUX pin. The top of the resistive divider must be connected to one of the auxiliary windings, which provide the IC supply. In Figure 26, the signal that feeds to the AUX pin comes from the VCCH auxiliary winding. In that case, resistor R37 must be redimensioned accordingly. This resistor determines the mains compensation for the OPP level. The resistive divider and resistor R35 set the level for OVP (see Section 3.7 for details).
4.6 Feedback section
Avoid any noise and disturbance to the signal connected to the CTRL pin. The signal route from the optocoupler to the CTRL and GND pin must consist of two PCB tracks that are as short as possible. They must be routed next to each other, perfectly in parallel and without branches, other components, or current paths. Place capacitor C20 close to the CTRL pin and preferably across the two tracks coming from the optocoupler. Capacitor C20 and the internal resistance of the CTRL pin (1.5 kΩ) create an additional pole, which improves the loop stability.
4.7 PROTECT pin
The PROTECT pin is mostly used to provide a system OTP. When the voltage on the pin is lower than 1.45 V, a current of 74 μA flows out of the pin. The circuit is designed to use a 100 kΩ NTC (RT1). The exact temperature at which the PROTECT pin is triggered, can be tuned with the series resistor R27. When the voltage drops to below 0.50 V, the protection is triggered. When the voltage increases to exceed 0.55 V, the protection is cleared. To avoid any pickup of noise or disturbance, place capacitor C18 and resistor R27 close to the PROTECT pin. The PROTECT pin can also be used for any other external protection. When the PROTECT pin is pulled down, switching stops. When the PROTECT pin is not pulled low any more, a safe restart initiates normal operation again. When the PROTECT pin is not used, only connect a 1 nF to 10 nF capacitor close to the pin. The internal current source charges the capacitor to 1.45 V at start-up. The internal current source is then pinched off, which minimizes power consumption.
NXP Semiconductors AN11879 TEA19361T GreenChip SMPS control IC Application note Rev. 1.1 — 5 October 2017
4.8 HV pin
Ensure that resistors R36 and R38 can withstand the maximum voltage at the highest mains input. The maximum DC voltage at capacitor C1 is 375 V, so resistors R36 and R38 must have a rating of at least 200 V. For the layout, the track from the HV pin with the resistors must not cross or come close to tracks leading to the PROTECT pin, the CTRL pin, or the AUX pin. When the HV pin track crosses or is routed near these tracks, crosstalk that originates from the very steep edges of the measuring pulses of the HV pin can cause a regulation disturbance.
4.9 Snubber section
To limit the overshoot of the ringing as a result of the primary to secondary stroke commutation, capacitor C15, resistors R21 and R22, and diode D4 constitute a clamp circuit. For proper working of the clamp, Diode D4 must be a slow type. Mains rectifier diodes are suited for this purpose. If necessary, the damping of the ringing can be controlled using resistor R22. Resistor R22 can be omitted in the circuit (use a short instead). Capacitor C15 and resistors R21 and R22 must have proper voltage ratings. When the leakage inductance (Llk) of the transformer T1 is known, the voltage rating of these components can be calculated with Equation 14: (14) which essentially results in: (15) Where:
- Vsnub is the voltage that the snubber components capacitor C15 and resistors R21 and R22 must support
- Llk is the maximum leakage inductance of the transformer
- Ipk is the highest peak current that can occur in the primary winding of the transformer This value is the maximum level on the ISENSE pin (510 mV) divided by the value of the sense resistor:
5 PCB layout aspects
feedback to the primary side via the optocoupler. Figure 28. Top copper and top silk screen
Figure 29. Bottom copper and top silk screen (mirrored)
5.1 High current, high-frequency current loops
It is very important that the high-current and the high-frequency current loops are small. emissions. They may also result in a higher than necessary susceptibility to induced EMI. The main secondary stroke current loop is on the secondary side of this application. R21 → R22 → T1 small as well.
NXP Semiconductors AN11879 TEA19361T GreenChip SMPS control IC Application note Rev. 1.1 — 5 October 2017
5.2 Lower current, high-frequency loops
The lower-current/high-frequency loops are less important. Keeping these loops small and the tracks short as well is beneficial for the application. The most important of the lower-current/high-frequency loops is the MOSFET gate drive loop. That loop follows the path C17 → U4 → R28 → R29//D8 → Q1 → R26// R32 → C17. Two additional lower-current/high-frequency loops are the VCCL loop and the VCCH loop:
- VCCL loop: T1 → D7 → C17 → T1
- VCCH loop: T1 → D25 → D6//R25 → C4 → T1 A short often replaces D6//R25, reducing the loop to T1 → D25 → C4 → T1.
5.3 Sensitive signals
The signals that are connected to the ISENSE pin, the AUX pin, the CTRL pin, and the PROTECT pin are relatively low-amplitude signals. High-amplitude signals that have their origin in other nodes of the SMPS application can easily influence them. For that reason, take some measures that prevent the influence on these sensitive signals.
- The ISENSE pin has a relatively low-impedance connection (via R31) to an even lower impedance node (the R26//R32 sense resistors). So, the ISENSE pin is already immune to induced noise. Nevertheless, mount capacitor C21 very close to the TEA19361T ISENSE pin and the GND pin. Resistor R31 must have a very short connection to the ISENSE pin. If the trace leading to the R26//R32 sense resistors is slightly longer, that is fine.
- Place resistors R35 and R37 very close to the TEA19361T AUX pin. If capacitor C22 is mounted, place it also very close to the AUX pin. In addition, resistor R35 must have a short connection to the TEA19361T GND pin. The PCB traces between resistor R37 and transformer T1 and between the TEA19361T GND pin and T1 are probably slightly longer, which is not a problem. However, these two traces must run in parallel and the enclosed area within the traces must be minimal. The latter causes the signal fed to the AUX pin to be less susceptible to magnetically induced disturbances.
- The TEA19361T CTRL pin is a current controlled input. Nevertheless, resistor R33 and capacitor C20 must be mounted close to the CTRL pin and the GND pin. The traces fed to the emitter and collector pins of the U3 optocoupler must run in parallel. The enclosed area within the traces must be minimal. The GND connection of the optocoupler must not be combined with any other signal. The optocoupler must have its own connection to the TEA19361T GND pin.
- Capacitor C18 must be mounted close to the TEA19361T PROTECT pin and GND pin. Mount resistor R27 close to the PROTECT pin also. It minimizes the amount of copper connected to the PROTECT pin and reduces the potential amount of capacitive (dV/dt) crosstalk to that pin. Thermistor RT1 is potentially mounted remotely. The PCB track from resistor R27 and the GND track leading to RT1 must run in parallel. The enclosed area within the traces must be minimal.
NXP Semiconductors AN11879 TEA19361T GreenChip SMPS control IC Application note Rev. 1.1 — 5 October 2017
5.4 Noisy signals
The TEA19361T application produces noise in several locations in the circuit. That noise can either be voltage (dV/dt) noise or current (dI/dt) noise. Taking placement and layout precautions can prevent that the noise influences the operation of other parts of the TEA19361T circuit and other appliances through the emission of EMI. Voltage (dV/dt) noise is coupled to other nodes in the circuit capacitively. The main high dV/dt nodes are:
- The drain node of MOSFET Q1 (the ‘hot’ side of the primary winding of transformer T1)
- The anode node of diode D5 (the ‘hot’ side of T1 VCCH auxiliary winding)
- The anode node of diode D7 (the ‘hot’ side of T1 VCCL auxiliary winding)
- The TEA19361T DRIVER pin
- The TEA19361T HV pin Ensure that copper areas and traces associated with these nodes cannot cause crosstalk to sensitive nodes. Commonly used approaches would be:
- To keep these nodes away from sensitive nodes
- To minimize the copper area attached to these nodes
- To shield the nodes through a low-impedance (for example GND or a ‘hard’ fixed voltage) copper plane or trace In this respect:
- Place MOSFET Q1 close to transformer T1
- Place diodes D5 and D7 close to transformer T1
- Try to keep the path from transformer T1 to R37//C22 short; R37//C22 must also be close to the TEA19361T AUX pin because of the sensitivity of the AUX pin node
- Place resistors R18 and R29 and diode D8 close to the TEA19361T DRIVER pin Try to keep the total length of the path from the DRIVER pin to the MOSFET Q1 gate short
- Place resistors R36 and R38 close to the TEA19361T HV pin It is not a problem when the path from the rectified mains voltage to resistor R38 is slightly longer. The reason is that the voltage at that node is a relatively ‘fixed’ (or low dV/dt) voltage Current (dI/dt) noise is inductively coupled to other nodes in the circuit. The high dI/dt current loops are described in Section 5.1 and Section 5.2. To limit inductive coupling:
- Keep all high dI/dt loops small Preferably the traces are kept short. More importantly, the enclosed area within the loop must be minimized (keep feeding and return traces in parallel). Sometimes, it is possible to lay out a current loop as an 8-pattern. In that case, the magnetic field caused by the upper half of the 8 and the magnetic field caused by the lower half of the 8 partially cancel each other out at a slightly greater distance. In this way, magnetic stray field is reduced. Keep the track from the HV pin away from tracks to the CTRL pin, AUX pin, and PROTECT pin.
- Place the inductive filtering components L1 and L3 such that the magnetic stray field from transformer T1 does not couple to L1 and L3 Using shielded magnetic components reduces susceptibility. However, placing the typical magnetic field patterns of the T1, L1, and L3 components perpendicularly, leads to minimized coupling. Taking the right precautions helps to achieve the EMI requirements of the application.
- Ensure that a high dI/dt trace or current path does not run close to and in parallel with a sensitive current path Especially applicable to the sensitive current path that connects the optocoupler to the TEA19361T CTRL and GND pins. When two PCB traces (or current paths) are perpendicular, there is no inductive coupling in theory. In practice, the inductive coupling is minimized.
5.5 GND shield
Most connections between components are made on the bottom side of the PCB. limits the propagation of self-induced and externally induced noise to sensitive nodes. GND shield is also a relevant aspect in thermal management.
- The GND copper plane must not conduct current; especially, high-frequency high- amplitude currents must not flow in the GND shield
- The GND shield must have a single ground connection to the GND star point; ground loops through the GND shield must be avoided
- The GND shield must not be taken as a reference plane for a sensitive signal like the ISENSE signal, the AUX signal, the CTRL signal, or the PROTECT signal
5.6 GND star point
The GND star point is at the negative electrode of capacitor C16. Figure 30. The GND star point
- The parallel circuit of sense resistors R26//R32
- The TEA19361T GND pin
NXP Semiconductors AN11879 TEA19361T GreenChip SMPS control IC Application note Rev. 1.1 — 5 October 2017 Longer connections to the GND star point are allowed for:
- The negative electrode of capacitor C3 The negative electrodes of capacitors C1 and C2, as well as the anodes of diodes D9 and D12 (rectifier bridge) must be connected to the negative electrode of capacitor C3. Do not connect them directly to the GND star point.
- The connection to the Y-capacitor CY1 (via resistor R24)
- The GND shield (see Section 5.5) The following components must have their (individual) connections to the TEA19361T GND pin. Do not connect them directly to the star point. Although, when the TEA19361T GND pin is very close to the star point, there may be little difference:
- Noise suppression capacitor C21
- Resistor R35
- Capacitor C18 Thermistor RT1 is preferably connected to the negative terminal of capacitor C18 and not directly to the TEA19361T GND pin
- Capacitor C20 The emitter of the U3 optocoupler is preferably connected to the negative terminal of capacitor C20 (via resistor R40) and not directly to the TEA19361T GND pin
- The ‘cold’ terminal of the T1 auxiliary windings
- Bulk capacitors C4 and C17 Generally, connecting the T1 ‘cold’ terminal and the C4 and C17 bulk capacitors to the star point is not a problem. When the connection between the TEA19361T GND pin and the star point is very short, the two points are the same. So, discriminating between the star point and the TEA19361T GND pin. is not necessary.
6 Secondary side implementations - various options
- Single fixed voltage SMPS For example, a single 19.5 V output voltage (for notebooks).
- Multiple fixed voltage SMPS For example, simultaneous 12 V and 5 V output voltages.
- Single variable voltage SMPS For example, switchable (5 V, 9 V, 12 V, 19.5 V) or autoswitchable output voltage (for USB PD) that typically uses a TEA1903 or TEA1905 secondary controller.
- Direct charging CC mode SMPS For example, a charger for a li-ion cell. Some implementation examples are described in the sections below. However, no extensive explanations are given. See the data sheets and application notes of the respective products that are used on the secondary side of that specific SMPS application for more information.
6.1 Single fixed output voltage
Figure 31. Typical single fixed output voltage SMPS
the efficiency loss is significant. The rectified voltage passes through a simple filter. It is then fed to the output terminals. produce the desired amount of power.
6.2 Multiple fixed output voltages
also determines the weight that each output voltage has on the regulation mechanism. Figure 32. Multiple fixed output voltages rectifier circuits diodes. However, the consequence is efficiency loss (see Section 6.1).
6.3 Single variable output voltage
TEA19361T controller is ‘instructed’ to produce the right amount of power. Figure 33. Typical variable output voltage USB PD SMPS
7 Abbreviations
Table 6. Abbreviations
8 References
1 TEA19361T data sheet GreenChip SMPS primary side control IC with fixed frequency
operation; 2016, NXP Semiconductors.
NXP Semiconductors AN11879 TEA19361T GreenChip SMPS control IC Application note Rev. 1.1 — 5 October 2017
9 Legal information
9.1 Definitions
Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information.
9.2 Disclaimers
Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Evaluation products — This product is provided on an “as is” and “with all faults” basis for evaluation purposes only. NXP Semiconductors, its affiliates and their suppliers expressly disclaim all warranties, whether express, implied or statutory, including but not limited to the implied warranties of non-infringement, merchantability and fitness for a particular purpose. The entire risk as to the quality, or arising out of the use or performance, of this product remains with customer. In no event shall NXP Semiconductors, its affiliates or their suppliers be liable to customer for any special, indirect, consequential, punitive or incidental damages (including without limitation damages for loss of business, business interruption, loss of use, loss of data or information, and the like) arising out the use of or inability to use the product, whether or not based on tort (including negligence), strict liability, breach of contract, breach of warranty or any other theory, even if advised of the possibility of such damages. Notwithstanding any damages that customer might incur for any reason whatsoever (including without limitation, all damages referenced above and all direct or general damages), the entire liability of NXP Semiconductors, its affiliates and their suppliers and customer’s exclusive remedy for all of the foregoing shall be limited to actual damages incurred by customer based on reasonable reliance up to the greater of the amount actually paid by customer for the product or five dollars (US$5.00). The foregoing limitations, exclusions and disclaimers shall apply to the maximum extent permitted by applicable law, even if any remedy fails of its essential purpose. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions.
9.3 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. GreenChip — is a trademark of NXP B.V.
NXP Semiconductors AN11879 TEA19361T GreenChip SMPS control IC Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © NXP B.V. 2017. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 5 October 2017 Document identifier: AN11879