AN1131 STMICROELECTRONICS | Alldatasheet
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Technical content
1 INTRODUCTION
signed and manufactured in a more recent technology. Table 1. Migration Cross-Reference Table migrate your application to ST72321 instead of ST72324.
MIGRATING APPLICATIONS FROM ST72511/311/314/124 TO ST72521/321/324
MIGRATING APPLICATIONS FROM ST72511/311/314/124 TO ST72521/321/324
2 FEATURE OVERVIEW
Table 2. 64-Pin Package Migration
1 Level
3 Levels
Table 3. 44-Pin Package Migration
3 HARDWARE COMPATIBILITY
3.1 PIN-OUT
el Interrupt) in the ST72521/321R, 321/324J.
3.2 HARDWARE CONFIGURATION
3.2.1 Oscillator load capacitance
3.2.2 Not Connected I/Os
3.2.3 Asynchronous RESET
tive transistor has been changed to a real resistor so it is not dependent on VDD . Table 4. RESET Pin Characteristics
4 TIMING
4.1 CYCLE ACCURACY
as a sequence of NOP instructions as opposed to polling a busy bit). This internal difference does not affect the general timings.
4.2 CLOCK SECURITY SYSTEM (CSS)
possible from the original clock frequency.
4.3 MAIN CLOCK OUT (MCO)
Figure 1. MCO Output
- When the application puts the ST7 in SLOW mode, the MCO output frequency is modified
accordingly, unlike the ST72511/311R, 314N, 314/124J where it is kept fixed at fOSC /2.
4.4 WATCHDOG TIMINGS
Figure 2. To guarantee upward compatibility, you have to take this into account when you de- sumption and EMC performance. Figure 1. Watchdog Block Diagram the PLL is activated or fOSC /2 =fCPU if the PLL is disabled).
Figure 2. Exact Timeout Duration (tmin and tmax ) Note: In the above formulae, division results must be rounded down to the next integer value.
MIGRATING APPLICATIONS FROM ST72511/311/314/124 TO ST72521/321/324
4.5 CAN CLOCK
In the ST72511 the CAN is directly clocked by fOSC2 , hence not modified in slow mode. In the ST72521 the CAN clock is fCPU like for all other peripherals. This means that in slow mode the CAN clock is also divided leading to a slower baudrate. Therefore in slow mode the bit timing must be adjusted or the CAN cell must be put in sleep mode.
5 REGISTER MAP
In the ST72521/321R, 321/324J, some register addresses and bit locations are changed. These changes have made it possible to use the free locations to add new features. Note: For easy software migration, two general rules have to be followed: n All “reserved” byte memory areas must never be “read” or “write”. n All “reserved” or “unused” bits must be left unchanged when accessing the byte.
5.1 REGISTER ADDRESS
These changes are classified in four groups: 1. I/O port register addresses changed 2. Miscellaneous registers changed (see Section 5.2 for more details) 3. MCCSR register address moved 4. ADC registers swapped Note: These register address changes can be easily performed if you group all the register definitions in a single header file.
Figure 3. Register Map Modifications
5.2 BIT LOCATION
isters which have been split into three different registers as shown below.
5.2.1 Main Clock System
Figure 4. Miscellaneous Register Bit Changes
000000 BC1 BC0
MIGRATING APPLICATIONS FROM ST72511/311/314/124 TO ST72521/321/324
5.2.2 External Interrupt
A single EICR register manages all the features linked to the external interrupt sources (I/O port interrupt sensitivity and TLI)
5.2.3 SPI/SS pin
The SPI SS pin alternate function is controlled from the SPI peripheral in the SPICSR register.
6 I/O PORT
6.1 EXTERNAL INTERRUPT HANDLING
To guarantee upward compatibility, the three following points have to be taken into account when you develop your application software: – In the ST72511/311R, 314N, 314/124J, parasitic interrupts occur when software changes the I/O port configuration. In the ST72521/321R, 321/324J, these parasitic interrupts no long- er occur. – In the ST72511/311R, 314N, 314/124J, the IPA and IPB control bits can be written at any time. In the ST72521/321R, 321/324J, these two bits can be written only when interrupts are masked (I[1:0]=”10” in the CC register). – In the ST72521/321R, 321/324J pending interrupts are cleared by software changing the val- ue of the ISx[1:0], IPA or IPB bits. In the ST72511/311R, 314N, 314/124J this is the case only for the ISx[1:0] bits.
7 PERIPHERALS
7.1 16-BIT TIMER The 16-bit timer of the ST72511/311R, 314N, 314/124J has been modified in the ST72521/ 321R, 321/324J to solve some issues related to PWM and One Pulse modes. If you use either of these two modes, you may need to change your software when transferring code from the ST72511/311 to the ST72521/321. ST72324J family devices have one limitation versus ST72314/124J: in ST72324J, Input Cap- ture 2 (IC2) and Output Compare 2 (OC2) functions are not available on Timer A. All other modes of the timer do not change.
7.1.1 PWM Mode
To avoid any uncontrolled status on the PWM output, a double buffering on the output com- pare registers (2 x 16 bits) is implemented in the ST72521/321R, 321/324J. This double buff- ering is not present in the ST72511/311R, 314N, 314/124J.
MIGRATING APPLICATIONS FROM ST72511/311/314/124 TO ST72521/321/324 In the ST72521/321R, 321/324J PWM mode, any new values written in the four OC1R and OC2R registers are taken into account only at the end of the PWM period (OC2 event) to avoid spikes on the PWM output. Note: Any modification on the OC1R and OC2R registers must be done just after the OC2 event (using the ICF1 interrupt routine for example).
7.1.2 One Pulse Mode
To be used more efficiently, the One Pulse mode sequence of the ST72511/311R, 314N, 314/ 124J has been improved in the ST72521/321R, 321/324J. When the ICAP1 event occurs (on falling or rising edge) the following sequence occurs: – 1. IC1R is loaded with the value of the counter when the event occurred (not FFFDh as in the ST72511/311R, 314N, 314/124J) – 2. The counter is immediately reset to FFFCh (not at the end like in the ST72511/311R, 314N, 314/124J) – 3. OLVL2 is applied to OCMP1 pin if OC1E=1 – 4. ICF1 is set
7.1.3 ST72324J Timer A Limitations
If the Timer A IC2/OC2 functions are required when migrating from ST72314/124J then you should migrate to the ST72321J. Timer A on the ST72324 only has one IC and one OC func- tion. This has the following impact on the application software: – The OC2HR and OC2LR registers are reserved (see Note 2). – The IC2HR and IC2LR registers are reserved (see Note 2). – The FOLV2 and OLVL2 i control bits in the CR1 register must be kept cleared. – The OC2E and IEDG2 control bits in the CR2 register must be kept cleared. – The ICF2 and OCF2 flags must always be masked (meaningless). – The PWM generated by timer A has a frequency given only by the timer overflow value (FFFFh) and the prescaler ratio selected by the CR2 CC[1:0] control bits. Notes: 1. Migration from the ST72314 to the ST72324 must take into account the discrepancy in Tim- er A functionality between these two devices. 2. A dummy read to the OC2LR and IC2LR registers has to be performed at the end of the Timer A interrupt routine.
7.2 SPI
7.2.1 Baud Rate
On the ST72521/321R, 321/324J the baud rate configurations are extended to f CPU /4 and fCPU /32. The SPR2 bit in the SPICR register controls these new baud rates. To keep the SPI
MIGRATING APPLICATIONS FROM ST72511/311/314/124 TO ST72521/321/324 baud rate compatible with the ST72511/311R, 314N, 314/124J the SPR2 bit must be left cleared.
7.2.2 HALT mode
The ST72521/321R, 321/324J is able to exit from HALT mode through a SPI interrupt. This is not the case in the ST72511/311R, 314N, 314/124J. To guarantee upward compatibility, if the SPI is used in slave mode, the SPI interrupt must be masked (via the SPE or SPIE bits) during HALT mode to avoid any unwanted wake-up event. 7.3 10-BIT ADC To meet application requirements for increased resolution, the ST72521/321R, 321/324J has a 10-bit ADC compared to the 8-bit ADC in the ST72511/311R, 314N, 314/124J. For upward compatibility, both ADCs have identical control registers and operating modes. The 8 most significant bits of the ST72521/321R, 321/324J data register (ADCDRH) are used in place of the ADCDR register of the ST72511/311R, 314N, 314/124J.
7.4 SCI
7.4.1 SCI Prescaler
To reach higher communication speeds and to increase the number of possible frequencies, the SCI prescaler has been modified in the ST72521/321R, 321/324J. These changes will re- quire a simple software change to program the correct baud rate. The two changes are listed below and illustrated in Figure 5: – The division by 2 of the input clock is removed in the ST72521/321R, 321/324J to reach high- er speed. – The enhanced prescaler is cascaded with the conventional prescaler after the PR prescaler to increase the number of possible frequencies.
Figure 5. SCI Baud Rate Prescalers
7.4.2 SCI TDO pin
pin can not be used as a standard I/O.
MIGRATING APPLICATIONS FROM ST72511/311/314/124 TO ST72521/321/324 "THE PRESENT NOTE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH A NOTE AND/OR THE USE MADE BY CUSTOMERS OF THE INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS." Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2001 STMicroelectronics - All Rights Reserved. Purchase of I2C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips. STMicroelectronics Group of Companies Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com