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GreenChip TEA1755 integrated PFC and flyback controller Rev. 2 — 13 September 2017 Application note COMPANY PUBLIC Document information Information Content Keywords GreenChip, TEA1755, PFC, flyback, high-efficiency, adapter, notebook, PC power, low-power standby mode Abstract The TEA1755 is a member of the new generation of combined PFC and flyback controller ICs, used for efficient switched mode power supplies. Burst mode enhances the overall efficiency of the system at low-output power and improves the audible noise performance. The TEA1755 has a high level of integration allowing cost-effective design of power supplies using the minimum number of external components. The TEA1755 is fabricated in a Silicon-On-Insulator (SOI) process, enabling it to operate at a wide voltage range.
NXP Semiconductors AN11142 GreenChip TEA1755 integrated PFC and flyback controller Application note Rev. 2 — 13 September 2017 COMPANY PUBLIC 2 / 56
Revision history
v.2 20170912 second, updated version Modifications: • Text and graphics have been updated throughout the document. v.1 20121112 first issue
NXP Semiconductors AN11142 GreenChip TEA1755 integrated PFC and flyback controller Application note Rev. 2 — 13 September 2017 COMPANY PUBLIC 3 / 56
1 Introduction
The TEA1755 is a combination controller comprising an integrated PFC and flyback controller in an SO16 package. Both controllers operate in Quasi-Resonant (QR) mode and in Discontinuous Conduction Mode (DCM) with valley detection and are independently switched. The PFC output power is on-time controlled for simplicity. It is not necessary to sense the phase of the mains voltage. The flyback output power is current mode controlled providing good input voltage ripple suppression. The integrated communication circuitry between the controllers does not require adjustment. Note: The voltage and current levels contained in this application note are typical values. The specification of the pin level spreading is given in the TEA1755T and TEA1755LT data sheets. Note: In all cases where a parameter value in this application note is different from the same parameter in the data sheet, the data sheet is leading.
1.1 Scope
This application note describes the functionality of the TEA1755 and the adjustments required within the power converter application. Excluded from this document are the large signal parts of the PFC/flyback power stages and the coil/transformer design and data.
1.2 The TEA1755 GreenChip controller
The GreenChip features allow the design of reliable, cost-effective, and efficient Switched Mode Power Supplies (SMPS) using the minimum number of external components.
1.2.1 Key features
- PFC and flyback controller integrated in one SO16 package
- Switching frequencies of PFC and flyback controller are independent of each other
- No external hardware required for the communication between both controllers
- High level of integration, resulting in a low external component count
- Integrated mains voltage enable and brownout protection
- Fast-latch reset function implemented
- Power-down functionality for very low Standby mode power requirements
NXP Semiconductors AN11142 GreenChip TEA1755 integrated PFC and flyback controller Application note Rev. 2 — 13 September 2017 COMPANY PUBLIC 4 / 56
1.2.2 System features
- Safe restart mode for system fault conditions
- High-voltage start-up current source (5 mA)
- Reduction of HV current source (1 mA) in safe restart mode
- Wide VCC range (13.4 V to 38 V)
- MOSFET driver voltage limited
- Easy control of start-up behavior and VCC circuit
- General-purpose input for latched protection
- Internal IC overtemperature protection
- Accurate PFC switch on/switch off control using flyback switching frequency measurement
- One high-voltage spacer between the HV pin and the next active pin
- Open pin protection on the VINSENSE, VOSENSE, PFCAUX, FBCTRL, and FBAUX pins
1.2.3 PFC features
- Dual-output voltage boost converter
- QR/DCM operation with valley switching
- Frequency limitation (139 kHz) to reduce switching losses and ElectroMagnetic Interference (EMI)
- ton controlled
- Mains input voltage compensation for control loop for good transient response
- OverCurrent Protection (OCP)
- Soft-start and soft-stop
- Open/short-circuit detection for PFC feedback loop: no external OverVoltage Protection (OVP) circuit necessary
- Adjustable delay for switching off the PFC
- Overriding the PFC switch on/switch off functionality
1.2.4 Flyback features
- Burst/FR/QR/DCM operation with valley switching
- Frequency Reduction (FR) with an adjustable minimum peak current and valley switching to maintain high efficiency at low output power levels
- Burst mode enhances the overall efficiency at low-output power
- Burst mode benefits the reduction of audible noise
- Frequency limitation (130 kHz) to reduce switching losses and EMI
- Current mode controlled
- Overcurrent protection
- Soft-start
- Accurate OVP through auxiliary winding
- Time-out protection for output overloads and open feedback loop, available as safe restart (TEA1755T) or latched (TEA1755LT) protection
- VCC undervoltage prevention during burst mode
1.3 Application schematic
Refer to Figure 1 (part 1) and Figure 2 (part 2) for an overview of a typical application. Figure 1. TEA1755 application schematic (part 1)
4 OPTO
Figure 2. TEA1755 application schematic (part 2)
2 Pin description
Table 1. Pin description 1 VCC Supply voltage; Vstartup = 22.3 V; Vth(UVLO) = 13.4 V. source is pinched off and VCC is regulated to Vstartup until the flyback starts. See Section 3.2 for a complete description of the start-up sequence. logic controls an internal 29 µA current source that is connected to the pin.
4 FBAUX Input from auxiliary winding for transformer demagnetization detection,
Protection (OVP) of the flyback. flyback OVP is detected at a current higher than 300 μA to the FBAUX pin. at a current lower than −100 μA from the FBAUX pin. 5 LATCH General-purpose latched protection input. PFC and the flyback are switched off. 6 PFCCOMP Frequency compensation pin for the PFC control loop.
NXP Semiconductors AN11142 GreenChip TEA1755 integrated PFC and flyback controller Application note Rev. 2 — 13 September 2017 COMPANY PUBLIC 8 / 56 Pin Name Functional description 7 VINSENSE Sense input for mains voltage. The VINSENSE pin has six functions:
- mains start level: Vstart(VINSENSE) = 1.16 V;
- mains stop level (brownout): Vstop(VINSENSE) = 0.89 V;
- mains voltage compensation for the PFC control loop gain bandwidth;
- fast-latch reset: Vflr = 0.75 V;
- dual-boost switch-over point: Vbst(dual) high = 2.28 V or low = 2.08 V (see Section 4 for more information
- Standby mode: Vth(pd) = 385 mV
- Exit Standby mode: Vth(pd)exit = 460 mV The voltage on the VINSENSE pin must be an averaged DC value, representing the AC line voltage. The pin is not used for sensing the phase of the mains voltage.
8 PFCAUX Input from an auxiliary winding of the PFC coil for demagnetization timing
and valley detection to control PFC switching. Connect the auxiliary winding using a 5 kΩ series resistor to prevent damage to the input because of EMI surges. 9 VOSENSE Sense input for the PFC output voltage.
- VOSENSE pin, open-loop, and short-circuit detection; Vth(stop) (VOSENSE) = 1 V;
- VOSENSE pin, start level Vth(start)VOSENSE = 1.1 V;
- PFC output voltage regulation; Vreg(VOSENSE) = 2.5 V;
- PFC soft OVP (cycle-by-cycle): Vovp(VOSENSE) = 2.62 V;
- Control output for the output voltage of the PFC; dual-boost current: Ibst(dual) = −8.1 μA 10 FBSENSE Flyback current sense input. On this pin, the sum of three voltages across three resistors is measured. Selecting the proper resistor values:
- Prevents or minimizes the risk of saturation of the flyback transformer;
- Allows some adjustment for switching on or switching off the PFC controller;
- Allows a system that operates line voltage independently. The maximum Vsense(fb)max level is 545 mV at dV/dt = 0 mV/μs. The Vsense(fb)min level is 232 mV at dV/dt = 0 mV/μs. Vsense(fb)min is related to the adjustable peak current through the flyback transformer when flyback is running in burst mode or frequency reduction mode. There are two internal current sources connected to this pin, Istart(soft)fb and Iadj(FBSENSE). The internal logic controls a 60 μA current source Istart(soft)fb. The current source is used to implement a soft-start function for the flyback controller. The flyback driver only starts when the internal current source can charge the soft-start capacitor to a voltage of more than 0.55 V. Therefore a minimum soft-start resistor of 15 kΩ is required to ensure that the flyback controller is switched on. The current source Iadj(FBSENSE) = 2.1 μA. It is intended to support the adjustment for switch on and switch off the PFC.
NXP Semiconductors AN11142 GreenChip TEA1755 integrated PFC and flyback controller Application note Rev. 2 — 13 September 2017 COMPANY PUBLIC 9 / 56 Pin Name Functional description 11 PFCSENSE PFC overcurrent protection input. This input is used to limit the maximum peak current in the PFC core. The PFCSENSE is a switching-cycle-by-switching-cycle protection. The PFC MOSFET switches off when the PFCSENSE reaches 495 mV at dV/ dt = 0 mV/μs. The logic controls a 60 µA current source which is connected to this pin. This current source is used to implement a soft-start and soft-stop function for the PFC to prevent audible noise. The PFC driver only starts when the internal current source can charge the soft-start capacitor to a voltage of more than 0.5 V. A soft-start resistor of at least 15 kΩ is required to ensure that the PFC starts up.
12 PFCDRIVER PFC MOSFET gate-driver output
13 FBDRIVER Flyback MOSFET gate-driver output
14 PFCTIMER This pin enables the use of two options:
- Option 1: The timer delays the switching off the PFC when the load of the flyback is removed or minimized. The PFC is switched off when two conditions are met: – the filtered flyback operating frequency < 53 kHz (only valid during FR mode) – the voltage across the PFCTIMER pin is high (≥ 3 V).
- Option 2: When an external voltage supply is connected to this pin, the typical PFC behavior is overridden. The PFC is switched on when the VPFCTIMER is forced ≤ 1.03 V. The PFC is switched off when the voltage ≥ 4.4 V. 15 HVS High-voltage safety spacer, not connected.
16 HV High-voltage input for the internal start-up current source (output on the
VCC pin) and valley sensing of the flyback. Valley detection input: The combination of demagnetization detection at the FBAUX pin and valley detection at the HV pin determine the switch-on moment of the flyback MOSFET in the valley.
3 System description and calculation
3.1 PFC and flyback start conditions
Figure 3. Switching on the PFC during initial start-up Figure 4. Switching on the flyback during initial start-up
3.2 Initial start-up sequence
- The HV current source is set to 1.1 mA and the electrolytic capacitor CVCC is charged
to 0.60 V to enable short-circuit detection on the VCC pin.
- At VCC = 0.60 V, the HV current source is set to 5 mA and the CVCC is quickly charged
- At VCC = Vth(UVLO), the HV current source is set to 1 mA and the VCC electrolytic
capacitor is charged to Vstartup.
- At Vstartup, the HV current source is switched off. The 30.5 μA LATCH pin current
FBSENSE soft-start current sources are switched on.
- When the LATCH pin is charged to 582 mV, the PFC can start switching when the
VOSENSE = 1.1 V and VINSENSE = 1.16 V.
- Two additional conditions for enabling the PFC driver are:
- Charge the soft-start capacitor on PFCSENSE to 0.5 V.
- Charge the capacitor connected to the PFCCOMP pin to either 1.92 V or 3.32 V depending on the VINSENSE voltage and wait until IPFCCOMP < 55 μA. 7. Conditions to enable the flyback driver are:
- all conditions for enabling the PFC are met.
- charge the soft-start capacitor on the FBSENSE pin to 0.55 V.
- ensure that the voltage on the FBCTRL pin is lower than 7.75 V. Normally, the voltage on the FBCTRL pin is lower than 7.75 V at the first flyback switching cycle, unless the FBCTRL pin is open. When flyback starts, the FBCTRL timeout current source is switched on. 8. When flyback has reached its nominal output voltage, the auxiliary winding takes over the VCC supply. If the flyback feedback loop signal is missing, the timeout protection on the FBCTRL pin is triggered. Both converters are switched off, VCC drops to the Vth(UVLO) level and the IC restarts at step 3 of the start-up cycle. Step 3 is the safe
step 3. Instead, VCC starts cycling between Vth(UVLO) and Vstartup without restarting. Figure 5. Start-up sequence at low mains voltage
3.3 VCC cycle in safe restart mode
3.4 Mains voltage sensing and brownout
other start conditions are also met (see Section 3.1). stops switching and enters safe restart mode. Figure 6. VINSENSE circuitry
3.4.1 Discharging the mains input capacitor
time constant of τ < 1 s for safety reasons.
- R = R1 = R2 A 90 W adapter often uses a value of 220 nF for CX1. Therefore, the RV value must be lower than or equal to: (2)
3.4.2 Brownout voltage adjustment
discharge of capacitors in equipment (Section 9). Example values are shown in Table 2. Table 2. VINSENSE component values
3.4.3 Minimizing the influence of the dark-current of the optocoupler
by pulling the VINSENSE voltage down to ground using an optocoupler.
Figure 7. Proposed VSENSE circuit for minimizing the influence of the dark current optocoupler. The optocoupler dark-current no longer influences the VINSENSE voltage. Figure 1 when Figure 7 is added.
3.5 Internal OverTemperature Protection (OTP)
pin. OTP is a latched protection.
3.6 LATCH pin
switching it on triggers the fast-latch reset circuit and resets the latch (see Section 3.7). are enabled. Charging of the LATCH pin starts when VCC = Vstartup. triggering. In addition, when the LATCH pin function is not used add a 10 nF capacitor.
Figure 8. Usage of the LATCH pin protection
3.7 Fast-latch reset
system restarts when the VCC pin is charged to Vstartup (See step 4 of Section 3.2).
4 PFC description and calculation
skipped to keep the frequency below 139 kHz. efficiency at low mains is improved because of the reduction of the PFC switching losses. to the total losses is relatively high. stable switchover of the PFC output voltage without hiccups. Figure 9. Transfer function of the VINSENSE voltage to the dual-boost current at VOSENSE off, the electrolytic bulk capacitor voltage VCbulk drops to line voltage × √2.
4.1 PFC output power and voltage control
good Power Factor (PF) and a class-D Mains Harmonics Reduction (MHR). voltage on pin VINSENSE, determines the PFC on-time.
Figure 10. TEA1755 PFC converter on-time control voltage. As a result the gain is constant over the entire mains input voltage range.
4.1.1 Setting the PFC output voltage
voltage on the VOSENSE pin is equal to Vreg(VOSENSE) (2.5 V). Figure 11. TEA1755 PFC converter output voltage setting resistor value (below the 104.4 kΩ) available in the E96 series is 102 kΩ. Note: MAX is the maximum limiting current value. In data sheet, it is a negative number. (voltage margin). In a universal mains adapter, the highest line voltage is typically 264 V.
At low line voltages, the recommended value for Vbulk(PFC)low ≥ 250 V. Table 3. Resistors R6 and R6A calculated using different values for resistor R7 cause audible noise and disturbance of the AC mains input current.
4.1.2 Calculation of the PFC soft-start and soft-stop components
Figure 12. PFC soft start and soft stop The total soft-start or soft-stop time is tsoft-start = 3 × RSSI × CSSI. burst mode even though CSS1 charges up to Vsense(PFC)max after switching off the PFC. The charged CSS1 capacitor allows a fast restart of the PFC when applicable. Using C6 = 100 nF and R11 = 15 kΩ results in a soft-start time of 4.5 ms.
4.2 PFC demagnetizing and valley detection
4.2 μs (tto(demag)PFC) after demagnetization was detected.
Figure 13. TEA1755 PFCAUX circuitry
4.2.1 Design of the PFCAUX winding and circuit
rating of ±25 V. This setting guarantees valley detection at low ringing amplitudes. The number of turns of the PFCAUX winding is calculated using Equation 12.
- VPFCAUX is the absolute maximum rating of the PFCAUX pin
- VL(max) is the maximum voltage across the PFC primary winding The PFC output voltage at the PFC OVP level determines the maximum voltage across the PFC primary winding and is calculated using Equation 13: (13) When a PFC coil with a higher number of auxiliary turns is used, place a resistor voltage divider between the auxiliary winding and the PFCAUX pin. The total resistive value of the divider must be ≤ 10 kΩ to prevent a valley detection delay due to parasitic capacitance. The polarity of the signal at the PFCAUX pin is reversed compared to the PFC MOSFET drain signal. To protect against electrical overstress during lightning surge events, add a 5 kΩ resistor between the PFC auxiliary winding and the PFCAUX pin. To prevent incorrect valley switching of the PFC because of external disturbances, place the resistor as close as possible to the IC.
NXP Semiconductors AN11142 GreenChip TEA1755 integrated PFC and flyback controller Application note Rev. 2 — 13 September 2017 COMPANY PUBLIC 22 / 56
4.3 PFC protection modes
4.3.1 VOSENSE overvoltage protection
Overvoltage can occur across the bulk electrolytic capacitor during the initial start-up and large load changes. The relative slow response of the PFC control loop causes this overvoltage. The PFC control loop response must be relatively slow to guarantee a good power factor and meet the MHR requirements. The OverVoltage Protection (OVP) on the VOSENSE pin limits the overvoltage. When the Vovp(VOSENSE) level = 2.62 V is detected, the PFC MOSFET is switched off immediately regardless of the on-time setting. The switching of the MOSFET is blocked until the voltage on the VOSENSE pin drops < 2.62 V again. OVP is also triggered when the resistor between the VOSENSE pin and ground is open. The peak voltage during an overshoot across the electrolytic bulk capacitor is calculated using Equation 14. (14)
4.3.2 VOSENSE open and short pin detection
The VOSENSE pin senses the PFC output voltage. The VOSENSE pin has an integrated protection circuit to detect an open and short circuited pin. The VOSENSE pin also senses that one of the resistors in the voltage divider is open making the VOSENSE pin fail-safe. It is not necessary to add an external OVP circuit for the PFC. When the pin is open, an internal current source pulls VVOSENSE up and VOVP(VOSENSE) is detected. The PFC stops switching when VOVP(VOSENSE) is detected and an internal voltage clamp limits the maximum VOSENSE voltage. The same condition applies when only resistor R7 is open (see Figure 11). The internal voltage clamp again limits the maximum VOSENSE voltage to acceptable values. The PFC is not switching when VVOSENSE ≤ VVth(stop)VOSENSE, this condition is applicable when VOSENSE is short circuited to ground. The same condition is applicable if only resistor R6 or R6A (see Figure 11) is open. However under the condition that R7 ≤ 104.4 kΩ (see Section 4.1.1).
4.3.3 VINSENSE open pin detection
The VINSENSE pin senses the mains input voltage, The VINSENSE pin has a protection circuit to detect an open pin. An internal current source pulls down the pin to ≤ Vstop(VINSENSE) (0.89 V) when the pin is open.
NXP Semiconductors AN11142 GreenChip TEA1755 integrated PFC and flyback controller Application note Rev. 2 — 13 September 2017 COMPANY PUBLIC 23 / 56
4.3.4 Overcurrent protection
The overcurrent protection limits the maximum current through the PFC MOSFET and PFC coil. The current is measured via a current sense resistor in series with the MOSFET source. The MOSFET is switched off immediately when the voltage on the PFCSENSE pin exceeds the Vsense(PFC)max level of 495 mV at dV/dt = 0 mV/μs. OCP is a cycle-by-cycle protection. To avoid false triggering of the PFC OCP by the flyback converter switching, use a 100 mV margin. False triggering of the Vsense(PFC)max protection can cause interference to the AC mains input current. To suppress any external disturbance, place a small capacitor between 100 pF and 220 pF next to the PFCSENSE pin. The current sense resistor is calculated using Equation 15: (15) Where: the maximum PFC peak current is IpQR(PFC)max at the high output load and low mains. The maximum peak current for the PFC operating in Quasi-Resonant (QR) mode is calculated using Equation 16: (16) Where:
- Po(max) is the maximum output power of the flyback
- Factor 1.1 is used to compensate the dead-time between zero-current in the PFC inductor at the end of the secondary stroke and the detection of the first valley in quasi- resonant mode
- η is the expected efficiency of the total converter at maximum output power
- V(AC)min is minimum mains input voltage.
NXP Semiconductors AN11142 GreenChip TEA1755 integrated PFC and flyback controller Application note Rev. 2 — 13 September 2017 COMPANY PUBLIC 24 / 56
5 Flyback description and calculation
5.1 Flyback output power control
The TEA1755 flyback system waits until the transformer is demagnetized and at least one valley has appeared before it is magnetized again for the next cycle. The FBAUX pin detects demagnetization via the auxiliary winding. The HV pin detects the bottom of the valley via the drain of the MOSFET or the central tap of the primary winding. The output power (PO) of the flyback is calculated using Equation 17: (17) Where:
- Lp is the flyback transformer primary inductance
- Ipk is the flyback transformer primary peak current
- fs is the flyback controller operating frequency
- η is the flyback controller efficiency Lp is selected at the start of the design. The primary peak current controls the (high) output power in QR and DCM mode. The switching frequency is a result of external application parameters and IC parameters. External application parameters are the transformer turns ratio, primary inductance, the drain source capacitance, input voltage, output voltage, and the feedback signal from the control loop. IC parameters are the oscillator setting, the peak current setting, and the demagnetization and valley detection. The primary current Ipk is fixed at medium and low output power. The power is controlled by changing the operating frequency. Output power and operating frequency are linearly related during this type of control. In this application note, it is called operating in frequency reduction mode (See Section 5.1.1.3). The minimum switching frequency in FR mode is 25 kHz. At even lower output powers, the IC enters the burst mode which minimizes audible noise. The burst mode is a hysteresis controlled system, used during low output-power. The primary peak current Ipk and operating frequency of the flyback are both fixed when the system supports power to the output. Using VFBCTRL as a hysteresis input results in a variable number of FBDRIVER switching pulses combined with a changing burst mode repetition frequency. The flyback input voltage is measured using the FBAUX pin and it is used to implement an OverPower Protection (OPP). OPP keeps the maximum output power of the flyback converter constant over the input voltage. The flyback has an accurate OverVoltage Protection (OVP) circuit. The overvoltage is measured through the FBAUX pin. Both flyback and PFC controllers are switched off in a latched protection when an overvoltage is detected.
5.1.1 Four TEA1755 operation modes
- Quasi-Resonant (QR) mode
- Discontinuous Conduction Mode (DCM)
- Frequency Reduction (FR) mode
- Burst Mode (BM) The internal demagnetization detection and valley switching circuitry is active in all four operating modes. aaa-002672 VFBCTRL (V) PFC off PFC on flyback switching frequency fsw(fb)max burst mode frequency FR minimum frequency FR DCM QR BM QR: Quasi Resonant DCM: Discontinuous Conduction Mode FR: Frequency Reduction BM: Burst Mode
Figure 14. Flyback operation modes
5.1.1.1 Quasi-resonant mode
- VFBCTRL is allowed to vary between the 4 V and 4.9 V (only valid in QR mode and DCM mode)
- Iadj(FBSENSE) related to a current source inside the IC, connected to the FBSENSE pin
- Resistors R16 and R17 are found in the circuit diagram, see Figure 15. C10 FBSENSE R16 Lp Rsense Rcomp C23 R16A FBDRIVERRSERIES = R17 + R16 Vi (DC) R17 Coutput Doutput 019aaa039 Iadj(FBSENSE) The FBSENSE pin has two internal reference levels: (1) Vsense(fb)max = 545 mV at dV/dt = 0 mV/μs (2) Vsense(fb)min = 232 mV at dV/dt = 0 mV/μs
Figure 15. Most important components for adjusting the flyback in the application conduction mode when the maximum switching frequency is reached.
5.1.1.2 Discontinuous conduction mode
operating mode switches from DCM to FR mode when VFBCTRL = 4 V (Vstart(red)f)).
5.1.1.3 Frequency reduction mode and PFC switch on/switch off control
Ipk(min) through the flyback transformer is kept constant during FR mode. operating frequency. As a result of the frequency reduction, more valleys are skipped.
overall efficiency at low output power. factor of the line current at high output power. low line voltages (see Section 5.1.2).
- The PFC is using the flyback operating frequency during FR mode (f ≥ fsw(fb)swon(PFC)).
- VFBCTRL ≥ Ven(PFC)FBCTRL (3.75 V), applicable at initial start-up or when the flyback
operating frequency cannot reach fsw(fb)swon(PFC).
- When the duty cycle of the FBDRIVER ≥ 50 %.
Table 4. PFC switch-on and switch-off signals the audible frequency for humans.
5.1.1.4 Burst mode
TEA1755 is partly shut down, resulting in a reduced supply current. The peak current Ipk(min) during burst mode is equal to the value in FR mode. feedback loop and output power. repetition frequency minimizes the risk on audible noise.
The FBCTRL voltages for BM and higher output powers are tuned to each other. when the driver starts. However, the IC remains in BM as long as VFBCTRL ≤ 2.8 V. switches to FR mode. Figure 16 shows this behavior. Figure 16. TEA1755 in burst mode
5.1.1.5 VCC undervoltage protection during burst mode
auxiliary winding when VCC is just above Vth(UVLO).
5.1.2 The relationship between inductance value and the PFC hysteresis
Equation 22 in Section 5.1.3. The MOSFET on-time depends on the selected inductance value and input voltage.
- The transformer turns ratio
- The output voltage excluding the influence of the short valley time
flyback controller at low and lower line voltages. Figure 17. Operating frequency as a function of low line voltages, assuming a relatively high selected primary the selected primary inductance is relatively high. In practice, the flyback driver supports a limited amount of power at low line voltages.
NXP Semiconductors AN11142 GreenChip TEA1755 integrated PFC and flyback controller Application note Rev. 2 — 13 September 2017 COMPANY PUBLIC 31 / 56 The following methods can be used to select the inductance value:
- using Figure 18
- using Equation 20 (20) Where:
- IO(nom) stands for the nominal output current according to the type plate of the adapter
- VO the output voltage
- Vf the forward voltage across the secondary diode
- Lp the flyback transformer primary inductance
- N the turns ratio between the primary and secondary windings (Np/Ns) Equation 20 gives some deviation at a low and a high value of the N × (VO + Vf) product. Keep this value between 80 V and 130 V. Example:
- IO(nom) = 4.62 A
- VO = 19.5 V
- Vf = 0.1 V The final value used is 450 μH.
5.1.3 Relationship between Ipk(min) and the required PFC(swon)/PFC(swoff) level
The PFC is switched on and switched off usually between 50 % and 25 % of the nominal output current of the flyback. The PFC is only switched on or switched off when the flyback controller is running in FR mode. The PFC switches on at a flyback operating frequency of 73 kHz (fsw(fb)swon(PFC)) and switches off the PFC at 53 kHz (fsw(fb)swoff(PFC)). The recommended PFC switch off output power is 30.3 % of the typical output-power. The margin between 30.3 % and the 25 % requirement is used for a range of tolerances. Use components with a tolerance values that comply with the components given in the Bill Of Materials section of the UM10514 user manual (see Section 9). Allowing more tolerance for the components requires a larger margin for the recommended output power when a 25 % power requirement is met. Using this information results in Equation 21:
NXP Semiconductors AN11142 GreenChip TEA1755 integrated PFC and flyback controller Application note Rev. 2 — 13 September 2017 COMPANY PUBLIC 32 / 56 (21) or: (22) Where:
- 0.303 is the recommended multiplying factor related to PFC(swoff)
- VO is the output voltage
- IO(nom) is the nominal output current according to the type of adapter plate
- Vf is forward voltage across the secondary diode
- Lp is the primary inductances of the flyback transformer
- fsw(fb)swoff(PFC) is 53000
- ηfb is the efficiency of the flyback (use relatively high values, such as 0.94 to 0.96) Example:
- IO(nom) = 4.62 A
- VO = 19.5 V
- Vf = 0.1 V
- Lp = 450 μH
- ηfb = 0.95 PFC(swon) is calculated using Equation 23: (23) Using the data results in: This value can be translated into an output current Iout(en): (24)
NXP Semiconductors AN11142 GreenChip TEA1755 integrated PFC and flyback controller Application note Rev. 2 — 13 September 2017 COMPANY PUBLIC 33 / 56
5.1.4 The influence of Rsense and the R16/R17 series resistance
The sense resistor, Rsense, together with the series impedance R16 and R17, has four functions:
- prevent or minimize the risk of saturation of the flyback transformer
- allow enough power to the output (assuming the inductance is not going into saturation)
- allow some adjustment for switching on or switching off the PFC at a certain output power level. The value of Rsense is more dominant for this adjustment than the value of R16, as its influence is much smaller
- R17 and C23 prevent FBSENSE being charged negative because of disturbances across Rsense The saturation level (Isat) of the transformer and the value of the sense resistor are important design parameters. Section 5.1.4.1 shows the calculation for the transformer saturation level. Next, the maximum peak current (Ipk(max)) through the transformer is determined. This value is preferably below the transformer saturation level.
5.1.4.1 Calculating the flyback transformer saturation current Isat
The transformer saturation level is calculated using Equation 25. (25) Example based on the following assumptions:
- Np = 32 turns
- Bmax = 390 mT (PQ3220, material PC44, Bmax at 100 °C)
- Ae = 170 × 10−6 m2 (from transformer supplier data sheet)
- Lp = 450 × 10−6 Result: Values for Ae and Bmax are contained in the transformer data sheet. The Bmax value depends on temperature. It decreases rapidly at high operating temperatures. Therefore, select the Bmax value at high operating temperatures. Core saturation does not occur when the maximum peak current (Ipk(max)) is less than the saturation current (Isat). Section 5.1.4.2 shows the calculation of Ipk(max). A saturated core deteriorates the overall system performance. It results in more stress, EMI and in the worst case, a possible system failure.
NXP Semiconductors AN11142 GreenChip TEA1755 integrated PFC and flyback controller Application note Rev. 2 — 13 September 2017 COMPANY PUBLIC 34 / 56
5.1.4.2 Calculation of Ipk(max) for flyback operating in Quasi-resonant mode
The flyback peak current in QR mode is calculated using Equation 26: (26) Where:
- a = N × Vi(DC)min × Lp
- b = −2 × IO × Lp × {N × (VO + Vf) + Vi(DC)min}
- c = −2 × IO × tvalley × N × Vi(DC)min × (VO + Vf) For a, b and c:
- VO is the output voltage
- N is the turns ratio between the primary and secondary windings (Np/Ns)
- Vf is the forward voltage across the secondary diode
- Lp is the inductance value of the primary winding
- tvalley is the valley time, sometimes also described as dead-time. This time is usually around the 1.1 μs
- Vi(DC)min is the minimum voltage across electrolytic bulk capacitor C3 during a load- step. The customer defines the load step but the maximum value of the load step is limited to the nominal output power. In this example, Vi(DC)min = 75 V (DC). The voltage depends on the load step, the value of the Cbulk and when the PFC is switched on during the mains cycle. It is recommended that this value is checked in every application. Examples:
- a = 5.3333 × 75 × 450× 10−6 = 180 × 10−3 (27) Allow a margin between the calculated value and the saturation level of the core. For example, the system could still run into a problem during a peak load. Check carefully for these instances in the final design. Assuming the PFC has been switched on for some time, Equation 28 shows the results using a peak output current of 5.7 A and Vbulk = 250 V (DC).
- a1 = 5.3333 × 250 × 450 × 10−6 = 0.6
NXP Semiconductors AN11142 GreenChip TEA1755 integrated PFC and flyback controller Application note Rev. 2 — 13 September 2017 COMPANY PUBLIC 35 / 56 (28) Select the highest Ipk(max) value (with IO = 4.62 A and IO = 5.7 A). Compare the Ipk(max) value with the Isat value. The highest Ipk(max) value must be lower than the Isat value. If so, use the Isat value for Ipmax to allow a better maximum output power margin.
5.1.4.3 Calculation of the current sense resistor Rsense
The next step is calculating the Rsense value, see Equation 29: (29) Note: fill in the highest for Ipk(max) level (see Section 5.1.4.2). Using the saturation current Isat for Ipk(max) is often preferred (assuming that Isat > Ipk(max)) because it allows a higher maximum output power. Using the highest peak current of all (Isat = 4.715 A, see Section 5.1.2) results in a value for Rsense as calculated in Equation 30: (30)
5.1.4.4 Calculation of the series resistance R16 and R17
Equation 31 calculates the series resistance of R16 and R17: (31) A typical 90 W adapter example: The value of R17 is often roughly between 680 Ω and 1.2 kΩ. Its purpose is to prevent C10 being charged in an unwanted way because of spikes across Rsense which can trigger the internal ESD protection. Selecting a value between these two limits allows some freedom for trimming R16 or the delay compensation resistor R16A. When the R17 value is chosen as 1000 Ω, R16 = 37100 Ω − 1000 Ω = 36100 Ω.
5.1.5 Calculation of the delay compensation resistors Rcomp and R16A
- the internal delay time of the IC
- the switch off time of the MOSFET
- the delay time related to R17 × C23 (filter in front of the FBSENSE pin) The transformer still conducts current on the primary side during the sum of all these delay times. These delay times are translated into an extra current IDELAY through the transformer (see Figure 19) which results in extra output energy. The amount of extra energy depends on the input voltage. The current flows through two resistors placed in series, R5 and R5A. The combined resistance of R5 and R5A resistors is called Rcomp. Select Rcomp ≤ 13.6 MΩ. Rcomp is calculated using Equation 32: (32) Resistors Rcomp and R16A compensate for the unwanted current (IDELAY) using a corresponding delay time. The voltage across R16A is translated to the current IPRESET with the corresponding preset time. When the preset values cancel the delay values, the system is compensated. The voltage across resistor R16A depends on the current passing through it. IDELAY IPREFERRED tPREFERRED IPRESET tDELAYtPRESET 019aaa042
Figure 19. Principle of delay compensation disturbances on the FBSENSE pin. An RC time selection that is too large cannot follow the input voltage ramp-up properly. interference on the FBSENSE pin.
NXP Semiconductors AN11142 GreenChip TEA1755 integrated PFC and flyback controller Application note Rev. 2 — 13 September 2017 COMPANY PUBLIC 37 / 56 td(FBDRIVER) defines the internal delay of the TEA1755 at 80 ns. Switching off the MOSFET usually takes around 60 ns. Note: Check the time for switching off the MOSFET (td(MOSFET)off) in the final application because using different MOSFETs and gate resistors can change its duration. The conduction time of the flyback MOSFET is shortest when the input voltage is at its highest. The highest value is usually 390 V (DC). Equation 33 shows the calculation for R17 × C23: (33) An example calculation for a typical 90 W adapter: A commonly used RC time for this filter is 220 ns using 1 kΩ for resistor R17 and 220 pF for capacitor C23. The RC time value is used in the subsequent equations. The tolerance of capacitor C23 is ≤ 10 %. Using a maximum tolerance of 10 % for C23 limits the impact on the overall spreading for the PFC(swon) on and PFC(swoff) level. The output follows the input with a delay of just one RC time after roughly five RC times. The total delay time is calculated using Equation 34: (34) An example for a typical 90 W adapter: The R16A value is calculated using Equation 35: (35) An example for a typical 90 W adapter:
NXP Semiconductors AN11142 GreenChip TEA1755 integrated PFC and flyback controller Application note Rev. 2 — 13 September 2017 COMPANY PUBLIC 38 / 56
5.1.6 Calculation of flyback soft start components
Soft start is implemented using the RC network connected to the FBSENSE pin. The sum of resistors R16, R16A, and R17 must be > 15 kΩ to ensure Vstart(soft)fb (0.55 V) is reached and flyback start-up is enabled. See the TEA1755T and TEA1755LT data sheets (see Section 9). In general, the R16A and R17 values are much smaller than the value of R16. Therefore, the soft-start time is: τsoft-start ≈ 3 × R16 × C10. Make τsoft-start for flyback longer than for the PFC. Keep τsoft-start in the range of 5 ms to 10 ms. When C10 = 68 nF and R16 = 36 kΩ, the total tsoft-start is approximately 7 ms.
5.2 Two PFCTIMER pin options
The PFCTIMER pin can be used to extend the PFC operating time when the output power drops below the PFC switch off level. This option prevents the PFC from constantly switching on and off because of fast, large dynamic load changes at the output. Preventing that the PFC switches on and off results in reduced audible noise. This option is further described in Section 5.2.1. Another option for the PFCTIMER pin is overriding the PFC switch-on (PFC(swon)) and switch off (PFC(swoff)) functionality. Refer to Section 5.2.2 for more information about this subject.
5.2.1 Option 1: adjustable PFC(swoff) time
A capacitor connected to an internal current source determines the adjustable PFC(swoff) time. Capacitor C24 charges from 0 V to 3 V during this adjustable time, the PFC typically switches off using a soft-stop when VPFCTIMER > 3 V. Equation 36 shows how this time is calculated. (36) Example: a capacitance of 1.5 μF for C24 results in a 0.96 s delay, approximately. Typically, after the PFC is switched off, C24 is charged to 3.8 V. Note: Always connect a capacitor with a minimum value of 1 nF to the PFCTIMER pin. Table 5 shows the behavior and conditions of the PFCTIMER pin when an external source does not override it.
Table 5. PFCTIMER adjustable PFC disable time [1] The PFC can only be switched on or switched off when the flyback is running in FR mode. Capacitor CPFCTIMER discharges when the PFC switches on. the 3 V causes the PFC to switch off. Figure 20. Control of the PFCTIMER pin when PFC is not overridden
5.2.2 Option 2: Overriding the PFC(swon) and PFC(swoff) functions
- The disabled PFC is overridden (PFC(swon)) when VPFCTIMER ≤ 1.0 V but VPFCTIMER > 1 V immediately switches off the PFC again.
- The enabled PFC is overridden (PFC(swoff)) when VPFCTIMER ≥ 4.4 V but VPFCTIMER < 4.4 V switches on PFC again. The TEA1755 does not allow overriding of the PFC during flyback burst mode. All other flyback operation modes enable overriding of the PFC(swon) and PFC(swoff) functionality. The recommended CPFCTIMER capacitor value is 1 nF. The recommended capacitance value results in the shortest PFCTIMER pin response time to an external signal. Correct timing is important if an external signal is used to override the PFC, especially when switching on the PFC. Keep VPFCTIMER close to the 4.4 V (Vth(off)PFCTIMER) when the PFC is switched off. This action minimizes the external driver current required to override the PFC. In addition, together with the small PFCTIMER capacitance, it allows the fastest response on the external PFC switch-on signal. Table 6 shows the behavior and required conditions of the PFCTIMER pin when an external source overrides it.
Table 6. PFCTIMER behavior and required conditions when overridden by an external source
4.4 V ≤ VPFCTIMER ≤ 10 V
[1] VPFCTIMER refers to the recommended value before overriding to allow the fast PFC(swon).
NXP Semiconductors AN11142 GreenChip TEA1755 integrated PFC and flyback controller Application note Rev. 2 — 13 September 2017 COMPANY PUBLIC 42 / 56
5.3 Flyback protection mode
5.3.1 Short-circuit on the FBCTRL pin
If the FBCTRL pin is shorted to ground, switching of the flyback controller is inhibited.
5.3.2 Open FBCTRL pin
As shown in Figure 23 , the FBCTRL pin is connected to an internal 7 V voltage source via an internal 13.2 kΩ resistor. When the voltage on the FBCTRL pin exceeds 5.5 V, this connection is disabled. The FBCTRL pin is biased with an internal 29 μA current source. When the voltage on the FBCTRL pin > Vto(FBCTRL) (7.7 V), a fault is assumed. Flyback and PFC switching is blocked and the controller:
- TEA1755T: enters the safe restart mode
- TEA1755LT: triggers the latched protection When the controller is blocked, an internal switch pulls the FBCTRL pin down.
5.3.3 Time-out flyback control loop
A timeout function can be created to protect against an output short-circuit at initial start- up or against an open control loop situation. This feature is made when a resistor is mounted in series with a capacitor between the FBCTRL pin and ground. Triggering the timeout protection generates:
- TEA1755T: a safe restart
- TEA1755LT: a latched protection When the voltage on the FBCTRL pin > 5.5 V (see Figure 23), the switch in series with the 13.2 kΩ resistor is opened. The FBCTRL pin and therefore the RC combination is biased with a 29 μA current source (Ito(FBCTRL)). When the voltage on the FBCTRL pin > 7.75 V, flyback and PFC switching is blocked and the controller enters the relevant protection mode. The resistor and capacitor are both used to set the time delay required to reach 7.75 V on the FBCTRL pin. The resistor is also necessary to separate the relatively large timeout capacitor from the control loop response. Use a resistor value ≥ 30 kΩ. The timeout time tto is calculated using Equation 37: (37) Note: dvto(FBCTRL) value 2.25 V in Equation 37 is related to Vto(FBCTRL), it is the trip value minus enable value: 7.75 V − 5.5 V = 2.25 V. An example based on the following assumptions:
- R24 = 39 kΩ
- C16 = 330 nF
Figure 23. Time-out protection
5.3.4 Overvoltage protection flyback
measuring the voltage on the auxiliary winding. to a current through the FBAUX pin.
Figure 24. Flyback OVP and OPP circuit to prevent false OVP detection which can occur during ESD or lightning events. reset circuit and resets the latch.
- Ns is the number of turns on the secondary winding.
- Naux is the number of turns on the flyback transformer auxiliary winding.
- Vclamp(FBAUX) is the FBAUX pin positive clamp voltage.
- Vf(D23A) is the forward voltage of D23A at a current of 300 μA.
- VO is the output voltage
- Vf is the forward voltage across the secondary diode Take the tolerances on Iovp(FBAUX) into account for the Vovp(VOSENSE) level calculation to avoid OVP triggering during normal operation.
NXP Semiconductors AN11142 GreenChip TEA1755 integrated PFC and flyback controller Application note Rev. 2 — 13 September 2017 COMPANY PUBLIC 45 / 56
5.3.5 OverPower Protection (OPP)
The maximum power that the flyback can support depends on its input voltage. A higher input voltage allows more output power which can result in more stress during fault conditions. The OPP circuit is implemented to limit the output power to a predefined value at higher input voltages. Triggering the OPP circuit results in activation of the timeout protection (see Section 5.3.3 for more information). The design of the circuit starts with calculating the required flyback input voltage that matches the predefined OPP level. Equation 40 shows the calculation (40) Where:
- N is the turn ratio between primary turns and secondary windings of the flyback transformer
- Lp is the primary inductances of the flyback transformer
- Isat is the calculated maximum peak current
- VO is the output voltage of the flyback
- Vf is forward voltage across the secondary diode (or conducting MOSFET)
- Popp is the requested maximum output power of the flyback
- tvalley is the measured valley time
- ηfb is the efficiency of the flyback. Use relatively high values, such as 0.94 to 0.96 The example is based on the following assumptions:
- N = 5.3333 (see Section 5.1.4.2)
- Isat = 4.715 A (see Section 5.1.4.1)
- VO = 19.5 V (see Section 5.1.2)
- Vf = 0.1 V (see Section 5.1.2)
- Popp = 131.3 W; the assumed and preferred OPP level of the flyback
- tvalley = 1.1 μs (see Section 5.1.4.2)
- ηfb = 0.95 (see Section 5.1.3) Using these values in Equation 40 results in: Vbulk(opp)min = 143.4 V (DC). The preferred OPP output power level is almost independent of the line voltage when Vbulk(opp)min < Vbulk(PCF)low. Refer to Section 4.1.1 for more information about Vbulk(PCF)low. Keep a margin of 50 V between Vbulk(PCF)low and Vbulk(opp)min. A transformer running very close to saturation has a negative effect on the tolerance of the OPP circuit. Using at least a margin of 50 V minimizes this effect. During the flyback primary stroke, the input voltage is sensed by measuring the current drawn from the FBAUX pin. A resistor, placed between the flyback transformer auxiliary winding and the FBAUX pin, converts the voltage to the current IFBAUX. The IC uses the current information to reduce the setting of the maximum flyback peak current measured through the FBSENSE pin. See Figure 24 for the limitation of the maximum VFBSENSE level as a function of IFBAUX.
Figure 25. OPP maximum FBSENSE voltage remaining part of the OPP resistor R23A can be calculated.
- Naux = 7 turns
- Np = 32 turns
- Vclamp(FBAUX) is the FBAUX pin negative clamp voltage.
- Vbulk(opp)min = 143.4 V (DC) The OPP resistance (Ropp) is limited by Equation 42. (42) Keep a margin to this maximum resistor value. The recommended maximum value for Ropp ≤ 650 kΩ. Higher resistor values can result in a slower output voltage increase during initial start-up. The slower output voltage increase can trigger the timeout protection (See Section 5.3.3).
6 Summary of calculations for flyback adjustment
See Section 1.3 application schematics for component reference numbers. Figure 26. Most important components and maximum inductance value for adjusting the
NXP Semiconductors AN11142 GreenChip TEA1755 integrated PFC and flyback controller Application note Rev. 2 — 13 September 2017 COMPANY PUBLIC 48 / 56 Step 1: Use the graph in Figure 26 to determine an indication for the maximum primary inductance value or use Equation 43. (43) Step 2: Select a transformer and calculate the saturation current: (44) Step 3: Calculate the required peak current through the flyback transformer. Calculate this value at nominal output power in combination with the minimum Vbulk and when the PFC is operating at maximum peak output power. Calculate using both values for Ipk(max) but only use the highest value of these two parameters. A common rule is that Isat > Ipk(max). Selecting the higher Isat value for Ipk(max) prevents transformer saturation and allows a power margin. In general, the calculation is carried out using Ipk(max) = Isat. (45) Where:
- a = N × Vi(DC)min × Lp
- b = −2 × IO × Lp × {N × (VO + Vf) + Vi(DC)min}
- c = −2 × IO × tvalley × N × Vi(DC)min × (VO + Vf) Step 4: Calculate Ipk(min) (related to switching off the PFC): (46) ηfb is the flyback efficiency. Use a relatively high value, for example, approximately 0.94 to 0.96. Step 5: Calculate the value of Rsense: (47) Step 6: Calculate the value of Rseries: (48) The Rseries resistance comprises two components, R16 and R17. The common value for R17 is between 820 Ω and 1.2 kΩ. A typical value that is used often is 1 kΩ.
NXP Semiconductors AN11142 GreenChip TEA1755 integrated PFC and flyback controller Application note Rev. 2 — 13 September 2017 COMPANY PUBLIC 49 / 56 Step 7: Checking/calculating the R17 × C23 time constant: (49) Where:
- td(FBDRIVER) = 80 ns
- td(MOSFET)off ≈ 60 ns (The value can be different in other applications. Check on the application board.) In general, the calculation often shows that R17 × C23 ≥ 220 ns. If so, 220 ns is sufficient for the constant R17 × C23. A smaller value can be acceptable but is not preferred. Step 8: Calculate the delay time: (50) Note: The commonly used value for R17 × C23 is 220 ns (see step 7). Step 9: Calculate the compensating resistor Rcomp: (51) Calculate the value of R16A: (52)
NXP Semiconductors AN11142 GreenChip TEA1755 integrated PFC and flyback controller Application note Rev. 2 — 13 September 2017 COMPANY PUBLIC 50 / 56
7 PCB layout considerations
A good layout is an important part of the final design. It minimizes many kinds of disturbances and makes the overall performance more robust with less risk of EMI. Guidelines for the improvement of the layout of the PCB are as follows:
- Separate large signal grounds from small signal grounds (see Figure 28). A triangular symbol indicates small signal grounds. All other ground symbols are related to large signal grounds
- Make the print area within the indicated large signal loops (see Figure 28) as small as possible. Each indicated large signal loop has its own color. Make the copper tracks as short and wide as possible
- The connection between both MOSFETs (PFC and flyback) and the IC driver outputs must be as short as possible (green line in Figure 28). Use wide tracks. Increase the distance between the copper tracks and/or preferably using a separate guided ground track for both connections minimizes the coupling between the PFCDRIVER and FBDRIVER. A circuit diagram according to Figure 27 can be added in case it is impossible to locate the MOSFET and IC close to each other.
- The power ground and small signal ground are only connected with one short copper track (make this track as short and as wide as possible). Preferably it should become one spot (connection between ground 4a and ground 6a, shown as a green line in Figure 28)
- Use a ground shield underneath the IC, connect this ground shield to the GND pin of the IC
- Connect all series connected resistors that are fixed to an IC pin as close as possible to that pin
- Connect heatsinks which are connected to the component nearest corresponding ground signal. Make this connection as short as possible. Connect the heat sink of diode bridge BD1 to ground 1, Q1 to 4 and Q2 to 4b. In typical applications, all three components are often mounted on a single heat sink. If so, make one wide copper track that connects all three grounds to each other. Also combine in this copper track ground 2
- Connect the grounds of 6b to each other
- Make a local "star ground" from ground 6a, 6b, 6c, and 7. Ground 6a is the middle of the star and is connected to the GND pin (the ground of the IC)
- Grounds marked 7 do not have to be a star ground
- Place the Y-capacitor across grounds 1 and 8. Use one copper track, separated from all others for this connection. Alternatively in a typical application setup, use the heatsinks connection copper track for this purpose.
- Place C4, C15, C23, and C22 (in order of priority) as close as possible to the IC. Reduce coupling between the PFC switching signals (PFC driver and PFCAUX) and the flyback sense signals (FBSENSE and FBCTRL) as much as possible. The coupling reduction minimizes the risk of electromagnetic interference and audible noise
- Figure 28 shows an overview of the hierarchy of the different grounds at the bottom
- Connect the anode of the TL431 (ground 8) to ground 9 using one special separate connecting copper track. Minimize all other currents in this special track. Make the connection as close as possible to the output
- Place the TEA1792 close to the power MOSFET Q4
- Connect the ground of the TEA1792 directly to a wide and short copper track to the source of Q4
- Connect the series resistor R32 directly between the drain of Q4 and the VCC pin of the IC. Use a separate copper track for this purpose
- Make the connection between MOSFET Q4 and the TEA1792 driver pin as short as possible (green line in Figure 28). Use a guided ground track
- Make the connection between R50 and SWDET of the TEA1703 as short as possible and place the resistor close to the IC Note: Use the circuit shown in Figure 27 when the distance between the IC drive output and corresponding MOSFET is relatively great. Qdch input Qswitch Dch RsenseRdch IC DRIVER Rch GND aaa-005304 Transistor is mounted close to the MOSFET with wide and short tracks. See Section 7 for the layout rules.
Figure 27. Switching off the MOSFET when the distance between IC and MOSFET is great
Figure 28. PCB layout considerations (part 1)
Figure 29. PCB layout considerations (part 2)
8 Abbreviations
Table 7. Abbreviations
9 References
1 TEA1755T data sheet HV start-up DCM/QR flyback controller with integrated DCM/
2 TEA1755LT data sheet HV start-up DCM/QR flyback controller with integrated DCM/
3 UM10514 user manual Notebook adapter using the TEA1755; 2016, NXP
NXP Semiconductors AN11142 GreenChip TEA1755 integrated PFC and flyback controller Application note Rev. 2 — 13 September 2017 COMPANY PUBLIC 55 / 56
10 Legal information
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Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). 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In no event shall NXP Semiconductors, its affiliates or their suppliers be liable to customer for any special, indirect, consequential, punitive or incidental damages (including without limitation damages for loss of business, business interruption, loss of use, loss of data or information, and the like) arising out the use of or inability to use the product, whether or not based on tort (including negligence), strict liability, breach of contract, breach of warranty or any other theory, even if advised of the possibility of such damages. Notwithstanding any damages that customer might incur for any reason whatsoever (including without limitation, all damages referenced above and all direct or general damages), the entire liability of NXP Semiconductors, its affiliates and their suppliers and customer’s exclusive remedy for all of the foregoing shall be limited to actual damages incurred by customer based on reasonable reliance up to the greater of the amount actually paid by customer for the product or five dollars (US$5.00). The foregoing limitations, exclusions and disclaimers shall apply to the maximum extent permitted by applicable law, even if any remedy fails of its essential purpose. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions.
10.3 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. GreenChip — is a trademark of NXP B.V.
NXP Semiconductors AN11142 GreenChip TEA1755 integrated PFC and flyback controller Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © NXP B.V. 2017. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 13 September 2017 Document identifier: AN11142