AN1089 STMICROELECTRONICS | Alldatasheet

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achieve a high PF (see Ref. [1]). of L6561-based PFC preregulators in boost topology and operated in Transition Mode (TM). range of operating conditions. Figure 1. Typical L6561-based TM PFC preregulator

(converter’s efficiency changes very little). sinusoid at the output of the multiplier. of the input voltage into pin 3. (km). Please refer to [1] and the Appendix for the relevant calculation technique. where the small-signal multiplier gain km could be assumed equal to KM for simplicity. Figure 6. Plot of KM vs. E/A output

As a tool to ease the design of L6561’s E/A compensation networks in TM boost PFC preregulators, the Appendix contains a Mathcad® file gathering the theory above illustrated and performing all the neces- sary calculations. Conclusions This paper gets an insight into the control loop of TM controlled Boost PFC preregulators based on the L6561 PFC controller. This reveals that the simple feedback capacitor used to compensate the error am- plifier in preregulators for lamp ballast may not be adequate in systems that may experience large vari- ations in input voltage and/or load current. Moreover it leads to an unstable loop if the load is a switching converter. Appropriate compensation schemes are suggested for both cases and a calculation tool (Mathcad® file) is provided so as to make control loop design easier in such systems. References [1] "L6561, Enhanced Transition Mode Power Factor Corrector", (AN966) [2] "L6569 - L6561 Lighting Application with PFC" (AN991) [3] "Electronic Ballast with PFC Using L6574 and L6561" (AN993) [4] "Design Equations of High-Power-Factor Flyback Converters Based on the L6561" (AN1059) [5] "Flyback Converters with the L6561 PFC Controller" (AN1060) Appendix This Mathcad® file allows to design the control loop and performs a stability analysis of PFC preregula- tors in boost topology operated in Transition Mode and controlled by the L6561. Highlighted equations indicate data that must be manually entered. These data are supposted to be known to the user as a result of the design of the PFC preregulator (the use of the PFC design software included in the CD-ROM "Linear and Switching Voltage Regulators" is recommended). The example val- ues are taken from the L6561 demo board circuit. PFC Converter Data: Output Voltage V O := 400 V Output Capacitor C O := 47 µF Sense Resistor R s := 0.41 Ω Output Overvoltage Threshold OVP := 40 V Expected Efficiency η := 0.9 Multiplier Biasing: Input Divider Upper Resistor R up := 1240 k Ω Input Divider Lower Resistor R low := 10 k Ω Analysis Setpoint: Mains RMS Voltage V irms := 264 V Output Power P O := 80 W AN1089 APPLICATION NOTE

Preliminary calculations & Service Variables: Equivalent Load Resistance Ro := VO 2 PO RO = 2 ⋅103 Ω Input Divider Gain KP := R low R low + Rup KP = 8 ⋅10-3 Large-signal Multiplier Gain: KM(V COMP ) := 0.651 ⋅ (1 - 85.29 ⋅ e-1.776 ⋅ VCOMP ) Error Amplifier Quiescent Point: V COMP := 4 VCOMP := root  2.5 + 2 ⋅ Po ⋅ RS η ⋅ KM(VCOMP ) ⋅ KP ⋅ Virms 2 − VCOMP , VCOMP VCOMP = 2.898 [V] Small signal Multiplier Gain km:= d dVCOMP [KM(VCOMP ) ⋅ (VCOMP − 2.5)] km = 0.557 n − 1 f: = 1 Control-to-Output Transfer Function (constant power load): G (ω) : = km ⋅ KP ⋅ Virms2 2 ⋅ VO ⋅ 1 R S ⋅ 106 j ⋅ ω ⋅ CO Compensated E/A Transfer Function (constant power load, refer to fig.8b) DC gain (ΔVO /ΔVCOMP ): G O := 0.30 Pole: p := 0.23 Hz Zero: z := 15 Hz 0.1 1 10 100 1 .10350 100 150 ¦G¦ f dB 0.1 1 10 100 1 .10391 f deg AN1089 APPLICATION NOTE

Transfer Function: G1 (ω) := GO ⋅ 1 + j ⋅ ω 2 ⋅ π ⋅ z 1 + j ⋅ ω 2 ⋅ π ⋅ p Open Loop Transfer Function (constant power load): Φ F(ω ): = arg (F(ω )) ⋅ 180 π Crossover Frequency: fc: = |root (|F(2 ⋅ π ⋅ f)| - 1, f)| fc = 18.836 Hz Phase Margin: Φ : = 180 + Φ F(2 ⋅ π ⋅ fc) Φ = 52.167 ° 0.1 1 10 100 1 .10360 ¦G1¦ f dB 0.1 1 10 100 1 .103100 /G1 f deg 0.1 1 10 100 1 .103100 100 ¦F¦ f dB 0.1 1 10 100 1 .103200 160 120 f deg AN1089 APPLICATION NOTE

Feedback Network Implementation (constant power load, refer to fig. 8b): Output Divider Upper Resistor R7: = OVP 40 ⋅ 103 R7 = 1 ⋅ 103 kΩ Output Divider Lower Resistor R8: = 2.5 VO − 2.5 ⋅ R7 R8 = 6.289 kΩ Parallel Feedback Resistor: R12: = G O ⋅ R7 R12 = 300 kΩ Series Feedback Capacitor C3: = 106 2 ⋅ π ⋅ R12 ⋅  p ⋅ 1 z C3 = 2.271 ⋅ 103 nF Series Feedback Resistor R11: = 106 2 ⋅ π ⋅ z ⋅ C3 R11 = 4.672 kΩ Control-to-Output Transfer Function (resistive load): G (ω) : = km ⋅ KP ⋅ Virms2 4 ⋅ VO ⋅ RO R s ⋅ 1 1 + j ⋅ ω ⋅ CO ⋅ R O 2 ⋅ 10−6 Pole Location: p : = 106 π ⋅ RO ⋅ CO p = 3.386 Hz 0.1 1 10 100 1 .10350 100 ¦G¦ f dB 0.1 1 10 100 1 .103100 f deg AN1089 APPLICATION NOTE

Compensated E/A Transfer Function (resistive Load, refer to fig. 8a): High Frequency Gain: G h := 0.005 Zero: z := 15 Hz Transfer Function: G1 (ω) := Gh ⋅ 2 ⋅ π ⋅ z ⋅ 1 + j ⋅ ω 2 ⋅ π ⋅ z j ⋅ ω Open Loop Transfer Function (resistive load) F(ω ): = G(ω ) ⋅ G1(ω ) Φ F(ω ): = arg (F(ω )) ⋅ 180 π Crossover Frequency: fc: = |root (|F(2 ⋅ π ⋅ f )| - 1, f)| fc = 19.805 Hz 0.1 1 10 100 1 .103100 100 ¦F¦ f dB 0.1 1 10 100 1 .103200 160 120 f deg 0.1 1 10 100 1 .10360 ¦G1¦ f dB 0.1 1 10 100 1 .103100 /G1 f deg AN1089 APPLICATION NOTE

Phase Margin: Φ : = 180 + Φ F(2 ⋅ π ⋅ fc) Φ = 62.563 ° Feedback Network Implementation (resistive load, refer to fig. 8a): Equivalent Load Resistance R7: = OVP 40 ⋅ 103 R7 = 1 ⋅103 kΩ Output Divider Lower Resistor R8: = 2.5 VO − 2.5 ⋅ R7 R8 = 6.289 kΩ Series Feedback Capacitor C3: = 106 2 ⋅ π ⋅ z ⋅ Gh ⋅ R7 C3 = 2122 ⋅ 103 nF Series Feedback Resistor R11: = 106 2 ⋅ π ⋅ z ⋅ C3 R11 = 5 k Ω AN1089 APPLICATION NOTE

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