AN1059

AN1059 STMICROELECTRONICS | Alldatasheet

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rent, especially in universal mains applications.

• for a given power rating, the input capacitance can be 200 times less, thus the bulky and costly high voltage electrolytic capacitor after the rectifier bridge will be replaced by a small-size, cheaper film ca- pacitor.
• efficiency is high at heavy load, more than 90% is achievable: TM operation ensures low turn-on losses in the MOSFET and the high PF reduces dissipation in the rectifier bridge. This, in turn, mini- mises requirements on heatsinks;
• low parts count, which helps reduce encumbrance and assembly cost. In addition, the unique features of the L6561 offer remarkable advantages in numerous applications:
• efficiency is high even at very light load: the low current consumption of the L6561 minimises the power dissipated by both the start-up resistor and the self-supply circuit. An L6561-based high-PF fly- back converter can easily meet Blue Angel regulations;
• additional functions available: the L6561 provides overvoltage protection as well as the possibility to enable/disable the converter by means of its ZCD pin. There are, on the other hand, some drawbacks, inherent in high-PF topologies, limiting the applications that such a converter can fit (AC-DC adaptors, battery chargers, low-power SMPS, etc.) and which one has to be aware of:
• twice-mains-frequency ripple on the output: unavoidable if a high PF is desired. A large output ca- pacitance will reduce its amount. Speeding up the control loop may lead to a compromise between a reasonably low output ripple and a PF still reasonably high;
• poor transient response: as to this point too, speeding up the control loop may lead to a compromise between an acceptable transient response and a reasonably high PF; MULTIPLIER VREF2 OVER-VOLTAGE DETECTION VOLTAGE REGULATOR UVLO INTERNAL SUPPLY 7V 2.5V R S Q DRIVER STARTER+ ZERO CURRENT DETECTOR DISABLE 2.1V 1.6V VCC 23 4 ZCD VCC INV COMP MULT CS GD GND D97IN547D 20V 40K 5pF

Figure 2. Internal Block Diagram of the L6561.

• large output capacitance (in the thousand µF, depending on the output power) is required: however, cheap standard capacitors and not costly high-quality parts are needed. In fact, a low ESR and an adequate AC current capability are automatically achieved. Besides, in conventional flyback convert- ers there is usually plenty of output capacitance too, thus this is not so dramatic as it may seem at first sight;
• secondary post-regulation will be required where tight specifications on the output ripple and/or on the transient behaviour are given. However, this is true also for a standard flyback;
• the system is unable to cope with line missing cycles at heavy load unless an exceedingly high output capacitance is used. In the following, the operation of a high-PF flyback converter will be discussed in details and numerous relationships, useful for its design, will be established. Preliminary statements In order to generate the equations governing the operation of a high-PF flyback converter working in TM, refer also to the internal block diagram of the L6561(see fig. 2). For details concerning the operation of the L6561, please refer to Ref. [1]. The following assumptions will be made: 1. the line voltage is perfectly sinusoidal and the rectifier bridge is ideal, thus the voltage downstream the bridge, sensed by the input of the L6561’s multiplier (MULT, pin 3) is a rectified sinusoid: V in (t) = VPK ⋅ |sin (2 ⋅ π ⋅ fL ⋅ t)| where VPK is equal to the RMS line voltage, VRMS , times the square root of 2, and fL is the line fre- quency (usually 50 or 60 Hz). 2. the output of L6561’s Error Amplifier (VCOMP ) is constant for a given line half-cycle; 3. transformer’s efficiency is 1 and its windings are perfectly coupled. 4. ZCD circuit’s delay is negligible thus the converter works exactly on the boundary between continuous and discontinuous current conduction mode (TM operation). As a result of the first two assumptions, the peak primary current is enveloped by a rectified sinusoid: Ipkp(t) = IPKp ⋅ |sin (2 ⋅ π ⋅ fL ⋅ t)| (1) One consequence of assumption 3 is that the peak secondary current is proportional to the primary one, depending on transformer’s primary-to-secondary turns ratio n: Ipks(t) = n ⋅ Ipkp(t) To simplify the notation, in the following the phase angle θ = 2 ⋅ π ⋅ fL ⋅ t of the sinusoidal quantities will be indicated and all the quantities depending on the instantaneous line voltage will be considered as a function of θ, instead of time. Timing relationships The ON-time of the power switch is expressed by: T ON = Lp ⋅ Ipkp (θ) Vin(θ) = Lp ⋅ IPKp VPK (2), where Lp is the inductance of transformer’s primary winding. Eqn. (2) shows that TON is constant over a line half-cycle, exactly like in boost topology. The OFF-time is instead variable: TOFF = Ls ⋅ Ipks(θ) (Vout + Vf) = Lp n2 ⋅ n ⋅ Ipkp(θ) (Vout + Vf) = Lp ⋅ IPKp ⋅ |sin (θ)| n ⋅ (Vout +Vf) (3), AN1059 APPLICATION NOTE

where Ls is the inductance of the secondary winding, Ipks(θ) the peak secondary current, Vout the output voltage of the converter (supposed to be a regulated DC value) and Vf the forward drop on the output catch diode. Since the system works in TM, the sum of the ON and the OFF times equals the switching period: T = TON + TOFF = Lp ⋅ IPKp VPK ⋅  1 + VPK VR ⋅ |sin(θ)| (4) where VR = n ⋅ (Vout + Vf ) is the so-called reflected voltage. The switching frequency fsw = T -1, therefore, varies with the instantaneous line voltage: fsw = VPK Lp ⋅ IPKp ⋅ 1 1 + VPK VR ⋅ |sin(θ)| and reaches its minimum value on the peak of the sinusoid (sin (θ)=1): fsw min = VPK Lp ⋅ IPKp ⋅ 1 1 + VPK VR (5) This value, calculated at the minimum line voltage, must be greater than the maximum one of the inter- nal starter of the L6561 (≈14 kHz ), in order to ensure a correct TM operation. To accomplish with this requirement, the primary inductance Lp will be properly selected (not exceeding an upper limit). Actually, to minimise the size of the transformer, the minimum frequency will usually be selected quite higher than 15 kHz, say 25-30 kHz or more, so the value of L p needs not have a tight tolerance. The duty cycle, that is the ratio between the ON-time and the switching period, will vary with the instan- taneous line voltage as well (because of the variation of TOFF ), as it is possible to find by dividing eqn.(2) by (4): D = TON T = 1 1 + VPK VR ⋅ |sin(θ)| (5’) Equations (2) and (4) show that TON and T, respectively, can be short at will if IPKp (i.e. the load) tends to zero, especially at high input voltage. In the real-world operation, it must be considered that TON cannot go below a minimum amount and so will do the switching period as well. This minimum (typically, 0.4- 0.5µs) is imposed by the internal delay of the L6561 and by the turn-off delay of the MOSFET. When this minimum is reached, the energy drawn each cycle exceeds the short-term demand from the load, thus the control loop causes some cycles to be skipped so as to maintain the long-term energy bal- ance. When the load is so low that many cycles need to be skipped, the amplitude of the drain voltage ringing becomes so small that it can no longer trigger the ZCD Block of the L6561. In that case the inter- nal starter of the IC will start a new switching cycles sequence. Something similar applies to the duty cycle as well, which eqn. (5’) predicts to be unity when θ = 0, that is at the zero-crossings of the mains voltage. In reality, a number of parasitic effects cause T ON and TOFF not to follow the ideal relationships (2) and (3). The effect of that on the overall operation is however negligible because the energy processed near a zero-crossing is very little. In the following, the ratio between the line peak voltage VPK and the reflected voltage VR will be indi- cated with Kv: Kv = VPK VR Energetic relationships Apart from the duty cycle, all the quantities expressed in the timing relationships depend on the through- put power, which is represented in the above equations by IPKp , the peak primary current occurring at AN1059 APPLICATION NOTE

be the "odd counterpart" of (6), at line frequency, as shown in fig. 4b). would be sinusoidal for Kv = 0 but will be distorted from an ideal sinusoid so much as Kv increases. does not permit unity power factor even in the ideal case, unlike boost topology. pending on their physical role. whose diagram as a function of the variable x is shown in fig. 5. Figure 5. High-PF Flyback characteristic

mention the constraints imposed by the specific application, if any. ductance required by the specific application. Figure 10. Maximum specific primary inductance required

The minimum resistor value can be found by imposing that the voltage on the capacitor at the beginning of each switching cycle never falls below the reflected voltage : R min = 1 fswmin ⋅ C ⋅ ln 1 + ΔV VR The power rating of this resistor can be estimated by considering the DC dissipation due to the reflected voltage and the leakage inductance energy: PR = VR2 R + 1 2 ⋅ (1 + Kvmin) ⋅ F2(Kvmin) ⋅ Llk ⋅ IPKpmax2 ⋅ fswmin. The blocking diode will be not only a very fast recovery type but will also feature a very fast turn-on time. In fact, the instantaneous forward drop at turn-on generates a spike, exceeding the overvoltage ΔV, that must be small. The diode will be rated for repetitive peak currents equal to IPKp , and with a breakdown voltage greater than VPKmax + VR . Considering a zener or a transil, its clamping voltage can be approximated with its breakdown voltage. In fact, the peak current is quite small and it is possible to neglect the contribution due to the dynamic resis- tance. The breakdown voltage, which should account for the drift due to the temperature rise, will then be: V(BR) ≈ VCL = VR + ΔV. The steady-state power dissipation capability must be at least: Ptransil = V(BR ) 2 ⋅ ( V(BR ) − VR ) ⋅ (1 + Kvmin) ⋅ F2(Kvmin) ⋅ Llk ⋅ IPKpmax2 ⋅ fswmin, while there is no concern about its peak power dissipation, since this is defined for power pulses of 1 ms (leakage inductance is typically demagnetized in less than 1 µs). As to the blocking diode, what said earlier about the one of the RCD clamp still applies. Output Capacitor The output capacitor undergoes the AC component of the secondary current Is(t), (see fig 3). Besides, to achieve a reasonably high PF, the voltage control loop is slow (typically, its bandwidth is be- low 100 Hz). As a result, there is a quite large voltage ripple appearing across the output capacitor. This ripple has two components. One is related to the high frequency triangles and depends almost entirely on the ESR of the output ca- pacitor, being the capacitive contribution practically negligible. Its maximum amplitude, occurring on the peak of the sinusoid, will be: ΔV o(HF ) = IPKs ⋅ ESR. The second component of the ripple is related to the twice line frequency envelope and, unlike the high frequency component, depends on the capacitance value, while the ESR contribution can be neglected. To calculate the amplitude of this component, only the fundamental harmonic of (11), at twice line fre- quency, will be taken into account. In fact, the amplitude of the higher order (even) harmonics is much smaller and the impedance of the capacitor decreases with frequency as well. According to Fourier’s analysis, the (peak) amplitude of the fundamental harmonic of (11) is: I o2 = IPKs ⋅ Kv π ⋅ ∫ π sin2(θ) ⋅ cos(2 ⋅ θ) 1 + Kv ⋅ sin(θ) dθ, that, defining the following function: AN1059 APPLICATION NOTE

H2 (x) = 1 π ⋅ π sin2(θ) ⋅ cos(2 ⋅ θ) 1 + x ⋅ sin(θ) dθ ≈ 0.25 − 1.5 ⋅ 10 −3 ⋅ x can be expressed as: Io2 = IPKs ⋅ Kv ⋅ H2(Kv) = 2 ⋅ Iout ⋅ H2 (Kv) F2(Kv). The absolute value in (19) is needed since the integral results negative, because the harmonic is 180° out of phase. Finally, the peak-to-peak amplitude of the low frequency output ripple is: ΔVo = 2 ⋅ Io2 ⋅ Z(2fL) (Co) = 1 π ⋅ H2 (Kv) F2(Kv) ⋅ Iout fL ⋅ Co In most cases, once a capacitor is selected so as to meet the requirement on the low frequency ripple, the ESR will be low enough to make the high frequency ripple negligible. Multiplier Bias and Sense Resistor Selection A resistor divider feeds a portion of the input voltage into pin 3 (MULT) to build the sinusoidal reference for the peak primary current. To set properly the operating point of the multiplier the following procedure is recommended. First, the maximum peak value for VMULT , VMULTpkmax , is selected. This value, which will occur at maxi- mum mains voltage, should be 2.5 to 3V in wide range mains applications and 1 to 1.5V in case of single mains. The minimum peak value, occurring at minimum mains voltage will be: V MULTpkmin = VMULTpkmax ⋅ VPKmin VPKmax This value, multiplied by the minimum guaranteed ΔVCS /ΔVCOMP will give the maximum peak output volt- age of the multiplier: Vcxpk = 1.65 ⋅ VMULTpkmin If the resulting Vcxpk exceeds the linearity limit of the current sense (1.6 V), the calculation should be re- peated beginning with a lower Vmultpkmax value. In this way, the divider ratio will be: KP = VMULTpkmax VPKmax and the individual resistor values can be chosen by setting the current through them, in the hundreds µA or less, to minimise power dissipation. The value of the sense resistor, connected between the source of the MOSFET and ground, across which the L6561 reads the primary current, is calculated as follows: R s ≤ Vcxpk IPKpmax The resistor will be rated for a power dissipation equal to: Ps = Rs ⋅ IPKpmax2 ⋅ F2(Kvmin) AN1059 APPLICATION NOTE

The pole is placed at a very low frequency so that the gain at twice line frequency is quite less than unity, while the zero boosts the phase in the neighbourhood of the open-loop crossover frequency so as to provide phase margin. A variation ΔVCOMP , due to a line and/or load change, modifies the amplitude Vcx of the rectified sinusoid at the output of the multiplier. This considering, the transfer function of the multiplier block will be: G2 = ΔVcx ΔVCOMP = KM ⋅ KP ⋅ VPK where KM is the gain of the multiplier (= 0.75 max.). The gain of the PWM modulator, which includes the current loop, is simply: G3 = ΔIPKp ΔVcx = 1 R s where Rs is the sense resistor. Small-Signal analysis shows that the gain G4(s) of the power stage is: G4 (s) = ΔVout ΔIPKp = n ⋅ Kv ⋅ F2(Kv) Γ(Kv) + 1 ⋅ R o 2 ⋅ 1 + s ⋅ (C o ⋅ ESR) 1 + s ⋅ (C o ⋅ R o Γ(Kv) + 1) where the function Γ(x) is defined as follows: Γ(x) = 1 + x F2(x) ⋅ dF2(x) dx ≈ 1 + 0.01 ⋅ x 1 + 0.8 ⋅ x. The feedback network can have different configurations, depending on the requirements on the toler- ance and on the regulation of the output voltage. In this context a popular configuration (see fig. 15) will be taken into consideration. It uses an optocou- pler for galvanic isolation between primary and secondary and a TL431, a cheap voltage reference/op- amp housed in a three pin package. The gain, H(s), at twice line frequency must be low. In fact, being the output voltage ripple quite high, a high gain could saturate the dynamics of the TL431 and/or of the optocoupler, besides complicating things in getting a narrow overall bandwidth. Referring to fig. 15, it is possible to write: H (s) = ΔV E ΔVout = 1 R 4 ⋅ R 5 ⋅ R6 R 5 + R6 s ⋅ (C 1 ⋅ R1) , where CTR is the Current Transfer Ratio of the optocoupler. When designing the control loop, first select the operating current of optocoupler’s transistor (IC ). It is ad- vantageous to selects a low IC value (e.g. 1 mA): this will not only extend the lifetime of the device but, in the present case, will also help keep low the gain of the feedback network at twice line frequency. Since in closed-loop operation the quiescent value of VE will be in the neighbourhood of 2.5V (internal reference of the L6561 E/A), R5 will be: R 5 = 2.5 IC R 4 will be selected so as to maintain VK voltage above 2.5V for a correct functionality of the TL431 even in the worst case, that is when the optocoupler exhibits its minimum CTR, because of the statistical spread of this parameter. AN1059 APPLICATION NOTE

where 2.5 is the internal reference of the TL431 and IR2 the current flowing through R2. 5 times less than R1. This yields the value of C1. tween a high enough PF and an acceptable transient response, ensuring also sufficient phase margin. path when the converter is turned off. Figure 15. Feedback network and connection to the error amplifier.

An example of step-by-step design procedure of an L6561-based, high-PF flyback converter will be here described for reference. It concerns a 30W AC adapter for portable equipment. The application was ac- tually realised and some experimental results are here presented. 1. Design Specifications: - Mains voltage range: VACmin = 88 Vac, VACmax = 264 Vac - Minimum mains frequency: fL = 50 Hz - DC Output Voltage: Vout = 15 V - Maximum output current: Iout = 2A - Maximum 2fL output ripple: ΔVo = 1V peak-to-peak 2. Pre-design Choices: - Minimum switching frequency: fswmin = 25 kHz - Reflected voltage: VR = 100V - Leakage inductance overvoltage: ΔV =70V - Expected efficiency: η = 85% 3. Preliminary Calculations: - Minimum Input Peak Voltage: VPKmin = VACmin ⋅ √2 = 88 ⋅ √2 −4 = 120V (4V total drop on RDS(on), Rs, ...) - Maximum Input Peak Voltage: VPKmin = VACmin ⋅ √2 = 264 ⋅ √2 = 373V - Maximum Output Power: Pout = Vout ⋅ Iout = 15 ⋅ 2 = 30W - Maximum Input Power: Pin = Pout η ⋅ 100 = 30 85 ⋅ 100 = 35.3W - Peak-to-reflected Voltage Ratio: Kv = VPKmin VR = 120 100 = 1.2 4. Operating Conditions: - Peak Primary Current: IPKp = 2 ⋅ Pin VPKmin ⋅ F2(Kv) = 2 ⋅ 35.3 120 ⋅ 0.254 = 2.32A - RMS Primary Current: IRMSp = IPKp ⋅ √ F2(Kv) 3 = 0.675A - Peak Secondary current: IPKs = 2 ⋅ Iout Kv ⋅ F2(Kv) = 2 ⋅ 2 - RMS Secondary Current: IRMSs = IPKs ⋅ √Kv ⋅ F3(Kv) 3 = 3.79A 5. Transformer: - Primary inductance: Lp = VPKmin (1 + Kv) ⋅ fswmin ⋅ IPKp = 120 = 940µH - Primary-to-secondary turns ratio: n = VR (Vout + Vf) = 100 15 + 0.6 = 6.41 From diagram of fig. 11, by interpolation, the minimum AP required is about 0.5 cm4. An ETD29 core (AP = 0.684 cm4), 3C85 grade is selected. From the relevant datasheet, with 1 AN1059 APPLICATION NOTE

mm air gap 90 primary turns will result in about 970µH primary inductance. 14 secondary turns give a 6.43 turns ratio, very close to the target. Estimating the thermal resistance of the ETD29 equal to 26°C/W, the maximum power dissipation (supposed to be on copper only) for 30°C hot-spot temperature rise will be 1.15W (half will be allocated to the primary and half to the secondary). This requires the resistance of the primary to be no more than 1.26 Ω and the secondary’s no more than 40 mΩ . An AWG27 (∅ ≈ 0.4 mm) wire for the primary and a strand of 5xAWG27 for the secondary will meet the requirement.The primary winding will be split in two halves of 45 turns each, series connected, and the secondary will be sandwiched in be- tween to reduce leakage inductance. 6. MOSFET selection - Maximum Drain Voltage:V DSmax = VPKmax + VR + ΔV = 373 + 100 + 70 = 543V There is margin to select a 600 V device. This will minimise gate drive and capacitive losses. Assuming that the MOSFET will dissipate 5% of the input power, that losses are due to con- duction only, and that RDS(on) doubles at working temperature, the RDS(on) at 25°C should be about 2Ω . An STP4NA60 (RDS(on) = 2.2 Ω max.) is selected. 7. Catch diode selection - Maximum reverse voltage: VREVmax = VPKmax n + Vout = 373 6.41 + 15 = 73.2V A 100V Schottky diode will minimise conduction losses. As to its current rating, a tentative could be the STPS8H100D. From the relevant datasheet, the power dissipation is estimated as: Pdiode = 0.48 ⋅ Iout + 0.013 ⋅ IRMSs 8. Output Capacitor Selection The minimum capacitance value that meets the specification on the 100/120 Hz ripple is: C outmin = 1 π ⋅ fL ⋅ H2 (Kv) F2(kv) ⋅ Iout ΔVo = 0.108 ⋅ 2 3.14 ⋅ 50 ⋅ 0.254 ⋅ 1 = 5417µF Three 2200µF electrolytic capacitors will have an ESR low enough to consider the high fre- quency ripple negligible as well as sufficient AC current capability. 9. Clamp network With a proper construction technique, the leakage inductance can be reduced to as much as 2% of the primary inductance, that is 20µH in the present case. A transil clamp is selected. The clamp voltage will be VCL = VR + ΔV = 100 + 70 = 170V. The steady-state power dissipa- tion is estimated to be about 2W. A P6KE170A transil is selected. The blocking diode is an STTA106. 10. Multiplier bias and sense resistor selection Assuming a peak value of 2.4V (@VAC = 264V) on the multiplier input (MULT, pin 3), the peak value at minimum line voltage will be VMULTpkmin = 2.4 ⋅ 88/264 = 0.8V which, multiplied by the maximum slope of the multiplier, 1.65, gives 1.32V peak voltage on current sense (CS, pin 4). Since the linearity limit (1.6V) is not exceeded, this is acceptable. The divider ratio will then be -3. Considering 120µA current for the divider, the lower resistor will is selected), while its power rating will be 0.5 ⋅ IRMSp 2 = 0.5 ⋅ 0.6752 = 228mW 11. Feedback and Control Loop The selected optocoupler is a 4N35 from Toshiba. 1 mA quiescent collector current is se- lected. From opto’s datasheet, with 1mA collector current, the diode current can be between 1 and 2 mA approximately (0.5 < CTR < 1). AN1059 APPLICATION NOTE

12kΩ . Select R3 = 2.2 kΩ . With C1 = 1µF the zero will be at about 70 Hz, which is acceptable. gin will be 50 Hz and 42° respectively. of its bench evaluation and fig. 18 shows some significant waveforms.

15 Vdc / 2A

3 MΩ 470 kΩ

≈1 mm airgap for 1 mH primary inductance. Figure 16. 30W High-PF Flyback with the L6561: electrical schematic Figure 17. 30W High-PF Flyback with the L6561: evaluation results

Figure 18. 30W High-PF Flyback with the L6561: principal waveforms

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