Amplifier

AN10436

NXP Semiconductors

TDA8932B/33(B) Class-D audio amplifier Rev. 01-12 December 2007

Manufacturer: NXP Semiconductors

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TDA8932B/33(B) Class-D audio amplifier Rev. 01 — 12 December 2007 Application note Document information Info Content Keywords Class-D amplifier, High efficiency, Switch mode amplifier, Flat TV. Abstract This application note describes a stereo Switched Mode Amplifier (SMA) for audio, based on either the TDA8932B or TDA8933(B) Class-D audio amplifier device of NXP Semiconductors, which has been designed for Flat TV applications. The TDA8932B device is the high-power version that delivers an output power of 2 × 10 W RMS to 2 × 25 WRMS in a Single Ended (SE) configuration or 10 WRMS to 50 WRMS in a Bridge Tied Load (BTL) configuration. The TDA8933(B) device is the low-power version that delivers an output power of 2 × 5 W RMS to 2 × 15 WRMS in a SE configuration or 10 WRMS to 30 WRMS in a BTL configuration. This high efficiency SMA device has been designed to operate without a heat sink and has the flexibility to operate from either an asymmetrical supply or a symmetrical supply with a wide range (10 V to 36 V or ±5Vt o ±18 V). The TDA8932B/33(B) device utilizes two advanced features, the Thermal Foldback (TF) and the cycle-by-cycle current limiting to avoid audio holes (interruptions) during normal operation. In addition, the TDA8932B/33(B) utilizes integrated Half Supply Voltage (HVP) buffers to simplify the design for an asymmetrical supply in the SE configuration. Control logic is integrated for a pop free transition between on/off. A SLEEP mode is incorporated to comply with the power saving regulations. An application designed around the TDA8932B/33(B) device is very robust because of the internal protection features, such as a number of voltage protections, OverCurrent Protection (OCP) and OverTemperature Protection (OTP).

AN10436_1 © NXP B.V. 2007. All rights reserved. Application note Rev. 01 — 12 December 2007 2 of 55 Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com NXP Semiconductors AN10436 TDA8932B/33(B) Class-D audio amplifier

Revision history

01.00 20071212 First release

AN10436_1 © NXP B.V. 2007. All rights reserved. Application note Rev. 01 — 12 December 2007 3 of 55 NXP Semiconductors AN10436 TDA8932B/33(B) Class-D audio amplifier 1. Introduction This application note describes a reference design of a Switched Mode Amplifier (SMA) for audio, based on the TDA8932B or TDA8933(B) device of NXP Semiconductors operating from an asymmetrical supply. The TDA8932B device and the TDA8933(B) device are pin-to-pin compatible and can be used in either a stereo SE configuration or a mono BTL configuration. The TDA8932B is the high-power version and the TDA8933(B) is the low-power version. Together they cover a wide power range per channel of 5 W RMS to 50 WRMS. The two versions are available in the SO32 package (TDA8932BT, TDA8933T) and the HTSSOP32 package (TDA8932BTW, TDA8933BTW). The TDA8932B/33(B) Class-D amplifier is intended for:

Flat TV application
Flat panel monitors
Multimedia systems, docking stations
Wireless speakers
Microsystems Distinctive features
High efficiency Class-D audio amplifier due to a low RDSon in SE configuration.
Operates from a wide voltage range 10 V to 36 V (asymmetrical) or ±5 V to ±18 V (symmetrical).
Maximum power capability: – TDA8932B is 2 × 30 WRMS short time output power in 4 Ω SE without heat sink. – TDA8933(B) is 2 × 20 WRMS short time output power in 8 Ω SE without heat sink.
Cycle-by-cycle current limiting to avoid interruption during normal operation.
Unique Thermal Foldback (TF) to avoid interruption during normal operation.
Integrated Half Supply Voltage (HVP) buffers for reference and SE output capacitance (asymmetrical supply).
Internal logic for pop free power supply on/off cycling.
Low standby current in SLEEP mode for power saving regulations. Protection features
Window Protection (WP)
UnderVoltage Protection (UVP)
OverVoltage Protection (OVP)
UnBalance Protection (UBP)
OverCurrent Protection (OCP)
OverTemperature Protection (OTP)
ESD protection These features enable an engineer to design a high performance, reliable and cost effective SMA with only a small number of external components.

1.1 Block diagram

1.2 Fixed frequency pulse widt h modulated Class-D concept

The TDA8932B/33(B) device is a closed loop fixed frequency pulse width modulated Class-D amplifier with two differential analog inputs, each driving an independent power stage (see Figure 2). The power stage consists out of a low side and a high side N-channel MOSFET. Fig 1. Block diagram 001aaf597 10 31 8 TDA8932B OSCILLATOR BOOT1 VDDP1 OUT1 VSSP1 PWM MODULATOR DRIVER HIGH DRIVER LOW CTRL MANAGER CTRLPWM MODULATOR PROTECTIONS: OVP, OCP, OTP, UVP, TF, WP STABILIZER 11 V STABILIZER 11 V REGULATOR 5 V MODE VDDA IN1P OSCREF OSCIO V DDA VSSD IN1N INREF IN2P IN2N 6POWERUP 4DIAG 7CGND BOOT2 VDDP2 OUT2

25 STAB1

24 STAB2

30 HVP1

19 HVP2

1, 16, 17, 32 VSSD(HW)

AN10436_1 © NXP B.V. 2007. All rights reserved. Application note Rev. 01 — 12 December 2007 5 of 55 NXP Semiconductors AN10436 TDA8932B/33(B) Class-D audio amplifier The TDA8932B/33(B) can be configured for use in either SE or BTL. The major benefits of an SE configuration compared to a BTL configuration are cost and efficiency. This is because:

Only one pair of power switches is required for each channel.
Only one LP filter (inductor and film capacitor) is required for each channel.
Only two power stages for stereo in one package, therefore no heat sink required. An internal feedback network has a fixed closed loop gain of 30 dB in the SE configuration (36 dB in the BTL configuration). The Pulse Width Modulation (PWM) output signal has a oscillator frequency that is fixed by either:
An internal oscillator when configured as master.
An external oscillator when configured as slave. The pulse width will be modulated according to the input signal. Section 3 describes the complete application design of the TDA8932B/33(B) and includes the dimensioning of the LP output filter.

1.3 Typical application circuits (simplified)

1.3.1 Asymmetrical supply stereo SE configuration

The simplified application circuit of the TDA8932B/33(B) device when operated from an asymmetrical supply (single supply) can be seen in Figure 3. The TDA8932B/33(B) incorporates three integrated half supply voltage buffers to simplify the design for an asymmetrical supply in SE configuration. One buffer is for the reference decoupling capacitor (CHVPREF) on HVPREF (pin 11) and two other buffers are for the two AC-couple capacitors (CSE) in series with the speaker. Fig 2. TDA8932B/33(B) in SE configuration IN1P 2 IN1N TDA8932B/33(B) IN2N 14 IN2P PWM OUT1 PWM OUT2 CSE LP FILTER 010aaa000 CSE LP FILTER

1.3.2 Symmetrical supply stereo SE configuration

The TDA8932B/33(B) can operate also from a symmetrical supply (see Figure 4). The three half supply voltage buffers are disabled. HVPREF (Pin 11), HVP1 (pin 30) and HVP2 (pin 19) should be connected to ground when supplied from a symmetrical supply. (1) The TDA8933T device requires a 1 M Ω resistor in parallel with the bootstrap capacitor Cbo. TDA8932BT, TDA8932BTW and TDA8933BTW devices do not require a 1 MΩ resistor. Fig 3. Simplified SE application TDA 8932B/33(B) (asymmetrical supply) TDA8932B/ 33(B) VSSD(HW) 470 nF Cin Cen 470 nF VSSD(HW) IN1P Cinref 100 nF Chvp 100 nF Chvpref 47 μF (25 V) Cvddp 220 μF (35 V) 470 nF Cin 470 nF Cin 470 nF Cin 100 nF Cosc 39 kΩ Rosc 10 Ω Rvdda MUTE control VPA SLEEP control Cvdda 100 nF VP VPA VP GND OSCIO IN1N HVP1 DIAG VDDP1 ENGAGE BOOT1 POWERUP OUT1 CGND VSSP1 VDDA STAB1 VSSA STAB2 OSCREF VSSP2 HVPREF OUT2 INREF BOOT2 TEST VDDP2 IN2N HVP2 IN2P DREF VSSD(HW) VSSD(HW) 010aaa418 − Csn 470 pF Csn 470 pF Rsn 10 Ω Rsn 10 Ω Llc Llc Cdref 100 nF HVP1 VP Cstab 100 nF Clc Cvddp 100 nF Cvddp 100 nF VP Cbo 15 nF Cvssp 100 nF Cbo 15 nF Cse HVP1 Clc Cse HVP2 CHVP 100 nF HVP2 (1) (1)

AN10436_1 © NXP B.V. 2007. All rights reserved. Application note Rev. 01 — 12 December 2007 7 of 55 NXP Semiconductors AN10436 TDA8932B/33(B) Class-D audio amplifier A symmetrical supply has some benefits compared to an asymmetrical supply. First, the power bandwidth is not limited by the size of the SE capacitor. Therefore, for a full bandwidth (20 Hz to 20 kHz) amplifier, a symmetrical supply should be considered to avoid a large value SE capacitor. Secondly, when the supply is either unregulated and/or weak (e.g., a 50 Hz / 60 Hz transformer), the output signal will not suffer from asymmetrical clipping (see Section 4.4

1.3.3 Asymmetrical supply mono BTL configuration

The TDA8932B/33(B) can operate in BTL configuration when a high output power is required at a low supply voltage (e.g., for driving a subwoofer in a 2.1 system). See Figure 5. (1) The TDA8933T device requires a 1 M Ω resistor in parallel with the bootstrap capacitor Cbo. TDA8932BT, TDA8932BTW and TDA8933BTW devices do not require a 1 MΩ resistor. Fig 4. Simplified SE application TDA 8932B/33(B) (symmetrical supply) TDA8932B/ 33(B) VSSD(HW) 470 nF Cin Cen 470 nF Csn 470 pF Csn 470 pF Rsn 10 Ω Rsn 10 Ω Llc Llc VSSD(HW) IN1P Cdref 100 nF Cinref 100 nF Cvddp 220 μF (25 V) 470 nF Cin 470 nF Cin 470 nF Cin 100 nF Cosc 39 kΩ Rosc 10 Ω Rvdda MUTE control VDDA VSSA VSS VSSVSSA VSSA VSSA VSSA SLEEP control Cvdda 100 nF VDD VDDA 10 Ω Rvssa VSS VSSA VDD VSS Cvssa 100 nF Cvssp 220 μF (25 V) GND OSCIO IN1N HVP1 DIAG VDDP1 ENGAGE BOOT1 VDD POWERUP OUT1 CGND VSSP1 VDDA STAB1 VSSA STAB2 OSCREF VSSP2 HVPREF OUT2 INREF Cstab 100 nF Clc ClcBOOT2 TEST VDDP2 IN2N HVP2 IN2P DREF VSSD(HW) VSSD(HW) 010aaa419 VSSA Cvddp 100 nF Cvddp 100 nF VSS VDD Cbo 15 nF Cvssp 100 nF Cbo 15 nF Cvssp 100 nF VSS (1) (1) VSSA

1.3.4 Symmetrical supply mono BTL configuration

The TDA8932B/33(B) can operate in BTL configuration when high output powers are required at a low supply voltage (e.g., for driving a subwoofer in a 2.1 system). See Figure 6. (1) The TDA8933T device requires a 1 M Ω resistor in parallel with the bootstrap capacitor Cbo. TDA8932BT, TDA8932BTW and TDA8933BTW devices do not require a 1 MΩ resistor. Fig 5. Simplified BTL application T DA8932B/33(B) (asymmetrical supply) TDA8932B/ 33(B) VSSD(HW) 470 nF Cin Cen 470 nF Csn 470 pF Rsn 10 Ω Llc Llc VSSD(HW) IN1P Cinref 100 nF Chvp 100 nF 470 nF Cin 100 nF Cosc 39 kΩ Rosc MUTE control VPA SLEEP control OSCIO IN1N HVP1 DIAG VDDP1 ENGAGE BOOT1 POWERUP OUT1 CGND VSSP1 VDDA STAB1 VSSA STAB2 OSCREF VSSP2 HVPREF OUT2 INREF Cstab 100 nF Clc Clc BOOT2 TEST VDDP2 IN2N HVP2 IN2P DREF VSSD(HW) VSSD(HW) 010aaa420 Cvddp 220 μF (35 V) 10 Ω Rvdda Cvdda 100 nF VP VPA VP GND HVPREF Csn 470 pF Rsn 10 Ω Cdref 100 nF Cvddp 100 nF VP Cbo 15 nF Chvp 100 nF Rhvp 470 Ω HVPREF Csn 470 pF Rsn 10 Ω HVPREF VP Cvddp 100 nF Cbo 15 nF Chvp 100 nF Rhvp 470 Ω (1) (1)

AN10436_1 © NXP B.V. 2007. All rights reserved. Application note Rev. 01 — 12 December 2007 9 of 55 NXP Semiconductors AN10436 TDA8932B/33(B) Class-D audio amplifier 2. Functional IC description This chapter briefly describes the main functionality of the TDA8932B/33(B) device and the different modes. It also describes the different features and the protections implemented in the TDA8932B/33(B). Table 3 in Section 2.8 in gives a description of each pin.

2.1 Control inputs

The TDA8932B/33(B) is controlled by two inputs, POWERUP (pin 6) and ENGAGE (pin 5). The POWERUP is a two-level high impedance input. The ENGAGE input has an internal pull-up current source and an internal pull-down resistor of 100 kΩ (typical). The internal pull-up current source is enabled after the power stages are (1) The TDA8933T device requires a 1 M Ω resistor in parallel with the bootstrap capacitor Cbo. TDA8932BT, TDA8932BTW and TDA8933BTW devices do not require a 1 MΩ resistor. Fig 6. Simplified BTL application TDA8932B/33(B) (symmetrical supply) TDA8932B/ 33(B) VSSD(HW) Cen 470 nF Llc Llc VSSD(HW) IN1P Cinref 100 nF 100 nF Cosc 39 kΩ Rosc MUTE control VDDA VSSA VSSA VSSA VSSA SLEEP control OSCIO IN1N HVP1 DIAG VDDP1 ENGAGE BOOT1 POWERUP OUT1 CGND VSSP1 VDDA STAB1 VSSA STAB2 OSCREF VSSP2 HVPREF OUT2 INREF Cstab 100 nF Clc Clc BOOT2 TEST VDDP2 IN2N HVP2 IN2P DREF VSSD(HW) VSSD(HW) 010aaa421 Cvddp 220 μF (25 V) 10 Ω Rvdda Cvdda 100 nF VDD VDDA 10 Ω Rvssa VSS VSSA VDD VSS Cvssa 100 nF Cvssp 220 μF (25 V) GND 1 μF Cin 1 μF Cin VSS Csn 470 pF Rsn 10 Ω VSSVSSA VDD Cvddp 100 nF Cbo 15 nF Cvssp 100 nF Csn 470 pF Rsn 10 Ω Cdref 100 nF VSSA Cvddp 100 nF VDD Cbo 15 nF Cvssp 100 nF VSS VSS (1) (1) VSSA

AN10436_1 © NXP B.V. 2007. All rights reserved. internal pull-up current source. [1] ENGAGE open pin voltage is 2.8 V in OPERATING mode. [2] DIAG open pin voltage is 2.5 V in MUTE and OPERATING mode. internal pull-up current source.

2.1.1 Mode description

SLEEP mode: The SLEEP mode is incorporated to reduce the power consumption in system idle mode. In SLEEP mode, the internal 5 V stabilizer (DREF), the 11 V stabilizers (STAB1, STAB2) and the half supply voltage buffers (HVPREF, HVP1, HVP2) are disabled to reduce supply current consumption.
MUTE mode: In MUTE mode, the 5 V (DREF) and the 11 V (STAB1, STAB2) stabilizers will be enabled (internal logic biased) and the half supply voltage buffers will charge respectively the reference decouple capacitor (CHVPREF) and the AC-couple capacitors (CSE) in series with the speaker. The power stage is enabled (starts switching) after the SE capacitors are charged completely.
OPERATING mode: In the OPERATING mode, the gain of the device is increased gradually to 30 dB per output stage to avoid pop noise. The complete start-up sequence will take about 500 ms in a typical SE application.
FAULT mode: The FAULT mode is entered when one of the internal protections is triggered (see Section 2.6) and as a consequence the DIAG (pin 4) is set to low. The internal pull-up current source of the ENGAGE pin is disabled in FAULT mode. Therefore, the external capacitor will be discharged by means of the internal pull-down resistor. The FAULT mode can be entered also by means of an external pull-down to CGND. Table 2 shows an overview of the internal protections.

Table 1. Control voltages referenced to CGND

2.2 Half Supply Voltage (HVP) chargers

The internal HVPREF, HVP1 and HVP2 buffers will quickly charge the reference capacitor (CHVPREF) and the SE capacitors (CSE) before the power stage is enabled. The typical charge current of the HVP1 (pin 30) and the HVP2 (pin 19) buffers is 80 mA (dependent on the junction temperature). The charge time of the SE capacitor can be estimated as follows: (1) Where: CSE = single ended capacitor (F) VDDA = analog supply voltage (V) VSSA = negative analog supply voltage (V) I = typical charge current (A) Example: Charging an SE capacitor of 1000 μF at a supply voltage of 22 V takes about 138 ms. Remark: The half supply voltage buffers are short circuit protected.

2.3 Pop free power supply on/off cycling

2.3.1 Supply turn-on

Internal logic will delay the operation (regardless of the control voltages) until the HVPREF, HVP1 and HVP2 buffers are settled at ½(VDDA − VSSA) to avoid pop noise. For an optimum pop performance, a capacitor of 470 nF should be attached to the ENGAGE (pin 5). This will make sure the gain and therefore the offset will be increased gradually to avoid pop sound (see Figure 21).

2.3.2 Supply turn-off

Either the UnBalance Protection (UBP) or the UnderVoltage Protection (UVP) will avoid pop noise when the power supply is turned off. The power stage is disabled when either VDDA drops more than 20 % (see Section 2.6.6 for more detail) or the UVP threshold level (9.5 V typical) is reached. Remark: During power supply on/off cycling, an unwanted input signal from the audio source can still cause a pop noise. To prevent this the ENGAGE pin should be pulled down to CGND to mute any unwanted signal.

2.4 Oscillator frequency

An external resistor connected between the OSCREF (pin 10) and VSSA sets the oscillator frequency of the PWM output. The oscillator frequency can be estimated with this equation: (2) t CSE 0.5 V DDA VSSA–()⋅⋅ fosc 12.45 10 9⋅ Rosc

AN10436_1 © NXP B.V. 2007. All rights reserved. Application note Rev. 01 — 12 December 2007 12 of 55 NXP Semiconductors AN10436 TDA8932B/33(B) Class-D audio amplifier Where: Rosc = resistor to set the oscillator frequency. The oscillator frequency can be set between 250 kHz and 500 kHz. Example: The use of a 39 kΩ resistor will result in a oscillator frequency of about 320 kHz. Remark: A decouple capacitor of 100 nF should be connected across Rosc for noise reduction. Remark: Synchronization is recommended when two or more TDA8932B/33(B) devices are used in the same application (see Section 2.5).

2.5 Device synchronization

Synchronization is recommended to avoid possible audible beat tones from the speakers when two or more TDA8932B/33(B) devices are used in the same application. Synchronization can be achieved by connecting all OSCIOs (pin 31) together and configuring one of the devices as master, while the other TDA8932B/33(B) device is configured as slave (see Figure 7 A device is configured as master when a resistor is connected between OSCREF (pin 10) and VSSA to set the oscillator frequency. The OSCIO (pin 31) of the master is then configured as an oscillator output for synchronization. The OSCREF (pin 10) of the slave devices should be shortened to VSSA to configure the OSCIO as an input. Remark: In a 2.1 system, the SE device for the L/R channel should be configured as master. Remark: The maximum number of slaves driven by one master is 12. Fig 7. Device synchronization in a 2.1 system VSSA OSCREF OSCIO VSSA OSCREF OSCIO MASTER L/R CHANNEL SLAVE SUBWOOFER CHANNEL TDA8932B/33(B) 31 31 99 10 Rosc 39 kΩ Cosc 100 nF 010aaa001 TDA8932B/33(B) VSSAVSSA

2.6 Limiting and protection features

Window Protection (WP)
UnderVoltage Protections (UVP)
OverVoltage Protection (OVP)
UnBalance Protection (UBP)
OverCurrent Protection (OCP)
OverTemperature Protection (OTP) When one of the above protections is triggered, the device will enter the FAULT mode and the power stage is disabled immediately (floating). Furthermore, an internal timer of about 100 ms is started and the DIAG (pin 4), referenced to CGND, is set low for the first 50 ms of the timer to indicate this protection status (FAULT mode). In addition the internal pull-up current of the ENGAGE pin is disabled in the FAULT mode, so the external capacitor will be discharged by means of the internal pull-down resistor (100 kΩ). After about 100 ms the device will restart (self-recovering), but only when the fault condition has been resolved. A microcontroller can use the diagnostic signal (DIAG) to, e.g., shut down either the amplifier or the power supply.

Table 2. Overview of all the limiting and pr otection features inside the TDA8932B/33(B)

AN10436_1 © NXP B.V. 2007. All rights reserved. [1] WP threshold level at V P = 22 V. See Equation 3 and Equation 4 for the threshold level versus the supply voltage. [2] DIAG is active low for at least 50 ms. [3] UBP threshold level at V P = 22 V. See Equation 5 and Equation 6 for the threshold level versus the supply voltage.

2.6.1 Thermal Foldback (TF)

maximum junction temperature will not go beyond the absolute maximum temperature. occur and the device will always stay within the Safe Operating Area (SOA).

2.6.2 Cycle-by-cycle current limiting

Remark: When the cycle-by-cycle current limiting becomes active, it will cause distortion. the supply voltage and the speaker impedance.

2.6.3 Window Protection (WP)

Table 2. Overview of all the limiting and pr otection features inside the TDA8932B/33(B) …continued

AN10436_1 © NXP B.V. 2007. All rights reserved. Application note Rev. 01 — 12 December 2007 15 of 55 NXP Semiconductors AN10436 TDA8932B/33(B) Class-D audio amplifier High threshold level: (4) Where: VO(wp) = window protection output voltage (low or high). Referenced to VSSA (V). VDDA = analog supply voltage (V). The TDA8932B/33(B) will recover when the output voltage at OUT1 and OUT2 is within (21/32) VDDA >V o >( 1 1 / 3 2 )VDDA.

2.6.4 UnderVoltage Protection (UVP)

The TDA8932B/33(B) requires a minimum supply voltage for proper operation. When the supply voltage drops below the UVP threshold level of 9.5 V (typical V DDA − VSSA), the power stage becomes floating and the DIAG is set low for at least 50 ms.

2.6.5 OverVoltage Protection (OVP)

An OVP is incorporated because an SE Class-D amplifier is able to increase the supply voltage when it is driven at low audio frequencies. This phenomenon is better known as "supply pumping" (see also Section 4.3). The OVP prevents that supply pumping exceeds the absolute maximum supply voltage rating of the TDA8932B/33(B). This is a protection against self-destruction. The OVP threshold level is an internal fixed level at 38.5 V (typical VDDA − VSSA). Beyond this OVP threshold level the power stage will become floating and the DIAG is set low for at least 50 ms. Remark: The OVP will neither prevent nor limit an overvoltage caused by the power supply.

2.6.6 UnBalance Protection (UBP)

The UBP senses the supply voltage unbalance between the analog supply voltages VDDA and VSSA with respect to the HVPREF voltage at pin 11. The UBP is triggered when the unbalance exceeds a certain level to avoid improper biasing resulting in e.g. pop. The DIAG is set low and remains low for at least 50 ms. The supply voltage where the UBP becomes active with an asymmetrical supply can be estimated as follows: Low threshold level: (5) High threshold level: (6) Where: VP(ubp) = unbalance protection supply voltage (low and high). VDDA (pin 8) referenced to VSSA (V). VOw p() h VP ubp() l 5--- VHVPREF⋅= VP ubp() h 3--- VHVPREF⋅=

AN10436_1 © NXP B.V. 2007. All rights reserved. Application note Rev. 01 — 12 December 2007 16 of 55 NXP Semiconductors AN10436 TDA8932B/33(B) Class-D audio amplifier VHVPREF = half supply voltage reference (pin 11) referenced to VSSA (V) The TDA8932B/33(B) will recover when the supply voltage is within (8/5) VHVPREF >V P >( 8 / 3 )VHVPREF. The supply voltage at which the UBP becomes active with a symmetrical supply can be estimated as follows: Low threshold level: (7) High threshold level: (8) Where: VDDA(ubp) = unbalance protection analog supply voltage. VDDA (pin 8) referenced to VHVPREF (V), HVPREF is connected to GND. VSSA = negative analog supply voltage (pin 9) referenced to VHVPREF (V) Example asymmetrical supply (use Equation 5 and Equation 6): At a supply voltage of 22 V, the voltage on HVPREF is equal to VHVPREF = 11 V. The HVPREF voltage is buffered so the level will change only very slowly. When the supply voltage drops quickly (dV/dt > 4 V/s), the UBP is triggered below 17.6 V. When the supply voltage increases quickly, the UBP is triggered above 29.3 V. Remark: With either an unregulated or a weak power supply, it might happen that this UBP is triggered, e.g., because of a voltage drop during a transient from no load to full load condition. See Section 4.4 for more detail.

2.6.7 OverCurrent Protection (OCP)

The OCP is activated only in a fault condition when the current exceeds 4 A (TDA8932B) or 2 A (TDA8933(B)) because of either a low ohmic short across the load or a low ohmic short from the demodulated output (after the inductor) to either VSS or VDD. The DIAG is set low for 50 ms and the internal timer of 100 ms is started. The timer or the WP will keep the power stage disabled for at least 100 ms. As long as the short remains across the load, this cycle will repeat. The average power dissipation in the TDA8932B/33(B) will be low because the short circuit current will flow only during a very small part of the timer cycle of 100 ms. When the current exceeds 4 A (TDA8932B) or 2 A (TDA8933(B)) during normal operation, only the cycle-by-cycle current limiting is active without causing any audio holes (interruptions). See also Section 2.6.2. VDDA ubp() l 5--- VSSA⋅= VDDA ubp() h 3--- VSSA⋅=

2.6.8 OverTemperature Protection (OTP)

The OTP is activated only in a fault condition when the junction temperature exceeds 155 °C (typical) e.g. during a short across the SE capacitor. The DIAG output is set low for at least 50 ms and an internal timer of 100 ms is started. The timer will keep the power stage disabled for at least 100 ms. When the junction temperature exceeds 140 °C during normal operation, the thermal foldback is active without causing any audio holes (interruptions). See also Section 2.6.1.

2.7 Pinning information

Fig 8. Pin configuration SO32 TDA8932BT TDA8933T VSSD(HW) VSSD(HW) IN1P OSCIO IN1N HVP1 DIAG V DDP1 ENGAGE BOOT1 POWERUP OUT1 CGND V SSP1 VDDA STAB1 VSSA STAB2 OSCREF VSSP2 HVPREF OUT2 INREF BOOT2 TEST V DDP2 IN2N HVP2 IN2P DREF VSSD(HW) VSSD(HW) 010aaa422

2.8 Pin description

Table 3. Pin description the VSSD(HW) is connected to the negative supply line, VSSA. IN1P 2 Positive audio input for power stage 1. IN1N 3 Negative audio input for power stage1. ENGAGE 5 Input with internal pull-up to switch between MUTE mode and OPERATING mode. POWERUP 6 Input to switch between SLEEP mode and MUTE mode. DDA 8 Positive analog supply voltage. VSSA 9 Negative analog supply voltage. this pin should be connected to VSSA. symmetrical supply, this pin should be connected to the CGND (supply ground). INREF 12 Decoupling for the input reference voltage. IN2N 14 Negative audio input for power stage 2. IN2P 15 Positive audio input for power stage 2. DREF 18 Decoupling of the internal 5 V regulator.

Design 2 x 5 W - 25 W audio amplifier (asymmetrical supply)

maximum short time output power is equal to 2 × 25 WRMS into 4 Ω (VP = 29 V). maximum short time output power is equal to 2 × 18 WRMS into 8 Ω (VP = 34 V). design based on the TDA8932B/33(B).

3.1 Output power estimation

symmetrical supply, this pin should be connected to the CGND (supply ground). VDDP2 20 Positive supply voltage for the power stage 2. BOOT2 21 Bootstrap for the high-side driver, power stage 2. OUT2 22 PWM output, power stage 2. SSP2 23 Negative supply voltage for the power stage 2. STAB2 24 Decoupling of the internal 11 V regulator for power stage 2. STAB1 25 Decoupling of the internal 11 V regulator for power stage 1. SSP1 26 Negative supply voltage for the power stage 1. OUT1 27 PWM output, power stage 1. BOOT1 28 Bootstrap for the high-side driver, channel 1. DDP1 29 Positive supply voltage for the power stage 1. symmetrical supply, this pin should be connected to the CGND (supply ground). OSCIO 31 Oscillator input in the slave configuration or the oscillator output in the master configuration.

AN10436_1 © NXP B.V. 2007. All rights reserved. Application note Rev. 01 — 12 December 2007 20 of 55 NXP Semiconductors AN10436 TDA8932B/33(B) Class-D audio amplifier (10) Where: VP = supply voltage (V) (VDDP − VSSP) RL = load impedance (Ω) RDSon = on-resistance power switch (Ω) Rs = series resistance output inductor (Ω) RESR = equivalent series resistance of SE capacitance (Ω) tW(min) = minimum pulse width (s) (80 ns typical) fosc = oscillator frequency (Hz) (320 kHz typical R7 = 39 kΩ) Remark: Equation 9 and Equation 10 are valid only when: Peak output current ≤ 4 A for TDA8932B (see Section 3.2). Peak output current ≤ 2 A for TDA8933(B). The output power at 10 % THD can be estimated as follows: (11)

3.1.1 TDA8932B output power estimation

Figure 10, Figure 11, Figure 12, and Figure 13 show the estimated output power for the TDA8932B at THD = 0.5 % and THD = 10 % as a function of the supply voltage for SE and BTL for different load impedances. BTL: Po(0.5%) RL a. THD+N = 0.5 % b. THD+N = 10 % Fig 10. SE output power as a function of supply voltage Fig 11. SE output power as a function of supply voltage VP (V) 10 40 3020 Po (W) RL = 4 Ω 6 Ω 8 Ω 001aad768 VP (V) 10 40 3020 Po (W) RL = 4 Ω 6 Ω 8 Ω 001aad769

AN10436_1 © NXP B.V. 2007. All rights reserved. Application note Rev. 01 — 12 December 2007 21 of 55 NXP Semiconductors AN10436 TDA8932B/33(B) Class-D audio amplifier Remark: Figure 10 and Figure 11 are calculated with RDSon =0 . 1 5Ω (at Tj =2 5 °C), Rs =0 . 0 5Ω, RESR =0 . 0 5Ω and IO(ocp) = 4.0 A (minimum). Remark: Figure 12 and Figure 13 are calculated with RDSon =0 . 1 5Ω (at Tj =2 5 °C), Rs =0 . 0 5Ω and IO(ocp) = 4.0 A (minimum). The horizontal parts in the figures indicate the region where current limiting becomes active, when a level of 4.0 A (minimum) is taken into account. It is recommended to avoid these regions because current limiting will cause unwanted distortion (see Section 3.2).

3.1.2 TDA8933(B) output power estimation

Figure 14, Figure 15, Figure 16, and Figure 17 show the estimated output power for the TDA8933(B) at THD = 0.5 % and THD = 10 % as a function of supply voltage for SE and BTL for different load impedances. a. THD+N = 0.5 % b. THD+N = 10 % Fig 12. BTL output power as a function of supply voltage Fig 13. BTL output power as a function of supply voltage VP (V) 10 40 3020 Po (W) RL = 8 Ω 6 Ω 4 Ω 001aad770 VP (V) 10 40 3020 Po (W) RL = 8 Ω 6 Ω 4 Ω 001aad771

AN10436_1 © NXP B.V. 2007. All rights reserved. Application note Rev. 01 — 12 December 2007 22 of 55 NXP Semiconductors AN10436 TDA8932B/33(B) Class-D audio amplifier Remark: Figure 14 and Figure 15 are calculated with RDSon =0 . 3 9Ω (at Tj =2 5 °C), Rs =0 . 0 5Ω, RESR =0 . 0 5Ω and IO(ocp) = 2.0 A (minimum). Remark: Figure 16 and Figure 17 are calculated with RDSon = 0.39 Ω (at Tj =2 5 °C), Rs =0 . 0 5Ω and IO(ocp) = 2.0 A (minimum). The horizontal parts in the figures indicate the region where current limiting becomes active when a level of 2.0 A (minimum) is taken into account. It is recommended to avoid these regions because current limiting will cause unwanted distortion (see Section 3.2). a. THD+N = 0.5 % b. THD+N = 10 % Fig 14. TDA8933(B): SE output power as a function of supply voltage Fig 15. TDA8933(B): SE output power as a function of supply voltage VP (V) 10 40 3020 Po (W) RL = 8 Ω 6 Ω 4 Ω 010aaa105 VP (V) 10 40 3020 Po (W) RL = 8 Ω 6 Ω 4 Ω 010aaa108 a. THD+N = 0.5 % b. THD+N = 10 % Fig 16. TDA8933(B): BTL output power as a function of supply voltage Fig 17. TDA8933(B): BTL output power as a function of supply voltage VP (V) 10 20 1814 1612 010aaa106 Po (W) RL = 6 Ω RL = 8 Ω VP (V) 10 20 1814 1612 010aaa107 Po (W) RL = 6 Ω RL = 8 Ω

3.2 Peak output cu rrent estimation

The most important benefit of cycle-by-cycle current limiting is the loss of audio holes without requiring a lot of head room towards the maximum peak output current of the TDA8932B/33(B). The peak output current is limited internally above:

4 A minimum for the TDA8932B.
2 A minimum for the TDA8933(B). During normal operation, the output current should not exceed the threshold level of IO(ocp) = 4 A minimum (TDA8932B) or IO(ocp) = 2 A minimum (TDA8933(B)) because it will cause distortion. The peak output current in either SE or BTL can be estimated through the use of these equations: (12) (13) Where: VP = supply voltage (V) (VDDP-VSSP) RL = load impedance (Ω) RDSon = on-resistance power switch (Ω) Rs = series resistance output inductor (Ω) RESR = equivalent series resistance of SE capacitance (Ω) Example TDA8932B (IO(ocp) = 4 A minimum): A 4 Ω speaker in the SE configuration can be used until a supply voltage of 33 V (approx.) without running into current limiting. A 4 Ω speaker in the BTL configuration can be used until a supply voltage of 17.5 V (approx.) without running into current limiting.

3.3 Control circuit

The recommended POWERUP circuit is a resistor divider between the supply voltage and CGND of the amplifier. Optionally a transistor can be used to enter SLEEP mode to reduce the power consumption in e.g., system idle mode. SE: IOp e a k()

0.5 V P⋅

BTL: IOp e a k() Vp

AN10436_1 © NXP B.V. 2007. All rights reserved. Application note Rev. 01 — 12 December 2007 24 of 55 NXP Semiconductors AN10436 TDA8932B/33(B) Class-D audio amplifier Figure 19 and Figure 20 show two alternative POWERUP circuits to control SLEEP mode from a 3.3 V or 5 V logic supply by means of a micro controller. Remark: Pull-up resistor should be ≥ 1k Ω. An external capacitor of 470 nF is recommended at the ENGAGE pin. The switch in series with the internal pull-up current source will be closed after the power stage is enabled and finally the external capacitor will “softly” engage the amplifier. Softly means that the gain is gradually increased depending on the capacitor value (dV/dt) attached to the ENGAGE pin avoiding pop noise due to DC offset. Fig 18. POWERUP circuit with optional sleep control OPTIONAL CIRCUIT FOR SLEEP CONTROL OPERATING SLEEP GND 47 kΩ 10 V .. 36 V 12 kΩ 010aaa006 VDDA POWERUP CGND Fig 19. Sleep control push-pull output Fig 20. Sleep control open-drain output PUSH-PULL OUTPUT OPERATING SLEEP

3.3 V or 5 V

10 kΩ 010aaa007 POWERUP CGND 10 kΩ OPEN-DRAIN OUTPUT OPERATING SLEEP 010aaa008 POWERUP CGND Fig 21. Engage circuit with optional mute control OPTIONAL CIRCUIT FOR MUTE CONTROL OPERATING SLEEP GND 2.8 V 10 kΩ 010aaa009 ENGAGE CGND 470 nF 100 kΩ 2 kΩ 50 μA

AN10436_1 © NXP B.V. 2007. All rights reserved. Application note Rev. 01 — 12 December 2007 25 of 55 NXP Semiconductors AN10436 TDA8932B/33(B) Class-D audio amplifier Remark: Do not use an external pull-up resistor at the ENGAGE input. Remark: For a quick enable of the MUTE mode it is recommended to short circuit the 10 k series resistor. The DIAG pin can be used to:

Read out the status of respectively OPERATING mode or FAULT mode.
Quickly disable the power stage in case of fault conditions at set level. The internal pull-up current is limited (approx. 50 μA) therefore the maximum resistive load (referenced to CGND) is 47 kΩ. DIAG open pin voltage is 2.8 V (typ). The absolute maximum sink current of the DIAG pin should be limited to 5 mA (internal pull-down resistance Rpd ≈1 kΩ when set low). Remark: The DIAG should be left floating when unused.

3.4 Analog audio input

The input signal is applied to the differential input of the TDA8932B/33(B) by means of AC-couple capacitors (see Figure 23). AC-couple capacitors are required for DC-blocking because the inputs (IN1P , IN1N, IN2P and IN2N) are biased at a voltage level of approximately +2.2 V (with respect to VSS) when operating from an asymmetrical supply. At symmetrical supply, the inputs are biased at a voltage level of approximately −2.2 V (with respect to HVPREF). The bias voltage is equal to the INREF voltage (pin 12). Remark: The input should be grounded close to the audio source (not at the amplifier side) to avoid a common ground with the power supply ground. Fig 22. DIAG circuit to disable power stage OPTIONAL CIRCUIT TO DISABLE POWER STAGE OPERATING FAULT GND 010aaa010 DIAG CGND 100 kΩ 1 kΩERROR 2.5 V 50 μA Fig 23. Input circuitry 010aaa011 Ri 100 kΩ 470 nF 470 nF 4.7 kΩ 4.7 kΩ 330 pF IN1P 2 IN1N 3

3.4.1 Input impedance

The input impedance of the TDA832B/33(B) device is equal to Ri =1 0 0kΩ. A low pass RC filter (R2, R3 and C6) is applied to reduce the sensitivity for out-of-band disturbances. The closed loop voltage gain at 1 kHz is equal to: (14) The cut-off frequency of the low-pass filter is equal to: (15) The AC couple capacitors form a high-pass filter, with the total input impedance (R2 + R3 + Ri). The cut-off frequency of the high-pass filter is equal to: (16) Example: Substituting R2, R3 = 4.7 kΩ and the AC-couple capacitors of C5, C7 = 470 nF in Equation 16 results in a cut-off frequency of 6 Hz, well below 20 Hz. Substituting R2, R3 = 4.7 kΩ and C6 = 330 pF in Equation 15 results in a cut-off frequency of 56 kHz, well above 20 kHz.

3.4.2 Gain reduction

The gain of the TDA8932B/33(B) is fixed internally at 30 dB for SE configuration (or 36 dB BTL configuration). The gain can be reduced by a resistive voltage divider at the input (see Figure 25 Fig 24. Input transfer function f−3dB(l) f−3dB(h) 0 dB 010aaa012 Gvc l() 20 Ri ⎛⎞log= f 3dB h()– R2 R3+() Ri⋅ f 3dB l()– 2π R2 R3 R i++() C5 C7⋅ ⎛⎞⋅⋅

AN10436_1 © NXP B.V. 2007. All rights reserved. Application note Rev. 01 — 12 December 2007 27 of 55 NXP Semiconductors AN10436 TDA8932B/33(B) Class-D audio amplifier The closed-loop voltage gain Gv(cl) when applying a resistive divider can be calculated through the use of this equation: (17) (18) Where: REQ = equivalent resistance (Ω) Rp = parallel resistor (Ω) Ri = 100 kΩ internal input resistance (Ω) R2, R3 = series resistors (Ω) Gv(cl) = closed-loop voltage gain 30 dB for SE and 36 dB for BTL (dB) Example: Substituting R2 = R3 = 4.7 kΩ and RP =2 2k Ω in Equation 17 and Equation 18 results in a gain of Gv(tot) =2 6 . 3d B . Remark: Applying a parallel resistance to reduce the gain will affect the cut-off frequencies of the input circuitry. It is required to compensate for this when requiring a 20 Hz to 20 kHz bandwidth.

3.4.3 Reference decoupling (HVPREF)

The HVPREF voltage (equal to ½(VDDA − VSSA)) is the reference for the output. The HVPREF is created internally by a resistor divider (2 × 90 kΩ) located between VDDA and VSSA. Proper decoupling with 47 μF and 100 nF is necessary to assure a good SVRR in the SE configuration. For the BTL configuration, there is a requirement only for a 100 nF capacitor since any ripple on the HVPREF is common for both output stages.

3.5 Speaker configuration and impedance

For a flat frequency response (second order Butterworth filter), it is necessary to change the low pass filter components L2 / L3 and C14 / C23 according to the speaker configuration and impedance. See Figure 35 for more information. Table 4 shows the required component values for speaker impedances of 4 Ω, 6 Ω or 8 Ω. Fig 25. Resistive voltage divider at the input 010aaa013 Ri 100 kΩ 470 nF 470 nF 4.7 kΩ 4.7 kΩ 330 pF RP 22 kΩ IN1P 2 IN1N 3 Gvt o t() Gvc l() 20 REQ ⎛⎞log+= REQ Rp Ri⋅

3.5.1 Filter inductor

Air coil, current independent inductance and no saturation effect.
Inductor with a magnetic core (ferrite or iron powder): – Magnetically unshielded version (pot core). – Magnetically shielded version (pot core or toroidal core). An air coil is used often in HiFi audio equipment, but is not very useful in mainstream audio because of the physical size. The major benefit of an unshielded inductor is cost. However, the magnetic stray field can cause either crosstalk issues or interference with other sensitive parts inside an audio or TV system (AM-receiver, picture interference, etc.). The benefit of the shielded magnetic inductor is that the magnetic field is captured inside the core, reducing the magnetic stray field. The most important parameters of an inductor are:
DC current rating to avoid magnetic saturation, causing an increase in audio distortion.
Linearity of the inductor, causing an increase in audio distortion (especially above 1k H z ) .
DC resistance having a direct impact on efficiency. The DC current capability needs to be high enough to avoid magnetic saturation. High peak currents are a result of saturation because the inductor tends to acts like a short. Therefore, for a proper inductor selection it is important to consider the maximum current delivered by the amplifier, and the temperature of the inductor (higher inductor temperature will decrease the saturation level). The maximum current occurs at voltage clipping and can be calculated through the use of either Equation 12 for SE configuration or Equation 13 for BTL configuration. Example: For a 2 × 15 W SE amplifier operating at 22 V the maximum output current is equal to to select an inductor that retains still at least 80 % of the nominal inductance at the maximum current of 2.1 A.

Table 4. Filter component values

3.5.2 Filter capacitor

25 % higher than the half the maximum supply voltage (VDDP − VSSP).

3.5.3 Zobel damping network

behavior (LE) of the speaker voice coil. Table 5. Recommended inductor types

AN10436_1 © NXP B.V. 2007. All rights reserved. least 15 % to 40 % lowering the risk of unwanted inductor saturation. since filter resonance can overstress the tweeter. A minimum zobel damping network CZ = 47 nF and RZ =8 2 Ω is strongly recommended. component values from Table 4, which are calculated based on fo =4 0k H z . with a 20 kHz unclipped sine wave. Figure 27 shows the sine wave power dissipation (20 kHz) as a function of supply voltage. Table 6. Damping resistors for different capacitor values

AN10436_1 © NXP B.V. 2007. All rights reserved. Application note Rev. 01 — 12 December 2007 31 of 55 NXP Semiconductors AN10436 TDA8932B/33(B) Class-D audio amplifier Remark: If the amplifier is driven at the resonance frequency (fo = 40 kHz) of the filter, the power dissipation in the resistor will rise causing the resistor to overheat.

3.5.4 Voltage clamp diodes

For a voice coil inductance LE greater than 10 times the filter inductance (LLC) the effectiveness of the zobel damping network is limited and the power dissipation in the resistor grows high, requiring bulky power resistors. In general, mostly subwoofer voice coils and HIFI multi-way speakers have such a high inductance. Remark: Applications for which the end user is able to disconnect the speaker and operate the amplifier without speaker, might also suffer from issues of robustness because of the inductor saturation. To avoid inductor saturation in case of high inductive load or no load, it is recommended to apply voltage clamp diodes at the output to the supply rails (see Figure 28). Relatively cheap general purpose diodes, like the 1N4001 (VR = 50 V) or the 1N4002 (VR = 100 V) can be used for this purpose. The reverse voltage of the diode should be at least 1.2 times the supply voltage and the repetitive peak current should be 1.2 times the maximum current of the amplifier.

3.6 Single ended capacitor

A single ended amplifier (Class-AB or Class-D) operating at an asymmetrical supply voltage will require an AC couple capacitor (SE capacitor) in series with the speaker. Especially for a low output power (< 25 W) it is a very cost effective solution compared to a BTL configuration. It should be noted, the SE capacitor has no major drawback on THD and audio performance in general. The SE capacitor forms a high-pass filter with the speaker impedance. Therefore, the frequency response will roll off with 20 dB per decade below the cut-off frequency f−3dB. The cut-off frequency is equal to: (19) Where: RL = load impedance (Ω). C15 (C24) = Single Ended capacitance (F) (see schematic Section 3.10). Fig 28. Voltage clamp diodes 010aaa428 VDD VSS PWM LLC Dcl2 Dcl1 CZ RZ LE RECLC voice coil equivalent circuit f 3dB–

3.6.1 Voltage rating

the SE capacitor can be almost equal to the supply voltage.

3.6.2 Lifetime

likely that an audio amplifier is driven continuously at rated output power over a lifetime. already of handling a 486 mA ripple current.

3.7 Bootstrap capacitor

STAB1 (pin 25) and the BOOT1 (pin 28) at the moment that the low side MOSFET is on. Table 7. Values SE capacitor

AN10436_1 © NXP B.V. 2007. All rights reserved. Application note Rev. 01 — 12 December 2007 33 of 55 NXP Semiconductors AN10436 TDA8932B/33(B) Class-D audio amplifier The voltage across the bootstrap capacitor is equal to VSTAB1 − VF (forward voltage drop internal diode). Therefore a voltage rating of 16 V is sufficient for the two bootstrap capacitors. Remark: Only the TDA8933T device requires a 1 MΩ across both bootstrap capacitors for discharging when the power stage becomes floating.

3.8 Output RC snubber network

An RC snubber network (see schematic Section 3.10) reduces the voltage ringing at the power stage output (pin 22 and pin 27) after a voltage transition. A proper implementation of this RC snubber will improve the EMC performance (see Figure 33 The worst case power dissipation in the snubber resistor R5 (R12) is equal to: (21) Where: C9 (C29) = snubber capacitor (F) VP = supply voltage (V) (VDDP − VSSP) fosc = oscillator frequency (Hz) Example: Substituting C9 = 470 pF, VP = 22 V and fosc = 320 kHz in Equation 21, results in a power dissipation of 73 mW, requiring an 0805 SMD. The voltage rating of the snubber capacitors (C9 and C26) should be 25 % higher than the maximum supply voltage in the application.

3.9 Layout recommendations

The PCB design of an SMA is probably the most difficult part of the design, because it might affect the audio performance, the EMC performance, the thermal performance, or even the functionality of the TDA8932B/33(B).

3.9.1 EMC considerations

A double-sided PCB with plated through holes and 35 μm copper is recommended, but a single layer is feasible as well. Figure 29 shows a proposed floor plan of the critical components that contribute to a good audio and EMC performance. The top side of this reference board is used to place the leaded components and the copper plane for thermal reasons. For more information on thermal considerations refer to Section 3.9.2. The bottom side of the double-layer PCB is used to place the SMD components, including the TDA8932B/33(B) and the majority of the signal tracks (see Figure 30 to Figure 33). P1 2 ⁄ C9 V P() 2 2f osc⋅⋅ ⋅ ⋅=

AN10436_1 © NXP B.V. 2007. All rights reserved. Application note Rev. 01 — 12 December 2007 34 of 55 NXP Semiconductors AN10436 TDA8932B/33(B) Class-D audio amplifier Some important notes for a proper layout are summarized below:

Input / output connectors at one side of the PCB (solid and "clean" star GND connection).
Supply buffer capacitor (C1) close to the IC.
Filter inductor (L2, L3) close to the IC.
Filter capacitor (C14, C23) close to the output connector, together with the SE capacitor (C15, C24).
Place the High Frequency (HF) supply decoupling capacitor close to the IC (see Figure 30
Place the HF decoupling capacitor STAB1/2 voltage close to the IC (see Figure 31).
Place the Bootstrap capacitor of the high-side driver close to the IC (see Figure 32).
Place the RC output snubber network close to the IC (see Figure 33).
Place the HF decoupling capacitor DREF voltage close to the IC (see Figure 33). Fig 29. Proposed floor plan of the components FILTER INDUCTOR SE CAPACITOR FILTER CAPACITOR Large signal supply and output L2 L3 C15 C14 C23 C24 Audio outputs Supply I/O CONNECTORS AT ONE SIDE SOLID “CLEAN” GND Small signal input TDA8932B/33(B) Audio inputs BUFFER CAPACITOR 010aaa056

AN10436_1 © NXP B.V. 2007. All rights reserved. Application note Rev. 01 — 12 December 2007 35 of 55 NXP Semiconductors AN10436 TDA8932B/33(B) Class-D audio amplifier Remark: SMD components are on the bottom layer, viewed from the top. Fig 30. HF decoupling supply C8, C25 Fig 31. HF decoupling STAB1/2 C17 C17 C10 C4 32 U1 1 C18R12 C31 C30 C3 1617 C25 010aaa060 C17 C10 C4 32 U1 1 C18R12 C31 C30 C3 1617 C25 010aaa061 Fig 32. Bootstrap capacitor high-side driver C10, C18 Fig 33. RC output snubber network C17 C10 C4 32 U1 1 C18R12 C31 C30 C3 1617 C25 010aaa057 C17 C10 C4 32 U1 1 C18R12 C31 C30 C3 1617 C25 010aaa058 Fig 34. HF decoupling DREF C30 C17 C10 C4 32 U1 1 C18R12 C31 C30 C3 C25 010aaa059

Minimizing the current loops that carry fast alternating currents will reduce magnetic radiation.
Minimizing the length / size of the PWM output track (fast alternating voltages) as much as possible, will prevent capacitive coupling to the environment. Otherwise this could lead to disturbances of high impedance inputs.

3.9.2 Thermal considerations

The thermal resistance is determined by the selected SMD package, the PCB layout implementation and the airflow inside the final enclosure of the amplifier. The TDA8932B/33(B) is available in two different thermally enhanced SMD packages:

TDA8932BT/33T in SO32 (SOT287-1) package for reflow and wave solder process.
TDA8932BTW/33BTW in an HTSSOP32 (SOT549-1) package for reflow solder process only. Thermal resistance SO32 package The SO32 package has special thermal corner leads, pins 1, 16, 17 and 32, increasing the power capability (reducing the overall Rth(j-a)) when soldered to a thermal copper plane at VSSA level. The SO package is very suitable for single layer PCB designs or PCB designs with limited space for a thermal plane. Due to the package size the SO32 is able to radiate a significant part of the heat directly into the air (thermal resistance is less depending on the heat transfer via the PCB). The thermal resistance of a S032 package will range from about 35 K/W to 50 K/W when mounted on a single or two layer PCB (free air natural convection). Mounting a heat sink can further decrease the thermal resistance with another 15 % to 25 %. The thermal resistance measured at the compact reference PCB (55 mm × 45 mm) with S032 package can be found in Section 5.3 Thermal resistance HTSSOP32 package The HTSSOP32 package has an exposed die-pad that only reduces the overall Rth(j-a) significantly when soldered to a thermal copper plane at VSSA level (thermal resistance is strongly depending on the size and the number of copper planes). This makes the HTSSOP package very suitable for multilayer PCB designs with sufficient space for two or three thermal copper planes. When applying three thermal copper planes it is even possible to reach a continuous time output power of 2 × 25 W without a heat sink. The thermal resistance of a HTSSOP32 package will range from about 25 K/W to 55 K/W when mounted on a multilayer PCB without heat sink (free air natural convection). Increasing the area of the thermal copper planes, the number of planes, or the copper thickness will further reduce the thermal resistance R th(j-a) of both packages.

AN10436_1 © NXP B.V. 2007. All rights reserved. Application note Rev. 01 — 12 December 2007 37 of 55 NXP Semiconductors AN10436 TDA8932B/33(B) Class-D audio amplifier Airflow inside enclosure At a set level the airflow inside the enclosure will be limited compared to the situation in free air natural convection. The airflow and other heat sources close to the amplifier will influence the temperature significantly. Therefore it is always recommended (and the responsibility of the set maker) to check the temperature behavior in the final environment of the amplifier. Remark: The TDA8932B/33(B) amplifier with the thermal foldback feature will never cause audio interruption (audio holes) due to the limited airflow and the limited presence of other heat sources close to the amplifier. Therefore this thermal foldback feature will improve the reliable of the amplifier application under extreme temperature conditions because the device itself will always stay within the Safe Operating Area (SOA). Thermal resistance Measured thermal resistance of both the SO32 and the HTSSOP32 reference design can be found in Section 5.3. Thermal via’s Thermal via’s should be applied for an optimum heat flow to other layers of the PCB to reduce the Rth(j−a). The thermal via’s should be placed close to corner leads and beyond the package for the SO32 package (see PCB layout Section 3.12). Remark: Do not use via’s with web construction, as they will have a high thermal resistance. Thermal calculations To estimate the maximum junction temperature, Equation 22 can be used: (22) Where: Tamb = ambient temperature (°C) P = power dissipation in U1 (W) (see Figure 50 or Figure 61, P versus PO) Rth(j−a) = thermal resistance junction ambient (K/W) Example: Estimation of the junction temperature at Prated (for FTC requirements). Power dissipation P = 2.5 W (see Figure 47) at Prated =2 × 15 W in 4 Ω. The estimated junction temperature at Tamb =2 5 °C and Rth(j−a) = 44 K/W, will be Tj(max) =1 3 5°C (approx.) (Equation 22), staying below the TF threshold level of 140 °C. At a Prated = 2 × 25 W in 4 Ω the TF becomes active. The TF will gradually reduce the gain and therefore reduce the long-term output power. See Section 5.3 for the output power as a function of time, when the TF becomes active. The major benefit of the TF feature is that the amplifier is not switched off when it reaches the maximum junction temperature. Remark: Lifetime is guaranteed because the TDA8932B/33(B) stays within the safe operating area due to the TF feature. Tjm a x() Tamb Rth j a–() P⋅+≈

AN10436_1 © NXP B.V. 2007. All rights reserved. Application note Rev. 01 — 12 December 2007 38 of 55 NXP Semiconductors AN10436 TDA8932B/33(B) Class-D audio amplifier Remark: For thermal reliability and/or quality requirements on set level, an average music power of ¼ Prated is assumed. This assumption can be made because audio amplifiers are not driven continuously at the rated output power. Taking this into account, shows the major benefit of Class-D as compared to Class-AB. Class-D dissipates less at ¼ Prated and that makes it possible to comply easily with the thermal reliability and/or quality regulations with a cheap SO32 or HTSSOP32 package without a heat sink. 3.10 Schematic - revision 3.00 (1) The TDA8933T device requires a 1 M Ω in parallel with the bootstrap capacitor Cbo. Fig 35. Schematic - version 3.00 VSSD/HW IN1P IN1N DIAG ENGAGE POWERUP CGND VDDA VSSA OSCREF HVPREF INREF IN2N IN2P TEST VSSD/HW VSSD/HW OSCIO HVP1 VDDP1 BOOT1 OUT1 VSSP1 STAB1 STAB2 VSSP2 OUT2 BOOT2 HVP2 VDDP2 VSSD/HW IN1 470 nF 1716 C11 470 nF R10 39 kΩ C16 100nF 100 nF VP C10 15 nF(1) 470 pF 100 nF 10 Ω C17 100 nF 22 μHC18 15 nF(1) R12 10 Ω C26 470 pF VP C25 100 nF VP = 10V ...35V GND VP VPA 220 μF/35 V 220 μF/35 V 10 Ω TDA8932BT /33T 010aaa062 HVP1 HVP2 C30 100 nF C31 100 nF 4.7 kΩ 4.7 kΩ 330 pF 12 kΩ SLEEP ON 47 kΩ VPA C20 47 μF C21 100 nF C22 100 nF C29 470 nF IN2 C27 470 nF R15 4.7 kΩ R14 4.7 kΩ C28 330 pF 10 kΩ MUTE OPERATING VPA R13 22 Ω C19 100 nF 2C23 680 nF C24 1000 μF , 25 V HVP2 + OUT2 4 Ω 22 Ω C12 100 nF 2C14 680 nF C15 1000 μF , 25 V HVP1 − OUT1 4 Ω 22 μH 100 nF BEAD

3.12 PCB layout - Revision 2

copper and FR4 base material. Table 8. Bill of materials

AN10436_1 © NXP B.V. 2007. All rights reserved. Application note Rev. 01 — 12 December 2007 40 of 55 NXP Semiconductors AN10436 TDA8932B/33(B) Class-D audio amplifier Fig 36. Top view, copper and silk screen top Fig 37. Top view, copper and silk screen bottom 010aaa078 010aaa110

4.1 Supply filtering

A CLC phi filter (C1, L1 and C2) is used to keep the High Frequency (HF) currents locally around the amplifier (see Figure 38). Two 100 nF SMD capacitors (C8 and C25) and an electrolytic buffer capacitor (C1) should be placed close to the amplifier to minimize the area of the HF current loops to avoid emission. The ferrite bead (L1) will avoid the flow of HF currents in (mostly) large supply voltage loops. The analog voltage (VDDA) of the TDA8932B/33(B) requires an RC filter of 10 Ω (R1) and 100 nF (C3) to avoid the HF noise entering the analog controller part of the device.

4.1.1 Lifetime electrolytic capacitor

The ambient temperature and the ripple current have the greatest effect on the lifetime of the aluminium electrolytic capacitors. The output power of an amplifier is assumed often to be ¼ of the total rated output power. At a power rating of 2 × 3.75 W (¼ × 15 W) the lifetime is not an issue when general-purpose electrolytic capacitors (with a value of at least 220 μF) are used.

4.2 Supply GND connection

The best practice to avoid any common ground path with the power supply is to leave the supply floating. The power supply should be attached to GND at the amplifier side. The differential input should be grounded at the sound processor and not at the amplifier side. Fig 38. Supply filtering POWER SUPPL Y FERRITE BEAD TDA8932B/33(B) 010aaa063 LP FILTER LP FILTER C3R1 10 ohm C1C2 C25 OUT 1 OUT 2 C15 C24 VDDA pin 8 HF CURRENTS

4.3 Low frequency supply pumping effect

A Single Ended (SE) Class-D amplifier will deliver energy back to the supply line (VP) during the negative part of the audio signal. Because most power supplies are not capable of sinking energy, the supply voltage will increase especially when driving the amplifier at low audio frequencies. This phenomenon is often called the pumping effect. The voltage increase caused by the pumping effect depends on:

The speaker impedance.
The supply voltage.
The audio signal frequency.
The capacitance value of the supply line.
The source/sink current of other channels (including the quiescent current of the amplifier).
The current drawn from other circuits attached to the same supply line. This voltage increase might trigger the OVP of the audio amplifier and/or cause incorrect control behavior of the regulated power supply. The most effective way to overcome the pumping effect in a stereo SE application is to apply one of the input signals to the negative input to invert the phase of that particular output (see Figure 40). Fig 39. Supply GND connection GND GND POWER SUPPL Y SOUND PROCESSOR DAC OUT GND FERRITE BEAD 100nF AMPLIFIER TDA8932B/33(B) LP FILTER SPEAKER DIFFERENTIAL INPUT SOLID GROUND PLANESTAR GROUND AMPLIFIER SIDE LEAVE FLOATING FROM GROUND (OR USE RC) 010aaa079 GND

AN10436_1 © NXP B.V. 2007. All rights reserved. Application note Rev. 01 — 12 December 2007 43 of 55 NXP Semiconductors AN10436 TDA8932B/33(B) Class-D audio amplifier With this method, OUT1 and OUT2 are out of phase to minimize the pumping effect. The inversion of one of the outputs will also halve the peak current drawn from the power supply at a low audio frequency. Remark: Do not forget to change the polarity of the speaker connection of channel 2 to get the original phase of the signal from the speaker.

4.4 Unregulated or weak power supply

The voltage ripple of an unregulated power supply can be quite significant, due to:

The output impedance (load regulation).
A variation on the AC mains (line regulation).
A cross regulation in a multiple output SMPS. Therefore, when operating from an asymmetrical supply, this voltage ripple will cause asymmetrical clipping. This might trigger also the UBP (UnBalance Protection) when the voltage ripple exceeds either −20 % or +33 % of the nominal supply voltage (see also Section 2.6.6). Therefore, any unregulated power supply (an auxiliary voltage from either an SMPS or a 50 Hz / 60 Hz transformer) might need some attention to minimize the load, the line and the cross regulation. The voltage dip during a transient from no load condition to full load condition should be considered. The average supply current in full load for a stereo amplifier can be estimated as follows: (23) (24) Where: Po = RMS output power per channel (W) ηpo = output power efficiency, audio amplifier Fig 40. Inverting the phase of one output and input (of channel 2) IN1P 2 IN1N TDA8932B/33(B) IN2N 14 IN2P OUT1 OUT2 C15 LP FILTER 010aaa064 C24 LP FILTER SE: IP(avg) 2P o⋅ BTL: IP(avg) Po

Performance characterization TDA8932B

5.1 Audio characterization SE

5.1.1 Performance figures SE

board (55 mm × 45 mm) configured in SE configuration. Table 9. Performance figures

5.1.2 Performance graphs SE

Table 9. Performance figures …continued

AN10436_1 © NXP B.V. 2007. All rights reserved. Application note Rev. 01 — 12 December 2007 46 of 55 NXP Semiconductors AN10436 TDA8932B/33(B) Class-D audio amplifier VP = 22 V, 2 × 4 Ω SE (1) = 10 W (2) = 1 W VP = 30 V, 2 × 8 Ω SE (1) = 10 W (2) = 1 W Fig 43. THD+N as a function of frequency Fig 44. THD+N as a function of frequency 001aad774 10−1 10−2 102 THD+N (%) 10−3 fi (Hz) 10 10 5104102 103 (1) (2) 001aad775 10−1 10−2 102 THD+N (%) 10−3 fi (Hz) 10 10 5104102 103 (1) (2) Vi = 100 mVRMS, Ri = 0 Ω, CSE = 1000 μF (1) 2 × 4 Ω SE @ VP = 22 V (2) 2 × 8 Ω SE @ VP = 30 V Vripple = 500 mVRMS w.r.t. GND, shorted input Ri = 0 Ω (1) = 2 × 4 Ω SE @ VP = 22 V (2) = 2 × 8 Ω SE @ VP = 30 V Fig 45. Gain as a function of frequency Fig 46. SVRR as a function of frequency 001aad776 G v (dB) fi (Hz) 10 10 5104102 103 (2) (1) 001aad777 −60 −40 −80 −20 SVRR (dB) −100 fi (Hz) 10 10 5104102 103 (2) (1)

AN10436_1 © NXP B.V. 2007. All rights reserved. Application note Rev. 01 — 12 December 2007 47 of 55 NXP Semiconductors AN10436 TDA8932B/33(B) Class-D audio amplifier Ri = 0 Ω (1) 2 × 4 Ω SE @ VP = 22 V (2) 2 × 8 Ω SE @ VP = 30 V PO = 1 W, CHVPREF = 47 μF (1) = 2 × 4 Ω SE @ VP = 22 V (2) = 2 × 8 Ω SE @ VP = 30 V Fig 47. S/N ratio as a function of output power Fig 48. Channel separation as a function of frequency 001aad778 Po (W/channel) 10−2 1021010−1 1 120 S/N (dB) (2) (1) 001aad779 −60 −40 −80 −20 αcs (dB) −100 fi (Hz) 10 10 5104102 103 (1) (2) fi = 1 kHz (1) 2 × 4 Ω SE @ VP = 22 V (2) 2 × 8 Ω SE @ VP = 30 V Remark: ηpo = (2 · Po) / (2 · Po + P) fi = 1 kHz (1) = 2 × 4 Ω SE @ VP = 22 V (2) = 2 × 8 Ω SE @ VP = 30 V Remark: Power dissipation in junction only. Fig 49. Efficiency as a function of output power Fig 50. Power dissipation as a function of output power Po (W/channel) 02 0 1551 0 001aad780 100 ηpo (%) (2) (1) 001aad781 1.0 2.0 3.0 P (W) P o (W/channel) 10−2 1021010−1 1 (2) (1)

5.2 Audio characterization BTL

5.2.1 Performance figures BTL

board (55 mm × 45 mm) configured in BTL configuration. Table 10. Performance figures

5.2.2 Performance graphs BTL

Table 10. Performance figures …continued

AN10436_1 © NXP B.V. 2007. All rights reserved. Application note Rev. 01 — 12 December 2007 50 of 55 NXP Semiconductors AN10436 TDA8932B/33(B) Class-D audio amplifier VP = 22 V, 8 Ω BTL (1) 10 W (2) 1 W VP = 12 V, 4 Ω BTL (1) 10 W (2) 1 W Fig 54. THD+N as a function of frequency Fig 55. THD+N as a function of frequency 001aae114 10−1 10−2 102 THD+N (%) 10−3 fi (Hz) 10 10 5104102 103 (1) (2) 001aae115 10−1 10−2 102 THD+N (%) 10−3 fi (Hz) 10 10 5104102 103 (2) (1) Vi = 100 mVRMS, Ri = 0 Ω (1) 4 Ω BTL @ VP = 12 V (2) 8 Ω BTL @ VP = 22 V Vripple = 500 mVRMS in relation to GND, shorted input, Ri = 0 Ω (1) 4 Ω BTL @ VP = 12 V (2) 8 Ω BTL @ VP = 22 V Fig 56. Gain as a function of frequency Fig 57. SVRR as a function of frequency 001aae116 G v (dB) fi (Hz) 10 10 5104102 103 (1)(2) 001aae117 −60 −40 −80 −20 SVRR (dB) −100 fi (Hz) 10 10 5104102 103 (1) (2)

AN10436_1 © NXP B.V. 2007. All rights reserved. Application note Rev. 01 — 12 December 2007 51 of 55 NXP Semiconductors AN10436 TDA8932B/33(B) Class-D audio amplifier Ri = 0 Ω (1) 4 Ω BTL @ VP = 12 V (2) 8 Ω BTL @ VP = 22 V fi = 1 kHz (1) 4 Ω BTL @ THD+N = 10 % (2) 4 Ω BTL @ THD+N = 0.5 % (3) 8 Ω BTL @ THD+N = 10 % (4) 8 Ω BTL @ THD+N = 0.5 % Fig 58. S/N ratio as a function of output power Fig 59. Maximum output power as a function of supply voltage 001aae118 Po (W) 10−2 1021010−1 1 120 S/N (dB) (2) (1) 001aaf893 VP (V) 10 34 261814 30 22 Po (W) (2) (1) (3) (4) fi = 1 kHz (1) 4 Ω BTL @ VP = 12 V (2) 8 Ω BTL @ VP = 22 V Remark: ηpo = (Po) / (Po + P) fi = 1 kHz (1) 4 Ω BTL @ VP =1 2 V (2) 8 Ω BTL @ VP =2 2 V Remark: Power dissipation in junction only Fig 60. Efficiency as a function of output power Fig 61. Power dissipation as a function of output power 001aae119 Po (W) 03 0 2010 100 ηpo (%) (2) (1) 001aae120 1.0 2.0 3.0 P (W) P o (W) 10−2 1021010−1 1 (2) (1)

5.3 Thermal characterization

The measured thermal resistance of the reference design with an SO32 package, a double-sided FR4 PCB (55 mm × 45 mm) and 35 μm copper, is equal to 44 K/W (free air and natural convection). When the junction temperature reaches the threshold level of the Thermal Foldback (140 °C to 150 °C), it starts to reduce gradually the output power so the maximum temperature will stay always within the Safe Operating Area. Figure 62 and Figure 63 show the TDA8932BT (S032) output power as a function of time at different supply voltages. The total output power of the device is 2 × Po, because the measurement is performed at SE configuration. Figure 64 and Figure 65 show the TDA8932BT output power as a function of time at different supply voltages. Total output power of the device is 1 × Po because the measurement is performed at BTL configuration. RL = 2 × 4 Ω SE; fi = 1 kHz; 2 layer SO32 application board (55 mm × 45 mm) without heat sink. (1) VP = 22 V (2) VP = 26 V (3) VP = 29 V RL = 2 × 8 Ω SE; fi = 1 kHz; 2 layer SO32 application board (55 mm × 45 mm) without heat sink. (1) VP = 30 V (2) VP = 34 V Fig 62. SE output power as a function of time Fig 63. SE output power as a function of time t (s) 0 600 480240 360120 001aaf887 Po (W/channel) (2) (1) (3) t (s) 0 600 480240 360120 001aaf888 Po (W/channel) (2) (1)

5.4 EMI characterization (FCC)

The TDA8932B/33(B) reference design can comply easily with the FCC radiated emissions standards with 1 m of cable attached to all the I/Os. The spectrum analyzer is set at MAX hold and the output power is 2 × 1/8 Prated. RL = 4 Ω; fi = 1 kHz; 2 layer SO32 application board (55 mm × 45 mm) without heat sink. (1) VP = 12 V (2) VP = 13.5 V (3) VP = 15 V RL = 8 Ω; fi = 1 kHz; 2 layer SO32 application board (55 mm × 45 mm) without heat sink. (1) VP = 22 V (2) VP = 26 V (3) VP = 29 V Fig 64. BTL output power as a function of time Fig 65. BTL output power as a function of time t (s) 0 600 480240 360120 001aaf896 Po (W) (2) (1) (3) t (s) 0 600 480240 360120 001aaf899 Po (W) (2) (1) (3) Fig 66. 150 kHz to 30 MHz Fig 67. 30 MHz to 300 MHz REF 80.0 dBμW ATTEN 10 dB START 150 kHz RES BW 10 kHz STOP 30.00 MHz SWP 750 msec DISPLAY LINE 50.0 dBμV 010aaa102 DL 50.0 dBμV VBW 10 kHz BATTERY 010aaa101REF 50.0 dBμW ATTEN 10 dB START 30 MHz RES BW 100 kHz STOP 300.0 MHz SWP 200 msec BATTERY DISPLAY LINE 50.0 dBμV DL 50.0 dBμV VBW 30 kHz

6.1 Definitions

Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information.

6.2 Disclaimers

General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

6.3 Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.

NXP Semiconductors AN10436 TDA8932B/33(B) Class-D audio amplifier © NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 12 December 2007 Document identifier: AN10436_1 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 7. Contents

1.2 Fixed frequency pulse width modulated Class-D

1.3.1 Asymmetrical supply st ereo SE configuration . 5 1.3.2 Symmetrical supply stereo SE configuration . . 6 1.3.3 Asymmetrical supply mono BTL configuration . 7 1.3.4 Symmetrical supply mono BTL configuration . . 8

3 Design 2 x 5 W - 25 W audio amplifier

5 Performance characterization TDA8932B. . . 44

Product Information

AN10436 specifications and overview.

Summary

TDA8932B/33(B) Class-D audio amplifier Rev. 01-12 December 2007

Description

TDA8932B/33(B) Class-D audio amplifier Rev. 01-12 December 2007

Source title AN10436 Datasheet(PDF) - NXP Semiconductors

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