AN014

AN014 AIC | Alldatasheet

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Technical content

Implement 3.3Vdual using AIC1730 for DRAM Supply on IAPC Motherboard Introduction Today, PCs need to remain constantly connected to the outside world, but at the same time consume minimum power. Even looking “idle”, it is still possible to receive a message from the Internet, an incoming fax, or a phone call. The PC must wake up from “sleep” mode to “on” mode automatically, that is, to be an Instantly Available PC (IAPC) The “Advanced Configuration and Power Interface”, or ACPI, is a system for controlling the use of power in a computer. It enables the computer manufacturer and the computer user to determine the computer power usage dynamically. As the ACPI specified, there are 3 ACPI states that are of primary concerns to the system designer, designated S0, S3 and S5 . S0 is the full-power state, the state of the computer when it is being actively used. The other two states are sleep states, reflecting differing levels of power-down. S3 and S5 S3 is a state in which the processor is powere d down, but its last state is reserved in IC memory, which is kept on . Since access speed of memory is fast, the computer can quickly come back up to full operation. However, this state continues to draw moderate power, due to the memory, which has been ke pt alive and also called STR (Suspend to RAM). S5 is a state in which memory is off, and the last state of the processor has been written to the hard disk. Since the access time of disk is slow, the computer takes longer time to come back to full operation. However, since memory is off, this state draws minimal power. Operation Description The 3.3V SDRAM output is intended to provide power to SDRAM memory. Most system will use this power. The 3.3V SDRAM is generated by either one of the two sources, whic h are +3.3V main and linear regulator from +5V standby, as shown in Figure 1. When main power is present, the MOSFET Q 1 is turned on as a switch. That makes input and output connected. When the main power is absent, the linear regulator is activated and ge nerating a regulated 3 3V from +5V standby . The MOSFET Q1 must be connected as shown in the figure to avoid back-feed.

Note:Remove Q3 and R5 and Connect Pin 1 and Pin 2 of U2A together, if 3.3V is not Supplied at Soft-off. asserted, the external switch is on and LDO is off. order to prevent unacceptable voltage dropout. Table 1. The 3.3VDual Output Truth Table

Application Information

The AIC1730 implemented here is a 150 mA LDO, which is originally used in some portable devices such as cellphone, PDA and pager etc … due to its shutdown function, ultra -low dropout, low noise and tiny little package. Now it’s implemented as an LDO, which can be shut down by the control logic in the application of motherboard for SDRAM power distribution. Control logic The control logic is designed not only to select the power route but also to minimize the output capacitance required to hold up the voltage dropout during transitions among different sleeping states. Thus, the 3.3V SDRAM output has guaranteed a 700uS delay time to cause the overlap times , the time during a state transition duration which both VCC3 and 5VSBY are connected to the output. This overlap time ensure s that a power source is always connected to the output, so that there will be no dig in the output voltage during state transitions. ATX power timing Further, according to ATX specification revision 2.03, there are still various regulation s specified to regulate the quality and electrical characteristics of the ATX SPS, and the time of PS_ON , PWR_OK, and germane voltage rails shoul d be as following figure 3 with the description in table 2: AC POWER IN PS_ON DC OUTPUT PWR_OK 95% 10% T1 T4 T5T3 Fig.3 ATX Power Timing Time Description Typical value T1 Power on time ＜500ms T2 Rise time 0.1ms＜T2＜20ms T3 Power OK delay 100ms＜T3＜500ms T4 AC loss to PWR_OK hold-up time T4＞16 ms T5 Power-down warning T5＞1ms Table 2. The ATX Rev.2.03 Timing Description Table beyond the under voltage threshold (usually 95%).

S3# PS-ON VCC3 LDO output 3.3V SDRAM S5# t4 t5 Fig.4 Timing Diagram for S5 to S0 to S3 PWRGOOD S3# PS-ON VCC3 LDO output 3.3V SDRAM S5# t1 t2 t3 Fig.5 Timing diagram for S3 to S0 to S5 Transitions Figure 4 shows the system in soft -off (S5) mode. 3.3V SDRAM output line should be low since VCC3 and LDO output are absent. Once the system activated at t1, the PS_ON asserted and 3.3V SDRAM output is eventually presen t, that is, the system is in full running mode (S0). The system didn’t transit to S3 (Suspend To DRAM) until t2 . The PWRGOOD line failed after a while. And according to the regulation, VCC3 is still valid for at least 1ms. Thus, it caused an overlap time t hat the 3.3V SDRAM connects to both power sources (i.e. t4 to t5). The figure 5 shows the power supply becomes activated again with the waking up of the system from the S3 state to S0. Instead of LDO output, the 3.3V SDRAM now sources supply from VCC3 line , and the system transits into soft -off (S5) again after time t3. Now since SDRAM is no longer needed to maintain the content inside, the transition issue is not so important here. Further, the transition issue from S5 to S0 in figure 4 is no need to be ca red as well. Transient characteristics An active load is used, setting the load current of 50mA and 150mA respectively at 3.3V. The transient characteristics are shown below: CH1: S3#、2V/100ms CH2: 3.3V SDRAM、500mV/100ms

Fig.6 S3 to S0 Fig.7 S0 to S3 Figure 6 shows the output current is 50mA . A nd 3.3V SDRAM switched from AIC1730 LDO output to VCC3 at the time when S3# line was de -asserted. There is no dig coming with the output line. Figure 7 also shows th e output current is 50mA. And an overlap of both two input sources is caused by a 700us RC delay (R3、R4). The following 2 figures show the transient when 150mA output current consumption on 3.3V SDRAM line, from both S3 to S0 and S0 to S3. Fig.8 S3 to S0 Fig.9 S0 to S3

Since the Q1 MOSFET serves as a switch during active state (S0), it should be sized based on load regulation requirement and the power consumption. A MOSFET with a low R DSON and an acceptable package for power dissipation is recommended. The maximu m RDSON can be expressed as the following equation: OUTMAX OUTMININMIN )MAX(DSON I VVR −= And it would be up to scratch for both Q2 and Q3 . They are the general-purpose bipolar transistors, for instance, 2N2222 for Q2 and 2N2907 for Q3. Output Capacitor Selection For t his application, there is a designed delay function to cause the overlap time between two sources when one source is turned on and the other turned off. The output capacitor here is not for holding up the supply, but for noise filtering and response to transient loading. A widely used Electrolytic capacitor in 220µF or larger is recommended. Conclusion As discussed previously , Instantly Available PCs require unique Power Management devices to provide regulated voltage sources and intelligent switches between power sources. This solution allows motherboard makers to distribute the power line to supply the SDRAM at every power saving state, which is also reducing the total BOM cost as the components are so easy to get in market. Remove Q3 and R5 and c onnect pin 1 and Pin 2 of U2A, if 3.3V is not supplied at Soft-off. Keep the output capacitor larger than 220uF to ensure the stability of the system and as close as possible to output line. It is highly recommended. Please note that 74HCT00 would be recommended for the logical control due to fan-out issue. Got any questions? Call AIC for applications assistance. References I. AIC1730 data sheet low noise 150mA LDO from Analog Integrated Corp. II. MT18LSDT1672 SDRAM module data sheet from Micron Technology, Inc. III. IAPC system power delivery requirements and recommendations Rev1.0 from Intel Corp.