AN012

AN012 AIC | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 7

Technical content

October, 2001 A Handy Method to Obtain Satisfactory Response of Buck Converter Introduction The focus of this application note is to help users to select a good set of components of the compensation section of the Buck converter. Traditionally, engineers first concern about the power circuit for a circuit design. After meeting the power requirement, what follows is control loop design. The first priority of control design is the stability. And after that, the choice of components can substantially effect the transient response. Here shows a simple method to obtain a satisfactory transient response with an acceptable steady state error. Analysis: Fig.1 shows the unity feedback system for Buck converter. We first identify transfer functions for each of the corresponding block. As to the modeling of the low -frequency behavior of power switches in square -wave power converters, please refer to appendix [1]. The circuit of Buck converter is shown in Fig.2 and the model of its power switches is shown in Fig.3 . Please note that the circuit in Fig.3 is linear. Fig.4 shows the circuit for small signal analysis. Gc(s) PWM Gp(s) dVOUT(s) dVOUT(s)=0 _ dVc(s) dD(s) Fig.1 The Unity Feedback Control Loop for Buck Converter VOUT VIN Fig. 2 Buck Converter

October, 2001 VOUT VIN D *D* IL Fig.3 21 D)R(1DRR −+= R dVOUT(s) VIN * rL rc L S RL Fig. 4 Small Signal Circuit The transfer function of output with respect to duty ratio is: )rR(R)]srRrrRrRrC(RR[LC)srCL(R R)sr(CRV sc R 1)r(RsL sc R VdD(s) (s)dV LLCLLCCLLL CL LCL IN CL L CL IN OUT ++++++++++ +×= +++ …… ..(1) where: VIN: input voltage VOUT: output voltage R: the equivalent resistance of power switches. L: the inductor C: the output capacitor rL: the DC resistance of inductor. rC: the ESR of output capacitor. RL: the loading of Buck converter. when RL is >> rL , rC and R Equation 1 can be simplified as below: LCsL rrR CRs Crs L rV CL L CCIN 1]1[ 1)]srrC(RR L[LCs 1CsrVdD(s) (s)dV CL L C IN OUT +++++ ××= +++++ +×=

October, 2001 where the zero ZP is at CrC the LCn 1=w Fig. 5 The Simulation of Typical Frequency REsponse of Buck Converter Fig. 5 represent s the simulation of t ypical frequency response of Buck converter. Note that the effect of complex conjugate poles of LC will make the gain curve at -40dB/decade and phase curve towards -180°. And after the region around ω n, we will meet the zero, which is donated by the E.S.R of output capacitor. The gain curve becomes -20dB/decade and the phase is towards -90°. As to the PWM (Pulse Width Modulation), its transfer function is MC V (s)dV where VM is the amplitude of ramp in PWM. About the compensation network, we choose the type that is shown in Fig. 6. According to its frequency response in Fig. 7 , the network has high gain at low frequency, which helps to reduce the steady state error. The attenuation of gain at high frequency helps to weaken the noise disturbance. R2 C2 _ dVc(s) dVout(s) Fig. 6 The Compensation Network Fig. 7 The Simulation of Typical Frequency Response of the Compensation Circuit Its transfer function is: b×++ += )//C(CsR)[1C(CsR sCR1 (s)dV (s)dV 322321 OUT C …… Where: the first pole P 0 is at zero frequency (ω =0). one zero Z 1 is at CR the 2nd pole P 2 is at 32322 )//C(CR CR≈ ( when C3<<C2 ) gain at low frequency: )( 1)(

321 CCsRsGC +=

gain at middle frequency:

October, 2001 )()( 321 CCR CRsGC += ….. (Constant) gain at high frequency: 1)( CsRsGC = b is the gain of the feedback resistor divider. Note that due to the origin pole, the phase at low frequency is -90° and the gain curve is at -20dB/ decade. When th e frequency approaches to zero, the phase increases toward 0° with a flat gain curve. When it moves toward the second pole, the frequency will be towards -90° and the gain curve goes back to -20dB/ decade again. Control Strategy The loop transfer function of Fig.1 is shown as below: ]LC 1)sL rrR CR 1(L[s )Cr 1(sr VV )//C(CR 1)(s//C(C)RC(CsR )CR 1(sCR (s)GPWM(s)GT(s) LC L C C IN M 32s 322321 PC +++++ ×××× ××= .………(5) After meeting the power circuit requirement, we start to design the control loop. Therefore the LC poles and output capacitor zero are already allocated. What we can do is to distribute the loc ation of pole and zero of compensation network to achieve the desired response demand. To obtain high gain at low frequency, the origin pole is already set. Then here comes the strategy for the location of the zero and the second pole. For the reason o f stability, the zero of compensation network must be set lower than the zero of Buck converter. Without compensation zero , the zero of Buck converter would face three poles before it. The phase of the loop transfer function falls down toward -270° and pas ses through -180° between the poles of LC and the zero of Buck converter. This situation can lead to an unstable condition . To avoid that, the compensation circuit zero is advised to be lower than that of Buck converter. However the location of the compensation zero will affect the phase margin around the crossover frequency. To improve the phase margin of the loop transfer function and keep high gain at low frequency, the compensation zero is suggested between ω n and ×1.0 ω n. (ω n= LC 1 ). The second pole of compensation network is suggested far from the zero of Buck converter. In this way, we can obtain the – 20dB/decade slope around the crossover frequency. According to the sampling theorem, the second pole of compensat ion network is suggested to be under one fifth of switching frequency of Buck converter ( Switchingf5 1 ) to reduce the noise at high frequency. Gc(s) PWM Gp(s) dVOUT(s) dVOUT(s)=0 _ dVc(s) dD(s) Fig. 8 The Unity Feedback Control Loop for Buck Converter

October, 2001 Design Example Design example: VIN=8V,VOUT=5V, the operation point of output current is 1A L=27µH, rL=38.5mΩ C=1000µH, rC=52mΩ MOSFET=IR3103, RDS-ON=14 mΩ RL=5Ω VM=1.3V Design Procedure: 1. Construct the model of Buck converter and obtain the transfer function. 14m dVOUT(s) VIN * 38.5m27µH S 552m 1000µF Fig. 9 The Model of the Given Buck Converter Mkss ksk 3707.4 )2.19(93.18dD(s) (s)dV OUT From equation (6), the location of zero and the complex conjugate poles can be easily obtained. 2. Locate the zero and the second pole of compensation network. Since ω n= 6.08k, zero of Buck= 19.2k, fSwitching= 200kHz= 1.25M(rad/s) Let zero of compensation network=2.04k Pole of compensation network=250k 3. Choose the components: According to the equation (4), Let R2=75k then C2=6800p, and C3=56p The transient response and the simulation of frequency response are shown in Fig. 10 and Fig. 11, respectively. Obviously, the rising time is too long and the overshoot is too large. To increase the speed of response and to have more phase margin, we tr y to extend the crossover frequency. Fig. 10 The Transient Response (Ch2 is Current Curve, 1A/div) Fig. 11 The Corresponding Simulation of Frequency Response According to equation (4), we can add the extra gain which is provided by the compensation n etwork at the middle frequency without changing the location of zero and pole of the original loop transfer function. Let R2=560k, then R2C2= 2.04k

1 C 2=875 ≈ 820p

October, 2001 R2C3= 250k Fig.12 The Transient Response (Ch2 is current curve, 1A/div) Fig.13 The Corresponding Simulation of Frequency Response Referring to Fig. 13, the crossover frequency of open loop transfer function is raised. And we could also expect the bandwidth of the closed loop transfer function being increased. Indeed, in Fig 1 2, the set of control component s, which we just used, shows high speed of response and less overshoot. Although the pole at origin (according to equation (5)) means the infinitive gain at DC ( ω =0), it is still a good idea to verify the steady state error by the load regulation. From Fig.1 4, it shows that the steady state error of two settings is small, and the two curves are almost identical. 4.9 4.95 5.05 5.1 0 2 4 6 8 10 12Iout(A) Vout(V) C2=820p R2=560k C3=8p C2=6800p R2=75k C3=56p Fig.14 The Comparison of Load Regulation of Different Components (VIN=8V, VOUT=5V) From the results of transient response and the steady state error, the second set of components can achieve a satisfactory response. Summary By taking the advan tage of a high gain at low frequency with a low gain at high frequenc y, the best performance of the Buck Converter can be achieved. The objectives are to improve the steady state error at low frequency and reduce noise disturbance at high frequency. The key points of the compensation are: 1) Locate the zero around the LC resonant frequency for the issue of stability. 2) Locate the pole around Switchingf5 1 for the noise reduction at high frequency. 3) The combination of the above 2 procedures can make the c rossover frequency at the -20dB/ decade situation . Thus a satisfactory phase

October, 2001 margin is achieved. Reference: [1] Yim-Shu Lee, Computer-Aided Analysis and Design of Switch -Mode Power Supplies., Marcel Dekker, Inc. Hong Kong,1993