AMPL138ZCE3

OMAP-L138_0908 TI | Alldatasheet

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www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 (RCPxP) and Square-Root Reciprocal Dual Core SoC Approximation (RSQRxP) Operations 300-MHz ARM926EJ-S RISC MPU Per Cycle 300-MHz C674x VLIW DSP Two Multiply Functional Units ARM926EJ-S Core Mixed-Precision IEEE Floating Point 32-Bit and 16-Bit (Thumb Instructions Multiply Supported up to: DSP Instruction Extensions SP x SP SP Per Clock Single Cycle MAC SP x SP DP Every Two Clocks ARM Jazelle Technology SP x DP DP Every Three Clocks EmbeddedICE-RT for Real-Time Debug DP x DP DP Every Four Clocks ARM9 Memory Architecture Fixed Point Multiply Supports Two x 32-Bit Multiplies, Four x 16-Bit C674x Instruction Set Multiplies, or Eight x 8-Bit Multiplies Superset of the C67x+ and C64x+ ISAs per Clock Cycle, and Complex Multiples C674x MIPS/MFLOPS Instruction Packing Reduces Code Size Byte-Addressable (8-/16-/32-/64-Bit Data) All Instructions Conditional 8-Bit Overflow Protection Hardware Support for Modulo Loop Bit-Field Extract, Set, Clear Operation Normalization, Saturation, Bit-Counting Protected Mode Operation Compact 16-Bit Instructions Exceptions Support for Error Detection and C674x Two Level Cache Memory Architecture Program Redirection 32K-Byte L1P Program RAM/Cache Software Support 32K-Byte L1D Data RAM/Cache TI DSP/BIOS 256K -Byte Unified Mapped RAM/Cache Chip Support Library and DSP Library Flexible RAM/Cache Partition (L1 and L2) 128K-Byte RAM Shared Memory 1024K-Byte Boot ROM 1.8V or 3.3V LVCMOS IOs (except for USB and Enhanced Direct-Memory-Access Controller DDR2 interfaces) (EDMA3): Two External Memory Interfaces: Channel Controllers EMIFA Transfer Controllers NOR (8-/16-Bit-Wide Data) Independent DMA Channels NAND (8-/16-Bit-Wide Data) Quick DMA Channels 16-Bit SDRAM With 128 MB Address Programmable Transfer Burst Size Space TMS320C674x Floating-Point VLIW DSP Core DDR2/Mobile DDR Memory Controller Load-Store Architecture With Non-Aligned 16-Bit DDR2 SDRAM With 512 MB Support Address Space or General-Purpose Registers (32 Bit) 16-Bit mDDR SDRAM With 256 MB Six ALU (32-/40-Bit) Functional Units Address Space Supports 32-Bit Integer, SP (IEEE Single Three Configurable 16550 type UART Modules: Precision/32-Bit) and DP (IEEE Double With Modem Control Signals Precision/64-Bit) Floating Point 16-byte FIFO Supports up to Four SP Additions Per 16x or 13x Oversampling Option Clock, Four DP Additions Every LCD Controller Clocks Supports up to Two Floating Point (SP Two Serial Peripheral Interface s (SPI) Each or DP) Reciprocal Approximation Please be aware that an important notice concerning availability, standard warranty, and use in critical document. TMS320C6000, C6000 are trademarks of Texas Instruments. ARM926EJ-S is a trademark of ARM Limited. PRODUCT PREVIEW information concerns products in the Copyright 2009 2009, Texas Instruments Incorporated formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.

www.ti.com RMII Reduced Media Independent Interface With Multiple Chip-Selects Management Data I/O (MDIO) Module Two Multimedia Card (MMC)/Secure Digital Video Port Interface (VPIF): (SD) Card Interface with Secure Data I/O (SDIO) Interfaces Two 8-bit SD (BT.656), Single 16-bit or Single Raw (8-/10-/12-bit) Video Capture Two Master/Slave Inter-Integrated Circuit C Channels Bus Two 8-bit SD (BT.656), Single 16-bit Video One Host-Port Interface (HPI) With 16-Bit-Wide Display Channels Muxed Address/Data Bus For High Bandwidth Universal Parallel Port (uPP): Programmable Real-Time Unit Subsystem High-Speed Parallel Interface to FPGAs and (PRUSS) Data Converters Two Independent Programmable Realtime Data Width on Each of Two Channels is Unit (PRU) Cores to 16-bit Inclusive 32-Bit Load/Store RISC architecture Single Data Rate or Dual Data Rate Byte instruction RAM per core Transfers 512 Bytes data RAM per core Supports Multiple Interfaces with START, PRU Subsystem (PRUSS) can be ENABLE and WAIT Controls disabled via software to save power Serial ATA (SATA) Controller: Register of each PRU is exported Supports SATA I (1.5 Gbps) and SATA II from the subsystem in addition to the (3.0 Gbps) normal R31 output of the PRU cores. Supports all SATA Power Management Standard power management mechanism a single PSC Queueing (NCQ) for up to Entries clock gating domain Supports Port Multiplier and Dedicated interrupt controller Command-Based Switching Dedicated switched central resource Real-Time Clock With KHz Oscillator and USB 1.1 OHCI (Host) With Integrated PHY Separate Power Rail (USB1) Three 64-Bit General-Purpose Timers USB 2.0 OTG Port With Integrated PHY (USB0) (Configurable as Two 32-Bit Timers) USB 2.0 High-/Full-Speed Client One 64-Bit General-Purpose Timer (Watch USB 2.0 High-/Full-/Low-Speed Host Dog) End Point (Control) Two Enhanced Pulse Width Modulators End Points 1,2,3,4 (Control, Bulk, Interrupt (eHRPWM): or ISOC) Rx and Tx Dedicated 16-Bit Time-Base Counter With One Multichannel Audio Serial Port: Period And Frequency Control Transmit/Receive Clocks up to MHz Single Edge, Dual Edge Symmetric or Two Clock Zones and Serial Data Pins Dual Edge Asymmetric Outputs Supports TDM, I2S, and Similar Formats Dead-Band Generation DIT-Capable PWM Chopping by High-Frequency Carrier FIFO buffers for Transmit and Receive Trip Zone Input Two Multichannel Buffered Serial Ports: Three 32-Bit Enhanced Capture Modules Transmit/Receive Clocks up to MHz (eCAP): Two Clock Zones and Serial Data Pins Configurable as Capture Inputs or Auxiliary Pulse Width Modulator (APWM) Supports TDM, I2S, and Similar Formats outputs AC97 Audio Codec Interface Single Shot Capture of up to Four Event Telecom Interfaces (ST-Bus, H100) Time-Stamps 128-channel TDM 361-Ball Pb-Free Plastic Ball Grid Array FIFO buffers for Transmit and Receive (PBGA) [ZCE Suffix], 0.65-mm Ball Pitch Mb/s Ethernet MAC (EMAC): 361-Ball Pb-Free Plastic Ball Grid Array IEEE 802.3 Compliant (PBGA) [ZWT Suffix], 0.80-mm Ball Pitch MII Media Independent Interface OMAP-L138 Low-Power

www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Commercial or Extended Temperature Submit Documentation Feedback OMAP-L138 Low-Power

1.2 Trademarks OMAP-L138 Low-Power www.ti.com DSP/BIOS, TMS320C6000, C6000, TMS320, TMS320C62x, and TMS320C67x are trademarks of Texas Instruments. All trademarks are the property of their respective owners. OMAP-L138 Low-Power

1.3

Description

www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 The device is a Low-power a C674x DSP core. It provides significantly lower power than other members of the TMS320C6000 platform of DSPs. The device enables OEMs and ODMs to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance life through the maximum flexibility of a fully integrated mixed processor solution The dual-core architecture of the device provides benefits of both DSP and Reduced Instruction Set Computer (RISC) technologies, incorporating a high-performance TMS320C674x DSP core and an ARM926EJ-S core. The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously. The ARM core has a coprocessor (CP15), protection module, and Data and program Memory Management Units (MMUs) with table look-aside buffers. It has separate 16K-byte instruction and 16K-byte data caches. Both are four-way associative with virtual index virtual tag (VIVT). The ARM core also has a 8KB RAM (Vector Table) and 64KB ROM. The device DSP core uses a two-level cache-based architecture. The Level program cache (L1P) is a 32KB direct mapped cache and the Level data cache (L1D) is a 32KB 2-way set-associative cache. The Level program cache (L2P) consists of a 256KB memory space that is shared between program and data space. also has a 1024KB Boot ROM. memory can be configured as mapped memory, cache, or combinations of the two. Although the DSP is accessible by ARM and other hosts in the system an additional 128KB RAM shared memory is available for use by other hosts without affecting DSP performance The peripheral set includes: a Mb/s Ethernet MAC (EMAC) with a Management Data Input/Output (MDIO) module; one USB2.0 OTG interface; one USB1.1 OHCI interface; two inter-integrated circuit (I2C) Bus interface s one multichannel audio serial port (McASP) with serializers and FIFO buffers; two multichannel buffered serial port s (McBSP) with FIFO buffers; two SPI interface s with multiple chip selects; four 64-bit general-purpose timers each configurable (one configurable as watchdog); a configurable 16-bit host port interface (HPI) up to banks of pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; three UART interface s each with RTS and CTS two enhanced high-resolution pulse width modulator (eHRPWM) peripherals; 32-bit enhanced capture (eCAP) module peripherals which can be configured as capture inputs or auxiliary pulse width modulator (APWM) outputs; and external memory interfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals, and a higher speed DDR2/Mobile DDR controller. The Ethernet Media Access Controller (EMAC) provides an efficient interface between the device and a network. The EMAC supports both 10Base-T and 100Base-TX, or Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode. Additionally an Management Data Input/Output (MDIO) interface is available for PHY configuration. The EMAC supports both MII and RMII interfaces. The SATA controller provides a high-speed interface to mass data storage devices. The SATA controller supports both SATA I (1.5 Gbps) and SATA II (3.0 Gbps). The Universal Parallel Port (uPP) provides a high-speed interface to many types of data converters, FPGAs or other parallel devices. The UPP supports programmable data widths between to 16-bits on each of two channels. Single-date rate and double-data rate transfers are supported as well as START, ENABLE and WAIT signals to provide control for a variety of data converters. A Video Port Interface (VPIF) is included providing a flexible video input/output port. Submit Documentation Feedback OMAP-L138 Low-Power

www.ti.com The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides. The device has a complete set of development tools for the ARM and DSP. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source code execution. OMAP-L138 Low-Power

1.4 Functional Block Diagram Switched□Central□Resource□(SCR) 1024KB□L2□ROM 256KB□L2□RAM 32KB L1□RAM 32KB L1□Pgm 16KB I-Cache 16KB D-Cache AET4KB□ETB C674x™ DSP CPU ARM926EJ-S□CPU With□MMU DSP SubsystemARM□SubsystemJTAG□Interface System□Control Input Clock(s) 64KB□ROM 8KB□RAM (Vector□Table) Power/Sleep Controller Pin Multiplexing PLL/Clock Generator w/OSC General- Purpose Timer□(x3) Serial□InterfacesAudio□Ports McASP w/FIFO DMA Peripherals Display Internal□Memory LCD Ctlr 128KB RAM External□Memory□InterfacesConnectivity EDMA3 (x2) Control□Timers ePWM (x2) eCAP (x3) EMIFA(8b/16B) NAND/Flash 16b□SDRAM DDR2/MDDR Controller RTC/ 32-kHz OSC I C (x2)

2 SPI

(x2) UART (x3) McBSP (x2) Video VPIF Parallel□Port uPP EMAC (MII/RMII) MDIO USB1.1 OHCI□Ctlr PHY USB2.0 OTG□Ctlr PHY HPI MMC/SD (8b) (x2) SATA Customizable□Interface PRU□Subsystem OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 (1) Note: Not all peripherals are available at the same time due to multiplexing. Figure 1-1. Functional Block Diagram Submit Documentation Feedback OMAP-L138 Low-Power

www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 NOTE: This is a placeholder for the Revision History Table for future revisions of the document. This data manual revision history highlights the changes made to the SPRS586 device-specific data manual to make it an SPRS586A revision. Table 2-1. Revision History ADDITIONS/MODIFICATIONS/DELETIONS Global: Added Programmable Real-Time Unit Subsystem (PRUSS) and made related changes to the list, Functional Block Diagram, Terminal functions tables and the Pin map diagrams. Global: Updated "UPP_CH0..." to "UPP_CHB..." Updated "UPP_CH1..." to "UPP_CHA..." Updated "UPP_CH1_CLK" to "UPP_CHA_CLOCK". Updated "UPP_CH0_CLK" to "UPP_CHB_CLOCK". Updated "UPP_CH0_D[n]" to "UPP_D[n]" Updated "UPP_CHB_D[n]" to "UPP_D[n]" Submit Documentation Feedback Revision History

3.1 Documentation Support 3.1.1 Related Documentation From Texas Instruments 3.2 Device Characteristics OMAP-L138 Low-Power www.ti.com The following documents are available on the Internet at www.ti.com Tip: Enter the literature number in the search box provided at www.ti.com. DSP Reference Guides SPRUG82 TMS320C674x DSP Cache User's Guide. Explains the fundamentals of memory caches and describes how the two-level cache-based internal memory architecture in the TMS320C674x digital signal processor (DSP) can be efficiently used in DSP applications. Shows how to maintain coherence with external memory, how to use DMA to reduce memory latencies, and how to optimize your code to improve cache efficiency. The internal memory architecture in the C674x DSP is organized in a two-level hierarchy consisting of a dedicated program cache (L1P) and a dedicated data cache (L1D) on the first level. Accesses by the CPU to the these first level caches can complete without CPU pipeline stalls. If the data requested by the CPU is not contained in cache, it is fetched from the next lower memory level, or external memory. SPRUFE8 TMS320C674x DSP CPU and Instruction Set Reference Guide. Describes the CPU architecture, pipeline, instruction set, and interrupts for the TMS320C674x digital signal processors (DSPs). The C674x DSP is an enhancement of the C64x+ and C67x+ DSPs with added functionality and an expanded instruction set. SPRUFK5 TMS320C674x DSP Megamodule Reference Guide. Describes the TMS320C674x digital signal processor (DSP) megamodule. Included is a discussion on the internal direct memory access (IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidth management, and the memory and cache. SPRUFK9 TMS320C674x/OMAP-L1x Processor Peripherals Overview Reference Guide. Provides an overview and briefly describes the peripherals available on the device. Table 3-1 provides an overview of the device. The table shows significant device, including the capacity of on-chip RAM, peripherals, and the package type with pin count. Device Overview Submit Documentation Feedback

www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 3-1. Characteristics of OMAP-L138 HARDWARE DDR2, 16-bit bus width, up to 150 MHz DDR2/mDDR Controller Mobile DDR, 16-bit bus width, up to 133 MHz Asynchronous (8/16-bit bus width) RAM, Flash, EMIFA 16-bit SDRAM, NOR, NAND Flash Card Interface MMC and SD cards supported. independent channels, QDMA channels, EDMA3 channel controllers, transfer controllers 64-Bit General Purpose (configurable as separate 32-bit Timers timers, configurable as Watch Dog) UART (each with RTS and CTS flow control) SPI (Each with one hardware chip select) I C (both Master/Slave) Peripherals Multichannel Audio Serial Port [McASP] (each with transmit/receive, FIFO buffer, serializers) Not all peripherals pins are available at the Multichannel Buffered Serial Port [McBSP] (each with transmit/receive, FIFO buffer, 16) same time (for more Ethernet MAC with Management Data I/O (MII or RMII Interface) detail, see the Device Configurations section). Single Edge, Dual Edge Symmetric, or eHRPWM Dual Edge Asymmetric Outputs eCAP 32-bit capture inputs or 32-bit auxiliary PWM outputs USB 2.0 (USB0) High-Speed OTG Controller with on-chip OTG PHY USB 1.1 (USB1) Full-Speed OHCI (as host) with on-chip PHY General-Purpose Input/Output Port banks of 16-bit LCD Controller SATA Controller (Support both SATA I and SATAII) Universal Parallel Port (uPP) Video Port Interface (VPIF) (video in and video out) PRU Subsystem (PRUSS) Programmable PRU Cores Size (Bytes) 488KB RAM, 1088KB Boot ROM DSP 32KB Program (L1P)/Cache (up to 32KB) 32KB Data (L1D)/Cache (up to 32KB) 256KB Unified Mapped RAM/Cache (L2) 1024KB ROM (L2) DSP Memories can be made accessible to ARM, EDMA3, and other peripherals. On-Chip Memory Organization ARM 16KB I-Cache 16KB D-Cache 8KB RAM (Vector Table) 64KB ROM ADDITIONAL SHARED MEMORY 128KB RAM C674x CPU ID CPU Control Status Register (CSR.[31:16]) 0x1400 Rev ID C674x Megamodule Revision ID Register (MM_REVID[15:0]) 0x0000 Revision JTAG BSDL_ID DEVIDR0 Register 0x0B7D_102F 674x DSP 300 MHz CPU Frequency MHz ARM926 300 MHz 674x DSP 3.3 ns Cycle Time ns ARM926 3.3 ns Core (V) 1.2 V Voltage I/O (V) 1.8V or 3.3 V Submit Documentation Feedback Device Overview

3.3 Device Compatibility 3.4 ARM Subsystem 3.4.1 ARM926EJ-S RISC CPU OMAP-L138 Low-Power www.ti.com Table 3-1. Characteristics of OMAP-L138 (continued) HARDWARE x mm, 361-Ball 0.65 mm pitch, PBGA (ZCE) Packages mm x mm, 361-Ball 0.80 mm pitch, PBGA (ZWT) Product Preview (PP), Product Status (1) Advance Information (AI), PP or Production Data (PD) (1) PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. The ARM926EJ-S RISC CPU is compatible with other ARM9 CPUs from ARM Holdings plc. The C674x DSP core is code-compatible with the C6000 DSP platform and supports families. The ARM Subsystem includes the following features: ARM926EJ-S RISC processor ARMv5TEJ (32/16-bit) instruction set Little endian System Control Co-Processor (CP15) MMU 16KB Instruction cache 16KB Data cache Write Buffer Embedded Trace Module and Embedded Trace Buffer (ETM/ETB) ARM Interrupt controller The ARM Subsystem integrates the ARM926EJ-S processor. The ARM926EJ-S processor is a member of ARM9 family of general-purpose microprocessors. This processor is targeted at multi-tasking management, high performance, low die size, and low power are all important. The ARM926EJ-S processor supports the 32-bit ARM and bit THUMB instruction sets, enabling the user to trade off between high performance and high code density. Specifically, the ARM926EJ-S processor supports the ARMv5TEJ instruction set, which includes codes, providing Java performance similar to Just in Time (JIT) Java interpreter, but without associated code overhead. The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both hardware and software debug. The ARM926EJ-S processor has a Harvard architecture and provides a complete high performance subsystem, including: ARM926EJ integer core CP15 system control coprocessor Memory Management Unit (MMU) Separate instruction and data caches Write buffer Separate instruction and data (internal RAM) interfaces Separate instruction and data AHB bus interfaces Embedded Trace Module and Embedded Trace Buffer (ETM/ETB) Device Overview Submit Documentation Feedback

3.4.2 CP15 3.4.3 MMU 3.4.4 Caches and Write Buffer OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 For more complete details on the ARM9, refer to the ARM926EJ-S Technical Reference Manual, available at http://www.arm.com The ARM926EJ-S system control coprocessor (CP15) is used to configure and control instruction and data caches, Memory Management Unit (MMU), and other ARM subsystem functions. The CP15 registers are programmed using the MRC and MCR ARM instructions, when the ARM in a privileged mode such as supervisor or system mode. A single set of two level page tables stored in main memory is used to control the address translation, permission checks and memory region attributes for both data and instruction accesses. The MMU uses a single unified Translation Lookaside Buffer (TLB) to cache the information held in the page tables. The MMU are: Standard ARM architecture and MMU mapping sizes, domains and access protection scheme. Mapping sizes are: 1MB (sections) 64KB (large pages) 4KB (small pages) 1KB (tiny pages) Access permissions for large pages and small pages can be specified separately for each quarter of the page (subpage permissions) Hardware page table walks Invalidate entire TLB, using CP15 register Invalidate TLB entry, selected by MVA, using CP15 register Lockdown of TLB entries, using CP15 register The size of the Instruction cache is 16KB, Data cache is 16KB. Additionally, the caches have the following features: Virtual index, virtual tag, and addressed using the Modified Virtual Address (MVA) Four-way set associative, with a cache line length of eight words per line (32-bytes per line) and with two dirty bits in the Dcache Dcache supports write-through and write-back (or copy back) cache operation, selected by memory region using the C and B bits in the MMU translation tables Critical-word first cache refilling Cache lockdown registers enable control over which cache ways are used for allocation on a line fill, providing a mechanism for both lockdown, and controlling cache corruption Dcache stores the Physical Address TAG (PA TAG) corresponding to each Dcache entry in the TAG RAM for use during the cache line write-backs, in addition to the Virtual Address TAG stored in the TAG RAM. This means that the MMU is not involved in Dcache write-back operations, removing the possibility of TLB misses related to the write-back address. Cache maintenance operations provide efficient invalidation of, the entire Dcache or Icache, regions of the Dcache or Icache, and regions of virtual memory. The write buffer is used for all writes to a noncachable bufferable region, write-through region and write misses to a write-back region. A separate buffer is incorporated in the Dcache for holding write-back for cache line evictions or cleaning of dirty cache lines. The main write buffer has 16-word data buffer and a four-address buffer. The Dcache write-back has eight data word entries and a single address entry. Submit Documentation Feedback Device Overview

3.4.5 Advanced High-Performance Bus (AHB) 3.4.6 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB) 3.4.7 ARM Memory Mapping OMAP-L138 Low-Power www.ti.com The ARM Subsystem uses the AHB port of the ARM926EJ-S to connect the ARM to the Config bus and the external memories. Arbiters are employed to arbitrate access to the separate D-AHB and I-AHB by the Config Bus and the external memories bus. To support real-time trace, the ARM926EJ-S processor provides an interface to enable connection of an Embedded Trace Macrocell (ETM). The ARM926ES-J Subsystem in the OMAP-L138 also includes the Embedded Trace Buffer (ETB). The ETM consists of two parts: Trace Port provides real-time trace capability for the ARM9. Triggering facilities provide trigger resources, which include address and data comparators, counter, and sequencers. The OMAP-L138 trace port is not pinned out and is instead only connected to the Embedded Trace Buffer. The ETB has a 4KB buffer memory. ETB enabled debug tools are required to read/interpret the captured trace data. By default the ARM has access to most on and off chip memory areas, including the DSP Internal memories, EMIFA, DDR2, and the additional 128K byte on chip shared SRAM. Likewise almost all of the on chip peripherals are accessible to the ARM by default. See Table 3-3 for a detailed top level OMAP-L138 memory map that includes the ARM memory space. Device Overview Submit Documentation Feedback

3.5 DSP Subsystem Instruction□Fetch C674x Fixed/Floating□Point□CPU Register File A Register File□B Cache□Control Memory□Protect Bandwidth□Mgmt L1P 256 Cache□Control Memory□Protect Bandwidth□Mgmt L1D 64 64 8□x□32 32K□Bytes L1D□RAM/ Cache 32K□Bytes L1P RAM/ Cache 256 Cache□Control Memory□Protect Bandwidth□Mgmt 256K□Bytes L2□RAM 256 1M□Byte L2□ROM 256 CFG MDMA SDMA EMC Power□Down Interrupt Controller IDMA 256 256 256 256 256 High Performance Switch□Fabric 64 64 64 Configuration Peripherals Bus OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 The DSP Subsystem includes the following features: C674x DSP CPU 32KB Program (L1P)/Cache (up to 32KB) 32KB Data (L1D)/Cache (up to 32KB) 256KB Unified Mapped RAM/Cache (L2) 1MB Mask-programmable ROM Little endian Figure 3-1. C674x Megamodule Block Diagram Submit Documentation Feedback Device Overview

3.5.1 C674x DSP CPU www.ti.com The C674x Central Processing Unit (CPU) consists of eight functional units, two register files, and two data paths as shown in Figure 3-2 The two general-purpose register files and each contain 32-bit registers for a total of registers. The general-purpose registers can be used for data or can be data address pointers. The data types supported include packed 8-bit data, packed 16-bit data, 32-bit data, 40-bit data, and 64-bit data. Values larger than bits, such as 40-bit-long or 64-bit-long values are stored in register pairs, with the LSBs of data placed in an even register and the remaining or MSBs in the next upper register (which is always an odd-numbered register). The eight functional units (.M1, .L1, .D1, .S1, .M2, .L2, .D2, and .S2) are each capable of executing one instruction every clock cycle. The functional units perform all multiply operations. The and units perform a general set of arithmetic, logical, and branch functions. The units primarily load data from memory to the register file and store results from the register file into memory. The C674x CPU combines the performance of the C64x+ core with the floating-point capabilities of the C67x+ core. Each C674x unit can perform one of the following each clock cycle: one x bit multiply, one x bit multiply, two x bit multiplies, two x bit multiplies, two x bit multiplies with add/subtract capabilities, four x bit multiplies, four x bit multiplies with add operations, and four x multiplies with add/subtract capabilities (including a complex multiply). There is also support for Galois field multiplication for 8-bit and 32-bit data. Many communications algorithms such as FFTs and modems require complex multiplication. The complex multiply (CMPY) instruction takes for 16-bit inputs and produces a 32-bit real and a 32-bit imaginary output. There are also complex multiplies with rounding capability that produces one 32-bit packed output that contain 16-bit real and 16-bit imaginary values. The x bit multiply instructions provide the extended precision necessary for high-precision algorithms on a variety of signed and unsigned 32-bit data types. The or (Arithmetic Logic Unit) now incorporates the ability to do parallel add/subtract operations on a pair of common inputs. Versions of this instruction exist to work on 32-bit data or on pairs of 16-bit data performing dual 16-bit add and subtracts in parallel. There are also saturated forms of these instructions. The C674x core enhances the unit in several ways. On the previous cores, dual 16-bit MIN2 and MAX2 comparisons were only available on the units. On the C674x core they are also available on the unit which increases the performance of algorithms that do searching and sorting. Finally, to increase data packing and unpacking throughput, the unit allows sustained high performance for the quad 8-bit/16-bit and dual 16-bit instructions. Unpack instructions prepare 8-bit data for parallel 16-bit operations. Pack instructions return parallel results to output precision including saturation support. Other new include: SPLOOP A small instruction buffer in the CPU that aids in creation of software pipelining loops where multiple iterations of a loop are executed in parallel. The SPLOOP buffer reduces the code size associated with software pipelining. Furthermore, loops in the SPLOOP buffer are fully interruptible. Compact Instructions The native instruction size for the C6000 devices is bits. Many common instructions such as MPY, AND, OR, ADD, and SUB can be expressed as bits if the C674x compiler can restrict the code to use certain registers in the register file. This compression is performed by the code generation tools. Instruction Set Enhancement As noted above, there are new instructions such as 32-bit multiplications, complex multiplications, packing, sorting, bit manipulation, and 32-bit Galois field multiplication. Exceptions Handling Intended to aid the programmer in isolating bugs. The C674x CPU is able to detect and respond to exceptions, both from internally detected sources (such as illegal op-codes) and from system events (such as a watchdog time expiration). Privilege Defines user and supervisor modes of operation, allowing the operating system to give a basic level of protection to sensitive resources. Local memory is divided into multiple pages, each with read, write, and execute permissions. Device Overview Submit Documentation Feedback

www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Time-Stamp Counter Primarily targeted for Real-Time Operating System (RTOS) robustness, a free-running time-stamp counter is implemented in the CPU which is not sensitive to system stalls. For more details on the C674x CPU and its enhancements over the C64x architecture, see the following documents: TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRUFE8 TMS320C64x Technical Overview (literature number SPRU395 Submit Documentation Feedback Device Overview

Á Á Á Á Á Á Á .D1 .M1 Á Á Á Á Á Á Á Á Á Á Á Á Á .S1 Á Á Á Á Á Á Á Á Á Á .L1 long src odd dst src2 src1 Á Á Á Á Á Á Á Á Á Á Á Á Á Á ÁÁ Á Á Á Á Á src1 src1 src1 even dst even dst odd dst dst1 dst src2 src2 src2 long src DA1 ST1b LD1b LD1a ST1a Data path A Odd register file A (A1, A3, A5...A31) Á Á Á Odd register file B (B1, B3, B5...B31) Á Á Á .D2 Á Á Á Á src1 dst src2DA2 LD2a LD2b src2 .M2 src1 Á Á Á dst1 Á Á Á .S2 src1 Á Á Á Á even dst long src odd dst ST2a ST2b long src .L2 Á Á Á Á even dst odd dst Á Á Á src1 Data path B Control Register

32 MSB

32 LSB

dst2 (A) (B) (B) (A) (C) (C) Even register file A (A0, A2, A4...A30) Even register file B (B0, B2, B4...B30) (D) (D) (D) (D) A. On .M unit, dst2 is 32 MSB. B. On .M unit, dst1 is 32 LSB. C. On C64x CPU .M unit, src2 is 32 bits; on C64x+ CPU .M unit, src2 is 64 bits. D. On .L and .S units, odd dst connects to odd register files and even dst connects to even register files. OMAP-L138 Low-Power www.ti.com Figure 3-2. TMS320C674x CPU (DSP Core) Data Paths Device Overview Submit Documentation Feedback

3.5.2 DSP Memory Mapping 3.5.2.1 ARM Internal Memories 3.5.2.2 External Memories 3.5.2.3 DSP Internal Memories 3.5.2.4 C674x CPU OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 The DSP memory map is shown in Section 3.6 By default the DSP also has access to most on and off chip memory areas with the exception of the ARM RAM, ROM, and AINTC interrupt controller Additionally, the DSP megamodule includes the capability to limit access to its internal memories through its SDMA port; without needing an external MPU unit. The DSP does not have access to the ARM internal memory. The DSP has access to the following External memories: Asynchronous EMIF SDRAM NAND NOR Flash (EMIFA) SDRAM (DDR2) The DSP has access to the following DSP memories: RAM L1P RAM L1D RAM The C674x core uses a two-level cache-based architecture. The Level Program cache (L1P) is KB direct mapped cache and the Level Data cache (L1D) is KB 2-way set associated cache. The Level memory/cache (L2) consists of a 256 KB memory space that is shared between program and data space. memory can be configured as mapped memory, cache, or a combination of both. Table 3-2 shows a memory map of the C674x CPU cache registers for the device. Table 3-2. C674x Cache Registers Byte Address Register Name Register

www.ti.com Table 3-2. C674x Cache Registers (continued) Byte Address Register Name Register (CS0) 0x4000 0000 0x0184 8100 0x0184 817F MAR64 MAR95 0x5FFF FFFF Memory Attribute Registers for EMIFA Async Data (CS2) 0x6000 0000 0x0184 8180 0x0184 8187 MAR96 MAR97 0x61FF FFFF Memory Attribute Registers for EMIFA Async Data (CS3) 0x6200 0000 0x0184 8188 0x0184 818F MAR98 MAR99 0x63FF FFFF Memory Attribute Registers for EMIFA Async Data (CS4) 0x6400 0000 0x0184 8190 0x0184 8197 MAR100 MAR101 0x65FF FFFF Memory Attribute Registers for EMIFA Async Data (CS5) 0x6600 0000 0x0184 8198 0x0184 819F MAR102 MAR103 0x67FF FFFF 0x0184 81A0 0x0184 81FF MAR104 MAR127 Reserved 0x6800 0000 0x7FFF FFFF Memory Attribute Register for Shared RAM 0x8000 0000 0x8001 FFFF 0x0184 8200 MAR128 Reserved 0x8002 0000 0x81FF FFFF 0x0184 8204 0x0184 82FF MAR129 MAR191 Reserved 0x8200 0000 0xBFFF FFFF Memory Attribute Registers for DDR2 Data (CS2) 0xC000 0000 0xDFFF 0x0184 8300 0x0184 837F MAR192 MAR223 FFFF 0x0184 8380 0x0184 83FF MAR224 MAR255 Reserved 0xE000 0000 0xFFFF FFFF See the following table for a detailed top level device memory map that includes the DSP memory space. Device Overview Submit Documentation Feedback

3.6 Memory Map Summary OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 3-3. OMAP-L138 Top Level Memory Map Start End Size ARM Mem DSP Mem EDMA Mem Map PRUSS Mem Master LCDC Address Address Map Map Map Peripheral Mem Mem Map Map 0x0000 0000 0x0000 0FFF PRUSS Local Address Space 0x0000 1000 0x006F FFFF 0x0070 0000 0x007F FFFF 1024K DSP ROM 0x0080 0000 0x0083 FFFF 256K DSP RAM 0x0084 0000 0x00DF FFFF 0x00E0 0000 0x00E0 7FFF 32K DSP L1P RAM 0x00E0 8000 0x00EF FFFF 0x00F0 0000 0x00F0 7FFF 32K DSP L1D RAM 0x00F0 8000 0x017F FFFF 0x0180 0000 0x0180 FFFF 64K DSP Interrupt Controller 0x0181 0000 0x0181 0FFF DSP Powerdown Controller 0x0181 1000 0x0181 1FFF DSP Security ID 0x0181 2000 0x0181 2FFF DSP Revision ID 0x0181 3000 0x0181 FFFF 52K 0x0182 0000 0x0182 FFFF 64K DSP EMC 0x0183 0000 0x0183 FFFF 64K DSP Internal Reserved 0x0184 0000 0x0184 FFFF 64K DSP Memory System 0x0185 0000 0x01BB FFFF 0x01BC 0000 0x01BC ARM ETB 0FFF memory 0x01BC 1000 0x01BC ARM ETB 17FF reg 0x01BC 1800 0x01BC 256 ARM Ice 18FF Crusher 0x01BC 1900 0x01BF FFFF 0x01C0 0000 0x01C0 7FFF 32K EDMA3 CC 0x01C0 8000 0x01C0 83FF EDMA3 TC0 0x01C0 8400 0x01C0 87FF EDMA3 TC1 0x01C0 8800 0x01C0 FFFF 0x01C1 0000 0x01C1 0FFF PSC 0x01C1 1000 0x01C1 1FFF PLL Controller 0x01C1 2000 0x01C1 3FFF 0x01C1 4000 0x01C1 4FFF SYSCFG0 0x01C1 5000 0x01C1 FFFF 0x01C2 0000 0x01C2 0FFF Timer0 Submit Documentation Feedback Device Overview

www.ti.com Table 3-3. OMAP-L138 Top Level Memory Map (continued) Start End Size ARM Mem DSP Mem EDMA Mem Map PRUSS Mem Master LCDC Address Address Map Map Map Peripheral Mem Mem Map Map 0x01C2 1000 0x01C2 1FFF Timer1 0x01C2 2000 0x01C2 2FFF I2C 0x01C2 3000 0x01C2 3FFF RTC 0x01C2 4000 0x01C3 FFFF 0x01C4 0000 0x01C4 0FFF MMC/SD 0x01C4 1000 0x01C4 1FFF SPI 0x01C4 2000 0x01C4 2FFF UART 0x01C4 3000 0x01CF FFFF 0x01D0 0000 0x01D0 0FFF McASP Control 0x01D0 1000 0x01D0 1FFF McASP AFIFO Ctrl 0x01D0 2000 0x01D0 2FFF McASP Data 0x01D0 3000 0x01D0 BFFF 0x01D0 C000 0x01D0 UART CFFF 0x01D0 D000 0x01D0 UART DFFF 0x01D0 E000 0x01D0 FFFF 0x01D1 0000 0x01D1 07FF McBSP0 0x01D1 0800 0x01D1 0FFF McBSP0 FIFO Ctrl 0x01D1 1000 0x01D1 17FF McBSP1 0x01D1 1800 0x01D1 1FFF McBSP1 FIFO Ctrl 0x01D1 2000 0x01DF FFFF 0x01E0 0000 0x01E0 FFFF 64K USB0 0x01E1 0000 0x01E1 0FFF UHPI 0x01E1 1000 0x01E1 2FFF 0x01E1 3000 0x01E1 3FFF LCD Controller 0x01E1 4000 0x01E1 5FFF 0x01E1 6000 0x01E1 6FFF UPP 0x01E1 7000 0x01E1 7FFF VPIF 0x01E1 8000 0x01E1 9FFF SATA 0x01E1 A000 0x01E1 PLL Controller AFFF 0x01E1 B000 0x01E1 MMCSD1 BFFF 0x01E1 C000 0x01E1 FFFF 0x01E2 0000 0x01E2 1FFF EMAC Control Module RAM 0x01E2 2000 0x01E2 2FFF EMAC Control Module Registers 0x01E2 3000 0x01E2 3FFF EMAC Control Registers 0x01E2 4000 0x01E2 4FFF EMAC MDIO port 0x01E2 5000 0x01E2 5FFF USB1 0x01E2 6000 0x01E2 6FFF GPIO 0x01E2 7000 0x01E2 7FFF PSC 0x01E2 8000 0x01E2 8FFF I2C Device Overview Submit Documentation Feedback

www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 3-3. OMAP-L138 Top Level Memory Map (continued) Start End Size ARM Mem DSP Mem EDMA Mem Map PRUSS Mem Master LCDC Address Address Map Map Map Peripheral Mem Mem Map Map 0x01E2 9000 0x01E2 BFFF 0x01E2 C000 0x01E2 SYSCFG1 CFFF 0x01E2 D000 0x01E2 FFFF 0x01E3 0000 0x01E3 7FFF 32K EDMA3 CC1 0x01E3 8000 0x01E3 83FF EDMA3 TC2 0x01E3 8400 0x01EF FFFF 0x01F0 0000 0x01F0 0FFF eHRPWM 0x01F0 1000 0x01F0 1FFF HRPWM 0x01F0 2000 0x01F0 2FFF eHRPWM 0x01F0 3000 0x01F0 3FFF HRPWM 0x01F0 4000 0x01F0 5FFF 0x01F0 6000 0x01F0 6FFF ECAP 0x01F0 7000 0x01F0 7FFF ECAP 0x01F0 8000 0x01F0 8FFF ECAP 0x01F0 9000 0x01F0 BFFF 0x01F0 C000 0x01F0 Timer2 CFFF 0x01F0 D000 0x01F0 Timer3 DFFF 0x01F0 E000 0x01F0 EFFF SPI1 0x01F0 F000 0x01F0 FFFF 0x01F1 0000 0x01F1 0FFF McBSP0 FIFO Data 0x01F1 1000 0x01F1 1FFF McBSP1 FIFO Data 0x01F1 2000 0x116F FFFF 0x1170 0000 0x117F FFFF 1024K DSP ROM 0x1180 0000 0x1183 FFFF 256K DSP RAM 0x1184 0000 0x11DF FFFF 0x11E0 0000 0x11E0 7FFF 32K DSP L1P RAM 0x11E0 8000 0x11EF FFFF 0x11F0 0000 0x11F0 7FFF 32K DSP L1D RAM 0x11F0 8000 0x3FFF FFFF 0x4000 0000 0x5FFF 512M EMIFA SDRAM data (CS0) FFFF 0x6000 0000 0x61FF FFFF 32M EMIFA async data (CS2) 0x6200 0000 0x63FF FFFF 32M EMIFA async data (CS3) 0x6400 0000 0x65FF FFFF 32M EMIFA async data (CS4) 0x6600 0000 0x67FF FFFF 32M EMIFA async data (CS5) 0x6800 0000 0x6800 7FFF 32K EMIFA Control Regs 0x6800 8000 0x7FFF FFFF 0x8000 0000 0x8001 FFFF 128K Shared RAM 0x8002 0000 0xAFFF FFFF Submit Documentation Feedback Device Overview

www.ti.com Table 3-3. OMAP-L138 Top Level Memory Map (continued) Start End Size ARM Mem DSP Mem EDMA Mem Map PRUSS Mem Master LCDC Address Address Map Map Map Peripheral Mem Mem Map Map 0xB000 0000 0xB000 7FFF 32K DDR2 Control Regs 0xB000 8000 0xBFFF FFFF 0xC000 0000 0xDFFF 512M DDR2 Data FFFF 0xE000 0000 0xFFFC FFFF 0xFFFD 0000 0xFFFD 64K ARM local FFFF ROM 0xFFFE 0000 0xFFFE DFFF 0xFFFE 0xFFFE ARM E000 FFFF Interrupt Controller 0xFFFF 0000 0xFFFF ARM local 1FFF RAM 0xFFFF 2000 0xFFFF FFFF Device Overview Submit Documentation Feedback

3.7 Pin Assignments 3.7.1 Pin Map (Bottom View) W V U T R P N M L K 10987654321 10987654321 DVDD3318_C VP_CLKOUT3/ PRU1_R30[0]/ GP6[1]/ PRU1_R31[1] SA T A_VSS SA T A_RXP VP_CLKOUT2/ MMCSD1_DA T[2]/ PRU1_R30[2]/ GP6[3]/ PRU1_R31[3] SA T A_RXN SA T A_VDD SA T A_REFCLKN SA T A_REGSA T A_REFCLKP SA T A_VDD SA T A_VDD SA T A_VDDRSA T A_VDD DVDD3313_C DDR_A[1 1] VP_DOUT[15]/ LCD_D[15]/ UPP_XD[7]/ GP7[7]/ BOOT[7] DVDD3318_C DVDD18 DDR_DVDD18 DDR_DVDD18 DDR_D[15]DDR_RASDDR_CLKPDDR_CLKNDDR_A[2]DDR_A[10] VSS LCD_AC_ENB_CS/ GP6[0]/ PRU1_R31[28] DDR_A[13] DDR_CAS DDR_A[5] DDR_CKE DDR_BA[0] VSS CVDDRVDD DDR_A[9] DDR_A[1] DDR_WE DDR_D[10] DDR_A[7] DDR_A[0] DDR_D[12] DDR_A[12] DDR_A[3] DDR_CS DDR_A[6] DDR_DQM[1] SA T A_VSS CVDD SA T A_VSS DDR_DVDD18 VP_DOUT[12]/ LCD_D[12]/ UPP_XD[4]/ GP7[4]/ BOOT[4] DDR_VREF DDR_BA[1] DDR_A[8] DDR_A[4] DDR_BA[2] SA T A_VSS W V U T R P N M L K DDR_D[13] V SS VSS VSS VSS DVDD18 VSS VSS VSS VSS NC VSS VSS VSS VSS CVDD CVDD VSS DDR_DVDD18DDR_DVDD18DDR_DVDD18DDR_DVDD18DVDD3318_C VP_DOUT[13]/ LCD_D[13]/ UPP_XD[5]/ GP7[5]/ BOOT[5] VP_DOUT[14]/ LCD_D[14]/ UPP_XD[6]/ GP7[6]/ BOOT[6] DDR_DVDD18 DDR_DVDD18 DDR_DVDD18 VP_DOUT[9]/ LCD_D[9]/ UPP_XD[1]/ GP7[1]/ BOOT[1] VP_DOUT[10]/ LCD_D[10]/ UPP_XD[2]/ GP7[2]/ BOOT[2] VP_DOUT[1 1]/ LCD_D[1 1]/ UPP_XD[3]/ GP7[3]/ BOOT[3] VP_DOUT[6]/ LCD_D[6]/ UPP_XD[14]/ GP7[14]/ PRU1_R31[14] VP_DOUT[7]/ LCD_D[7]/ UPP_XD[15]/ GP7[15]/ PRU1_R31[15] VP_DOUT[8]/ LCD_D[8]/ UPP_XD[0]/ GP7[0]/ BOOT[0] VP_DOUT[3]/ LCD_D[3]/ UPP_XD[1 1]/ GP7[1 1]/ PRU1_R31[1 1] VP_DOUT[4]/ LCD_D[4]/ UPP_XD[12]/ GP7[12]/ PRU1_R31[12] VP_DOUT[5]/ LCD_D[5]/ UPP_XD[13]/ GP7[13]/ PRU1_R31[12] VP_DOUT[0]/ LCD_D[0]/ UPP_XD[8]/ GP7[8]/ PRU1_R31[8] VP_DOUT[1]/ LCD_D[1]/ UPP_XD[9]/ GP7[9]/ PRU1_R31[9] VP_DOUT[2]/ LCD_D[2]/ UPP_XD[10]/ GP7[10]/ PRU1_R31[10] OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in the smallest possible package. Pin multiplexing is controlled using a combination of hardware configuration at device reset and software programmable register settings. The following graphics show the bottom view of the ZCE and ZWT packages pin assignments in four quadrants (A, and D). The pin assignments for both packages are identical. Figure 3-3. Pin Map (Quad Submit Documentation Feedback Device Overview

W V U T R P N M L K 191817161514131211 191817161514131211 USB1_VDD33 DVDD3318_CCVDD USB_CVDD DVSS3318_C DDR_DQGATE0 DVDD18DDR_DQGATE1 DDR_D[9] DDR_D[8] DDR_D[11] DVDD18 RTC_CVDD RESET USB0_DM USB0_DP VP_DIN[11]/ UHPI_HD[3]/ UPP_D[3]/ PRU0_R30[11]/ PRU0_R31[11] USB0_VDDA33 USB0_VBUS USB1_DM VP_DIN[0]/ UHPI_HD[8]/ UPP_D[8]/ RMII_CRS_DV/ PRU1_R31[29] VP_DIN[1]/ UHPI_HD[9]/ UPP_D[9]/ RMII_MHZ_50_CLK□/ PRU0_R31[23] VP_DIN[2]/ UHPI_HD[10]/ UPP_D[10]/ RMII_RXER□/ PRU0_R31[24] VP_DIN[4]/ UHPI_HD[12]/ UPP_D[12]/ RMII_RXD[1]/ PRU0_R31[26] PRU0_R30[28]/ UHPI_HCNTL1/ UPP_CHA_START/ GP6[10] USB1_DP PLL0_VDDA12 PRU0_R30[30]□/ PRU1_R30[11]/ GP6[12] UHPI_HINT USB0_VDDA18 VP_DIN[5]/ UHPI_HD[13]/ UPP_D[13]/ RMII_TXEN/ PRU0_R31[27] DDR_D[1] VP_DIN[7]/ UHPI_HD[15]/ UPP_D[15]/ RMII_TXD[1]/ PRU0_R31[29] OSCVSS DDR_D[2] VP_DIN[6]/ UHPI_HD[14]/ UPP_D[14]/ RMII_TXD[0]/ PRU0_R31[28] VP_DIN[3]/ UHPI_HD[11]/ UPP_D[11]/ RMII_RXD[0]/ PRU0_R31[25] VP_DIN[14]_ HSYNC/ UHPI_HD[6]/ UPP_D[6]/ PRU0_R30[14]/ PRU0_R31[14] EMU1 VP_DIN[8]/ UHPI_HD[0]/ UPP_D[0]/ GP6[5]/ PRU1_R31[0] USB0_VDDA12 TDI NC PRU0_R30[26]/ UHPI_HR / UPP_CHA_WAIT/ GP6[8]/ PRU1_R31[17] W VP_DIN[12]/ UHPI_HD[4]/ UPP_D[4]/ PRU0_R30[12]/ PRU0_R31[12] RESETOUT UHPI_HAS PRU1_R30[14]/ GP6[15] RSV2 RTCK/ GP8[0] OSCOUT DDR_D[0] PRU0_R30[27]/ UHPI_HHWIL/ UPP_CHA_ENABLE/ GP6[9] VP_DIN[13]_ FIELD/ UHPI_HD[5]/ UPP_D[5]/ PRU0_R30[13]/ PRU0_R31[13] TRST OSCIN VP_CLKIN1/ PRU1_R30[9]/ GP6[6]/ PRU1_R31[16] UHPI_HDS1 VP_DIN[15]_ VSYNC/ UHPI_HD[7]/ UPP_D[7]/ PRU0_R30[15]/ PRU0_R31[15] VP_CLKIN0/ PRU1_R30[10]/ GP6[7]/ UPP_2xTXCLK UHPI_HCS VP_DIN[10]/ UHPI_HD[2]/ UPP_D[2]/ PRU0_R30[10]/ PRU0_R31[10] VSS DVDD3318_B PLL0_VSSA12 TMS PRU0_R30[31]/ PRU1_R30[12] GP6[13] UHPI_HRDY NC PLL1_VSSA12 PLL1_VDDA12 USB1_VDD18 USB0_ID VP_DIN[9]/ UHPI_HD[1]/ UPP_D[1]/ PRU0_R30[9]/ PRU0_R31[9] CLKOUT/ PRU1_R30[13]/ GP6[14] UHPI_HDS2 USB0_DRVVBUS DDR_DQS[0] PRU0_R30[29]/ UHPI_HCNTL0/ UPP_CHA_CLOCK/ GP6[11] W V U T R P N M L K DDR_DQM[0] DDR_D[3] DDR_D[4] DDR_D[6] DDR_ZP DDR_D[5] DDR_D[7] DDR_D[14] DDR_DQS[1] V SS VSS VSS VSS VSS CVDD DVDD3318_C DVDD3318_C DVDD3318_C OMAP-L138 Low-Power www.ti.com Figure 3-4. Pin Map (Quad Device Overview Submit Documentation Feedback

H G F E D C B A 19181716151413121 1 19181716151413121 1 CVDD EMA_A[8]/ PRU1_R30[16]/ GP5[8] EMA_A[14]/ MMCSD0_DA T[7]/ PRU1_R30[22]/ GP5[14] EMA_A[15]/ MMCSD0_DA T[6]/ PRU1_R30[23]/ GP5[15] EMA_A[10]/ PRU1_R30[18]/ GP5[10] EMA_A[9]/ PRU1_R30[17]/ GP5[9] EMA_A[13]/ PRU0_R30[21]/ PRU1_R30[21] GP5[13] EMA_A[12]/ PRU1_R30[20]/ GP5[12] EMA_A[16]/ MMCSD0_DA T[5]/ PRU1_R30[24]/ GP4[0] EMA_A[18]/ MMCSD0_DA T[3]/ PRU1_R30[26]/ GP4[2]/ PRU1_R31[18] DVDD3318_B DVDD18 EMA_A[6]/ GP5[6] EMA_A[5]/ GP5[5] EMA_A[2]/ GP5[2] EMA_A7/ PRU1_R30[15]/ GP5[7] EMA_A[4]/ GP5[4] SPI0_SIMO/ EPWMSYNCO/ GP8[5]/ MII_CRS SPI0_SCS[5]/ UART0_RXD/ GP8[4]/ MII_RXD[3] SPI1_SCS[1]/ EPWM1A/ PRU0_R30[7]/ GP2[15]/ TM64P2_IN12 SPI0_SCS[4]/ UART0_TXD/ GP8[3]/ MII_RXD[2] SPI0_CLK/ EPWM0A/ GP1[8]/ MII_RXCLK/ SPI1_SCS[3]/ UART1_RXD/ SA T A_LED/ GP1[1] SPI1_SCS[0]/ EPWM1B/ PRU0_R30[8]/ GP2[14]/ TM64P3_IN12 EMA_OE/ GP3[10] SPI1_SCS[4]/ UART2_TXD/ I2C1_SDA/ GP1[2] EMA_A[3]/ GP5[3] DVDD18 RTC_VSS EMA_WAIT[0]/ PRU0_R30[0]/ GP3[8]/ PRU0_R31[0] EMA_RAS/ PRU0_R30[3]/ GP2[5]/ PRU0_R31[3] SPI0_SCS[3] UART0_CTS GP8[2]/ MII_RXD[1]/ SA T A_MP_SWITCH SPI0_SCS[0]/ TM64P1_OUT12/ GP1[6]/ MDIO_D/ TM64P1_IN12 SPI0_SOMI/ EPWMSYNCI/ GP8[6]/ MII_RXER SPI0_SCS[2] UART0_RTS GP8[1]/ MII_RXD[0]/ SA T A_CP_DET SPI1_SCS[7]/ I2C0_SCL/ TM64P2_OUT12/ GP1[15] SPI1_SIMO/ GP2[10] SPI1_CLK/ GP2[13] EMA_CS[3]/ GP3[14] VSS VSS SPI1_ENA/ GP2[12] RTC_XO EMA_CS[2]/ GP3[15] EMA_WAIT[1]/ PRU0_R30[1]/ GP2[1]/ PRU0_R31[1] EMA_A[20]/ MMCSD0_DA T[1]/ PRU1_R30[28]/ GP4[4]/ PRU1_R31[20] EMA_BA[1]/ GP2[9] SPI0_ENA/ EPWM0B/ PRU0_R30[6]/ MII_RXDV EMA_CS[5]/ GP3[12] SPI1_SCS[5]/ UART2_RXD/ I2C1_SCL/ GP1[3] EMA_A[0]/ GP5[0] EMA_BA[0]/ GP2[8] EMA_A[1]/ GP5[1] DVDD3318_B SPI0_SCS[1]/ TM64P0_OUT12/ GP1[7]/ MDIO_CLK/ TM64P0_IN12 DVDD3318_A SPI1_SCS[6]/ I2C0_SDA/ TM64P3_OUT12/ GP1[4] EMA_CS[0]/ GP2[0] CVDD SPI1_SOMI/ GP2[1 1] H G F E D C B A J TDOTCK EMU0 RTC_XINMI J SPI1_SCS[2]/ UART1_TXD/ SA T A_CP_POD/ GP1[0] EMA_A[1 1]/ PRU1_R30[19]/ GP5[1 1] EMA_A[17]/ MMCSD0_DA T[4]/ PRU1_R30[25] GP4[1] DVDD3318_BDVDD3318_B DVDD18 CVDD DVDD3318_A DVDD3318_A RVDDCVDDCVDD VSS CVDD DVDD18 DVDD3318_B OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Figure 3-5. Pin Map (Quad Submit Documentation Feedback Device Overview

J H G F E D C B A 10987654321 10987654321 EMA_D[15]/ GP3[7] AXR15/ EPWM0TZ[0]/ ECAP2_APWM2/ GP0[7] ACLKR/ PRU0_R30[20]/ GP0[15]/ PRU0_R31[22] ACLKX/ PRU0_R30[19]/ GP0[14]/ PRU0_R31[21] AHCLKX/ USB_REFCLKIN/ GP0[10]/ PRU0_R31[17] UART1_CTS AFSX/ GP0[12]/ PRU0_R31[19] AFSR/ GP0[13]/ PRU0_R31[20] AXR9/ DX1/ GP0[1] AXR4/ FSR0/ GP1[12]/ MII_COL AXR5/ CLKX0/ GP1[13]/ MII_TXCLK AXR7/ EPWM1TZ[0]/ PRU0_R30[17] GP1[15]/ PRU0_R31[7] AXR10/ DR1/ GP0[2] AXR1/ DX0/ GP1[19]/ MII_TXD[1] AXR3/ FSX0/ GP1[1 1]/ MII_TXD[3] AXR2/ DR0/ GP2[10]/ MII_TXD[2] MMCSD1_DA T[6]/ LCD_MCLK/ PRU1_R30[6]/ GP8[10]/ PRU1_R31[7] RSVD/ RTC_ALARM/ GP0[8]/ UART2_CTS DEEPSLEEP AXR0/ ECAP0_APWM0/ GP8[7]/ MII_TXD[0]/ CLKS0 PRU0_R30[24]/ MMCSD1_CLK/ UPP_CHB_ST ART/ GP8[14]/ PRU1_R31[26] MMCSD1_DA T[4]/ LCD_VSYNC/ PRU1_R30[4]/ GP8[8]/ PRU1_R31[5] SA T A_VSS PRU0_R30[22]/ PRU1_R30[8]/ UPP_CHB_WAIT/ GP8[12]/ PRU1_R31[24] AXR8/ CLKS1/ ECAP1_APWM1/ GP0[0]/ PRU0_R31[8] AXR12/ FSR1/ GP0[4] EMA_D[4]/ GP4[12] AXR14/ CLKR1/ GP0[6] EMA_WEB_DQM[1]/ GP2[2] EMA_D[0]/ GP4[8] EMA_A[19]/ MMCSD0_DA T[2]/ PRU1_R30[27]/ GP4[3]/ PRU1_R31[19] EMA_D[9]/ GP3[1] EMA_A_R / GP3[9] W EMA_A[23]/ MMCSD0_CLK/ PRU1_R30[31]/ GP4[7]/ PRU1_R31[23] EMA_D[8]/ GP3[0] EMA_D[13]/ GP3[5] VP_CLKIN2/ MMCSD1_DA T[3]/ PRU1_R30[3]/ GP6[4]/ PRU1_R31[4] VP_CLKIN3/ MMCSD1_DA T[1]/ PRU1_R30[1]/ GP6[2]/ PRU1_R31[2] AMUTE/ GP0[9]/ PRU0_R31[16] PRU0_R30[16]/ UART2_RTS/ DVDD3318_A DVDD3318_A EMA_WE/ GP3[1 1] EMA_D[10]/ GP3[2] EMA_D[3]/ GP4[1 1] EMA_SDCKE/ PRU0_R30[4]/ GP2[6]/ PRU0_R31[4] EMA_D[14]/ GP3[6] EMA_D[7]/ GP4[15] EMA_D[1]/ GP4[9] EMA_A[22]/ MMCSD0_CMD/ PRU1_R30[30]/ GP4[6]/ PRU1_R31[22] EMA_D[2]/ GP4[10] EMA_A[21]/ MMCSD0_DA T[0]/ PRU1_R30[29]/ GP4[5]/ PRU1_R31[21] PRU0_R30[23]/ MMCSD1_CMD/ UPP_CHB_ENABLE/ GP8[13]/ PRU1_R31[25] AHCLKR/ GP0[1 1]/ PRU0_R31[18] PRU0_R30[18]/ UART1_RTS EMA_D[12]/ GP3[4] EMA_WEN_DQM[0]/ GP2[3] EMA_CLK/ PRU0_R30[5]/ GP2[7]/ PRU0_R31[5] AXR6/ CLKR0/ GP1[14]/ MII_TXEN/ PRU0_R31[6] AXR1 1/ FSX1/ GP0[3] EMA_D[6]/ GP4[14] EMA_D[1 1]/ GP3[3] RVDD EMA_D[5]/ GP4[13] MMCSD1_DA T[7]/ LCD_PCLK/ PRU1_R30[7]/ GP8[1 1] MMCSD1_DA T[5]/ LCD_HSYNC/ PRU1_R30[5]/ GP8[9]/ PRU1_R31[6] PRU0_R30[25]/ MMCSD1_DA T[0]/ UPP_CHB_CLOCK/ GP8[15]/ PRU1_R31[27] AXR13/ CLKX1/ GP0[5] J H G F E D C B A EMA_CS[4]/ GP3[13] EMA_CAS/ PRU0_R30[2]/ GP2[4]/ PRU0_R31[2] DVDD3318_B DVDD3318_B DVDD3318_B DVDD3318_B DVDD18 CVDD CVDD DVDD3318_B DVDD18 SA T A_VSS DVDD3318_A VSS VSS CVDD CVDD VSS VSS CVDD SA T A_TXP SA T A_TXN DVDD3318_C CVDD VSS VSS 3.8 Pin Multiplexing Control OMAP-L138 Low-Power www.ti.com Figure 3-6. Pin Map (Quad Device level pin multiplexing is controlled by registers PINMUX0 PINMUX19 in the SYSCFG module. For the device family, pin multiplexing can be controlled on a pin-by-pin basis. Each pin that is multiplexed with several different functions has a corresponding 4-bit field in one of the PINMUX registers. Pin multiplexing selects which of several peripheral pin functions controls the pin's IO buffer output data and output enable values only. The default pin multiplexing control for almost every pin is to select 'none' of the peripheral functions in which case the pin's IO buffer is held tri-stated. Note that the input from each pin is always routed to all of the peripherals that share the pin; the PINMUX registers have no effect on input from a pin. Device Overview Submit Documentation Feedback

3.9 Terminal Functions 3.9.1 Device Reset, NMI and JTAG OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 3-4 to Table 3-29 identify the external signal names, the associated pin/ball numbers along with the mechanical package designator, the pin type (I, IO, OZ, or PWR), whether the pin/ball has any internal pullup/pulldown resistors, whether the pin/ball is configurable as an IO in GPIO mode, and a functional pin description. Table 3-4. Reset, NMI and JTAG Terminal Functions SIGNAL POWER TYPE (1) PULL (2) (3) NAME NO. RESET RESET K14 I IPU B Device reset input NMI J17 I IPU B Non-Maskable Interrupt RESETOUT UHPI_HAS PRU1_R30[14] T17 O (4) IPD C Reset output GP6[15] JTAG TMS L16 I IPU B JTAG test mode select TDI M16 I IPU B JTAG test data input TDO J18 O IPU B JTAG test data output TCK J15 I IPU B JTAG test clock TRST L17 I IPD B JTAG test reset EMU[0 J16 I/O IPU B Emulation pin EMU[1] K16 I/O IPU B Emulation pin RTCK GP8[0] K17 I/O IPD B JTAG Test Clock Return Clock Output (1) I Input, O Output, I/O Bidirectional, Z High impedance, PWR Supply voltage, GND Ground, A Analog signal. Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. (2) IPD Internal Pulldown resistor, IPU Internal Pullup resistor (3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power supply DVDD3318_C. (4) Open drain mode for RESETOUT function. Submit Documentation Feedback Device Overview

3.9.2 High-Frequency Oscillator and PLL OMAP-L138 Low-Power www.ti.com Table 3-5. High-Frequency Oscillator and PLL Terminal Functions SIGNAL POWER TYPE (1) PULL (2) (3) NAME NO. CLKOUT UHPI_HDS2 T18 O IPU C PLL Observation Clock PRU1_R30[13] GP6[14] 1.2-V OSCILLATOR OSCIN L19 I Oscillator input OSCOUT K19 O Oscillator output OSCVSS L18 GND Oscillator ground (for filter only) 1.2-V PLL0 PLL0_VDDA L15 PWR PLL analog V DD (1.2-V filtered supply) PLL0_VSSA M17 GND PLL analog V SS (for filter) 1.2-V PLL1 PLL1_VDDA N15 PWR PLL analog V DD (1.2-V filtered supply) PLL1_VSSA M15 GND PLL analog V SS (for filter) (1) I Input, O Output, I/O Bidirectional, Z High impedance, PWR Supply voltage, GND Ground, A Analog signal. Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. (2) IPD Internal Pulldown resistor; IPU Internal Pullup resistor; CP[ n configurable pull-up/pull-down (where n is the pin group) using the PUPDENA and PUPDSEL registers in the System Module. (3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power supply DVDD3318_C. Device Overview Submit Documentation Feedback

3.9.3 Real-Time Clock and 32-kHz Oscillator 3.9.4 DEEPSLEEP Power Control OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 3-6. Real-Time Clock (RTC) and 1.2-V, 32-kHz Oscillator Terminal Functions SIGNAL POWER TYPE (1) PULL (2) (3) NAME NO. RTC_XI J19 I RTC 32-kHz oscillator input RTC_XO H19 O RTC 32-kHz oscillator output RTC_ALARM UART2_CTS GP0[8] DEEPSLEEP O CP[0] A RTC Alarm RTC module core power RTC_CVDD L14 PWR (isolated from chip CV DD RTC_V ss H18 GND Oscillator ground (for filter) (1) I Input, O Output, I/O Bidirectional, Z High impedance, PWR Supply voltage, GND Ground, A Analog signal. Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. (2) IPD Internal Pulldown resistor; IPU Internal Pullup resistor; CP[ n configurable pull-up/pull-down (where n is the pin group) using the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the device is out of reset. During reset, all of the pins associated with these registers are weakly pulled down. If the application requires a pull-up, an external pull-up can be used. (3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power supply DVDD3318_C. Table 3-7. DEEPSLEEP Power Control Terminal Functions SIGNAL POWER TYPE (1) PULL (2) (3) NAME NO. RTC_ALARM UART2_CTS GP0[8] DEEPSLEEP I CP[0] A DEEPSLEEP power control output (1) I Input, O Output, I/O Bidirectional, Z High impedance, PWR Supply voltage, GND Ground, A Analog signal. Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. (2) IPD Internal Pulldown resistor; IPU Internal Pullup resistor; CP[ n configurable pull-up/pull-down (where n is the pin group) using the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the device is out of reset. During reset, all of the pins associated with these registers are weakly pulled down. If the application requires a pull-up, an external pull-up can be used. (3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power supply DVDD3318_C. Submit Documentation Feedback Device Overview

3.9.5 External Memory Interface A (EMIFA) OMAP-L138 Low-Power www.ti.com Table 3-8. External Memory Interface A (EMIFA) Terminal Functions SIGNAL POWER TYPE (1) PULL (2) (3) NAME NO. EMA_D[15] GP3[7] I/O CP[17] B EMA_D[14] GP3[6] I/O CP[17] B EMA_D[13] GP3[5] I/O CP[17] B EMA_D[12] GP3[4] I/O CP[17] B EMA_D[11] GP3[3] I/O CP[17] B EMA_D[10] GP3[2] I/O CP[17] B EMA_D[9] GP3[1] I/O CP[17] B EMA_D[8] GP3[0] E10 I/O CP[17] B EMIFA data bus EMA_D[7] GP4[15] I/O CP[17] B EMA_D[6] GP4[14] I/O CP[17] B EMA_D[5] GP4[13] I/O CP[17] B EMA_D[4] GP4[12] I/O CP[17] B EMA_D[3] GP4[11] I/O CP[17] B EMA_D[2] GP4[10] I/O CP[17] B EMA_D[1] GP4[9] I/O CP[17] B EMA_D[0] GP4[8] I/O CP[17] B (1) I Input, O Output, I/O Bidirectional, Z High impedance, PWR Supply voltage, GND Ground, A Analog signal. Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. (2) IPD Internal Pulldown resistor; IPU Internal Pullup resistor; CP[ n configurable pull-up/pull-down (where n is the pin group) using the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the device is out of reset. During reset, all of the pins associated with these registers are weakly pulled down. If the application requires a pull-up, an external pull-up can be used. (3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power supply DVDD3318_C. Device Overview Submit Documentation Feedback

www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 3-8. External Memory Interface A (EMIFA) Terminal Functions (continued) SIGNAL POWER TYPE (1) PULL (2) (3) NAME NO. EMA_A[23] MMCSD0_CLK O CP[18] B PRU1_R30[31] GP4[7] PRU1_R31[23] EMA_A[22] MMCSD0_CMD A10 O CP[18] B PRU1_R30[30] GP4[6] PRU1_R31[22] EMA_A[21] MMCSD0_DAT[0] B10 O CP[18] B PRU1_R30[29] GP4[5] PRU1_R31[21] EMA_A[20] MMCSD0_DAT[1] A11 O CP[18] B PRU1_R30[28] GP4[4] PRU1_R31[20] EMA_A[19] MMCSD0_DAT[2] C10 O CP[18] B PRU1_R30[27] GP4[3] PRU1_R31[19] EMA_A[18] MMCSD0_DAT[3] E11 O CP[18] B PRU1_R30[26] GP4[2] PRU1_R31[18] EMA_A[17] MMCSD0_DAT[4] B11 O CP[18] B PRU1_R30[25] GP4[1] EMA_A[16] MMCSD0_DAT[5] E12 O CP[18] B PRU1_R30[24] GP4[0] EMA_A[15] MMCSD0_DAT[6] C11 O CP[19] B PRU1_R30[23] GP5[15] EMA_A[14] MMCSD0_DAT[7] EMIFA address bus A12 O CP[19] B PRU1_R30[22] GP5[14] EMA_A[13] /PRU0_R30[21] PRU1_R30[21] D11 O CP[19] B GP5[13] EMA_A[12] PRU1_R30[20] GP5[12] D13 O CP[19] B EMA_A[11] PRU1_R30[19] GP5[11] B12 O CP[19] B EMA_A[10] PRU1_R30[18] GP5[10] C12 O CP[19] B EMA_A[9] PRU1_R30[17] GP5[9] D12 O CP[19] B EMA_A[8] PRU1_R30[16] GP5[8] A13 O CP[19] B EMA_A[7] PRU1_R30[15] GP5[7] B13 O CP[20] B EMA_A[6] GP5[6] E13 O CP[20] B EMA_A[5] GP5[5] C13 O CP[20] B EMA_A[4] GP5[4] A14 O CP[20] B EMA_A[3] GP5[3] D14 O CP[20] B EMA_A[2] GP5[2] B14 O CP[20] B EMA_A[1] GP5[1] D15 O CP[20] B EMA_A[0] GP5[0] C14 O CP[20] B EMA_BA[0] GP2[8] C15 O CP[16] B EMIFA bank address EMA_BA[1] GP2[9] A15 O CP[16] B EMA_CLK PRU0_R30[5] GP2[7] O CP[16] B EMIFA clock PRU0_R31[5] EMA_SDCKE PRU0_R30[4] GP2[6] O CP[16] B EMIFA SDRAM clock enable PRU0_R31[4] EMA_RAS PRU0_R30[3] GP2[5] A16 O CP[16] B EMIFA SDRAM row address strobe PRU0_R31[3] EMA_CAS PRU0_R30[2] GP2[4] O CP[16] B EMIFA SDRAM column address strobe PRU0_R31[2] EMA_CS[0] GP2[0] A18 O CP[16] B EMA_CS[2] GP3[15] B17 O CP[16] B EMA_CS[3] GP3[14] A17 O CP[16] B EMIFA Async Chip Select EMA_CS[4] GP3[13] O CP[16] B EMA_CS[5] GP3[12] B16 O CP[16] B EMA_A_R W GP3[9] D10 O CP[16] B EMIFA Async Read/Write control Submit Documentation Feedback Device Overview

www.ti.com Table 3-8. External Memory Interface A (EMIFA) Terminal Functions (continued) SIGNAL POWER TYPE (1) PULL (2) (3) NAME NO. EMA_WE GP3[11] O CP[16] B EMIFA SDRAM write enable EMIFA write enable/data mask for EMA_WEN_DQM[1] GP2[2] O CP[16] B EMA_D[15:8] EMA_WEN_DQM[0] GP2[3] O CP[16] B EMIFA write enable/data mask for EMA_D[7:0] EMA_OE GP3[10] B15 O CP[16] B EMIFA output enable EMA_WAIT[0] PRU0_R30[0] GP3[8] B18 I CP[16] B PRU0_R31[0] EMIFA wait input/interrupt EMA_WAIT[1] PRU0_R30[1] GP2[1] B19 I CP[16] B PRU0_R31[1] Device Overview Submit Documentation Feedback

3.9.6 DDR2 Controller (DDR2) OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 3-9. DDR2 Controller (DDR2) Terminal Functions SIGNAL TYPE (1) PULL (2) NO. DDR_D[15] W10 I/O IPD DDR_D[14] U11 I/O IPD DDR_D[13] V10 I/O IPD DDR_D[12] U10 I/O IPD DDR_D[11] T12 I/O IPD DDR_D[10] T10 I/O IPD DDR_D[9] T11 I/O IPD DDR_D[8] T13 I/O IPD DDR2 SDRAM data bus DDR_D[7] W11 I/O IPD DDR_D[6] W12 I/O IPD DDR_D[5] V12 I/O IPD DDR_D[4] V13 I/O IPD DDR_D[3] U13 I/O IPD DDR_D[2] V14 I/O IPD DDR_D[1] U14 I/O IPD DDR_D[0] U15 I/O IPD DDR_A[13] O IPD DDR_A[12] O IPD DDR_A[11] O IPD DDR_A[10] O IPD DDR_A[9] O IPD DDR_A[8] O IPD DDR_A[7] O IPD DDR2 row/column address DDR_A[6] O IPD DDR_A[5] O IPD DDR_A[4] O IPD DDR_A[3] O IPD DDR_A[2] O IPD DDR_A[1] O IPD DDR_A[0] O IPD DDR_CLKP O IPD DDR2 clock (positive) DDR_CLKN O IPD DDR2 clock (negative) DDR_CKE O IPD DDR2 clock enable DDR_WE O IPD DDR2 write enable DDR_RAS O IPD DDR2 row address strobe DDR_CAS O IPD DDR2 column address strobe DDR_CS O IPD DDR2 chip select DDR_DQM[0] W13 O IPD DDR2 data mask outputs DDR_DQM[1] R10 O IPD (1) I Input, O Output, I/O Bidirectional, Z High impedance, PWR Supply voltage, GND Ground, A Analog signal. Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. (2) IPD Internal Pulldown resistor; IPU Internal Pullup resistor; CP[ n configurable pull-up/pull-down (where n is the pin group) using the PUPDENA and PUPDSEL registers in the System Module. Submit Documentation Feedback Device Overview

www.ti.com Table 3-9. DDR2 Controller (DDR2) Terminal Functions (continued) SIGNAL TYPE (1) PULL (2) NO. DDR_DQS[0] T14 I/O IPD DDR2 data strobe inputs/outputs DDR_DQS[1] V11 I/O IPD DDR_BA[2] O IPD DDR_BA[1] O IPD DDR2 SDRAM bank address DDR_BA[0] O IPD DDR2 loopback signal for external DQS gating. DDR_DQGATE0 R11 O IPD Route to DDR and back to DDR_DQGATE1 with same constraints as used for DDR clock and data. DDR2 loopback signal for external DQS gating. DDR_DQGATE1 R12 I IPD Route to DDR and back to DDR_DQGATE0 with same constraints as used for DDR clock and data. DDR2 reference output for drive strength calibration DDR_ZP U12 O of N and P channel outputs. Tie to ground via ohm resistor 0.5% tolerance. DDR voltage input for the DDR2/mDDR I/O buffers. DDR_VREF I Note even in the case of mDDR an external resistor divider connected to this pin is necessary. N6, N9, N10, P7, P8, P9, DDR_DVDD18 PWR DDR PHY 1.8V power supply pins P10, R7, R8, Device Overview Submit Documentation Feedback

3.9.7 Serial Peripheral Interface Modules (SPI) OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 3-10. Serial Peripheral Interface (SPI) Terminal Functions SIGNAL POWER TYPE (1) PULL (2) (3) NAME NO. SPI0 SPI0_CLK EPWM0A GP1[8] MII_RXCLK D19 O CP[7] A SPI0 clock SPI0_ENA EPWM0B PRU0_R30[6] MII_RXDV C17 O CP[7] A SPI0 enable SPI0_SCS[0] TM64P1_OUT12 GP1[6] MDIO_D TM64P1_IN12 D17 O CP[10] A SPI0_SCS[1] TM64P0_OUT12 GP1[7] MDIO_CLK E16 O CP[10] A TM64P0_IN12 SPI0_SCS[2] UART0_RTS GP8[1] MII_RXD[0] /SATA_CP_DET D16 O CP[9] A SPI0 chip selects SPI0_SCS[3] UART0_CTS GP8[2] MII_RXD[1] E17 O CP[9] A SATA_MP_SWITCH SPI0_SCS[4] UART0_TXD GP8[3] MII_RXD[2] D18 O CP[8] A SPI0_SCS[5] UART0_RXD GP8[4] MII_RXD[3] C19 O CP[8] A SPI0 data SPI0_SIMO EPWMSYNCO GP8[5] MII_CRS C18 I/O/Z CP[7] A slave-in-master-out SPI0 data SPI0_SOMI EPWMSYNCI GP8[6] MII_RXER C16 I/O/Z CP[7] A slave-out-master-in SPI1 SPI1_CLK GP2[13] G19 O CP[15] A SPI1 clock SPI1_ENA GP2[12] H16 O CP[15] A SPI1 enable SPI1_SCS[0] EPWM1B PRU0_R30[8] GP2[14] TM64P3_IN12 E19 O CP[14] A SPI1_SCS[1] EPWM1A PRU0_R30[7] GP2[15] TM64P2_IN12 F18 O CP[14] A SPI1_SCS[2] UART1_TXD SATA_CP_POD GP1[0] F19 O CP[13] A SPI1_SCS[3] UART1_RXD SATA_LED GP1[1] E18 O CP[13] A SPI1 chip selects SPI1_SCS[4] UART2_TXD I2C1_SDA GP1[2] F16 O CP[12] A SPI1_SCS[5] UART2_RXD I2C1_SCL GP1[3] F17 O CP[12] A SPI1_SCS[6] I2C0_SDA TM64P3_OUT12 GP1[4] G18 O CP[11] A SPI1_SCS[7] I2C0_SCL TM64P2_OUT12 GP1[5] G16 O CP[11] A SPI1 data SPI1_SIMO GP2[10] G17 I/O/Z CP[15] A slave-in-master-out SPI1 data SPI1_SOMI GP2[11] H17 I/O/Z CP[15] A slave-out-master-in (1) I Input, O Output, I/O Bidirectional, Z High impedance, PWR Supply voltage, GND Ground, A Analog signal. Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. (2) IPD Internal Pulldown resistor; IPU Internal Pullup resistor; CP[ n configurable pull-up/pull-down (where n is the pin group) using the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the device is out of reset. During reset, all of the pins associated with these registers are weakly pulled down. If the application requires a pull-up, an external pull-up can be used. (3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power supply DVDD3318_C. Submit Documentation Feedback Device Overview

3.9.8 Programmable Real-Time Unit (PRU) OMAP-L138 Low-Power www.ti.com Table 3-11. Programmable Real-Time Unit (PRU) Terminal Functions SIGNAL POWER TYPE (1) PULL (2) (3) NAME NO. PRU0 Output Signals (1) I Input, O Output, I/O Bidirectional, Z High impedance, PWR Supply voltage, GND Ground, A Analog signal. Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. (2) IPD Internal Pulldown resistor; IPU Internal Pullup resistor; CP[ n configurable pull-up/pull-down (where n is the pin group) using the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the device is out of reset. During reset, all of the pins associated with these registers are weakly pulled down. If the application requires a pull-up, an external pull-up can be used. (3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power supply DVDD3318_C. Device Overview Submit Documentation Feedback

www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 3-11. Programmable Real-Time Unit (PRU) Terminal Functions (continued) SIGNAL POWER TYPE (1) PULL (2) (3) NAME NO. PRU0_R30[31] UHPI_HRDY PRU1_R30[12] GP6[13] R17 O CP[23] C PRU0_R30[30] UHPI_HINT PRU1_R30[11] GP6[12] R16 O CP[23] C PRU0_R30[29] UHPI_HCNTL0 UPP_CHA_CLOCK GP6[11] U17 O CP[24] C PRU0_R30[28] UHPI_HCNTL1 UPP_CHA_START GP6[10] W15 O CP[24] C PRU0_R30[27] UHPI_HHWIL UPP_CHA_ENABLE GP6[9] U16 O CP[24] C PRU0_R30[26] UHPI_HR W UPP_CHA_WAIT GP6[8] T15 O CP[24] C PRU1_R31[17] PRU0_R30[25] MMCSD1_DAT[0] UPP_CHB_CLOCK GP8[15] O CP30] C PRU1_R31[27] PRU0_R30[24] MMCSD1_CLK UPP_CHB_START GP8[14] O CP[30] C PRU1_R31[26] PRU0_R30[23] MMCSD1_CMD UPP_CHB_ENABLE GP8[13] O CP[30] C PRU1_R31[25] PRU0_R30[22] PRU1_R30[8] UPP_CHB_WAIT GP8[12] O CP[30] C PRU1_R31[24] EMA_A[13] PRU0_R30[21] PRU1_R30[21] GP5[13] D11 O CP[19] B ACLKR PRU0_R30[20] GP0[15] PRU0_R31[22] O CP[0] A ACLKX PRU0_R30[19] GP0[14] PRU0_R31[21] O CP[0] A AHCLKR PRU0_R30[18] UART1_RTS GP0[11] PRU0_R31[18] O CP[0] A AXR7 EPWM1TZ[0] PRU0_R30[17] GP1[15] PRU0_R31[7] O CP[4] A AMUTE PRU0_R30[16] UART2_RTS GP0[9] PRU0_R31[16] O CP[0] A PRU0 Output Signals VP_DIN[15]_VSYNC UHPI_HD[7] UPP_D[7] PRU0_R30[15] V18 O CP[27] C PRU0_R31[15] VP_DIN[14]_HSYNC UHPI_HD[6] UPP_D[6] PRU0_R30[14] V19 O CP[27] C PRU0_R31[14] VP_DIN[13]_FIELD UHPI_HD[5] UPP_D[5] PRU0_R30[13] U19 O CP[27] C PRU0_R31[13] VP_DIN[12] UHPI_HD[4] UPP_D[4] PRU0_R30[12] T16 O CP[27] C PRU0_R31[12] VP_DIN[11] UHPI_HD[3] UPP_D[3] PRU0_R30[11] R18 O CP[27] C PRU0_R31[11] VP_DIN[10] UHPI_HD[2] UPP_D[2] PRU0_R30[10] R19 O CP[27] C PRU0_R31[10] VP_DIN[9] UHPI_HD[1] UPP_D[1] PRU0_R30[9] PRU0_R31[9] R15 O CP[27] C SPI1_SCS[0] EPWM1B PRU0_R30[8] GP2[14] TM64P3_IN12 E19 O CP[14] A SPI1_SCS[1] EPWM1A PRU0_R30[7] GP2[15] TM64P2_IN12 F18 O CP[14] A SPI0_ENA EPWM0B PRU0_R30[6] MII_RXDV C17 O CP[7] A EMA_CLK PRU0_R30[5] GP2[7] PRU0_R31[5] O CP[16] B EMA_SDCKE PRU0_R30[4] GP2[6] PRU0_R31[4] O CP[16] B EMA_RAS PRU0_R30[3] GP2[5] PRU0_R31[3] A16 O CP[16] B EMA_CAS PRU0_R30[2] GP2[4] PRU0_R31[2] O CP[16] B EMA_WAIT[1] PRU0_R30[1] GP2[1] PRU0_R31[1] B19 O CP[16] B EMA_WAIT[0] PRU0_R30[0] GP3[8] PRU0_R31[0] B18 O CP[16] B PRU0 Input Signals Submit Documentation Feedback Device Overview

www.ti.com Table 3-11. Programmable Real-Time Unit (PRU) Terminal Functions (continued) SIGNAL POWER TYPE (1) PULL (2) (3) NAME NO. VP_DIN[7] UHPI_HD[15] UPP_D[15] RMII_TXD[1] U18 I CP[26] C PRU0_R31[29] VP_DIN[6] UHPI_HD[14] UPP_D[14] RMII_TXD[0] V16 I CP[26] C PRU0_R31[28] VP_DIN[5] UHPI_HD[13] UPP_D[13] RMII_TXEN R14 I CP[26] C PRU0_R31[27] VP_DIN[4] UHPI_HD[12] UPP_D[12] RMII_RXD[1] W16 I CP[26] C PRU0_R31[26] VP_DIN[3] UHPI_HD[11] UPP_D[11] RMII_RXD[0] V17 I CP[26] C PRU0_R31[25] VP_DIN[2] UHPI_HD[10] UPP_D[10] RMII_RXER W17 I CP[26] C PRU0_R31[24] VP_DIN[1] UHPI_HD[9] UPP_D[9] RMII_MHZ_50_CLK W18 I CP[26] C PRU0_R31[23] ACLKR PRU0_R30[20] GP0[15] PRU0_R31[22] I CP[0] A ACLKX PRU0_R30[19] GP0[14] PRU0_R31[21] I CP[0] A AFSR GP0[13] PRU0_R31[20] I CP[0] A AFSX GP0[12] PRU0_R31[19] I CP[0] A AHCLKR PRU0_R30[18] UART1_RTS GP0[11] PRU0_R31[18] I CP[0] A AHCLKX USB_REFCLKIN UART1_CTS GP0[10] I CP[0] A PRU0_R31[17] AMUTE PRU0_R30[16] UART2_RTS GP0[9] PRU0_R31[16] I CP[0] A PRU0 Input Signals VP_DIN[15]_VSYNC UHPI_HD[7] UPP_D[7] PRU0_R30[15] V18 I CP[27] C PRU0_R31[15] VP_DIN[14]_HSYNC UHPI_HD[6] UPP_D[6] PRU0_R30[14] V19 I CP[27] C PRU0_R31[14] VP_DIN[13]_FIELD UHPI_HD[5] UPP_D[5] PRU0_R30[13] U19 I CP[27] C PRU0_R31[13] VP_DIN[12] UHPI_HD[4] UPP_D[4] PRU0_R30[12] T16 I CP[27] C PRU0_R31[12] VP_DIN[11] UHPI_HD[3] UPP_D[3] PRU0_R30[11] R18 I CP[27] C PRU0_R31[11] VP_DIN[10] UHPI_HD[2] UPP_D[2] PRU0_R30[10] R19 I CP[27] C PRU0_R31[10] VP_DIN[9] UHPI_HD[1] UPP_D[1] PRU0_R30[9] PRU0_R31[9] R15 I CP[27] C AXR8 CLKS1 ECAP1_APWM1 GP0[0] PRU0_R31[8] I CP[3] A AXR7 EPWM1TZ[0] PRU0_R30[17] GP1[15] PRU0_R31[7] I CP[4] A AXR6 CLKR0 GP1[14] MII_TXEN PRU0_R31[6] I CP[5] A EMA_CLK PRU0_R30[5] GP2[7] PRU0_R31[5] I CP[16] B EMA_SDCKE PRU0_R30[4] GP2[6] PRU0_R31[4] I CP[16] B EMA_RAS PRU0_R30[3] GP2[5] PRU0_R31[3] A16 I CP[16] B EMA_CAS PRU0_R30[2] GP2[4] PRU0_R31[2] I CP[16] B EMA_WAIT[1] PRU0_R30[1] GP2[1] PRU0_R31[1] B19 I CP[16] B EMA_WAIT[0] PRU0_R30[0] GP3[8] PRU0_R31[0] B18 I CP[16] B PRU1 Output Signals Device Overview Submit Documentation Feedback

www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 3-11. Programmable Real-Time Unit (PRU) Terminal Functions (continued) SIGNAL POWER TYPE (1) PULL (2) (3) NAME NO. EMA_A[23] MMCSD0_CLK PRU1_R30[31] /GP4[7] O CP[18] B PRU1_R31[23] EMA_A[22] MMCSD0_CMD PRU1_R30[30] GP4[6] A10 O CP[18] B PRU1_R31[22] EMA_A[21] MMCSD0_DAT[0] PRU1_R30[29] GP4[5] B10 O CP[18] B PRU1_R31[21] EMA_A[20] MMCSD0_DAT[1] PRU1_R30[28] GP4[4] A11 O CP[18] B PRU1_R31[20] EMA_A[19] MMCSD0_DAT[2] PRU1_R30[27] GP4[3] C10 O CP[18] B PRU1_R31[19] EMA_A[18] MMCSD0_DAT[3] PRU1_R30[26] GP4[2] E11 O CP[18] B PRU1_R31[18] EMA_A[17] MMCSD0_DAT[4] PRU1_R30[25] GP4[1] B11 O CP[18] B EMA_A[16] MMCSD0_DAT[5] PRU1_R30[24] GP4[0] E12 O CP[18] B EMA_A[15] MMCSD0_DAT[6] PRU1_R30[23] GP5[15] C11 O CP[19] B EMA_A[14] MMCSD0_DAT[7] PRU1_R30[22] GP5[14] A12 O CP[19] B EMA_A[13] PRU0_R30[21] PRU1_R30[21] GP5[13] D11 O CP[19] B EMA_A[12] PRU1_R30[20] GP5[12] D13 O CP[19] B EMA_A[11] PRU1_R30[19] GP5[11] B12 O CP[19] B EMA_A[10] PRU1_R30[18] GP5[10] C12 O CP[19] B EMA_A[9] PRU1_R30[17] GP5[9] D12 O CP[19] B EMA_A[8] PRU1_R30[16] GP5[8] A13 O CP[19] B EMA_A[7] PRU1_R30[15] GP5[7] B13 O CP[20] B PRU1 Output Signals RESETOUT UHPI_HAS PRU1_R30[14] GP6[15] T17 O CP[21] C CLKOUT UHPI_HDS2 PRU1_R30[13] GP6[14] T18 O CP[22] C PRU0_R30[31] UHPI_HRDY PRU1_R30[12] GP6[13] R17 O CP[23] C PRU0_R30[30] UHPI_HINT PRU1_R30[11] GP6[12] R16 O CP[23] C VP_CLKIN0 UHPI_HCS PRU1_R30[10] GP6[7] W14 O CP[25] C UPP_2xTXCLK VP_CLKIN1 UHPI_HDS1 PRU1_R30[9] GP6[6] PRU1_R31[16] V15 O CP[25] C PRU0_R30[22] PRU1_R30[8] UPP_CHB_WAIT GP8[12] O CP[30] C PRU1_R31[24] MMCSD1_DAT[7] LCD_PCLK PRU1_R30[7] GP8[11] O CP[31] C MMCSD1_DAT[6] LCD_MCLK PRU1_R30[6] GP8[10] O CP[31] C PRU1_R31[7] MMCSD1_DAT[5] LCD_HSYNC PRU1_R30[5] GP8[9] O CP[31] C PRU1_R31[6] MMCSD1_DAT[4] LCD_VSYNC PRU1_R30[4] GP8[8] O CP[31] C PRU1_R31[5] VP_CLKIN2 MMCSD1_DAT[3] PRU1_R30[3] GP6[4] O CP[30] C PRU1_R31[4] VP_CLKOUT2 MMCSD1_DAT[2] PRU1_R30[2] GP6[3] O CP[30] C PRU1_R31[3] VP_CLKIN3 MMCSD1_DAT[1] PRU1_R30[1] GP6[2] O CP[30] C PRU1_R31[2] VP_CLKOUT3 PRU1_R30[0] GP6[1] PRU1_R31[1] O CP[30] C PRU1 Input Signals Submit Documentation Feedback Device Overview

www.ti.com Table 3-11. Programmable Real-Time Unit (PRU) Terminal Functions (continued) SIGNAL POWER TYPE (1) PULL (2) (3) NAME NO. VP_DIN[0] UHPI_HD[8] UPP_D[8] RMII_CRS_DV W19 I CP[26] C PRU1_R31[29] LCD_AC_ENB_CS GP6[0] PRU1_R31[28] I CP[31] C PRU0_R30[25] MMCSD1_DAT[0] UPP_CHB_CLOCK GP8[15] I CP[30] C PRU1_R31[27] PRU0_R30[24] MMCSD1_CLK UPP_CHB_START GP8[14] I CP[30] C PRU1_R31[26] PRU0_R30[23] MMCSD1_CMD UPP_CHB_ENABLE GP8[13] I CP[30] C PRU1_R31[25] PRU0_R30[22] PRU1_R30[8] UPP_CHB_WAIT GP8[12] I CP[30] C PRU1_R31[24] EMA_A[23] MMCSD0_CLK PRU1_R30[31] /GP4[7] I CP[18] B PRU1_R31[23] EMA_A[22] MMCSD0_CMD PRU1_R30[30] GP4[6] A10 I CP[18] B PRU1_R31[22] EMA_A[21] MMCSD0_DAT[0] PRU1_R30[29] GP4[5] B10 I CP[18] B PRU1_R31[21] EMA_A[20] MMCSD0_DAT[1] PRU1_R30[28] GP4[4] A11 I CP[18] B PRU1_R31[20] EMA_A[19] MMCSD0_DAT[2] PRU1_R30[27] GP4[3] C10 I CP[18] B PRU1_R31[19] EMA_A[18] MMCSD0_DAT[3] PRU1_R30[26] GP4[2] E11 I CP[18] B PRU1_R31[18] PRU0_R30[26] UHPI_HR W UPP_CHA_WAIT GP6[8] T15 I CP[24] C PRU1_R31[17] PRU1 Input Signals VP_CLKIN1 UHPI_HDS1 PRU1_R30[9] GP6[6] PRU1_R31[16] V15 I CP[25] C VP_DOUT[7] LCD_D[7] UPP_XD[15] GP7[15] PRU1_R31[15] I CP[28] C VP_DOUT[6] LCD_D[6] UPP_XD[14] GP7[14] PRU1_R31[14] I CP[28] C VP_DOUT[5] LCD_D[5] UPP_XD[13] GP7[13] PRU1_R31[13] I CP[28] C VP_DOUT[4] LCD_D[4] UPP_XD[12] GP7[12] PRU1_R31[12] I CP[28] C VP_DOUT[3] LCD_D[3] UPP_XD[11] GP7[11] PRU1_R31[11] I CP[28] C VP_DOUT[2] LCD_D[2] UPP_XD[10] GP7[10] PRU1_R31[10] I CP[28] C VP_DOUT[1] LCD_D[1] UPP_XD[9] GP7[9] PRU1_R31[9] I CP[28] C VP_DOUT[0] LCD_D[0] UPP_XD[8] GP7[8] PRU1_R31[8] I CP[28] C MMCSD1_DAT[6] LCD_MCLK PRU1_R30[6] GP8[10] I CP[31] C PRU1_R31[7] MMCSD1_DAT[5] LCD_HSYNC PRU1_R30[5] GP8[9] I CP[31] C PRU1_R31[6] MMCSD1_DAT[4] LCD_VSYNC PRU1_R30[4] GP8[8] I CP[31] C PRU1_R31[5] VP_CLKIN2 MMCSD1_DAT[3] PRU1_R30[3] GP6[4] I CP[30] C PRU1_R31[4] VP_CLKOUT2 MMCSD1_DAT[2] PRU1_R30[2] GP6[3] I CP[30] C PRU1_R31[3] VP_CLKIN3 MMCSD1_DAT[1] PRU1_R30[1] GP6[2] I CP[30] C PRU1_R31[2] VP_CLKOUT3 PRU1_R30[0] GP6[1] PRU1_R31[1] I CP[30] C VP_DIN[8] UHPI_HD[0] UPP_D[0] GP6[5] PRU1_R31[0] P17 I CP[27] C Device Overview Submit Documentation Feedback

3.9.9 Enhanced Capture/Auxiliary PWM Modules (eCAP0) OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 The eCAP Module pins function as either input captures or auxiliary PWM 32-bit outputs, depending upon how the eCAP module is programmed. Table 3-12. Enhanced Capture Module (eCAP) Terminal Functions SIGNAL POWER TYPE (1) PULL (2) (3) NAME NO. eCAP0 enhanced capture input or AXR0 ECAP0_APWM0 GP8[7] MII_TXD[0] CLKS0 I/O CP[6] A auxiliary PWM output eCAP1 enhanced capture input or AXR8 CLKS1 ECAP1_APWM1 GP0[0] PRU0_R31[8] I/O CP[3] A auxiliary PWM output eCAP2 enhanced capture input or AXR15 EPWM0TZ[0] ECAP2_APWM2 GP0[7] I/O CP[1] A auxiliary PWM output (1) I Input, O Output, I/O Bidirectional, Z High impedance, PWR Supply voltage, GND Ground, A Analog signal. Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. (2) IPD Internal Pulldown resistor; IPU Internal Pullup resistor; CP[ n configurable pull-up/pull-down (where n is the pin group) using the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the device is out of reset. During reset, all of the pins associated with these registers are weakly pulled down. If the application requires a pull-up, an external pull-up can be used. (3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power supply DVDD3318_C. Submit Documentation Feedback Device Overview

3.9.10 Enhanced Pulse Width Modulators (eHRPWM) OMAP-L138 Low-Power www.ti.com Table 3-13. Enhanced Pulse Width Modulator (eHRPWM) Terminal Functions SIGNAL POWER TYPE (1) PULL (2) (3) NAME NO. eHRPWM0 eHRPWM0 A output SPI0_CLK EPWM0A GP1[8] MII_RXCLK D19 I/O CP[7] A (with high-resolution) SPI0_ENA EPWM0B PRU0_R30[6] MII_RXDV C17 I/O CP[7] A eHRPWM0 B output AXR15 EPWM0TZ[0] ECAP2_APWM2 GP0[7] I/O CP[1] A eHRPWM0 trip zone input SPI0_SOMI EPWMSYNCI GP8[6] MII_RXER C16 I/O CP[7] A eHRPWM0 sync input SPI0_SIMO EPWMSYNCO GP8[5] MII_CRS C18 I/O CP[7] A eHRPWM0 sync output eHRPWM1 SPI1_SCS[1] EPWM1A PRU0_R30[7] GP2[15] eHRPWM1 A output F18 I/O CP[14] A TM64P2_IN12 (with high-resolution) SPI1_SCS[0] EPWM1B PRU0_R30[8] GP2[14] E19 I/O CP[14] A eHRPWM1 B output TM64P3_IN12 AXR7 EPWM1TZ[0] PRU0_R30[17] GP1[15] I/O CP[4] A eHRPWM1 trip zone input PRU0_R31[7] (1) I Input, O Output, I/O Bidirectional, Z High impedance, PWR Supply voltage, GND Ground, A Analog signal. Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. (2) IPD Internal Pulldown resistor; IPU Internal Pullup resistor; CP[ n configurable pull-up/pull-down (where n is the pin group) using the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the device is out of reset. During reset, all of the pins associated with these registers are weakly pulled down. If the application requires a pull-up, an external pull-up can be used. (3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power supply DVDD3318_C. Device Overview Submit Documentation Feedback

3.9.11 Boot OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 3-14. Boot Mode Selection Terminal Functions (1) SIGNAL POWER TYPE (2) PULL (3) (4) NAME NO. VP_DOUT[15/]/ LCD_D[15]/ UPP_XD[7] GP7[7] BOOT[7] I CP[29] C VP_DOUT[14] LCD_D[14] UPP_XD[6] GP7[6] BOOT[6] I CP[29] C VP_DOUT[13] LCD_D[13] UPP_XD[5] GP7[5] BOOT[5] I CP[29] C VP_DOUT[12] LCD_D[12] UPP_XD[4] GP7[4] BOOT[4] I CP[29] C Boot Mode Selection Pins VP_DOUT[11] LCD_D[11] UPP_XD[3] GP7[3] BOOT[3] I CP[29] C VP_DOUT[10] LCD_D[10] UPP_XD[2] GP7[2] BOOT[2] I CP[29] C VP_DOUT[9] LCD_D[9] UPP_XD[1] GP7[1] BOOT[1] I CP[29] C VP_DOUT[8] LCD_D[8] UPP_XD[0] GP7[0] BOOT[0] I CP[29] C (1) Boot decoding is defined in the bootloader application report. (2) I Input, O Output, I/O Bidirectional, Z High impedance, PWR Supply voltage, GND Ground, A Analog signal. Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. (3) IPD Internal Pulldown resistor; IPU Internal Pullup resistor; CP[ n configurable pull-up/pull-down (where n is the pin group) using the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the device is out of reset. During reset, all of the pins associated with these registers are weakly pulled down. If the application requires a pull-up, an external pull-up can be used. (4) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power supply DVDD3318_C. Submit Documentation Feedback Device Overview

3.9.12 Universal Asynchronous Receiver/Transmitters (UART0 UART1, UART2 OMAP-L138 Low-Power www.ti.com Table 3-15. Universal Asynchronous Receiver/Transmitter (UART) Terminal Functions SIGNAL POWER TYPE (1) PULL (2) (3) NAME NO. UART0 SPI0_SCS[5] UART0_RXD GP8[4] MII_RXD[3] C19 I CP[8] A UART0 receive data SPI0_SCS[4] UART0_TXD GP8[3] MII_RXD[2] D18 O CP[8] A UART0 transmit data SPI0_SCS[2] UART0_RTS GP8[1] MII_RXD[0] D16 O CP[9] A UART0 ready-to-send output SATA_CP_DET SPI0_SCS[3] UART0_CTS GP8[2] MII_RXD[1] E17 I CP[9] A UART0 clear-to-send input SATA_MP_SWITCH UART1 SPI1_SCS[3] UART1_RXD SATA_LED GP1[1] E18 I CP[13] A UART1 receive data SPI1_SCS[2] UART1_TXD SATA_CP_POD GP1[0] F19 O CP[13] A UART1 transmit data AHCLKR PRU0_R30[18] UART1_RTS /GP0[11] O CP[0] A UART1 ready-to-send output PRU0_R31[18] AHCLKX USB_REFCLKIN UART1_CTS GP0[10] I CP[0] A UART1 clear-to-send input PRU0_R31[17] UART2 SPI1_SCS[5] UART2_RXD I2C1_SCL GP1[3] F17 I CP[12] A UART2 receive data SPI1_SCS[4] UART2_TXD I2C1_SDA GP1[2] F16 O CP[12] A UART2 transmit data AMUTE PRU0_R30[16] UART2_RTS GP0[9] O CP[0] A UART2 ready-to-send output PRU0_R31[16] RSVD /RTC_ALARM UART2_CTS GP0[8] DEEPSLEEP I CP[0] A UART2 clear-to-send input (1) I Input, O Output, I/O Bidirectional, Z High impedance, PWR Supply voltage, GND Ground, A Analog signal. Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. (2) IPD Internal Pulldown resistor; IPU Internal Pullup resistor; CP[ n configurable pull-up/pull-down (where n is the pin group) using the PUPDENA and PUPDSEL registers in the System Module.The pull-up and pull-down control of these pins is not active until the device is out of reset. During reset, all of the pins associated with these registers are weakly pulled down. If the application requires a pull-up, an external pull-up can be used. (3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power supply DVDD3318_C. Device Overview Submit Documentation Feedback

3.9.13 Inter-Integrated Circuit Modules(I2C0 I2C1 OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 3-16. Inter-Integrated Circuit (I2C) Terminal Functions SIGNAL POWER TYPE (1) PULL (2) (3) NAME NO. I2C0 SPI1_SCS[6] I2C0_SDA TM64P3_OUT12 GP1[4] G18 I/O CP[11] A I2C0 serial data SPI1_SCS[7] I2C0_SCL TM64P2_OUT12 GP1[5] G16 I/O CP[11] A I2C0 serial clock I2C1 SPI1_SCS[4] UART2_TXD I2C1_SDA GP1[2] F16 I/O CP[12] A I2C1 serial data SPI1_SCS[5] UART2_RXD I2C1_SCL GP1[3] F17 I/O CP[12] A I2C1 serial clock (1) I Input, O Output, I/O Bidirectional, Z High impedance, PWR Supply voltage, GND Ground, A Analog signal. Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. (2) IPD Internal Pulldown resistor; IPU Internal Pullup resistor; CP[ n configurable pull-up/pull-down (where n is the pin group) using the PUPDENA and PUPDSEL registers in the System Module.The pull-up and pull-down control of these pins is not active until the device is out of reset. During reset, all of the pins associated with these registers are weakly pulled down. If the application requires a pull-up, an external pull-up can be used. (3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power supply DVDD3318_C. Submit Documentation Feedback Device Overview

3.9.14 Timers OMAP-L138 Low-Power www.ti.com Table 3-17. Timers Terminal Functions SIGNAL POWER TYPE (1) PULL (2) (3) NAME NO. TIMER0 SPI0_SCS[1] TM64P0_OUT12 GP1[7] MDIO_CLK TM64P0_IN12 E16 I CP[10] A Timer0 lower input. Timer0 lower SPI0_SCS[1] TM64P0_OUT12 GP1[7] MDIO_CLK TM64P0_IN12 E16 O CP[10] A output TIMER1 (Watchdog) SPI0_SCS[0] TM64P1_OUT12 GP1[6] MDIO_D TM64P1_IN12 D17 I CP[10] A Timer1 lower input. Timer1 lower SPI0_SCS[0] TM64P1_OUT12 GP1[6] MDIO_D TM64P1_IN12 D17 O CP[10] A output TIMER2 SPI1_SCS[1] EPWM1A PRU0_R30[7] GP2[15] TM64P2_IN12 F18 I CP[14] A Timer2 lower input. Timer2 lower SPI1_SCS[7] I2C0_SCL TM64P2_OUT12 GP1[5] G16 O CP[11] A output TIMER3 SPI1_SCS[0] EPWM1B PRU0_R30[8] GP2[14] TM64P3_IN12 E19 I CP[14] A Timer3 lower input. Timer3 lower SPI1_SCS[6] I2C0_SDA TM64P3_OUT12 GP1[4] G18 O CP[11] A output (1) I Input, O Output, I/O Bidirectional, Z High impedance, PWR Supply voltage, GND Ground, A Analog signal. Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. (2) IPD Internal Pulldown resistor; IPU Internal Pullup resistor; CP[ n configurable pull-up/pull-down (where n is the pin group) using the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the device is out of reset. During reset, all of the pins associated with these registers are weakly pulled down. If the application requires a pull-up, an external pull-up can be used. (3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power supply DVDD3318_C. Device Overview Submit Documentation Feedback

3.9.15 Multichannel Audio Serial Ports (McASP) OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 3-18. Multichannel Audio Serial Ports Terminal Functions SIGNAL POWER TYPE (1) PULL (2) (3) NAME NO. McASP0 AXR15 EPWM0TZ[0] ECAP2_APWM2 GP0[7] I/O CP[1] A AXR14 CLKR1 GP0[6] I/O CP[2] A AXR13 CLKX1 GP0[5] I/O CP[2] A AXR12 FSR1 GP0[4] I/O CP[2] A AXR11 FSX1 GP0[3] I/O CP[2] A AXR10 DR1 GP0[2] I/O CP[2] A AXR9 DX1 GP0[1] I/O CP[2] A AXR8 CLKS1 ECAP1_APWM1 GP0[0] PRU0_R31[8] I/O CP[3] A McASP0 serial data AXR7 EPWM1TZ[0] PRU0_R30[17] GP1[15] I/O CP[4] A PRU0_R31[7] AXR6 CLKR0 GP1[14] MII_TXEN PRU0_R31[6] I/O CP[5] A AXR5 CLKX0 GP1[13] MII_TXCLK I/O CP[5] A AXR4 FSR0 GP1[12] MII_COL I/O CP[5] A AXR3 FSX0 GP1[11] MII_TXD[3] I/O CP[5] A AXR2 DR0 GP1[10] MII_TXD[2] I/O CP[5] A AXR1 DX0 GP1[9] MII_TXD[1] I/O CP[5] A AXR0 ECAP0_APWM0 GP8[7] MII_TXD[0] CLKS0 I/O CP[6] A AHCLKX USB_REFCLKIN UART1_CTS GP0[10] I/O CP[0] A McASP0 transmit master clock PRU0_R31[17] ACLKX PRU0_R30[19]/ GP0[14] PRU0_R31[21] I/O CP[0] A McASP0 transmit bit clock AFSX GP0[12] PRU0_R31[19] I/O CP[0] A McASP0 transmit frame sync AHCLKR PRU0_R30[18] UART1_RTS GP0[11] I/O CP[0] A McASP0 receive master clock PRU0_R31[18] ACLKR PRU0_R30[20] GP0[15]/ PRU0_R31[22] I/O CP[0] A McASP0 receive bit clock AFSR GP0[13] PRU0_R31[20] I/O CP[0] A McASP0 receive frame sync AMUTE PRU0_R30[16] UART2_RTS GP0[9] I/O CP[0] A McASP0 mute output PRU0_R31[16] (1) I Input, O Output, I/O Bidirectional, Z High impedance, PWR Supply voltage, GND Ground, A Analog signal. Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. (2) IPD Internal Pulldown resistor; IPU Internal Pullup resistor; CP[ n configurable pull-up/pull-down (where n is the pin group) using the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the device is out of reset. During reset, all of the pins associated with these registers are weakly pulled down. If the application requires a pull-up, an external pull-up can be used. (3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power supply DVDD3318_C. Submit Documentation Feedback Device Overview

3.9.16 Multichannel Buffered Serial Ports (McBSP) OMAP-L138 Low-Power www.ti.com Table 3-19. Multichannel Buffered Serial Ports (McBSPs) Terminal Functions SIGNAL POWER TYPE (1) PULL (2) (3) NAME NO. McBSP0 AXR0 ECAP0_APWM0 GP8[7] MII_TXD[0] I CP[6] A McBSP0 sample rate generator clock input CLKS0 AXR6 CLKR0 GP1[14] MII_TXEN I/O CP[5] A McBSP0 receive clock PRU0_R31[6] AXR4 FSR0 GP1[12] MII_COL I/O CP[5] A McBSP0 receive frame sync AXR2 DR0 GP1[10] MII_TXD[2] I CP[5] A McBSP0 receive data AXR5 CLKX0 GP1[13] MII_TXCLK I/O CP[5] A McBSP0 transmit clock AXR3 FSX0 GP1[11] MII_TXD[3] I/O CP[5] A McBSP0 transmit frame sync AXR1 DX0 GP1[9] MII_TXD[1] O CP[5] A McBSP0 transmit data McBSP1 AXR8 CLKS1 ECAP1_APWM1 GP0[0] I CP[3] A McBSP1 sample rate generator clock input PRU0_R31[8] AXR14 CLKR1 GP0[6] I/O CP[2] A McBSP1 receive clock AXR12 FSR1 GP0[4] I/O CP[2] A McBSP1 receive frame sync AXR10 DR1 GP0[2] I CP[2] A McBSP1 receive data AXR13 CLKX1 GP0[5] I/O CP[2] A McBSP1 transmit clock AXR11 FSX1 GP0[3] I/O CP[2] A McBSP1 transmit frame sync AXR9 DX1 GP0[1] O CP[2] A McBSP1 transmit data (1) I Input, O Output, I/O Bidirectional, Z High impedance, PWR Supply voltage, GND Ground, A Analog signal. Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. (2) IPD Internal Pulldown resistor; IPU Internal Pullup resistor; CP[ n configurable pull-up/pull-down (where n is the pin group) using the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the device is out of reset. During reset, all of the pins associated with these registers are weakly pulled down. If the application requires a pull-up, an external pull-up can be used. (3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power supply DVDD3318_C. Device Overview Submit Documentation Feedback

3.9.17 Universal Serial Bus Modules (USB0 USB1 OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 3-20. Universal Serial Bus (USB) Terminal Functions SIGNAL POWER TYPE (1) PULL (2) (3) NAME NO. USB0 2.0 OTG (USB0) USB0_DM M18 A USB0 PHY data minus USB0_DP M19 A USB0 PHY data plus USB0_VDDA33 N18 PWR USB0 PHY 3.3-V supply USB0 PHY identification USB0_ID P16 A (mini-A or mini-B plug) USB0_VBUS N19 A USB0 bus voltage USB0_DRVVBUS K18 B USB0 controller VBUS control output. AHCLKX USB_REFCLKIN UART1_CTS I CP[0] A USB_REFCLKIN. Optional clock input GP0[10] PRU0_R31[17] USB0_VDDA18 N14 PWR USB0 PHY 1.8-V supply input USB0_VDDA12 N17 PWR USB0 PHY 1.2-V LDO output for bypass cap USB0 and USB1 core logic 1.2-V supply USB_CVDD M12 PWR input USB1 1.1 OHCI (USB1) USB1_DM P18 A USB1 PHY data minus USB1_DP P19 A USB1 PHY data plus AHCLKX USB_REFCLKIN UART1_CTS I CP[0] A USB_REFCLKIN. Optional clock input GP0[10] PRU0_R31[17] USB1_VDDA33 P15 PWR USB1 PHY 3.3-V supply USB1_VDDA18 P14 PWR USB1 PHY 1.8-V supply USB0 and USB1 core logic 1.2-V supply USB_CVDD M12 PWR input (1) I Input, O Output, I/O Bidirectional, Z High impedance, PWR Supply voltage, GND Ground, A Analog signal. Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. (2) IPD Internal Pulldown resistor; IPU Internal Pullup resistor; CP[ n configurable pull-up/pull-down (where n is the pin group) using the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the device is out of reset. During reset, all of the pins associated with these registers are weakly pulled down. If the application requires a pull-up, an external pull-up can be used. (3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power supply DVDD3318_C. Submit Documentation Feedback Device Overview

3.9.18 Ethernet Media Access Controller (EMAC) OMAP-L138 Low-Power www.ti.com Table 3-21. Ethernet Media Access Controller (EMAC) Terminal Functions SIGNAL POWER TYPE (1) PULL (2) (3) NAME NO. MII AXR6 CLKR0 GP1[14] MII_TXEN PRU0_R31[6] O CP[5] A EMAC MII Transmit enable output AXR5 CLKX0 GP1[13] MII_TXCLK I CP[5] A EMAC MII Transmit clock input AXR4 FSR0 GP1[12] MII_COL I CP[5] A EMAC MII Collision detect input AXR3 FSX0 GP1[11] MII_TXD[3] O CP[5] A AXR2 DR0 GP1[10] MII_TXD[2] O CP[5] A EMAC MII transmit data AXR1 DX0 GP1[9] MII_TXD[1] O CP[5] A AXR0 ECAP0_APWM0 GP8[7] MII_TXD[0] O CP[6] A CLKS0 SPI0_SOMI EPWMSYNCI GP8[6] MII_RXER C16 I CP[7] A EMAC MII receive error input SPI0_SIMO EPWMSYNCO GP8[5] MII_CRS C18 I CP[7] A EMAC MII carrier sense input SPI0_CLK EPWM0A GP1[8] MII_RXCLK D19 I CP[7] A EMAC MII receive clock input SPI0_ENA EPWM0B PRU0_R30[6] MII_RXDV C17 I CP[7] A EMAC MII receive data valid input SPI0_SCS[5] UART0_RXD GP8[4] MII_RXD[3] C19 I CP[8] A SPI0_SCS[4] UART0_TXD GP8[3] MII_RXD[2] D18 I CP[8] A SPI0_SCS[3] UART0_CTS GP8[2] MII_RXD[1] EMAC MII receive data E17 I CP[9] A SATA_MP_SWITCH SPI0_SCS[2] UART0_RTS GP8[1] MII_RXD[0] D16 I CP[9] A SATA_CP_DET RMII VP_DIN[1] UHPI_HD[9] UPP_D[9] W18 I/O CP[26] C EMAC 50-MHz clock input or output RMII_MHZ_50_CLK PRU0_R31[23] VP_DIN[2] UHPI_HD[10] UPP_D[10] RMII_RXER W17 I CP[26] C EMAC RMII receiver error PRU0_R31[24] VP_DIN[3] UHPI_HD[11] UPP_D[11] RMII_RXD[0] V17 I CP[26] C PRU0_R31[25] EMAC RMII receive data VP_DIN[4] UHPI_HD[12] UPP_D[12] W16 I CP[26] C RMII_RXD[1] /PRU0_R31[26] VP_DIN[0] UHPI_HD[8] UPP_D[8] RMII_CRS_DV/ W19 I CP[26] C EMAC RMII carrier sense data valid PRU1_R31[29] VP_DIN[5] UHPI_HD[13] UPP_D[13] R14 O CP[26] C EMAC RMII transmit enable RMII_TXEN /PRU0_R31[27] VP_DIN[6] UHPI_HD[14] UPP_D[14] V16 O CP[26] C RMII_TXD[0] PRU0_R31[28] EMAC RMII transmit data VP_DIN[7] UHPI_HD[15] UPP_D[15] U18 O CP[26] C RMII_TXD[1] PRU0_R31[29] MDIO SPI0_SCS[0] TM64P1_OUT12 GP1[6] MDIO_D D17 I/O CP[10] A MDIO serial data TM64P1_IN12 (1) I Input, O Output, I/O Bidirectional, Z High impedance, PWR Supply voltage, GND Ground, A Analog signal. Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. (2) IPD Internal Pulldown resistor; IPU Internal Pullup resistor; CP[ n configurable pull-up/pull-down (where n is the pin group) using the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the device is out of reset. During reset, all of the pins associated with these registers are weakly pulled down. If the application requires a pull-up, an external pull-up can be used. (3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power supply DVDD3318_C. Device Overview Submit Documentation Feedback

www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 3-21. Ethernet Media Access Controller (EMAC) Terminal Functions (continued) SIGNAL POWER TYPE (1) PULL (2) (3) NAME NO. SPI0_SCS[1] TM64P0_OUT12 GP1[7] MDIO_CLK E16 O CP[10] A MDIO clock TM64P0_IN12 Submit Documentation Feedback Device Overview

3.9.19 Multimedia Card/Secure Digital (MMC/SD) OMAP-L138 Low-Power www.ti.com Table 3-22. Multimedia Card/Secure Digital (MMC/SD) Terminal Functions SIGNAL POWER TYPE (1) PULL (2) (3) NAME NO. MMCSD0 EMA_A[23] MMCSD0_CLK PRU1_R30[31] /GP4[7] O CP[18] B MMCSD0 Clock PRU1_R31[23] EMA_A[22] MMCSD0_CMD PRU1_R30[30] GP4[6] A10 I/O CP[18] B MMCSD0 Command PRU1_R31[22] EMA_A[21] MMCSD0_DAT[0] PRU1_R30[29] GP4[5] B10 I/O CP[18] B PRU1_R31[21] EMA_A[20] MMCSD0_DAT[1] PRU1_R30[28] GP4[4] A11 I/O CP[18] B PRU1_R31[20] EMA_A[19] MMCSD0_DAT[2] PRU1_R30[27] GP4[3] C10 I/O CP[18] B PRU1_R31[19] MMC/SD0 data EMA_A[18] MMCSD0_DAT[3] PRU1_R30[26] GP4[2] E11 I/O CP[18] B PRU1_R31[18] EMA_A[17] MMCSD0_DAT[4] PRU1_R30[25] GP4[1] B11 I/O CP[18] B EMA_A[16] MMCSD0_DAT[5] PRU1_R30[24] GP4[0] E12 I/O CP[18] B EMA_A[15] MMCSD0_DAT[6] PRU1_R30[23] GP5[15] C11 I/O CP[19] B EMA_A[14] MMCSD0_DAT[7] PRU1_R30[22] GP5[14] A12 I/O CP[19] B MMCSD1 PRU0_R30[24] MMCSD1_CLK UPP_CHB_START O CP[30] C MMCSD1 Clock GP8[14]/PRU1_R31[26]/ PRU0_R30[23] MMCSD1_CMD UPP_CHB_ENABLE I/O CP[30] C MMCSD1 Command GP8[13]/PRU1_R31[25] MMCSD1_DAT[7] LCD_PCLK PRU1_R30[7] GP8[11] I/O CP[31] C MMCSD1_DAT[5] LCD_HSYNC PRU1_R30[5] GP8[9] I/O CP[31] C PRU1_R31[6] MMCSD1_DAT[4] LCD_VSYNC PRU1_R30[4] GP8[8] I/O CP[31] C PRU1_R31[5] MMCSD1_DAT[6] LCD_MCLK PRU1_R30[6] GP8[10] I/O CP[31] C PRU1_R31[7] MMC/SD1 data VP_CLKIN2 MMCSD1_DAT[3] PRU1_R30[3] GP6[4] I/O CP[30] C PRU1_R31[4] VP_CLKIN3 MMCSD1_DAT[1] PRU1_R30[1] GP6[2] I/O CP[30] C PRU1_R31[2] VP_CLKOUT2 MMCSD1_DAT[2] PRU1_R30[2] GP6[3] I/O CP[30] C PRU1_R31[3] PRU0_R30[25] MMCSD1_DAT[0] UPP_CHB_CLOCK GP8[15]/ I/O CP[30] C PRU1_R31[27] (1) I Input, O Output, I/O Bidirectional, Z High impedance, PWR Supply voltage, GND Ground, A Analog signal. Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. (2) IPD Internal Pulldown resistor; IPU Internal Pullup resistor; CP[ n configurable pull-up/pull-down (where n is the pin group) using the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the device is out of reset. During reset, all of the pins associated with these registers are weakly pulled down. If the application requires a pull-up, an external pull-up can be used. (3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power supply DVDD3318_C. Device Overview Submit Documentation Feedback

3.9.20 Liquid Crystal Display Controller(LCD) OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 3-23. Liquid Crystal Display Controller (LCD) Terminal Functions SIGNAL POWER TYPE (1) PULL (2) (3) NAME NO. VP_DOUT[15] LCD_D[15] UPP_XD[7] GP7[7] BOOT[7] I/O CP[29] C VP_DOUT[14] LCD_D[14] UPP_XD[6] GP7[6] BOOT[6] I/O CP[29] C VP_DOUT[13] LCD_D[13] UPP_XD[5] GP7[5] BOOT[5] I/O CP[29] C VP_DOUT[12] LCD_D[12] UPP_XD[4] GP7[4] BOOT[4] I/O CP[29] C VP_DOUT[11] LCD_D[11] UPP_XD[3] GP7[3] BOOT[3] I/O CP[29] C VP_DOUT[10] LCD_D[10] UPP_XD[2] GP7[2] BOOT[2] I/O CP[29] C VP_DOUT[9] LCD_D[9] UPP_XD[1] GP7[1] BOOT[1] I/O CP[29] C VP_DOUT[8] LCD_D[8] UPP_XD[0] GP7[0] BOOT[0] I/O CP[29] C VP_DOUT[7] LCD_D[7] UPP_XD[15] GP7[15] I/O CP[28] C PRU1_R31[15] LCD data bus VP_DOUT[6] LCD_D[6] UPP_XD[14] GP7[14] I/O CP[28] C PRU1_R31[14] VP_DOUT[5] LCD_D[5] UPP_XD[13] GP7[13] I/O CP[28] C PRU1_R31[13] VP_DOUT[4] LCD_D[4] UPP_XD[12] GP7[12] I/O CP[28] C PRU1_R31[12] VP_DOUT[3] LCD_D[3] UPP_XD[11] GP7[11] I/O CP[28] C PRU1_R31[11] VP_DOUT[2] LCD_D[2] UPP_XD[10] GP7[10] I/O CP[28] C PRU1_R31[10] VP_DOUT[1] LCD_D[1] UPP_XD[9] GP7[9] PRU1_R31[9] I/O CP[28] C VP_DOUT[0] LCD_D[0] UPP_XD[8] GP7[8] PRU1_R31[8] I/O CP[28] C MMCSD1_DAT[7] LCD_PCLK PRU1_R30[7] GP8[11] O CP[31] C LCD pixel clock MMCSD1_DAT[5] LCD_HSYNC PRU1_R30[5] GP8[9] O CP[31] C LCD horizontal sync PRU1_R31[6] MMCSD1_DAT[4] LCD_VSYNC PRU1_R30[4] GP8[8] O CP[31] C LCD vertical sync PRU1_R31[5] LCD AC bias enable chip LCD_AC_ENB_CS GP6[0]/ PRU1_R31[28] O CP[31] C select MMCSD1_DAT[6] LCD_MCLK PRU1_R30[6] GP8[10] O CP[31] C LCD memory clock PRU1_R31[7] (1) I Input, O Output, I/O Bidirectional, Z High impedance, PWR Supply voltage, GND Ground, A Analog signal. Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. (2) IPD Internal Pulldown resistor; IPU Internal Pullup resistor; CP[ n configurable pull-up/pull-down (where n is the pin group) using the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the device is out of reset. During reset, all of the pins associated with these registers are weakly pulled down. If the application requires a pull-up, an external pull-up can be used. (3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power supply DVDD3318_C. Submit Documentation Feedback Device Overview

3.9.21 Serial ATA Controller (SATA) OMAP-L138 Low-Power www.ti.com Table 3-24. Serial ATA Controller (SATA) Terminal Functions SIGNAL POWER TYPE (1) PULL (2) (3) NAME NO. SATA_RXP I SATA receive data (positive) SATA_RXN I SATA receive data (negative) SATA_TXP O SATA transmit data (positive) SATA_TXN O SATA transmit data (negative) SATA_REFCLKP I SATA PHY reference clock (positive) SATA_REFCLKN I SATA PHY reference clock (negative) SPI0_SCS[3] UART0_CTS GP8[2] E17 I CP[9] A SATA mechanical presence switch input MII_RXD[1] SATA_MP_SWITCH SPI0_SCS[2] UART0_RTS GP8[1] D16 I CP[9] A SATA cold presence detect input MII_RXD[0] SATA_CP_DET SPI1_SCS[2] UART1_TXD F19 O CP[13] A SATA cold presence power-on output SATA_CP_POD GP1[0] SPI1_SCS[3] UART1_RXD SATA_LED E18 O CP[13] A SATA LED control output GP1[1] SATA PHY PLL regulator output. Requires an SATA_REG A external 0.1uF filter capacitor. SATA_VDDR PWR SATA PHY 1.8V internal regulator supply M2, P1, SATA_VDD PWR SATA PHY 1.2V logic supply P2, H1, H2, K1, SATA_VSS GND SATA PHY ground reference K2, L3, (1) I Input, O Output, I/O Bidirectional, Z High impedance, PWR Supply voltage, GND Ground, A Analog signal. Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. (2) IPD Internal Pulldown resistor; IPU Internal Pullup resistor; CP[ n configurable pull-up/pull-down (where n is the pin group) using the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the device is out of reset. During reset, all of the pins associated with these registers are weakly pulled down. If the application requires a pull-up, an external pull-up can be used. (3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power supply DVDD3318_C. Device Overview Submit Documentation Feedback

3.9.22 Universal Host-Port Interface (UHPI) OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 3-25. Universal Host-Port Interface (UHPI) Terminal Functions SIGNAL POWER TYPE (1) PULL (2) (3) NAME NO. VP_DIN[7] UHPI_HD[15] UPP_D[15] RMII_TXD[1] U18 I/O CP[26] C PRU0_R31[29] VP_DIN[6] UHPI_HD[14] UPP_D[14] RMII_TXD[0] V16 I/O CP[26] C PRU0_R31[28] VP_DIN[5] UHPI_HD[13] UPP_D[13] RMII_TXEN R14 I/O CP[26] C PRU0_R31[27] VP_DIN[4] UHPI_HD[12] UPP_D[12] RMII_RXD[1] W16 I/O CP[26] C PRU0_R31[26] VP_DIN[3] UHPI_HD[11] UPP_D[11] RMII_RXD[0] V17 I/O CP[26] C PRU0_R31[25] VP_DIN[2] UHPI_HD[10] UPP_D[10] RMII_RXER W17 I/O CP[26] C PRU0_R31[24] VP_DIN[1] UHPI_HD[9] UPP_D[9] RMII_MHZ_50_CLK W18 I/O CP[26] C PRU0_R31[23] VP_DIN[0] UHPI_HD[8] UPP_D[8] RMII_CRS_DV W19 I/O CP[26] C UHPI data bus PRU1_R31[29] VP_DIN[15]_VSYNC UHPI_HD[7] UPP_D[7]/ PRU0_R30[15] V18 I/O CP[27] C PRU0_R31[15] VP_DIN[14]_HSYNC UHPI_HD[6] UPP_D[6]/ PRU0_R30[14] V19 I/O CP[27] C PRU0_R31[14] VP_DIN[13]_FIELD UHPI_HD[5] UPP_D[5] PRU0_R30[13] U19 I/O CP[27] C PRU0_R31[13] VP_DIN[12] UHPI_HD[4] UPP_D[4] PRU0_R30[12] T16 I/O CP[27] C PRU0_R31[12] VP_DIN[11] UHPI_HD[3] UPP_D[3] PRU0_R30[11] R18 I/O CP[27] C PRU0_R31[11] VP_DIN[10] UHPI_HD[2] UPP_D[2] PRU0_R30[10] R19 I/O CP[27] C PRU0_R31[10] VP_DIN[9] UHPI_HD[1] UPP_D[1] PRU0_R30[9] PRU0_R31[9] R15 I/O CP[27] C VP_DIN[8] UHPI_HD[0] UPP_D[0] GP6[5] PRU1_R31[0] P17 I/O CP[27] C PRU0_R30[29] UHPI_HCNTL0 UPP_CHA_CLOCK GP6[11] U17 I CP[24] C UHPI access control PRU0_R30[28] UHPI_HCNTL1 UPP_CHA_START GP6[10] W15 I CP[24] C UHPI half-word PRU0_R30[27] UHPI_HHWIL UPP_CHA_ENABLE GP6[9] U16 I CP[24] C identification control PRU0_R30[26] /UHPI_HR W UPP_CHA_WAIT T15 I CP[24] C UHPI read/write GP6[8] /PRU1_R31[17] VP_CLKIN0 UHPI_HCS PRU1_R30[10] GP6[7] UPP_2xTXCLK W14 I CP[25] C UHPI chip select VP_CLKIN1 UHPI_HDS1 PRU1_R30[9] GP6[6] PRU1_R31[16] V15 I CP[25] C UHPI data strobe CLKOUT UHPI_HDS2 PRU1_R30[13] GP6[14] T18 I CP[22] C PRU0_R30[30] UHPI_HINT PRU1_R30[11] GP6[12] R16 I CP[23] C UHPI host interrupt (1) I Input, O Output, I/O Bidirectional, Z High impedance, PWR Supply voltage, GND Ground, A Analog signal. Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. (2) IPD Internal Pulldown resistor; IPU Internal Pullup resistor; CP[ n configurable pull-up/pull-down (where n is the pin group) using the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the device is out of reset. During reset, all of the pins associated with these registers are weakly pulled down. If the application requires a pull-up, an external pull-up can be used. (3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power supply DVDD3318_C. Submit Documentation Feedback Device Overview

www.ti.com Table 3-25. Universal Host-Port Interface (UHPI) Terminal Functions (continued) SIGNAL POWER TYPE (1) PULL (2) (3) NAME NO. PRU0_R30[31] /UHPI_HRDY PRU1_R30[12] /GP6[13] R17 O CP[23] C UHPI ready RESETOUT UHPI_HAS PRU1_R30[14] GP6[15] T17 I CP[21] C UHPI address strobe Device Overview Submit Documentation Feedback

3.9.23 Universal Parallel Port (uPP) OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 3-26. Universal Parallel Port (uPP) Terminal Functions SIGNAL POWER TYPE (1) PULL (2) (3) NAME NO. VP_CLKIN0 UHPI_HCS1 /PRU1_R30[10] GP6[7] uPP transmit clock W14 I CP[25] C UPP_2xTXCLK input PRU0_R30[25] /MMCSD1_DAT[0] UPP_CHB_CLOCK I/O CP[30] C uPP channel clock GP8[15]/PRU1_R31[27] PRU0_R30[24]/ MMCSD1_CLK UPP_CHB_START GP8[14] I/O CP[30] C uPP channel start PRU1_R31[26] PRU0_R30[23] MMCSD1_CMD UPP_CHB_ENABLE I/O CP[30] C uPP channel enable GP8[13]/PRU1_R31[25] PRU0_R30[22] PRU1_R30[8] UPP_CHB_WAIT GP8[12]/ I/O CP[30] C uPP channel wait PRU1_R31[24] PRU0_R30[29] /UHPI_CNTL0 UPP_CHA_CLOCK GP6[11] U17 I/O CP[24] C uPP channel clock PRU0_R30[28] UHPI_HCNTL1 UPP_CHA_START GP6[10] W15 I/O CP[24] C uPP channel start PRU0_R30[27] UHPI_HHWIL UPP_CHA_ENABLE GP6[9] U16 I/O CP[24] C uPP channel enable PRU0_R30[26] /UHPI_HR W UPP_CHA_WAIT GP6[8] T15 I/O CP[24] C uPP channel wait PRU1_R31[17] (1) I Input, O Output, I/O Bidirectional, Z High impedance, PWR Supply voltage, GND Ground, A Analog signal. Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. (2) IPD Internal Pulldown resistor; IPU Internal Pullup resistor; CP[ n configurable pull-up/pull-down (where n is the pin group) using the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the device is out of reset. During reset, all of the pins associated with these registers are weakly pulled down. If the application requires a pull-up, an external pull-up can be used. (3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power supply DVDD3318_C. Submit Documentation Feedback Device Overview

www.ti.com Table 3-26. Universal Parallel Port (uPP) Terminal Functions (continued) SIGNAL POWER TYPE (1) PULL (2) (3) NAME NO. VP_DOUT[7] LCD_D[7] UPP_XD[15] GP7[15] I/O CP[28] C PRU1_R31[15] VP_DOUT[6] LCD_D[6] UPP_XD[14] GP7[14] I/O CP[28] C PRU1_R31[14] VP_DOUT[5] LCD_D[5] UPP_XD[13] GP7[13] I/O CP[28] C PRU1_R31[13] VP_DOUT[4] LCD_D[4] UPP_XD[12] GP7[12] I/O CP[28] C PRU1_R31[12] VP_DOUT[3] LCD_D[3] UPP_XD[11] GP7[11] I/O CP[28] C PRU1_R31[11] VP_DOUT[2] LCD_D[2] UPP_XD[10] GP7[10] I/O CP[28] C PRU1_R31[10] VP_DOUT[1] LCD_D[1] UPP_XD[9] GP7[9] PRU1_R31[9] I/O CP[28] C VP_DOUT[0] LCD_D[0] UPP_XD[8] GP7[8] PRU1_R31[8] I/O CP[28] C VP_DOUT[15] LCD_D[15] UPP_XD[7] GP7[7] BOOT[7] I/O CP[29] C VP_DOUT[14] LCD_D[14] UPP_XD[6] GP7[6] BOOT[6] I/O CP[29] C VP_DOUT[13] LCD_D[13] UPP_XD[5] GP7[5] BOOT[5] I/O CP[29] C VP_DOUT[12] LCD_D[12] UPP_XD[4] GP7[4] BOOT[4] I/O CP[29] C VP_DOUT[11] LCD_D[11] UPP_XD[3] GP7[3] BOOT[3] I/O CP[29] C VP_DOUT[10] LCD_D[10] UPP_XD[2] GP7[2] BOOT[2] I/O CP[29] C VP_DOUT[9] LCD_D[9] UPP_XD[1] GP7[1] BOOT[1] I/O CP[29] C VP_DOUT[8] LCD_D[8] UPP_XD[0] GP7[0] BOOT[0] I/O CP[29] C VP_DIN[7] UHPI_HD[15] UPP_D[15] RMII_TXD[1] U18 I/O CP[26] C PRU0_R31[29] VP_DIN[6] UHPI_HD[14] UPP_D[14] RMII_TXD[0] V16 I/O CP[26] C PRU0_R31[28] uPP data bus VP_DIN[5] UHPI_HD[13] UPP_D[13] RMII_TXEN R14 I/O CP[26] C PRU0_R31[27] VP_DIN[4] UHPI_HD[12] UPP_D[12] RMII_RXD[1] W16 I/O CP[26] C PRU0_R31[26] VP_DIN[3] UHPI_HD[11] UPP_D[11] RMII_RXD[0] V17 I/O CP[26] C PRU0_R31[25] VP_DIN[2] UHPI_HD[10] UPP_D[10] RMII_RXER W17 I/O CP[26] C PRU0_R31[24] VP_DIN[1] UHPI_HD[9] UPP_D[9] RMII_MHZ_50_CLK W18 I/O CP[26] C PRU0_R31[23] VP_DIN[0] UHPI_HD[8] UPP_D[8] RMII_CRS_DV W19 I/O CP[26] C PRU1_R31[29] VP_DIN[15]_VSYNC UHPI_HD[7] UPP_D[7] /PRU0_R30[15] V18 I/O CP[27] C PRU0_R31[15] VP_DIN[14]_HSYNC UHPI_HD[6] UPP_D[6] PRU0_R30[14] V19 I/O CP[27] C PRU0_R31[14] VP_DIN[13]_FIELD UHPI_HD[5] UPP_D[5] PRU0_R30[13] U19 I/O CP[27] C PRU0_R31[13] VP_DIN[12] UHPI_HD[4] UPP_D[4] PRU0_R30[12] T16 I/O CP[27] C PRU0_R31[12] VP_DIN[11] UHPI_HD[3] UPP_D[3] PRU0_R30[11] R18 I/O CP[27] C PRU0_R31[11] VP_DIN[10] UHPI_HD[2] UPP_D[2] PRU0_R30[10] R19 I/O CP[27] C PRU0_R31[10] VP_DIN[9] UHPI_HD[1] UPP_D[1] PRU0_R30[9] R15 I/O CP[27] C PRU0_R31[9] VP_DIN[8] UHPI_HD[0] UPP_D[0] GP6[5] PRU1_R31[0] P17 I/O CP[27] C Device Overview Submit Documentation Feedback

3.9.24 Video Port Interface (VPIF) OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 3-27. Video Port Interface (VPIF) Terminal Functions SIGNAL POWER TYPE (1) PULL (2) (3) NAME NO. VIDEO INPUT VP_CLKIN0 UHPI_HCS PRU1_R30[10] GP6[7] VPIF capture channel W14 I CP[25] C UPP_2xTXCLK input clock VPIF capture channel VP_CLKIN1 UHPI_HDS1 /PRU1_R30[9] GP6[6] PRU1_R31[16] V15 I CP[25] C input clock VP_DIN[15]_VSYNC UHPI_HD[7] UPP_D[7] PRU0_R30[15] V18 I CP[27] C PRU0_R31[15] VP_DIN[14]_HSYNC UHPI_HD[6] UPP_D[6]/ PRU0_R30[14] V19 I CP[27] C PRU0_R31[14] VP_DIN[13]_FIELD UHPI_HD[5] UPP_D[5] PRU0_R30[13] U19 I CP[27] C PRU0_R31[13] VP_DIN[12] UHPI_HD[4] UPP_D[4]/ PRU0_R30[12] T16 I CP[27] C PRU0_R31[12] VP_DIN[11] UHPI_HD[3] UPP_D[3]/ PRU0_R30[11] R18 I CP[27] C PRU0_R31[11] VP_DIN[10] UHPI_HD[2] UPP_D[2] PRU0_R30[10] R19 I CP[27] C PRU0_R31[10] VP_DIN[9] UHPI_HD[1] UPP_D[1] PRU0_R30[9] R15 I CP[27] C PRU0_R31[9] VP_DIN[8] UHPI_HD[0] UPP_D[0] GP6[5] PRU1_R31[0] P17 I CP[27] C VPIF capture data bus VP_DIN[7] UHPI_HD[15] UPP_D[15] RMII_TXD[1] U18 I CP[26] C PRU0_R31[29] VP_DIN[6] UHPI_HD[14] UPP_D[14] RMII_TXD[0] V16 I CP[26] C PRU0_R31[28] VP_DIN[5] UHPI_HD[13] UPP_D[13] RMII_TXEN R14 I CP[26] C PRU0_R31[27] VP_DIN[4] UHPI_HD[12] UPP_D[12] RMII_RXD[1] W16 I CP[26] C PRU0_R31[26] VP_DIN[3] UHPI_HD[11] UPP_D[11] RMII_RXD[0] V17 I CP[26] C PRU0_R31[25] VP_DIN[2] UHPI_HD[10] UPP_D[10] RMII_RXER W17 I CP[26] C PRU0_R31[24] VP_DIN[1] UHPI_HD[9] UPP_D[9] RMII_MHZ_50_CLK W18 I CP[26] C PRU0_R31[23] VP_DIN[0] UHPI_HD[8] UPP_D[8] RMII_CRS_DV W19 I CP[26] C PRU1_R31[29] VIDEO OUTPUT VP_CLKIN2 MMCSD1_DAT[3] PRU1_R30[3] GP6[4] VPIF display channel I CP[30] C PRU1_R31[4] input clock VP_CLKOUT2 MMCSD1_DAT[2] PRU1_R30[2] GP6[3] VPIF display channel O CP[30] C PRU1_R31[3] output clock (1) I Input, O Output, I/O Bidirectional, Z High impedance, PWR Supply voltage, GND Ground, A Analog signal. Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. (2) IPD Internal Pulldown resistor; IPU Internal Pullup resistor; CP[ n configurable pull-up/pull-down (where n is the pin group) using the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the device is out of reset. During reset, all of the pins associated with these registers are weakly pulled down. If the application requires a pull-up, an external pull-up can be used. (3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power supply DVDD3318_C. Submit Documentation Feedback Device Overview

www.ti.com Table 3-27. Video Port Interface (VPIF) Terminal Functions (continued) SIGNAL POWER TYPE (1) PULL (2) (3) NAME NO. VP_CLKIN3 MMCSD1_DAT[1] PRU1_R30[1] GP6[2] VPIF display channel I CP[30] C PRU1_R31[2] input clock VPIF display channel VP_CLKOUT3 PRU1_R30[0] GP6[1] PRU1_R31[1] O CP[30] C output clock VP_DOUT[15] LCD_D[15] UPP_XD[7] GP7[7] BOOT[7] O CP[29] C VP_DOUT[14] LCD_D[14] UPP_XD[6] GP7[6] BOOT[6] O CP[29] C VP_DOUT[13] LCD_D[13] UPP_XD[5] GP7[5] BOOT[5] O CP[29] C VP_DOUT[12] LCD_D[12] UPP_XD[4] GP7[4] BOOT[4] O CP[29] C VP_DOUT[11] LCD_D[11] UPP_XD[3] GP7[3] BOOT[3] O CP[29] C VP_DOUT[10] LCD_D[10] UPP_XD[2] GP7[2] BOOT[2] O CP[29] C VP_DOUT[9] LCD_D[9] UPP_XD[1] GP7[1] BOOT[1] O CP[29] C VP_DOUT[8] LCD_D[8] UPP_XD[0] GP7[0] BOOT[0] O CP[29] C VPIF display data bus VP_DOUT[7] LCD_D[7] UPP_XD[15] GP7[15] PRU1_R31[15] O CP[28] C VP_DOUT[6] LCD_D[6] UPP_XD[14] GP7[14] PRU1_R31[14] O CP[28] C VP_DOUT[5] LCD_D[5] UPP_XD[13] GP7[13] PRU1_R31[13] O CP[28] C VP_DOUT[4] LCD_D[4] UPP_XD[12] GP7[12] PRU1_R31[12] O CP[28] C VP_DOUT[3] LCD_D[3] UPP_XD[11] GP7[11] PRU1_R31[11] O CP[28] C VP_DOUT[2] LCD_D[2] UPP_XD[10] GP7[10] PRU1_R31[10] O CP[28] C VP_DOUT[1] LCD_D[1] UPP_XD[9] GP7[9] PRU1_R31[9] O CP[28] C VP_DOUT[0] LCD_D[0] UPP_XD[8] GP7[8] PRU1_R31[8] O CP[28] C Device Overview Submit Documentation Feedback

3.9.25 Reserved and No Connect OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 3-28. Reserved and No Connect Terminal Functions SIGNAL TYPE (1) NO. Reserved. For proper device operation, this pin must be tied either directly to RSV2 T19 PWR CVDD or left unconnected (do not connect to ground). NC M3, M14, N16 No connect (Leave unconnected, do not connect to power or ground.) (1) PWR Supply voltage. Submit Documentation Feedback Device Overview

3.9.26 Supply and Ground OMAP-L138 Low-Power www.ti.com Table 3-29. Supply and Ground Terminal Functions SIGNAL TYPE (1) NO. E15, G7, G8, G13, H6, H7, H10, H11, CVDD (Core supply) H12, H13, J6, PWR Variable (1.2V 1.0V) core supply voltage pins J12, K6, K12, L12, M8, M9, N8, M12 RVDD (Internal RAM supply) E5, H14, PWR 1.2V internal ram supply voltage pins F14, G6, G10, G11, G12, J13, K5, L6, DVDD18 (I/O supply) N6, N9, N10, PWR 1.8V I/O supply voltage pins P7, P8, P9, P10, P13, R7, R8, R9, R13 F5, F15, G5, DVDD3318_A (I/O supply) PWR 1.8V or 3.3-V dual-voltage LVCMOS I/O supply voltage pins, Group A G14, G15, E14, F6, F7, F8, F10, F11, DVDD3318_B (I/O supply) PWR 1.8V or 3.3-V dual-voltage LVCMOS I/O supply voltage pins, Group B F12, F13, G9, J14, K15 J5, K13, L4, L13, M13, DVDD3318_C (I/O supply) PWR 1.8V or 3.3-V dual-voltage LVCMOS I/O supply voltage pins, Group C N13, P5, P6, P12, A19, H8, H9, H15, J7, J8, J9, J10, J11, K7, K8, K9, K10, K11, L5, VSS (Ground) GND Ground pins. L7, L8, L9, L10, L11, M4, M5, M6, M7, M10, M11, N5, N11, N12, P11 (1) PWR Supply voltage, GND Ground. Device Overview Submit Documentation Feedback

4.1 Boot Modes 4.2 SYSCFG Module OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 This device supports a variety of boot modes through an internal ARM ROM bootloader This device does not support dedicated hardware boot modes; therefore, all boot modes utilize the internal DSP ROM. The input states of the BOOT pins are sampled and latched into the BOOTCFG register, which is part of the system configuration (SYSCFG) module, when device reset is deasserted. Boot mode selection is determined by the values of the BOOT pins. See Using the D800K002 ARM Bootloader Application Report (SPRAB41) for more details on the ROM Boot Loader. The following boot modes are supported: NAND Flash boot 8-bit NAND NOR Flash boot NOR Direct boot (8-bit or 16-bit) NOR Legacy boot (8-bit or 16-bit) NOR AIS boot (8-bit or 16-bit) HPI Boot I2C0 /I2C1 Boot EEPROM (Master Mode) External Host (Slave Mode) SPI0/ SPI1 Boot Serial Flash (Master Mode) SERIAL EEPROM (Master Mode) External Host (Slave Mode) UART0 /UART1/UART2 Boot External Host The following system level peripheral: Readable Device, Die, and Chip Revision ID Control of Pin Multiplexing Priority of bus accesses different bus masters in the system Capture at power on reset the chip BOOT pin values and make them available to software Control of the DeepSleep power management function Enable and selection of the programmable pin pullups and pulldowns Special case settings for peripherals: Locking of PLL controller settings Default burst sizes for EDMA3 transfer controllers Selection of the source for the eCAP module input capture (including on chip sources) McASP AMUTEIN selection and clearing of AMUTE status for the McASP Control of the reference clock source and other side-band signals for both of the integrated USB PHYs Clock source selection for EMIFA DDR2 Controller PHY settings SATA PHY power management controls Selects the source of emulation suspend signal (from either ARM or DSP) of peripherals supporting Submit Documentation Feedback Device Configuration

www.ti.com this function. Control of on-chip inter-processor interrupts for signaling between ARM and DSP Since the SYSCFG peripheral controls global operation of the device, its registers are protected against erroneous accesses by several mechanisms: A special key sequence must be written to KICK0, KICK1 registers before any other registers are writeable. Additionally, many registers are accessible only by a host ARM or DSP) when it is operating in its privileged mode. (ex. from the kernel, but not from user space code). Table 4-1. System Configuration (SYSCFG) Module Register Access Register Address Register Name Register

www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 4-1. System Configuration (SYSCFG) Module Register Access (continued) Register Address Register Name Register CHIPSIG_CLR Chip Signal Clear Register 0x01C1 417C CFGCHIP0 Chip Configuration Register Privileged mode 0x01C1 4180 CFGCHIP1 Chip Configuration Register Privileged mode 0x01C1 4184 CFGCHIP2 Chip Configuration Register Privileged mode 0x01C1 4188 CFGCHIP3 Chip Configuration Register Privileged mode 0x01C1 418C CFGCHIP4 Chip Configuration Register Privileged mode 0x01E2 C000 VTPIO_CTL VTPIO COntrol Register Privileged mode 0x01E2 C004 DDR_SLEW DDR Slew Register Privileged mode 0x01E2 C008 DeepSleep DeepSleep Register Privileged mode 0x01E2 C00C PUPD_ENA Pullup Pulldown Enable Register Privileged mode 0x01E2 C010 PUPD_SEL Pullup Pulldown Selection Register Privileged mode 0x01E2 C014 RXACTIVE RXACTIVE Control Register Privileged mode 0x01E2 C018 PWRDN PWRDN Control Register Privileged mode Submit Documentation Feedback Device Configuration

5.1 Absolute Maximum Ratings Over Operating Junction Temperature Range OMAP-L138 Low-Power www.ti.com (Unless Otherwise Noted) (1) Core Logic, Variable and Fixed -0.5 V to 1.4 V (CVDD, RVDD, RTC_CVDD, PLL0_VDDA PLL1_VDDA SATA_VDD, USB_CVDD (2) (3) I/O, 1.8V -0.5 V to V Supply voltage ranges (USB0_VDDA18, USB1_VDDA18, SATA_VDDR, DDR_DVDD18) (3) I/O, 3.3V -0.5 V to 3.8V (DVDD3318_A, DVDD3318_B, DVDD3318_C, USB0_VDDA33 USB1_VDDA33 (3) Oscillator inputs (OSCIN, RTC_XI), 1.2V -0.3 V to CVDD 0.3V Dual-voltage LVCMOS inputs, 3.3V or 1.8V (Steady State) -0.3V to DVDD 0.3V Dual-voltage LVCMOS inputs, 3.3V or 1.8V (Transient) DVDD 20% up to 20% of Signal Input voltage I ranges Period USB Tolerant IOs: 5.25V (4) (USB0_DM, USB0_DP, USB0_ID USB1_DM, USB1_DP USB0 VBUS Pin 5.50V (4) Dual-voltage LVCMOS outputs, 3.3V or 1.8V -0.5 V to DVDD 0.3V (Steady State) Output voltage O ranges Dual-voltage LVCMOS outputs, 3.3V or 1.8V DVDD 20% (Transient) up to 20% of Signal Period Input or Output Voltages 0.3V above or below their respective power 20mA Clamp Current rails. Limit clamp current that flows through the I/O's internal diode protection cells. Commercial (default) C to C Operating Junction Temperature ranges, T J Extended version) -40 C to 105 C Storage temperature range, T stg (default) -55 C to 150 C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) This pin is an internal LDO output and connected via 0.22 F capacitor to VSS (3) All voltage values are with respect to VSS, USB0_VSSA33, USB0_VSSA, PLL0_VSSA, OSCVSS, RTC_VSS (4) Up to a maximum of hours. Device Operating Conditions Submit Documentation Feedback

5.2 Recommended Operating Conditions OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 NAME (variable) 1.2V operating point 1.14 1.2 or 1.26 1.32 V 1.1V operating point 1.05 1.1 1.16 V 1.0V operating point 0.95 1.0 1.05 V RVDD Internal RAM Supply Voltage 1.14 1.2 or 1.26 1.32 V RTC_CVDD RTC Core Logic Supply Voltage 1.14 1.2 or 1.26 1.32 V PLL0_VDDA PLL0 Supply Voltage 1.14 1.2 or 1.26 1.32 V PLL1_VDDA PLL1 Supply Voltage 1.14 1.2 or 1.26 1.32 V SATA_VDD SATA Core Logic Supply Voltage 1.14 1.2 or 1.26 1.32 V USB_CVDD (1) USB0, USB1 Core Logic Supply Voltage 1.14 1.2 or 1.26 1.32 V USB0_VDDA18 USB0 PHY Supply Voltage 1.71 1.8 1.89 V USB0_VDDA33 USB0 PHY Supply Voltage 3.15 3.3 3.45 V USB1_VDDA18 USB1 IO Supply Voltage 1.71 1.8 1.89 V Supply USB1_VDDA33 USB1 IO Supply Voltage 3.15 3.3 3.45 V Voltage SATA_VDDR SATA PHY Internal Regulator Supply Voltage 1.71 1.8 1.89 V DDR_DVDD18 DDR2 PHY Supply Voltage 1.71 1.8 1.89 V 0.5* 0.49* 0.51* DDR_VREF DDR2/mDDR reference voltage DDR_DVDD1 V DDR_DVDD18 DDR_DVDD18 DDR2/mDDR impedance control, DDR_ZP Vss V connected via Ω resistor to Vss 1.8V operating point 1.71 1.8 1.89 V Power Group A Dual-voltage IO DVDD3318_A Supply Voltage 3.3V operating point 3.15 3.3 3.45 V 1.8V operating point 1.71 1.8 1.89 V Power Group B Dual-voltage IO DVDD3318_B Supply Voltage 3.3V operating point 3.15 3.3 3.45 V 1.8V operating point 1.71 1.8 1.89 V Power Group C Dual-voltage IO DVDD3318_C Supply Voltage 3.3V operating point 3.15 3.3 3.45 V VSS Core Logic Digital Ground V PLL0_VSSA PLL0 Ground V PLL1_VSSA PLL1 Ground V SATA_VSS SATA PHY Ground V Supply Ground OSCVSS (2) Oscillator Ground V RTC_VSS (2) RTC Oscillator Ground V USB0_VSSA USB0 PHY Ground V USB0_VSSA33 USB0 PHY Ground V V IH High-level input voltage, Dual-voltage I/O, 3.3V (3) V High-level input voltage, Dual-voltage I/O, 1.8V (3) 0.65*DVDD V Voltage Input High High-level input voltage, RTC_XI 0.8*RTC_CVDD V High-level input voltage, OSCIN 0.8*CVDD V High-level input voltage, SATA_REFCLKP and TBD V SATA_REFCLKN V IL Low-level input voltage, Dual-voltage I/O, 3.3V (3) 0.8 V High-level input voltage, Dual-voltage I/O, 1.8V (3) 0.35*DVDD V Voltage Input Low Low-level input voltage, RTC_XI 0.2*RTC_CVDD V Low-level input voltage, OSCIN 0.2*CVDD V Low-level input voltage, SATA_REFCLKP and TBD V SATA_REFCLKN Transition t t 10%-90%, All Inputs (except SATA, USB0 and DDR2) ns Time (1) This pin is an internal LDO output and connected via 0.22 F capacitor to VSS (2) When an external crystal is used oscillator (OSC_VSS, RTC_VSS) ground must be kept separate from other grounds and connected directly to the crystal load capacitor ground. These pins are shorted to VSS on the device itself and should not be connected to VSS on the circuit board. If a crystal is not used and the clock input is driven directly, then the oscillator VSS may be connected to board ground. (3) These IO specifications apply to the dual-voltage IOs only and do not apply to DDR2/mDDR or SATA interfaces DDR2/mDDR IOs are 1.8V IOs and adhere to the JESD79-2A standard. Submit Documentation Feedback Device Operating Conditions

www.ti.com Recommended Operating Conditions (continued) NAME 1.2V 300 operating point Commercial temperature grade CVDD 1.1V 200 MHz (default) operating point CVDD 1.0V 100 operating point Operating F SYSCLK1,6 Frequency CVDD 1.2V 300 operating point Extended temperature grade CVDD 1.1V 200 MHz suffix) operating point CVDD 1.0V 100 operating point Device Operating Conditions Submit Documentation Feedback

5.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Junction Temperature (Unless Otherwise Noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Low/full speed: 2.8 USB0_VDDA33 V USB0_DM and USB0_DP High speed: 360 440 mV USB_DM and USB_DP Low/full speed: 2.8 USB1_VDDA33 V V OH USB1_DM and USB1_DP DVDD 3.15V, I OH mA 2.4 V High-level output voltage (dual-voltage LVCMOS IOs at 3.3V) (1) DVDD 3.15V, I OH -100 µ A 2.95 V High-level output voltage DVDD 1.65V, I OH mA DVDD-0.45 V (dual-voltage LVCMOS IOs at 1.8V) (1) Low/full speed: 0.0 0.3 V USB_DM and USB_DP High speed: -10 mV USB_DM and USB_DP V OL DVDD 3.15V, I OL 4mA 0.4 V Low-level output voltage (dual-voltage LVCMOS I/Os at 3.3V) DVDD 3.15V, I OL 100 µ A 0.2 V Low-level output voltage DVDD 1.65V, I OL 2mA 0.45 V (dual-voltage LVCMOS I/Os at 1.8V) V I VSS to DVDD without opposing µ A internal resistor Input current (1) V I VSS to DVDD with opposing I I (2) 310 µ A (dual-voltage LVCMOS I/Os) internal pullup resistor (3) V I VSS to DVDD with opposing -75 -270 µ A internal pulldown resistor (3) High-level output current (1) I OH All peripherals mA (dual-voltage LVCMOS I/Os) Low-level output current (1) I OL All peripherals mA (dual-voltage LVCMOS I/Os) Input capacitance (dual-voltage LVCMOS) pF Capacit Output capacitance (dual-voltage ance pF LVCMOS) (1) These IO specifications apply to the dual-voltage IOs only and do not apply to DDR2/mDDR or SATA interfaces DDR2/mDDR IOs are 1.8V IOs and adhere to the JESD79-2A standard. (2) I I applies to input-only pins and bi-directional pins. For input-only pins, I I indicates the input leakage current. For bi-directional pins, I I indicates the input leakage current and off-state (Hi-Z) output leakage current. (3) Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor. Submit Documentation Feedback Device Operating Conditions

6.1 Parameter Information 6.1.1 Parameter Information Device-Specific Information Transmission□Line 4.0□pF 1.85□pF Z0□=□50 Ω (see□note) Tester Pin□Electronics Data Sheet□Timing□Reference□Point Output Under Test 42 Ω 3.5□nH Device□Pin (see□note) 6.1.1.1 Signal Transition Levels Vref OMAP-L138 Low-Power www.ti.com The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. A transmission line with a delay of ns or longer can be used to produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay ns or longer) from the data sheet timings. Input requirements in this data sheet are tested with an input slew rate of Volts per nanosecond V/ns) at the device pin. Figure 6-1. Test Load Circuit for AC Timing Measurements The load capacitance value stated is only for characterization and measurement of AC timing signals. This load capacitance value does not indicate the maximum load the device is capable of driving. All input and output timing parameters are referenced to V ref for both "0" and "1" logic levels. For 3.3 V I/O, V ref 1.65 For 1.8 V I/O, V ref 0.9 Figure 6-2. Input and Output Voltage Reference Levels for AC Timing Measurements All rise and fall transition timing parameters are referenced to V IL MAX and V IH MIN for input clocks, V OL MAX and V OH MIN for output clocks Figure 6-3. Rise and Fall Transition Time Voltage Reference Levels Peripheral Information and Electrical Specifications Submit Documentation Feedback

6.2 Recommended Clock and Control Signal Transition Behavior 6.3 Power Supplies 6.3.1 Power-on Sequence 6.3.2 Power-off Sequence OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 All clocks and control signals must transition between V IH and V IL (or between V IL and V IH in a monotonic manner. The device should be powered-on in the following order: RTC (RTC_CVDD) may be powered from an external device (such as a battery) prior to all other supplies being applied. If the RTC is not used, RTC_CVDD should be connected to CVDD. 2a) All variable 1.2V 1.0V core logic supplies (CVDD) 2b) All static 1.2V logic supplies (RVDD, VDDA_12_PLL0, VDDA_12_PLL1 USB_CVDD SATA_VDD If voltage scaling is not used on the device, groups 2a) and 2b) can be controlled from the same power supply and powered up together. All static 1.8V IO supplies (DVDD18, DDR_DVDD18 USB0_VDDA18 USB1_VDDA18 and SATA_VDDR and any of the LVCMOS IO supply groups used at 1.8V nominal (DVDD3318_A, DVDD3318_B, or DVDD3318_C). All analog 3.3V PHY supplies (USB0_VDDA33 and USB1_VDDA33; these are not required if both USB0 and USB1 are not used) and any of the LVCMOS IO supply groups used at 3.3V nominal (DVDD3318_A, DVDD3318_B, or DVDD3318_C). There is no specific required voltage ramp rate for any of the supplies as long as the LVCMOS supplies operated at 3.3V (DVDD3318_A, DVDD3318_B, or DVDD3318_C) never exceed the STATIC 1.8V supplies by more than volts. The power supplies can be powered-off in any order as long as LVCMOS supplies operated at 3.3V (DVDD3318_A, DVDD3318_B, or DVDD3318_C) never exceed static 1.8V supplies by more than volts. There is no specific required voltage ramp down rate for any of the supplies (except as required to meet the above mentioned voltage condition). Submit Documentation Feedback Peripheral Information and Electrical Specifications

6.4 Reset 6.4.1 Power-On Reset (POR) 6.4.2 Warm Reset OMAP-L138 Low-Power www.ti.com A power-on reset (POR) is required to place the device in a known good state after power-up. Power-On Reset is initiated by bringing RESET and TRST low at the same time. POR sets all of the device internal logic to its default state. All pins are tri-stated with the exception of RESETOUT which remains active through the reset sequence. RESETOUT is an output for use by other controllers in the system that indicates the device is currently in reset. RTCK is maintained active through a POR. A summary of the effects of Power-On Reset is given below: All internal logic (including emulation logic and the PLL logic) is reset to its default state Internal memory is not maintained through a POR RESETOUT goes active All device pins go to a high-impedance state The RTC peripheral is not reset during a POR. A software sequence is required to reset the RTC A watchdog reset triggers a POR. A warm reset provides a limited reset to the device. Warm Reset is initiated by bringing only RESET low TRST is maintained high through a warm reset). Warm reset sets certain portions of the device to their default state while leaving others unaltered. All pins are tri-stated with the exception of RESETOUT which remains active through the reset sequence. RESETOUT is an output for use by other controllers in the system that indicates the device is currently in reset. RTCK is maintained active through a POR. A summary of the effects of Warm Reset is given below: All internal logic (except for the emulation logic and the PLL logic) is reset to its default state Internal memory is maintained through a warm reset RESETOUT goes active All device pins go to a high-impedance state The RTC peripheral is not reset during a warm reset. A software sequence is required to reset the RTC Peripheral Information and Electrical Specifications Submit Documentation Feedback

6.4.3 Reset Electrical Data Timings OSCIN RESET RESETOUT Boot□Pins Config Power Supplies Ramping Power□Supplies□Stable Clock□Source□Stable 2 3 TRST OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 6-1 assumes testing over the recommended operating conditions. Table 6-1. Reset Timing Requirements (1) (2) 1.2V 1.1V 1.0V NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX t w(RSTL) Pulse width, RESET TRST low 100 100 100 ns t su(BPV-RSTH) Setup time, boot pins valid before RESET TRST high ns t h(RSTH-BPV) Hold time, boot pins valid after RESET TRST high ns t d(RSTH-RESETOUTH) RESET high to RESETOUT high; Warm reset cycles (3) RESET high to RESETOUT high; Power-on Reset t d(RSTL-RESETOUTL) Delay time, RESET TRST low to RESETOUT low ns (1) RESETOUT is multiplexed with other pin functions. See the Terminal Functions table, Table 3-4 for details. (2) For power-on reset (POR), the reset timings in this table refer to RESET and TRST together. For warm reset, the reset timings in this table refer to RESET only TRST is held high). (3) OSCIN cycles. Figure 6-4. Power-On Reset (RESET and TRST active) Timing Submit Documentation Feedback Peripheral Information and Electrical Specifications

Boot□Pins Config Power□Supplies□Stable 2 3 Driven□or□Hi-Z OMAP-L138 Low-Power www.ti.com Figure 6-5. Warm Reset (RESET active, TRST high) Timing Peripheral Information and Electrical Specifications Submit Documentation Feedback

6.5 Crystal Oscillator or External Clock Input OSCOUT OSCIN OSCVSS Clock□Input to□PLL OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 The device includes two choices to provide an external clock input, which is fed to the on-chip PLLs to generate high-frequency system clocks. These options are illustrated in Figure 6-6 and Figure 6-7 For input clock frequencies between and MHz, a crystal with ohm max ESR is recommended. For input clock frequencies between and MHz, a crystal with ohm max ESR is recommended. Typical C1, values are 10-20 pF. Figure 6-6 illustrates the option that uses on-chip 1.2V oscillator with external crystal circuit. Figure 6-7 illustrates the option that uses an external 1.2V clock input. Figure 6-6. On-Chip Oscillator Table 6-2. Oscillator Timing Requirements PARAMETER MIN MAX UNIT f osc Oscillator frequency range (OSCIN/OSCOUT) MHz Submit Documentation Feedback Peripheral Information and Electrical Specifications

to□PLL NC 6.6 Clock PLLs 6.6.1 PLL Device-Specific Information OMAP-L138 Low-Power www.ti.com Figure 6-7. External 1.2V Clock Source Table 6-3. OSCIN Timing Requirements for an Externally Driven Clock PARAMETER MIN MAX UNIT f CLKIN OSCIN frequency range MHz t c(CLKIN) Cycle time, external clock driven on OSCIN ns t w(CLKINH) Pulse width high, external clock on OSCIN 0.4 t c(CLKIN) ns t w(CLKINL) Pulse width low, external clock on OSCIN 0.4 t c(CLKIN) ns t t(CLKIN) Transition time, OSCIN ns The device has two PLL controllers that provide clocks to different parts of the system. PLL0 provides clocks (though various dividers) to most of the components of the device. PLL1 provides clocks to the mDDR/DDR2 Controller and provides an alternate clock source for the ASYNC3 clock domain. This allows the peripherals on the ASYNC3 clock domain to be immune to frequency scaling operation on PLL0. The PLL controller provides the following: Glitch-Free Transitions (on changing clock settings) Domain Clocks Alignment Clock Gating PLL power down The various clock outputs given by the controller are as follows: Domain Clocks: SYSCLK [1:n] Auxiliary Clock from reference clock source: AUXCLK Various dividers that can be used are as follows: Post-PLL Divider: POSTDIV SYSCLK Divider: D1, Dn Various other controls supported are as follows: PLL Multiplier Control: PLLM Software programmable PLL Bypass: PLLEN The device DSP generates the high-frequency internal clocks it requires through an on-chip PLL. Peripheral Information and Electrical Specifications Submit Documentation Feedback

0.1 µF 0.01 µF 50R1.14V□-□1.32V 50RVSS PLLn_VDDA PLLn_VSSA Ferrite□Bead:□Murata□BLM31PG500SN1L or□Equivalent OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 The PLL requires some external filtering components to reduce power supply noise as shown in Figure 6-8 Figure 6-8. PLL External Filtering Components The input to the PLL is either from the on-chip oscillator or from an external clock on the OSCIN pin. PLL0 outputs seven clocks that have programmable divider options. PLL1 outputs three clocks that have programmable divider options. Figure 6-9 illustrates the high-level view of the PLL Topology. The PLLs are disabled by default after a device reset. They must be configured by software according to the allowable operating conditions listed in Table 6-4 before enabling the device to run from the PLL by setting PLLEN Submit Documentation Feedback Peripheral Information and Electrical Specifications

PLLDIV1□(/1) SYSCLK1 PLLDIV2□(/2) SYSCLK2 PLLDIV4□(/4) SYSCLK4 PLLDIV5□(/3) SYSCLK5 PLLDIV6□(/1) SYSCLK6 PLLDIV7□(/6) SYSCLK7 DIV4.5 1

0 EMIFA

CFGCHIP3[EMA_CLKSRC] PREDIV PLLM CLKIN OSCIN PLL1_SYSCLK3 PLLCTL[EXTCLKSRC] AUXCLK PLL PLLDIV3□(/3) SYSCLK3 DDR2/mDDR Internal Clock Source PLLDIV2□(/2) PLLDIV3□(/3) PLLDIV1□(/1) PLLCTL[PLLEN] POSTDIV PLLM PLL PLLCTL[PLLEN] PLLCTL[CLKMODE] POSTDIV OBSCLK (OBSCLK□Pin) DIV4.5 OSCDIV PLL Controller□0 PLL Controller□1 SYSCLK2 SYSCLK3 SYSCLK1 OMAP-L138 Low-Power www.ti.com Figure 6-9. PLL Topology Peripheral Information and Electrical Specifications Submit Documentation Feedback

2000 NMax PLL Lock Time =

m where N = Pre-Divider Ratio M = PLL Multiplier 6.6.2 Device Clock Generation OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 6-4. Allowed PLL Operating Conditions (PLL0 and PLL1) Default NO. PARAMETER MIN MAX UNIT Value PLLRST Assertion time during initialization N/A 1000 N/A ns Lock time The time that the application has to wait for the PLL to acquire lock before setting OSCIN N/A N/A PLLEN, after changing PREDIV, PLLM, or cycles OSCIN PREDIV Pre-divider value /32 ns PLLREF PLL input frequency MHz PLLM PLL multiplier values x20 x32 PLLOUT PLL output frequency N/A 400 600 (1) MHz POSTDIV Post-divider value (1) /32 ns (1) PLL post divider must be used. The /4.5 clock path can be used to generate an EMIF clock from the undivided (i.e. 600 MHz) PLL output clock. PLL0 is controlled by PLL Controller and PLL1 is controlled by PLL Controller PLLC0 and PLLC1 manage the clock ratios, alignment, and gating for the system clocks to the chip. The PLLCs are responsible for controlling all modes of the PLL through software, in terms of pre-division of the clock inputs (PLLC0 only), multiply factors within the PLLs, and post-division for each of the chip-level clocks from the PLLs outputs. PLLC0 also controls reset propagation through the chip, clock alignment, and test points. PLLC0 provides clocks for the majority of the system but PLLC1 provides clocks to the mDDR/DDR2 Controller and the ASYNC3 clock domain to provide frequency scaling immunity to a defined set or peripherals. The ASYNC3 clock domain can either derive its clock from PLL1_SYSCLK2 (for frequency scaling immunity from PLL0) or from PLL0_SYSCLK2 (for synchronous timing with PLL0) depending on the application requirements. In addition, some peripherals have specific clock options independent of the ASYNC clock domain. Submit Documentation Feedback Peripheral Information and Electrical Specifications

6.7 Interrupts 6.7.1 ARM CPU Interrupts 6.7.1.1 ARM Interrupt Controller (AINTC) Interrupt Signal Hierarchy 6.7.1.2 AINTC Hardware Vector Generation 6.7.1.3 AINTC Hardware Interrupt Nesting Support OMAP-L138 Low-Power www.ti.com The device has a large number of interrupts to service the needs of its many peripherals and subsystems. Both the ARM and C674x CPUs are capable of servicing these interrupts equally. The interrupts can be selectively enabled or disabled in either of the controllers. Also, the ARM and DSP can communicate with each other through interrupts controlled by registers in the SYSCFG module. The ARM9 CPU core supports direct interrupts: FIQ and IRQ. The ARM Interrupt Controller (AINTC) extends the number of interrupts to 100, and provides masking, priority, hardware nesting support, and interrupt vector generation. The ARM Interrupt controller organizes interrupts into the following hierarchy: Peripheral Interrupt Requests Individual Interrupt Sources from Peripherals 101 System Interrupts One or more Peripheral Interrupt Requests are combined (fixed configuration) to generate a System Interrupt. After prioritization, the AINTC will provide an interrupt vector based unique to each System Interrupt Interrupt Channels Each System Interrupt is mapped to one of the Interrupt Channels Channel Number determines the first level of prioritization, Channel is highest priority and lowest. If more than one system interrupt is mapped to a channel, priority within the channel is determined by system interrupt number highest priority) Host Interrupts (FIQ and IRQ) Interrupt Channels and generate the ARM FIQ interrupt Interrupt Channels through Generate the ARM IRQ interrupt Debug Interrupts Two Debug Interrupts are supported and can be used to trigger events in the debug subsystem Sources can be selected from any of the System Interrupts or Host Interrupts The AINTC also generates an interrupt vector in hardware for both IRQ and FIQ host interrupts. This may be used to accelerate interrupt dispatch. A unique vector is generated for each of the 100 system interrupts. The vector is computed in hardware as: VECTOR BASE (SYSTEM INTERRUPT NUMBER SIZE) Where BASE and SIZE are programmable. The computed vector is a 32-bit address which may dispatched to using a single instruction of type LDR PC, [PC, offset_12 at the FIQ and IRQ vector locations (0xFFFF0018 and 0xFFFF001C respectively). Interrupt nesting occurs when an interrupt service routine re-enables interrupts, to allow the CPU to interrupt the ISR if a higher priority event occurs. The AINTC provides hardware support to facilitate interrupt nesting. It supports both global and per host interrupt (FIQ and IRQ in this case) automatic nesting. If enabled, the AINTC will automatically update an internal nesting register that temporarily masks interrupts at and below the priority of the current interrupt channel. Then if the ISR re-enables interrupts; only higher priority channels will be able to interrupt it. The nesting level is restored by the ISR by writing to the nesting level register on completion. Support for nesting can be enabled/disabled by software, with the option of automatic nesting on a global or per host interrupt basis; or manual nesting. Peripheral Information and Electrical Specifications Submit Documentation Feedback

6.7.1.4 AINTC System Interrupt Assignments OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 System Interrupt assignments are listed in Table 6-5 Table 6-5. AINTC System Interrupt Assignments System Interrupt Interrupt Name Source COMMTX ARM COMMRX ARM NINT ARM PRU_EVTOUT0 PRUSS Interrupt PRU_EVTOUT1 PRUSS Interrupt PRU_EVTOUT2 PRUSS Interrupt PRU_EVTOUT3 PRUSS Interrupt PRU_EVTOUT4 PRUSS Interrupt PRU_EVTOUT5 PRUSS Interrupt PRU_EVTOUT6 PRUSS Interrupt PRU_EVTOUT7 PRUSS Interrupt EDMA3_0_CC0_INT0 EDMA3_0 Channel Controller Shadow Region Transfer Completion Interrupt EDMA3_0_CC0_ERRINT EDMA3_0 Channel Controller Error Interrupt EDMA3_0_TC0_ERRINT EDMA3_0 Transfer Controller Error Interrupt EMIFA_INT EMIFA IIC0_INT I2C0 MMCSD0_INT0 MMCSD0 MMC/SD Interrupt MMCSD0_INT1 MMCSD0 SDIO Interrupt PSC0_ALLINT PSC0 RTC_IRQS[1:0] RTC SPI0_INT SPI0 T64P0_TINT12 Timer64P0 Interrupt T64P0_TINT34 Timer64P0 Interrupt T64P1_TINT12 Timer64P1 Interrupt T64P1_TINT34 Timer64P1 Interrupt UART0_INT UART0 Reserved PROTERR SYSCFG Protection Shared Interrupt SYSCFG_CHIPINT0 SYSCFG CHIPSIG Register SYSCFG_CHIPINT1 SYSCFG CHIPSIG Register SYSCFG_CHIPINT2 SYSCFG CHIPSIG Register SYSCFG_CHIPINT3 SYSCFG CHIPSIG Register EDMA3_0_TC1_ERRINT EDMA3_0 Transfer Controller Error Interrupt EMAC_C0RXTHRESH EMAC Core Receive Threshold Interrupt EMAC_C0RX EMAC Core Receive Interrupt EMAC_C0TX EMAC Core Transmit Interrupt EMAC_C0MISC EMAC Core Miscellaneous Interrupt EMAC_C1RXTHRESH EMAC Core Receive Threshold Interrupt EMAC_C1RX EMAC Core Receive Interrupt EMAC_C1TX EMAC Core Transmit Interrupt EMAC_C1MISC EMAC Core Miscellaneous Interrupt DDR2_MEMERR DDR2 Controller GPIO_B0INT GPIO Bank Interrupt Submit Documentation Feedback Peripheral Information and Electrical Specifications

www.ti.com Table 6-5. AINTC System Interrupt Assignments (continued) System Interrupt Interrupt Name Source GPIO_B1INT GPIO Bank Interrupt GPIO_B2INT GPIO Bank Interrupt GPIO_B3INT GPIO Bank Interrupt GPIO_B4INT GPIO Bank Interrupt GPIO_B5INT GPIO Bank Interrupt GPIO_B6INT GPIO Bank Interrupt GPIO_B7INT GPIO Bank Interrupt GPIO_B8INT GPIO Bank Interrupt IIC1_INT I2C1 LCDC_INT LCD Controller UART_INT1 UART1 MCASP_INT McASP0 Combined RX TX Interrupts PSC1_ALLINT PSC1 SPI1_INT SPI1 UHPI_ARMINT UHPI ARM Interrupt USB0_INT USB0 Interrupt USB1_HCINT USB1 OHCI Host Controller Interrupt USB1_RWAKEUP USB1 Remote Wakeup Interrupt UART2_INT UART2 Reserved EHRPWM0 HiResTimer PWM0 Interrupt EHRPWM0TZ HiResTimer PWM0 Trip Zone Interrupt EHRPWM1 HiResTimer PWM1 Interrupt EHRPWM1TZ HiResTimer PWM1 Trip Zone Interrupt SATA_INT SATA Controller T64P2_ALL Timer64P2 Combined TINT12 and TINT34 ECAP0 ECAP0 ECAP1 ECAP1 ECAP2 ECAP2 MMCSD1_INT0 MMCSD1 MMC/SD Interrupt MMCSD1_INT1 MMCSD1 SDIO Interrupt T64P0_CMPINT0 Timer64P0 Compare T64P0_CMPINT1 Timer64P0 Compare T64P0_CMPINT2 Timer64P0 Compare T64P0_CMPINT3 Timer64P0 Compare T64P0_CMPINT4 Timer64P0 Compare T64P0_CMPINT5 Timer64P0 Compare T64P0_CMPINT6 Timer64P0 Compare T64P0_CMPINT7 Timer64P0 Compare T64P1_CMPINT0 Timer64P1 Compare T64P1_CMPINT1 Timer64P1 Compare T64P1_CMPINT2 Timer64P1 Compare T64P1_CMPINT3 Timer64P1 Compare T64P1_CMPINT4 Timer64P1 Compare T64P1_CMPINT5 Timer64P1 Compare T64P1_CMPINT6 Timer64P1 Compare T64P1_CMPINT7 Timer64P1 Compare Peripheral Information and Electrical Specifications Submit Documentation Feedback

www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 6-5. AINTC System Interrupt Assignments (continued) System Interrupt Interrupt Name Source ARMCLKSTOPREQ PSC0 uPP_ALLINT uPP Combined Interrupt Channel I End-of-Line Interrupt Channel I End-of-Window Interrupt Channel I DMA Access Interrupt Channel I Overflow-Underrun Interrupt Channel I DMA Programming Error Interrupt Channel Q End-of-Line Interrupt Channel Q End-of-Window Interrupt Channel Q DMA Access Interrupt Channel Q Overflow-Underrun Interrupt Channel Q DMA Programming Error Interrupt VPIF_ALLINT VPIF Combined Interrupt Channel Frame Interrupt Channel Frame Interrupt Channel Frame Interrupt Channel Frame Interrupt Error Interrupt EDMA3_1_CC0_INT0 EDMA3_1 Channel Controller Shadow Region Transfer Completion Interrupt EDMA3_1_CC0_ERRINT EDMA3_1Channel Controller Error Interrupt EDMA3_1_TC0_ERRINT EDMA3_1 Transfer Controller Error Interrupt T64P3_ALL Timer64P Combined TINT12 and TINT34 MCBSP0_RINT McBSP0 Receive Interrupt MCBSP0_XINT McBSP0 Transmit Interrupt MCBSP1_RINT McBSP1 Receive Interrupt 100 MCBSP1_XINT McBSP1 Transmit Interrupt Submit Documentation Feedback Peripheral Information and Electrical Specifications

6.7.1.5 AINTC Memory Map OMAP-L138 Low-Power www.ti.com Table 6-6. AINTC Memory Map BYTE ADDRESS ACRONYM SRSR[0] System Interrupt Status Raw Set Registers 0xFFFE E204 SRSR[1] 0xFFFE E208 SRSR[2] 0xFFFE E20C SRSR[3] 0xFFFE E210- 0xFFFE E27F Reserved 0xFFFE E280 SECR[0] System Interrupt Status Enabled Clear Registers 0xFFFE E284 SECR[1] 0xFFFE E288 SECR[2] 0xFFFE E28C SECR[3] 0xFFFE E290 0xFFFE E2FF Reserved 0xFFFE E300 ESR[0] System Interrupt Enable Set Registers 0xFFFE E304 ESR[1] 0xFFFE E308 ESR[2] 0xFFFE E30C ESR[3] 0xFFFE E310 0xFFFE E37F Reserved 0xFFFE E380 ECR[0] System Interrupt Enable Clear Registers 0xFFFE E384 ECR[1] 0xFFFE E388 ECR[2] 0xFFFE E38C ECR[3] 0xFFFE E390 0xFFFE E3FF Reserved Peripheral Information and Electrical Specifications Submit Documentation Feedback

www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 6-6. AINTC Memory Map (continued) BYTE ADDRESS ACRONYM CMR[0] Channel Map Registers 0xFFFE E404 CMR[1] 0xFFFE E408 CMR[2] 0xFFFE E40C CMR[3] 0xFFFE E410 CMR[4] 0xFFFE E414 CMR[5] 0xFFFE E418 CMR[6] 0xFFFE E41C CMR[7] 0xFFFE E420 CMR[8] 0xFFFE E424 CMR[9] 0xFFFE E428 CMR[10] 0xFFFE E42C CMR[11] 0xFFFE E430 CMR[12] 0xFFFE E434 CMR[13] 0xFFFE E438 CMR[14] 0xFFFE E43C CMR[15] 0xFFFE E440 CMR[16] 0xFFFE E444 CMR[17] 0xFFFE E448 CMR[18] 0xFFFE E44C CMR[19] 0xFFFE E450 CMR[20] 0xFFFE E454 CMR[21] 0xFFFE E458 CMR[22] 0xFFFE E45C CMR[23] 0xFFFE E460 CMR[24] 0xFFFE E464 CMR[25] 0xFFFE E468 0xFFFE E8FF Reserved 0xFFFE E900 HIPIR[0] Host Interrupt Prioritized Index Registers 0xFFFE E904 HIPIR[1] 0xFFFE E908 0xFFFE EEFF Reserved 0xFFFE EF00 DSR[0] Debug Select Registers 0xFFFE EF04 DSR[1] 0xFFFE EF08 0xFFFE F0FF Reserved 0xFFFE F100 HINLR[0] Host Interrupt Nesting Level Registers 0xFFFE F104 HINLR[1] 0xFFFE F108 0xFFFE F4FF Reserved 0xFFFE F500 HIER[0] Host Interrupt Enable Register 0xFFFE F504 0xFFFE F5FF Reserved 0xFFFE F600 HIPVR[0] Host Interrupt Prioritized Vector Registers 0xFFFE F604 HIPVR[1] 0xFFFE F608 0xFFFE FFFF Reserved Submit Documentation Feedback Peripheral Information and Electrical Specifications

6.7.2 DSP Interrupts OMAP-L138 Low-Power www.ti.com The C674x DSP interrupt controller combines device events into prioritized interrupts. The source for each of the CPU interrupts is user programmable and is listed in Table 6-7 Also, the interrupt controller controls the generation of the CPU exceptions, NMI, and emulation interrupts. Table 6-8 summarizes the C674x interrupt controller registers and memory locations. Peripheral Information and Electrical Specifications Submit Documentation Feedback

www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 6-7. OMAP-L138 DSP Interrupts EVT# Interrupt Name Source EVT0 C674x Int Ctl EVT1 C674x Int Ctl EVT2 C674x Int Ctl EVT3 C674x Int Ctl T64P0_TINT12 Timer64P0 TINT12 SYSCFG_CHIPINT2 SYSCFG CHIPSIG Register PRU_EVTOUT0 PRUSS Interrupt EHRPWM0 HiResTimer/PWM0 Interrupt EDMA3_0_CC0_INT1 EDMA3_0 Channel Controller Shadow Region Transfer Completion Interrupt EMU_DTDMA C674x-ECM EHRPWM0TZ HiResTimer/PWM0 Trip Zone Interrupt EMU_RTDXRX C674x-RTDX EMU_RTDXTX C674x-RTDX IDMAINT0 C674x-EMC IDMAINT1 C674x-EMC MMCSD0_INT0 MMCSD0 MMC/SD Interrupt MMCSD0_INT1 MMCSD0 SDIO Interrupt PRU_EVTOUT1 PRUSS Interrupt EHRPWM1 HiResTimer/PWM1 Interrupt USB0_INT USB0 Interrupt USB1_HCINT USB1 OHCI Host Controller Interrupt USB1_RWAKEUP USB1 Remote Wakeup Interrupt PRU_EVTOUT2 PRUSS Interrupt EHRPWM1TZ HiResTimer/PWM1 Trip Zone Interrupt SATA_INT SATA Controller T64P2_TINTALL Timer64P2 Combined TINT12 and TINT Interrupt EMAC_C0RXTHRESH EMAC Core Receive Threshold Interrupt EMAC_C0RX EMAC Core Receive Interrupt EMAC_C0TX EMAC Core Transmit Interrupt EMAC_C0MISC EMAC Core Miscellaneous Interrupt EMAC_C1RXTHRESH EMAC Core Receive Threshold Interrupt EMAC_C1RX EMAC Core Receive Interrupt EMAC_C1TX EMAC Core Transmit Interrupt EMAC_C1MISC EMAC Core Miscellaneous Interrupt UHPI_DSPINT UHPI DSP Interrupt PRU_EVTOUT3 PRUSS Interrupt IIC0_INT I2C0 SP0_INT SPI0 UART0_INT UART0 PRU_EVTOUT5 PRUSS Interrupt T64P1_TINT12 Timer64P1 Interrupt GPIO_B1INT GPIO Bank Interrupt IIC1_INT I2C1 SPI1_INT SPI1 PRU_EVTOUT6 PRUSS Interrupt ECAP0 ECAP0 Submit Documentation Feedback Peripheral Information and Electrical Specifications

www.ti.com Table 6-7. OMAP-L138 DSP Interrupts (continued) EVT# Interrupt Name Source UART_INT1 UART1 ECAP1 ECAP1 T64P1_TINT34 Timer64P1 Interrupt GPIO_B2INT GPIO Bank Interrupt PRU_EVTOUT7 PRUSS Interrupt ECAP2 ECAP2 GPIO_B3INT GPIO Bank Interrupt MMCSD1_INT1 MMCSD1 SDIO Interrupt GPIO_B4INT GPIO Bank Interrupt EMIFA_INT EMIFA EDMA3_0_CC0_ERRINT EDMA3_0 Channel Controller Error Interrupt EDMA3_0_TC0_ERRINT EDMA3_0 Transfer Controller Error Interrupt EDMA3_0_TC1_ERRINT EDMA3_0 Transfer Controller Error Interrupt GPIO_B5INT GPIO Bank Interrupt DDR2_MEMERR DDR2 Memory Error Interrupt MCASP0_INT McASP0 Combined RX/TX Interrupts GPIO_B6INT GPIO Bank Interrupt RTC_IRQS RTC Combined T64P0_TINT34 Timer64P0 Interrupt GPIO_B0INT GPIO Bank Interrupt PRU_EVTOUT4 PRUSS Interrupt SYSCFG_CHIPINT3 SYSCFG_CHIPSIG Register MMCSD1_INT0 MMCSD1 MMC/SD Interrupt UART2_INT UART2 PSC0_ALLINT PSC0 PSC1_ALLINT PSC1 GPIO_B7INT GPIO Bank Interrupt LCDC_INT LDC Controller PROTERR SYSCFG Protection Shared Interrupt GPIO_B8INT GPIO Bank Interrupt Reserved Reserved T64P2_CMPINT0 Timer64P2 Compare Interrupt T64P2_CMPINT1 Timer64P2 Compare Interrupt T64P2_CMPINT2 Timer64P2 Compare Interrupt T64P2_CMPINT3 Timer64P2 Compare Interrupt T64P2_CMPINT4 Timer64P2 Compare Interrupt T64P2_CMPINT5 Timer64P2 Compare Interrupt T64P2_CMPINT6 Timer64P2 Compare Interrupt T64P2_CMPINT7 Timer64P2 Compare Interrupt T64P3_TINTALL Timer64P3 Combined TINT12 and TINT Interrupt MCBSP0_RINT McBSP0 Receive Interrupt MCBSP0_XINT McBSP0 Transmit Interrupt MCBSP1_RINT McBSP1 Receive Interrupt MCBSP1_XINT McBSP1 Transmit Interrupt EDMA3_1_CC0_INT1 EDMA3_1 Channel Controller Shadow Region Transfer Completion Interrupt Peripheral Information and Electrical Specifications Submit Documentation Feedback

www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 6-7. OMAP-L138 DSP Interrupts (continued) EVT# Interrupt Name Source EDMA3_1_CC0_ERRINT EDMA3_1 Channel Controller Error Interrupt EDMA3_1_TC0_ERRINT EDMA3_1 Transfer Controller Error Interrupt UPP_INT uPP Combined Interrupt VPIF_INT VPIF Combined Interrupt INTERR C674x-Int Ctl EMC_IDMAERR C674x-EMC Reserved Reserved 100 Reserved 101 Reserved 102 Reserved 103 Reserved 104 Reserved 105 Reserved 106 Reserved 107 Reserved 108 Reserved 109 Reserved 110 Reserved 111 Reserved 112 Reserved 113 PMC_ED C674x-PMC 114 Reserved 115 Reserved 116 UMC_ED1 C674x-UMC 117 UMC_ED2 C674x-UMC 118 PDC_INT C674x-PDC 119 SYS_CMPA C674x-SYS 120 PMC_CMPA C674x-PMC 121 PMC_CMPA C674x-PMC 122 DMC_CMPA C674x-DMC 123 DMC_CMPA C674x-DMC 124 UMC_CMPA C674x-UMC 125 UMC_CMPA C674x-UMC 126 EMC_CMPA C674x-EMC 127 EMC_BUSERR C674x-EMC Submit Documentation Feedback Peripheral Information and Electrical Specifications

www.ti.com Table 6-8. C674x DSP Interrupt Controller Registers BYTE ADDRESS REGISTER NAME

6.8 Power and Sleep Controller (PSC) OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 The Power and Sleep Controllers (PSC) are responsible for managing transitions of system power on/off, clock on/off, resets (device level and module level). It is used primarily to provide granular power control for on chip modules (peripherals and CPU). A PSC module consists of a Global PSC (GPSC) and a set of Local PSCs (LPSCs). The GPSC contains memory mapped registers, PSC interrupts, a state machine for each peripheral/module it controls. An LPSC is associated with every module that is controlled by the PSC and provides clock and reset control. The PSC includes the following features: Provides a software interface to: Control module clock enable/disable Control module reset Control CPU local reset Supports IcePick emulation features: power, clock and reset PSC0 controls local PSCs. PSC1 controls local PSCs. Table 6-9. Power and Sleep Controller (PSC) Registers PSC0 BYTE PSC1 BYTE ACRONYM REGISTER (module 0-15) (PSC0) Module Error Pending Register (module 0-31) (PSC1) 0x01C1 0050 0x01E2 7050 MERRCR0 Module Error Clear Register (module 0-15) (PSC0) Module Error Clear Register (module 0-31) (PSC1) 0x01C1 0060 0x01E2 7060 PERRPR Power Error Pending Register 0x01C1 0068 0x01E2 7068 PERRCR Power Error Clear Register 0x01C1 0120 0x01E2 7120 PTCMD Power Domain Transition Command Register 0x01C1 0128 0x01E2 7128 PTSTAT Power Domain Transition Status Register 0x01C1 0200 0x01E2 7200 PDSTAT0 Power Domain Status Register 0x01C1 0204 0x01E2 7204 PDSTAT1 Power Domain Status Register 0x01C1 0300 0x01E2 7300 PDCTL0 Power Domain Control Register 0x01C1 0304 0x01E2 7304 PDCTL1 Power Domain Control Register 0x01C1 0400 0x01E2 7400 PDCFG0 Power Domain Configuration Register 0x01C1 0404 0x01E2 7404 PDCFG1 Power Domain Configuration Register 0x01C1 0800 0x01E2 7800 MDSTAT0 Module Status Register 0x01C1 0804 0x01E2 7804 MDSTAT1 Module Status Register 0x01C1 0808 0x01E2 7808 MDSTAT2 Module Status Register 0x01C1 080C 0x01E2 780C MDSTAT3 Module Status Register 0x01C1 0810 0x01E2 7810 MDSTAT4 Module Status Register 0x01C1 0814 0x01E2 7814 MDSTAT5 Module Status Register 0x01C1 0818 0x01E2 7818 MDSTAT6 Module Status Register 0x01C1 081C 0x01E2 781C MDSTAT7 Module Status Register 0x01C1 0820 0x01E2 7820 MDSTAT8 Module Status Register 0x01C1 0824 0x01E2 7824 MDSTAT9 Module Status Register 0x01C1 0828 0x01E2 7828 MDSTAT10 Module Status Register 0x01C1 082C 0x01E2 782C MDSTAT11 Module Status Register 0x01C1 0830 0x01E2 7830 MDSTAT12 Module Status Register 0x01C1 0834 0x01E2 7834 MDSTAT13 Module Status Register Submit Documentation Feedback Peripheral Information and Electrical Specifications

www.ti.com Table 6-9. Power and Sleep Controller (PSC) Registers (continued) PSC0 BYTE PSC1 BYTE ACRONYM REGISTER

6.8.1 Power Domain and Module Topology OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 6-9. Power and Sleep Controller (PSC) Registers (continued) PSC0 BYTE PSC1 BYTE ACRONYM REGISTER modules. Each PSC module controls clock states for several of the on chip modules, controllers and interconnect components. Table 6-10 and Table 6-11 lists the set of peripherals/modules that are controlled by the PSC, the power domain they are associated with, the LPSC assignment and the default (power-on reset) module states. See the device-specific data manual for the peripherals available on a given device. The module states and terminology are defined in Section 6.8.1.2 Table 6-10. PSC0 Default Module Configuration LPSC Module Name Power Domain Default Module State Auto Sleep/Wake Only Number EDMA3 Channel Controller AlwaysON (PD0) SwRstDisable EDMA3 Transfer Controller AlwaysON (PD0) SwRstDisable EDMA3 Transfer Controller AlwaysON (PD0) SwRstDisable EMIFA (Br7) AlwaysON (PD0) SwRstDisable SPI AlwaysON (PD0) SwRstDisable MMC/SD AlwaysON (PD0) SwRstDisable ARM Interrupt Controller AlwaysON (PD0) SwRstDisable ARM RA M/ROM AlwaysON (PD0) Enable Yes UART AlwaysON (PD0) SwRstDisable SCR0 (Br Br Br Br AlwaysON (PD0) Enable Yes SCR1 (Br AlwaysON (PD0) Enable Yes SCR2 (Br Br Br AlwaysON (PD0) Enable Yes PRUSS AlwaysON (PD0) SwRstDisable ARM AlwaysON (PD0) SwRstDisable DSP PD_DSP (PD1) Enable Submit Documentation Feedback Peripheral Information and Electrical Specifications

www.ti.com Table 6-11. PSC1 Default Module Configuration LPSC Module Name Power Domain Default Module State Auto Sleep/Wake Only Number EDMA3 Channel Controller AlwaysON (PD0) SwRstDisable USB0 (USB2.0) AlwaysON (PD0) SwRstDisable USB1 (USB1.1) AlwaysON (PD0) SwRstDisable GPIO AlwaysON (PD0) SwRstDisable UHPI AlwaysON (PD0) SwRstDisable EMAC AlwaysON (PD0) SwRstDisable DDR2 (and SCR_F3) AlwaysON (PD0) SwRstDisable McASP0 McASP0 FIFO) AlwaysON (PD0) SwRstDisable SATA AlwaysON (PD0) SwRstDisable VPIF AlwaysON (PD0) SwRstDisable SPI AlwaysON (PD0) SwRstDisable I2C AlwaysON (PD0) SwRstDisable UART AlwaysON (PD0) SwRstDisable UART AlwaysON (PD0) SwRstDisable McBSP0 McBSP0 FIFO) AlwaysON (PD0) SwRstDisable McBSP1 McBSP1 FIFO) AlwaysON (PD0) SwRstDisable LCDC AlwaysON (PD0) SwRstDisable eHRPWM0/1 AlwaysON (PD0) SwRstDisable MMCSD1 AlwaysON (PD0) SwRstDisable uPP AlwaysON (PD0) SwRstDisable ECAP0/1/2 AlwaysON (PD0) SwRstDisable EDMA3 Transfer Controller AlwaysON (PD0) SwRstDisable SCR_F0 (and bridge F0) AlwaysON (PD0) Enable Yes SCR_F1 (and bridge F1) AlwaysON (PD0) Enable Yes SCR_F2 (and bridge F2) AlwaysON (PD0) Enable Yes SCR_F6 (and bridge F3) AlwaysON (PD0) Enable Yes SCR_F7 (and bridge F4) AlwaysON (PD0) Enable Yes SCR_F8 (and bridge F5) AlwaysON (PD0) Enable Yes Bridge (DDR Controller path) AlwaysON (PD0) Enable Yes Shared RAM (including SCR_F4 PD_SHRAM Enable and bridge F6) Peripheral Information and Electrical Specifications Submit Documentation Feedback

6.8.1.1 Power Domain States 6.8.1.2 Module States OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 A power domain can only be in one of the two states: ON or OFF, defined as follows: ON: power to the domain is on OFF: power to the domain is off For both PSC0 and PSC1, the Always ON domain, or PD0 power domain, is always in the ON state when the chip is powered-on. This domain is not programmable to OFF state. On PSC0 PD1/PD_DSP Domain: Controls the sleep state for DSP and Memories On PSC1 PD1/PD_SHRAM Domain: Controls the sleep state for the 128K Shared RAM The PSC defines several possible states for a module. This states are essentially a combination of the module reset asserted or de-asserted and module clock on/enabled or off/disabled. The module states are defined in Table 6-12 Table 6-12. Module States Module State Module Reset Module Module State Definition Clock Enable De-asserted On A module in the enable state has its module reset de-asserted and it has its clock on. This is the normal operational state for a given module Disable De-asserted Off A module in the disabled state has its module reset de-asserted and it has its module clock off. This state is typically used for disabling a module clock to save power. The device is designed in full static CMOS, so when you stop a module clock, it retains the module s state. When the clock is restarted, the module resumes operating from the stopping point. SyncReset Asserted On A module state in the SyncReset state has its module reset asserted and it has its clock on. Generally, software is not expected to initiate this state SwRstDisable Asserted Off A module in the SwResetDisable state has its module reset asserted and it has its clock disabled. After initial power-on, several modules come up in the SwRstDisable state. Generally, software is not expected to initiate this state Auto Sleep De-asserted Off A module in the Auto Sleep state also has its module reset de-asserted and its module clock disabled, similar to the Disable state. However this is a special state, once a module is configured in this state by software, it can automatically transition to Enable state whenever there is an internal read/write request made to it, and after servicing the request it will automatically transition into the sleep state (with module reset re de-asserted and module clock disabled), without any software intervention. The transition from sleep to enabled and back to sleep state has some cycle latency associated with it. It is not envisioned to use this mode when peripherals are fully operational and moving data. Auto Wake De-asserted Off A module in the Auto Wake state also has its module reset de-asserted and its module clock disabled, similar to the Disable state. However this is a special state, once a module is configured in this state by software, it will automatically transition to Enable state whenever there is an internal read/write request made to it, and will remain in the Enabled state from then on (with module reset re de-asserted and module clock on), without any software intervention. The transition from sleep to enabled state has some cycle latency associated with it. It is not envisioned to use this mode when peripherals are fully operational and moving data. Submit Documentation Feedback Peripheral Information and Electrical Specifications

6.9 EDMA 6.9.1 EDMA3 Channel Synchronization Events OMAP-L138 Low-Power www.ti.com The EDMA controller handles all data transfers between memories and the device slave peripherals on the device. These data transfers include cache servicing, non-cacheable memory accesses, user-programmed data transfers, and host accesses. Each EDMA channel controller supports up to channels which service peripherals and memory. Table 6-13 lists the source of the EDMA synchronization events associated with each of the programmable EDMA channels. Table 6-13. EDMA Synchronization Events EDMA0 Channel Controller Event Event Name Source Event Event Name Source McASP0 Receive MMCSD0 Receive McASP0 Transmit MMCSD0 Transmit McBSP0 Receive SPI1 Receive McBSP0 Transmit SPI1 Transmit McBSP1 Receive PRU_EVTOUT6 McBSP1 Transmit PRU_EVTOUT7 GPIO Bank Interrupt GPIO Bank Interrupt GPIO Bank Interrupt GPIO Bank Interrupt UART0 Receive I2C0 Receive UART0 Transmit I2C0 Transmit Timer64P0 Event Out I2C1 Receive Timer64P0 Event Out I2C1 Transmit UART1 Receive GPIO Bank Interrupt UART1 Transmit GPIO Bank Interrupt SPI0 Receive UART2 Receive SPI0 Transmit UART2 Transmit EDMA1 Channel Controller Event Event Name Source Event Event Name Source Timer64P2 Compare Event GPIO Bank Interrupt Timer64P2 Compare Event GPIO Bank Interrupt Timer64P2 Compare Event GPIO Bank Interrupt Timer64P2 Compare Event Reserved Timer64P2 Compare Event Reserved Timer64P2 Compare Event Reserved Timer64P2 Compare Event Reserved Timer64P2 Compare Event Reserved Timer64P3 Compare Event Timer64P2 Event Out Timer64P3 Compare Event Timer64P2 Event Out Timer64P3 Compare Event Timer64P3 Event Out Timer64P3 Compare Event Timer64P3 Event Out Timer64P3 Compare Event MMCSD0 Receive Timer64P3 Compare Event MMCSD0 Transmit Timer64P3 Compare Event Reserved Timer64P3 Compare Event Reserved Peripheral Information and Electrical Specifications Submit Documentation Feedback

6.9.2 EDMA Peripheral Register Descriptions OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 6-14 is the list of EDMA3 Channel Controller Registers and Table 6-15 is the list of EDMA3 Transfer Controller registers. Table 6-14. EDMA3 Channel Controller (EDMA3CC) Registers EDMA0 Channel Controller EDMA1 Channel Controller ACRONYM REGISTER (1) 0x01C0 0300 0x01E3 0300 EMR Event Missed Register 0x01C0 0308 0x01E3 0308 EMCR Event Missed Clear Register 0x01C0 0310 0x01E3 0310 QEMR QDMA Event Missed Register 0x01C0 0314 0x01E3 0314 QEMCR QDMA Event Missed Clear Register 0x01C0 0318 0x01E3 0318 CCERR EDMA3CC Error Register 0x01C0 031C 0x01E3 031C CCERRCLR EDMA3CC Error Clear Register 0x01C0 0320 0x01E3 0320 EEVAL Error Evaluate Register 0x01C0 0340 0x01E3 0340 DRAE0 DMA Region Access Enable Register for Region 0x01C0 0348 0x01E3 0348 DRAE1 DMA Region Access Enable Register for Region 0x01C0 0350 0x01E3 0350 DRAE2 DMA Region Access Enable Register for Region 0x01C0 0358 0x01E3 0358 DRAE3 DMA Region Access Enable Register for Region 0x01C0 0380 0x01E3 0380 QRAE0 QDMA Region Access Enable Register for Region 0x01C0 0384 0x01E3 0384 QRAE1 QDMA Region Access Enable Register for Region 0x01C0 0388 0x01E3 0388 QRAE2 QDMA Region Access Enable Register for Region 0x01C0 038C 0x01E3 038C QRAE3 QDMA Region Access Enable Register for Region 0x01C0 0400 0x01C0 043C 0x01E3 0400 0x01E3 043C Q0E0-Q0E15 Event Queue Entry Registers Q0E0-Q0E15 0x01C0 0440 0x01C0 047C 0x01E3 0440 0x01E3 047C Q1E0-Q1E15 Event Queue Entry Registers Q1E0-Q1E15 0x01C0 0600 0x01E3 0600 QSTAT0 Queue Status Register 0x01C0 0604 0x01E3 0604 QSTAT1 Queue Status Register 0x01C0 0620 0x01E3 0620 QWMTHRA Queue Watermark Threshold A Register 0x01C0 0640 0x01E3 0640 CCSTAT EDMA3CC Status Register Global Channel Registers (1) On previous architectures, the EDMA3TC priority was controlled by the queue priority register (QUEPRI) in the EDMA3CC memory-map. However for this device, the priority control for the transfer controllers is controlled by the chip-level registers in the System Configuration Module. You should use the chip-level registers and not QUEPRI to configure the TC priority. Submit Documentation Feedback Peripheral Information and Electrical Specifications

www.ti.com Table 6-14. EDMA3 Channel Controller (EDMA3CC) Registers (continued) EDMA0 Channel Controller EDMA1 Channel Controller ACRONYM REGISTER

www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 6-14. EDMA3 Channel Controller (EDMA3CC) Registers (continued) EDMA0 Channel Controller EDMA1 Channel Controller ACRONYM REGISTER (PaRAM) Table 6-15. EDMA3 Transfer Controller (EDMA3TC) Registers EDMA0 EDMA0 EDMA1 ACRONYM REGISTER

www.ti.com Table 6-15. EDMA3 Transfer Controller (EDMA3TC) Registers (continued) EDMA0 EDMA0 EDMA1 ACRONYM REGISTER events. Each of the parameter register sets consist of 32-bit word entries. Table 6-17 shows the parameter set entry registers with relative memory address locations within each of the parameter sets. Table 6-16. EDMA Parameter Set RAM EDMA0 EDMA1 Channel Controller Channel Controller words) 0x01C0 4020 0x01C0 403F 0x01E3 4020 0x01E3 403F Parameters Set 32-bit words) 0x01C0 4040 0x01CC0 405F 0x01E3 4040 0x01CE3 405F Parameters Set 32-bit words) 0x01C0 4060 0x01C0 407F 0x01E3 4060 0x01E3 407F Parameters Set 32-bit words) 0x01C0 4080 0x01C0 409F 0x01E3 4080 0x01E3 409F Parameters Set 32-bit words) 0x01C0 40A0 0x01C0 40BF 0x01E3 40A0 0x01E3 40BF Parameters Set 32-bit words) ... ... ... 0x01C0 4FC0 0x01C0 4FDF 0x01E3 4FC0 0x01E3 4FDF Parameters Set 126 32-bit words) 0x01C0 4FE0 0x01C0 4FFF 0x01E3 4FE0 0x01E3 4FFF Parameters Set 127 32-bit words) Peripheral Information and Electrical Specifications 102 Submit Documentation Feedback

www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 6-17. Parameter Set Entries OFFSET BYTE ADDRESS ACRONYM PARAMETER ENTRY WITHIN THE PARAMETER SET 0x0000 OPT Option 0x0004 SRC Source Address 0x0008 A_B_CNT A Count, B Count 0x000C DST Destination Address 0x0010 SRC_DST_BIDX Source B Index, Destination B Index 0x0014 LINK_BCNTRLD Link Address, B Count Reload 0x0018 SRC_DST_CIDX Source C Index, Destination C Index 0x001C CCNT C Count Submit Documentation Feedback Peripheral Information and Electrical Specifications 103

6.10 External Memory Interface A (EMIFA) 6.10.1 EMIFA Asynchronous Memory Support 6.10.2 EMIFA Synchronous DRAM Memory Support OMAP-L138 Low-Power www.ti.com EMIFA is one of two external memory interfaces supported on the device. It is primarily intended to support asynchronous memory types, such as NAND and NOR flash and Asynchronous SRAM. However on this device, EMIFA also provides a secondary interface to SDRAM. EMIFA supports asynchronous: SRAM memories NAND Flash memories NOR Flash memories The EMIFA data bus width is up to 16-bits. The device supports up to address lines and two external wait/interrupt inputs. Up to four asynchronous chip selects are supported by EMIFA (EMA_CS[5:2]) Each chip select has the following individually programmable attributes: Data Bus Width Read cycle timings: setup, hold, strobe Write cycle timings: setup, hold, strobe Bus turn around time Extended Wait Option With Programmable Timeout Select Strobe Option NAND flash controller supports 1-bit and 4-bit ECC calculation on blocks of 512 bytes. The device supports 16-bit SDRAM in addition to the asynchronous memories listed in Section 6.10.1 It has a single SDRAM chip select (EMA_CS[0]). SDRAM configurations that are supported are: One, Two, and Four Bank SDRAM devices Devices with Eight, Nine, Ten, and Eleven Column Address CAS Latency of two or three clock cycles Sixteen Bit Data Bus Width Additionally, the SDRAM interface of EMIFA supports placing the SDRAM in Self Refresh and Powerdown Modes. Self Refresh mode allows the SDRAM to be put into a low power state while still retaining memory contents; since the SDRAM will continue to refresh itself even without clocks from the device Powerdown mode achieves even lower power, except the device must periodically wake the SDRAM up and issue refreshes if data retention is required. Finally, note that the EMIFA does not support Mobile SDRAM devices. Table 6-18 shows the supported SDRAM configurations for EMIFA. Peripheral Information and Electrical Specifications 104 Submit Documentation Feedback

6.10.3 EMIFA SDRAM Loading Limitations OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 6-18. EMIFA Supported SDRAM Configurations (1) SDRAM EMIFA Data Total Total Memory Memory Number of Bus Size Rows Columns Banks Memory Memory Density Data Bus Memories (bits) (Mbits) (Mbytes) (Mbits) Width (bits) 256 256 512 512 1024 128 1024 512 512 1024 128 1024 2048 256 2048 1024 128 1024 2048 256 2048 4096 512 4096 2048 256 2048 4096 512 4096 4096 512 4096 256 128 512 256 1024 128 512 512 256 1024 128 512 2048 256 1024 1024 128 512 2048 256 1024 4096 512 2048 2048 256 1024 4096 512 2048 4096 512 2048 (1) The shaded cells indicate configurations that are possible on the EMIFA interface but as of this writing SDRAM memories capable of supporting these densities are not available in the market. EMIFA supports SDRAM up to 100 MHz with up to two SDRAM or asynchronous memory loads. Additional loads will limit the SDRAM operation to lower speeds and the maximum speed should be confirmed by board simulation using IBIS models. Submit Documentation Feedback Peripheral Information and Electrical Specifications 105

6.10.5 External Memory Interface Register Descriptions OMAP-L138 Low-Power www.ti.com Table 6-19 is a list of the EMIF registers. For more information about these registers, see the C674x DSP External Memory Interface (EMIF) User's Guide (literature number SPRUFL6). Table 6-19. External Memory Interface (EMIFA) Registers BYTE ADDRESS ACRONYM REGISTER (CS2 Space) 0x6800 0074 NANDF2ECC NAND Flash ECC Register (CS3 Space) 0x6800 0078 NANDF3ECC NAND Flash ECC Register (CS4 Space) 0x6800 007C NANDF4ECC NAND Flash ECC Register (CS5 Space) 0x6800 00BC NAND4BITECCLOAD NAND Flash 4-Bit ECC Load Register 0x6800 00C0 NAND4BITECC1 NAND Flash 4-Bit ECC Register 0x6800 00C4 NAND4BITECC2 NAND Flash 4-Bit ECC Register 0x6800 00C8 NAND4BITECC3 NAND Flash 4-Bit ECC Register 0x6800 00CC NAND4BITECC4 NAND Flash 4-Bit ECC Register 0x6800 00D0 NANDERRADD1 NAND Flash 4-Bit ECC Error Address Register 0x6800 00D4 NANDERRADD2 NAND Flash 4-Bit ECC Error Address Register 0x6800 00D8 NANDERRVAL1 NAND Flash 4-Bit ECC Error Value Register 0x6800 00DC NANDERRVAL2 NAND Flash 4-Bit ECC Error Value Register Peripheral Information and Electrical Specifications 106 Submit Documentation Feedback

6.10.6 EMIFA Electrical Data/Timing OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 6-20 through Table 6-23 assume testing over recommended operating conditions. Table 6-20. Timing Requirements for EMIFA SDRAM Interface 1.2V 1.1V 1.0V NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX Input setup time, read data valid on EMA_D[31:0] before t su(EMA_DV-EM_CLKH) ns EMA_CLK rising Input hold time, read data valid on EMA_D[31:0] after t h(CLKH-DIV) 1.6 1.6 1.6 ns EMA_CLK rising Table 6-21. Switching Characteristics for EMIFA SDRAM Interface 1.2V 1.1V 1.0V NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX t c(CLK) Cycle time, EMIF clock EMA_CLK ns t w(CLK) Pulse width, EMIF clock EMA_CLK high or low ns t d(CLKH-CSV) Delay time, EMA_CLK rising to EMA_CS[0] valid 9.5 ns t oh(CLKH-CSIV) Output hold time, EMA_CLK rising to EMA_CS[0] invalid ns t d(CLKH-DQMV) Delay time, EMA_CLK rising to EMA_ WE _DQM[1:0] valid 9.5 ns Output hold time, EMA_CLK rising to EMA_ WE _DQM[1:0] t oh(CLKH-DQMIV) ns invalid Delay time, EMA_CLK rising to EMA_A[12:0] and t d(CLKH-AV) 9.5 ns EMA_BA[1:0] valid Output hold time, EMA_CLK rising to EMA_A[12:0] and t oh(CLKH-AIV) ns EMA_BA[1:0] invalid t d(CLKH-DV) Delay time, EMA_CLK rising to EMA_D[15:0] valid 9.5 ns t oh(CLKH-DIV) Output hold time, EMA_CLK rising to EMA_D[15:0] invalid ns t d(CLKH-RASV) Delay time, EMA_CLK rising to EMA_RAS valid 9.5 ns t oh(CLKH-RASIV) Output hold time, EMA_CLK rising to EMA_RAS invalid ns t d(CLKH-CASV) Delay time, EMA_CLK rising to EMA_CAS valid 9.5 ns t oh(CLKH-CASIV) Output hold time, EMA_CLK rising to EMA_CAS invalid ns t d(CLKH-WEV) Delay time, EMA_CLK rising to EMA_WE valid 9.5 ns t oh(CLKH-WEIV) Output hold time, EMA_CLK rising to EMA_WE invalid ns t dis(CLKH-DHZ) Delay time, EMA_CLK rising to EMA_D[15:0] tri-stated 9.5 ns t ena(CLKH-DLZ) Output hold time, EMA_CLK rising to EMA_D[15:0] driving ns Submit Documentation Feedback Peripheral Information and Electrical Specifications 107

EMA_CLK EMA_BA[1:0] EMA_A[12:0] EMA_D[15:0] 2 2 BASIC SDRAM WRITE OPERA TION EMA_CS[0] EMA_WE _DQM[1:0] EMA_RAS EMA_CAS EMA_WE EMA_CLK EMA_BA[1:0] EMA_A[12:0] EMA_D[15:0] 2 2 17 182 EM_CLK Delay BASIC SDRAM READ OPERA TION EMA_CS[0] EMA_WE _DQM[1:0] EMA_RAS EMA_CAS EMA_WE OMAP-L138 Low-Power www.ti.com Figure 6-12. EMIFA Basic SDRAM Write Operation Figure 6-13. EMIFA Basic SDRAM Read Operation 108 Peripheral Information and Electrical Specifications Submit Documentation Feedback

www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 6-22. Timing Requirements for EMIFA Asynchronous Memory Interface (1) 1.2V 1.1V 1.0V NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX READS and WRITES t w(EM_WAIT) Pulse duration, EM_WAIT assertion and deassertion ns READS t su(EMDV-EMOEH) Setup time, EM_D[15:0] valid before EM_OE high TBD TBD ns t h(EMOEH-EMDIV) Hold time, EM_D[15:0] valid after EM_OE high 0.5 TBD TBD ns Setup Time, EM_WAIT asserted before end of Strobe t su (EMOEL-EMWAIT) 4E+3 4E+3 4E+3 ns Phase (2) WRITES Setup Time, EM_WAIT asserted before end of Strobe t su (EMWEL-EMWAIT) 4E+3 4E+3 4E+3 ns Phase (2) (1) E EMA_CLK period or in ns. EMA_CLK is selected either as SYSCLK3 or the PLL output clock divided by 4.5. As an example, when SYSCLK3 is selected and set to 100MHz, E=10ns. (2) Setup before end of STROBE phase (if no extended wait states are inserted) by which EM_WAIT must be asserted to add extended wait states. Figure 6-16 and Figure 6-17 describe EMIF transactions that include extended wait states inserted during the STROBE phase. However, cycles inserted as part of this extended wait period should not be counted; the requirement is to the start of where the HOLD phase would begin if there were no extended wait cycles. Table 6-23. Switching Characteristics for EMIFA Asynchronous Memory Interface (1) (2) (3) 1.2V, 1.1V, 1.0V NO PARAMETER UNIT MIN Nom MAX READS and WRITES t d(TURNAROUND) Turn around time (TA)*E (TA)*E (TA)*E ns READS (RS+RST+RH)*E (RS+RST+RH)*E EMIF read cycle time (EW (RS+RST+RH)*E ns t c(EMRCYCLE) (RS+RST+RH+(E (RS+RST+RH+(EW (RS+RST+RH+(E EMIF read cycle time (EW ns WC*16))*E C*16))*E WC*16))*E Output setup time, EMA_CE[5:2] low to (RS)*E-3 (RS)*E (RS)*E+3 ns EMA_OE low (SS t su(EMCEL-EMOEL) Output setup time, EMA_CE[5:2] low to ns EMA_OE low (SS Output hold time, EMA_OE high to (RH)*E (RH)*E (RH)*E ns EMA_CE[5:2] high (SS t h(EMOEH-EMCEH) Output hold time, EMA_OE high to ns EMA_CE[5:2] high (SS Output setup time, EMA_BA[1:0] valid to t su(EMBAV-EMOEL) (RS)*E-3 (RS)*E (RS)*E+3 ns EMA_OE low Output hold time, EMA_OE high to t h(EMOEH-EMBAIV) (RH)*E-3 (RH)*E (RH)*E+3 ns EMA_BA[1:0] invalid Output setup time, EMA_A[13:0] valid to t su(EMBAV-EMOEL) (RS)*E-3 (RS)*E (RS)*E+3 ns EMA_OE low Output hold time, EMA_OE high to t h(EMOEH-EMAIV) (RH)*E-3 (RH)*E (RH)*E+3 ns EMA_A[13:0] invalid EMA_OE active low width (EW (RST)*E-3 (RST)*E (RST)*E+3 ns t w(EMOEL) (RST+(EWC*16)) (RST+(EWC*16)) EMA_OE active low width (EW (RST+(EWC*16))*E ns *E-3 *E+3 (1) TA Turn around, RS Read setup, RST Read strobe, RH Read hold, WS Write setup, WST Write strobe, WH Write hold, MEWC Maximum external wait cycles. These parameters are programmed via the Asynchronous Bank and Asynchronous Wait Cycle Configuration Registers. These support the following range of values: TA[4-1], RS[16-1], RST[64-1], RH[8-1], WS[16-1], WST[64-1], WH[8-1], and MEW[1-256]. (2) E EMA_CLK period or in ns. EMA_CLK is selected either as SYSCLK3 or the PLL output clock divided by 4.5. As an example, when SYSCLK3 is selected and set to 100MHz, E=10ns. (3) EWC external wait cycles determined by EMA_WAIT input signal. EWC supports the following range of values EWC[256-1]. Note that the maximum wait time before timeout is specified by bit field MEWC in the Asynchronous Wait Cycle Configuration Register. Submit Documentation Feedback Peripheral Information and Electrical Specifications 109

www.ti.com Table 6-23. Switching Characteristics for EMIFA Asynchronous Memory Interface (continued) 1.2V, 1.1V, 1.0V NO PARAMETER UNIT MIN Nom MAX t d(EMWAITH- Delay time from EMA_WAIT deasserted to 3E-3 4E+3 ns EMOEH) EMA_OE high WRITES (WS+WST+WH)* (WS+WST+WH)* EMIF write cycle time (EW (WS+WST+WH)*E ns E-3 E+3 t c(EMWCYCLE) (WS+WST+WH+( (WS+WST+WH+(E (WS+WST+WH+( EMIF write cycle time (EW ns EWC*16))*E WC*16))*E EWC*16))*E Output setup time, EMA_CE[5:2] low to (WS)*E (WS)*E (WS)*E ns EMA_WE low (SS t su(EMCEL-EMWEL) Output setup time, EMA_CE[5:2] low to ns EMA_WE low (SS Output hold time, EMA_WE high to (WH)*E-3 (WH)*E (WH)*E+3 ns EMA_CE[5:2] high (SS t h(EMWEH-EMCEH) Output hold time, EMA_WE high to ns EMA_CE[5:2] high (SS t su(EMDQMV- Output setup time, EMA_BA[1:0] valid to (WS)*E-3 (WS)*E (WS)*E+3 ns EMWEL) EMA_WE low t h(EMWEH- Output hold time, EMA_WE high to (WH)*E-3 (WH)*E (WH)*E+3 ns EMDQMIV) EMA_BA[1:0] invalid Output setup time, EMA_BA[1:0] valid to t su(EMBAV-EMWEL) (WS)*E-3 (WS)*E (WS)*E+3 ns EMA_WE low Output hold time, EMA_WE high to t h(EMWEH-EMBAIV) (WH)*E-3 (WH)*E (WH)*E+3 ns EMA_BA[1:0] invalid Output setup time, EMA_A[13:0] valid to t su(EMAV-EMWEL) (WS)*E-3 (WS)*E (WS)*E+3 ns EMA_WE low Output hold time, EMA_WE high to t h(EMWEH-EMAIV) (WH)*E-3 (WH)*E (WH)*E+3 ns EMA_A[13:0] invalid EMA_WE active low width (EW (WST)*E-3 (WST)*E (WST)*E+3 ns t w(EMWEL) (WST+(EWC*16)) (WST+(EWC*16)) EMA_WE active low width (EW (WST+(EWC*16))*E ns *E-3 *E+3 t d(EMWAITH- Delay time from EMA_WAIT deasserted to 3E-3 4E+3 ns EMWEH) EMA_WE high Output setup time, EMA_D[15:0] valid to t su(EMDV-EMWEL) (WS)*E-3 (WS)*E (WS)*E+3 ns EMA_WE low Output hold time, EMA_WE high to t h(EMWEH-EMDIV) (WH)*E-3 (WH)*E (WH)*E+3 ns EMA_D[15:0] invalid Peripheral Information and Electrical Specifications 110 Submit Documentation Feedback

EMA_CE[5:2] EMA_BA[1:0] EMA_A[12:0] EMA_OE EMA_D[15:0] EMA_WE EMA_ _DQM[1:0]WE 3029 EMA_CE[5:2] EMA_BA[1:0] EMA_A[12:0] EMA_WE EMA_D[15:0] EMA_OE EMA_ _DQM[1:0]WE OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Figure 6-14. Asynchronous Memory Read Timing for EMIFA Figure 6-15. Asynchronous Memory Write Timing for EMIFA Submit Documentation Feedback Peripheral Information and Electrical Specifications 111

EMA_CE[5:2] Asserted Deasserted EMA_BA[1:0] EMA_A[12:0] EMA_D[15:0] EMA_OE EMA_WAIT SETUP S ROBE T Extended□Due□to□EMA_WAIT S ROBET HOLD EMA_CE[5:2] Asserted Deasserted EMA_BA[1:0] EMA_A[12:0] EMA_D[15:0] EMA_WE EMA_WAIT SETUP STROBE Extended□Due□to□EMA_WAIT STROBE HOLD OMAP-L138 Low-Power www.ti.com Figure 6-16. EMA_WAIT Read Timing Requirements Figure 6-17. EMA_WAIT Write Timing Requirements 112 Peripheral Information and Electrical Specifications Submit Documentation Feedback

6.11 DDR2/mDDR Controller 6.11.1 DDR2/mDDR Memory Controller Electrical Data/Timing OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 The DDR2/mDDR Memory Controller is a dedicated interface to DDR2/mDDR SDRAM. It supports JESD79D-2A standard compliant DDR2 SDRAM devices and compliant Mobile DDR SDRAM devices. The DDR2/mDDR Memory Controller support the following features: JESD79D-2A standard compliant DDR2 SDRAM Mobile DDR SDRAM 512 MByte memory space for DDR2 256 MByte memory space for mDDR CAS latencies: DDR2: and mDDR: and Internal banks: DDR2: and mDDR:1, and Burst length: Burst type: sequential chip select (CS) signal Page sizes: 256, 512, 1024 and 2048 SDRAM autoinitialization Self-refresh mode Partial array self-refresh (for mDDR) Power down mode Prioritized refresh Programmable refresh rate and backlog counter Programmable timing parameters Little endian Table 6-24. Switching Characteristics Over Recommended Operating Conditions for DDR2/mDDR Memory Controller No. PARAMETER 1.2V 1.1V 1.0V UNIT MIN MAX MIN MAX MIN MAX DDR2 125 150 125 150 (1) (1) MHz t c(DDR_CLK) Cycle time, DDR_CLKP DDR_CLKN mDDR 100 133 100 133 100 133 (1) DDR2 is not supported at this voltage operating point. Submit Documentation Feedback Peripheral Information and Electrical Specifications 113

6.11.2 DDR2/mDDR Controller Register Description(s) 6.11.3 DDR2/mDDR Interface 6.11.3.1 DDR2/mDDR Interface Schematic OMAP-L138 Low-Power www.ti.com Table 6-25. DDR2/mDDR Controller Registers BYTE ADDRESS ACRONYM REGISTER VTPIO_CTL VTP IO Control Register This section provides the timing specification for the DDR2/mDDR interface as a PCB design and manufacturing specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk, and signal timing. These rules, when followed, result in a reliable DDR2/mDDR memory system without the need for a complex timing closure process. For more information regarding guidelines for using this DDR2/mDDR specification, Understanding TI's PCB Routing Rule-Based DDR2 Timing Specification SPRAAV0 Figure 6-18 shows the DDR2/mDDR interface schematic for a single-memory DDR2/mDDR system. The dual-memory system shown in Figure 6-19 Pin numbers for the device can be obtained from the pin section. 114 Peripheral Information and Electrical Specifications Submit Documentation Feedback

DDR2/mDDR□Memory□Controller DDR_D[7] DDR2/mDDR DDR_DQM[0] ODT DQ0 DQ7 DDR_D[8] DDR_D[15] DQ8 DQ15 LDM LDQS LDQS DDR_DQM[1] DDR_DQS[1] UDM UDQS UDQS DDR_BA[0] DDR_BA[2] BA0 BA2 DDR_A[0] DDR_A[13] DDR_CS DDR_CAS CS CAS DDR_RAS DDR_WE RAS WE DDR_CKE CKE DDR_CLKP DDR_CLKN CK CK DDR_DQGATE0 DDR_DQGATE1 T T DDR_ZP VREFDDR_VREF 1□K Ω 1% DDR_DVDD18 VREF 1□K Ω 1%0.1 μF 0.1 μF 0.1 Fμ 0.1 Fμ 50 .5 Ω % T Terminator,□if□desired.□See□terminator□comments. DDR2/mDDR ODT DQ0 DQ7 DQ8 DQ15 LDM LDQS LDQS UDM UDQS UDQS BA0 BA2 A13 DDR_CS DDR_CAS CS CAS DDR_RAS DDR_WE RAS WE DDR_CKE CKE CK CK DDR_DQGATE0 DDR_DQGATE1 T T VREF 1□K Ω 1% VREF 1□K Ω 1%0.1 μF 0.1 μF 50 .5 Ω % T Terminator,□if□desired.□See□terminator□comments. DDR_D[0] DDR2/mDDR ODT DQ0 DQ7 DQ8 DQ15 NC LDQS LDQS UDM UDQS UDQS BA0 BA2 DDR_CS DDR_CAS CS CAS DDR_RAS DDR_WE RAS WE DDR_CKE CKE CK CK DDR_DQGATE0 DDR_DQGATE1 TTT TTT TTT TTT TTT TTT TTT TTT TTT TTT TTT TTT TTT TTT TTT TTT TTT TTT TTT T T VREF 1□K Ω 1% VREF 1□K Ω 1%0.1 μF 0.1 μF 50 .5 Ω % T Terminator,□if□desired.□See□terminator□comments. 0.1 Fμ DDR_DQS[0] NC (1) OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 (1) See Figure 6-25 for DQGATE routing specifications. Figure 6-18. DDR2/mDDR Single-Memory High Level Schematic Submit Documentation Feedback Peripheral Information and Electrical Specifications 115

DDR2/mDDR□Memory□Controller DDR_D[0:7] Lower□ByteDDR2/mDDR DDR_DQM[0] DDR_DQS[0] ODT DQ0□-□DQ7 BA0-BA2CK CK DM DQS DQS CS CAS RAS DDR_BA[0:2] CKE BA0-BA2 DDR_A[0:13] DDR_CLKP A0-A13 DDR_CLKN DDR_CS CK CS DDR_CAS DDR_RAS CAS RAS DDR_WE WE DDR_D[8:15] DQS DQ0□-□DQ7 DDR_DQGATE0 DDR_DQGATE1 T T T T T T T T T T T T T T DDR_ZP VREF DDR_VREF 1□K Ω 1% DDR_DVDD18 VREF 1□K Ω 1%0.1 μF 0.1 μF 0.1 μF 0.1 μF 0.1 μF 50 .5 Ω % T Terminator,□if□desired.□See□terminator□comments. ODT A0-A13 WE VREF Upper□ByteDDR2/mDDR CK DDR_CKE CKET DDR_DQM1 DMT DDR_DQS1 DQST NC NC (1) OMAP-L138 Low-Power www.ti.com (1) See Figure 6-25 for DQGATE routing specifications. Figure 6-19. DDR2/mDDR Dual-Memory High Level Schematic Peripheral Information and Electrical Specifications 116 Submit Documentation Feedback

6.11.3.2 Compatible JEDEC DDR2/mDDR Devices 6.11.3.3 PCB Stackup OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 6-26 shows the parameters of the JEDEC DDR2/mDDR devices that are compatible with this interface. Generally, the DDR2/mDDR interface is compatible with x16 DDR2/mDDR-400 speed grade DDR2/mDDR devices. The device also supports JEDEC DDR2/mDDR devices in the dual chip configuration. In this case, one chip supplies the upper byte and the second chip supplies the lower byte. Addresses and most control signals are shared just like regular dual chip memory configurations. Table 6-26. Compatible JEDEC DDR2/mDDR Devices No. Parameter Min Max Unit Notes JEDEC DDR2/mDDR Device Speed Grade DDR2/mDDR-400 See Note (1) JEDEC DDR2/mDDR Device Bit Width x16 Bits JEDEC DDR2/mDDR Device Count Devices (1) Higher DDR2/mDDR speed grades are supported due to inherent JEDEC DDR2/mDDR backwards compatibility. The minimum stackup required for routing the device is a six layer stack as shown in Table 6-27 Additional layers may be added to the PCB stack up to accommodate other circuitry or to reduce the size of the PCB footprint.Complete stack up specifications are provided in Table 6-28 Table 6-27. OMAP-L138 Minimum PCB Stack Up Layer Type 6-28. PCB Stack Up Specifications No. Parameter Min Typ Max Unit Notes PCB Routing/Plane Layers Signal Routing Layers Full ground layers under DDR2/mDDR routing region Number of ground plane cuts allowed within DDR routing region Number of ground reference planes required for each DDR2/mDDR routing layer Number of layers between DDR2/mDDR routing layer and reference ground plane PCB Routing Feature Size Mils PCB Trace Width w Mils PCB BGA escape via pad size Mils PCB BGA escape via hole size Mils SoC Device BGA pad size See Note (1) DDR2/mDDR Device BGA pad size See Note (2) Single Ended Impedance, Zo Ω Impedance Control Z-5 Z Z+5 Ω See Note (3) (1) Please refer to the Flip Chip Ball Grid Array Package Reference Guide SPRU811 for device BGA pad size. (2) Please refer to the DDR2/mDDR device manufacturer documentation for the DDR2/mDDR device BGA pad size. (3) Z is the nominal singled ended impedance selected for the PCB specified by item 12. Submit Documentation Feedback Peripheral Information and Electrical Specifications 117

6.11.3.4 Placement X Y OFFSET Recommended□DDR2/mDDR Device□Orientation Y Y OFFSET DDR2/mDDR Device DDR2/mDDRController OMAP-L138 Low-Power www.ti.com Figure 6-19 shows the required placement for the OMAP-L138 device as well as the DDR2/mDDR devices. The dimensions for Figure 6-20 are defined in Table 6-29 The placement does not restrict the side of the PCB that the devices are mounted on. The ultimate purpose of the placement is to limit the maximum trace lengths and allow for proper routing space. For single-memory DDR2/mDDR systems, the second DDR2/mDDR device is omitted from the placement. Figure 6-20. OMAP-L138 and DDR2/mDDR Device Placement Table 6-29. Placement Specifications No. Parameter Min Max Unit Notes X 1750 Mils See Notes (1) (2) Y 1280 Mils See Notes (1) (2) Y Offset 650 Mils See Notes (1) (2) (3) Clearance from non-DDR2/mDDR signal to DDR2/mDDR Keepout Region w See Note (4) (1) See Figure 6-20 for dimension definitions. (2) Measurements from center of device to center of DDR2/mDDR device. (3) For single memory systems it is recommended that Y Offset be as small as possible. (4) Non-DDR2/mDDR signals allowed within DDR2/mDDR keepout region provided they are separated from DDR2/mDDR routing layers by a ground plane. 118 Peripheral Information and Electrical Specifications Submit Documentation Feedback

6.11.3.5 DDR2/mDDR Keep Out Region DDR2/mDDR Controller DDR2/mDDR Device Region□should□encompass□all□DDR2/mDDR□circuitry□and□varies depending□on□placement.□Non-DDR2/mDDR□signals□should□not□be routed□on□the□DDR□signal□layers□within□the□DDR2/mDDR□keep□out region.□Non-DDR2/mDDR□signals□may□be□routed□in□the□region provided□they□are□routed□on□layers□separated□from□DDR2/mDDR signal□layers□by□a□ground□layer.□No□breaks□should□be□allowed□in□the reference□ground□layers□in□this□region.□In□addition,□the□1.8□V□power plane□should□cover□the□entire□keep□out□region. OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 The region of the PCB used for the DDR2/mDDR circuitry must be isolated from other signals. The DDR2/mDDR keep out region is defined for this purpose and is shown in Figure 6-21 The size of this region varies with the placement and DDR routing. Additional clearances required for the keep out region are shown in Table 6-29 Figure 6-21. DDR2/mDDR Keepout Region Submit Documentation Feedback Peripheral Information and Electrical Specifications 119

6.11.3.6 Bulk Bypass Capacitors 6.11.3.7 High-Speed Bypass Capacitors OMAP-L138 Low-Power www.ti.com Bulk bypass capacitors are required for moderate speed bypassing of the DDR2/mDDR and other circuitry. Table 6-30 contains the minimum numbers and capacitance required for the bulk bypass capacitors. Note that this table only covers the bypass needs of the Soc and DDR2/mDDR interfaces. Additional bulk bypass capacitance may be needed for other circuitry. Table 6-30. Bulk Bypass Capacitors No. Parameter Min Max Unit Notes DDR_DVDD18 Supply Bulk Bypass Capacitor Count Devices See Note (1) DDR_DVDD18 Supply Bulk Bypass Total Capacitance µ F DDR#1 Bulk Bypass Capacitor Count Devices See Note (1) DDR#1 Bulk Bypass Total Capacitance µ F DDR#2 Bulk Bypass Capacitor Count Devices See Notes (1) (2) DDR#2 Bulk Bypass Total Capacitance µ F See Note (2) (1) These devices should be placed near the device they are bypassing, but preference should be given to the placement of the high-speed (HS) bypass caps. (2) Only used on dual-memory systems High-speed (HS) bypass capacitors are critical for proper DDR2/mDDR interface operation. It is particularly important to minimize the parasitic series inductance of the HS bypass cap, Soc /DDR2/mDDR power, and Soc /DDR2/mDDR ground connections. Table 6-31 contains the specification for the HS bypass capacitors as well as for the power connections on the PCB. Table 6-31. High-Speed Bypass Capacitors No. Parameter Min Max Unit Notes HS Bypass Capacitor Package Size 0402 Mils See Note (1) Distance from HS bypass capacitor to device being bypassed 250 Mils Number of connection vias for each HS bypass capacitor Vias See Note (2) Trace length from bypass capacitor contact to connection via Mils Number of connection vias for each DDR2/mDDR device power or Vias ground balls Trace length from DDR2/mDDR device power ball to connection via Mils DDR_DVDD18 Supply HS Bypass Capacitor Count Devices See Note (3) DDR_DVDD18 Supply HS Bypass Capacitor Total Capacitance 0.6 µ F DDR#1 HS Bypass Capacitor Count Devices See Note (3) DDR#1 HS Bypass Capacitor Total Capacitance 0.4 µ F DDR#2 HS Bypass Capacitor Count Devices See Notes (3) (4) DDR#2 HS Bypass Capacitor Total Capacitance 0.4 µ F See Note (4) (1) LxW, mil units, i.e., a 0402 is a 40x20 mil surface mount capacitor (2) An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board. (3) These devices should be placed as close as possible to the device being bypassed. (4) Only used on dual-memory systems 120 Peripheral Information and Electrical Specifications Submit Documentation Feedback

6.11.3.8 Net Classes 6.11.3.9 DDR2/mDDR Signal Termination OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 6-32 lists the clock net classes for the DDR2/mDDR interface. Table 6-33 lists the signal net classes, and associated clock net classes, for the signals in the DDR2/mDDR interface. These net classes are used for the termination and routing rules that follow. Table 6-32. Clock Net Class Definitions Clock Net Class Soc Pin Names CK DDR_CLKP DDR_CLKN DQS0 DDR_DQS[0] DQS1 DDR_DQS[1] Table 6-33. Signal Net Class Definitions Associated Clock Net Clock Net Class Class Soc Pin Names ADDR_CTRL CK DDR_BA[2:0], DDR_A[13:0], DDR_CS DDR_CAS DDR_RAS DDR_WE DDR_CKE DQS0 DDR_D[7:0], DDR_DQM0 DQS1 DDR_D[15:8], DDR_DQM1 DQGATE CK, DQS0, DQS1 DDR_DQGATE0, DDR_DQGATE1 No terminations of any kind are required in order to meet signal integrity and overshoot requirements. Serial terminators are permitted, if desired, to reduce EMI risk; however, serial terminations are the only type permitted. Table 6-34 shows the specifications for the series terminators. Table 6-34. DDR2/mDDR Signal Terminations No. Parameter Min Typ Max Unit Notes CK Net Class Ω See Note (1) ADDR_CTRL Net Class Zo Ω See Notes (1) (2) (3) Data Byte Net Classes (DQS[0], DQS[1], D0, D1) Zo Ω See Notes (1) (2) (3) (4) DQGATE Net Class (DQGATE) Zo Ω See Notes (1) (2) (3) (1) Only series termination is permitted, parallel or SST specifically disallowed. (2) Terminator values larger than typical only recommended to address EMI issues. (3) Termination value should be uniform across net class. (4) When no termination is used on data lines Ω the DDR2/mDDR devices must be programmed to operate in 60% strength mode. Submit Documentation Feedback Peripheral Information and Electrical Specifications 121

6.11.3.10 VREF Routing DDR2/mDDR□Device VREF□Nominal□Minimum Trace□Width□is□20□Mils VREF□Bypass□Capacitor Neck□down□to□minimum□in□BGA escape regions□is□acceptable.□Narrowing□to accomodate□via□congestion□for□short distances□is□also□acceptable.□Best performance□is□obtained□if□the□width of□VREF□is□maximized. DDR2/mDDR OMAP-L138 Low-Power www.ti.com VREF is used as a reference by the input buffers of the DDR2/mDDR memories as well as the OMAP-L138 VREF is intended to be half the DDR2/mDDR power supply voltage and should be created using a resistive divider as shown in Figure 6-18 Other methods of creating VREF are not recommended. Figure 6-22 shows the layout guidelines for VREF. Figure 6-22. VREF Routing and Topology Peripheral Information and Electrical Specifications 122 Submit Documentation Feedback

6.11.3.11 DDR2/mDDR CK and ADDR_CTRL Routing C B A T DDR2/mDDRController OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Figure 6-23 shows the topology of the routing for the CK and ADDR_CTRL net classes. The route is a balanced T as it is intended that the length of segments B and C be equal. In addition, the length of A should be maximized. Figure 6-23. CK and ADDR_CTRL Routing and Topology Table 6-35. CK and ADDR_CTRL Routing Specification No. Parameter Min Typ Max Unit Notes CK A to B/A to C Skew Length Mismatch Mils See Note (1) CK B to C Skew Length Mismatch Mils Center to center CK to other DDR2/mDDR trace spacing See Note (2) CK/ADDR_CTRL nominal trace length CACLM-50 CACLM CACLM+50 Mils See Note (3) ADDR_CTRL to CK Skew Length Mismatch 100 Mils ADDR_CTRL to ADDR_CTRL Skew Length Mismatch 100 Mils Center to center ADDR_CTRL to other DDR2/mDDR trace spacing See Note (2) Center to center ADDR_CTRL to other ADDR_CTRL trace spacing See Note (2) ADDR_CTRL A to B/A to C Skew Length Mismatch 100 Mils See Note (1) ADDR_CTRL B to C Skew Length Mismatch 100 Mils (1) Series terminator, if used, should be located closest to Soc (2) Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing congestion. (3) CACLM is the longest Manhattan distance of the CK and ADDR_CTRL net classes. Submit Documentation Feedback Peripheral Information and Electrical Specifications 123

T DDR2/mDDRController T OMAP-L138 Low-Power www.ti.com Figure 6-24 shows the topology and routing for the DQS and DQ net class; the routes are point to point. Skew matching across bytes is not needed nor recommended. Figure 6-24. DQS and DQ Routing and Topology Table 6-36. DQS and DQ Routing Specification No. Parameter Min Typ Max Unit Notes DQS E Skew Length Mismatch Mils Center to center DQS to other DDR2/mDDR trace See Note (1) spacing DQS/D nominal trace length DQLM-50 DQLM DQLM+50 Mils See Notes (2) (3) D to DQS Skew Length Mismatch 100 Mils See Note (3) D to D Skew Length Mismatch 100 Mils See Note (3) Center to center D to other DDR2/mDDR trace See Notes (1) (4) spacing Center to Center D to other D trace spacing See Notes (5) (1) DQ/DQS E Skew Length Mismatch 100 Mils See Note (3) (1) Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing congestion. (2) Series terminator, if used, should be located closest to DDR. (3) There is no need and it is not recommended to skew match across data bytes, i.e., from DQS0 and data byte to DQS1 and data byte (4) D's from other DQS domains are considered other DDR2/mDDR trace (5) DQLM is the longest Manhattan distance of each of the DQS and D net class. Peripheral Information and Electrical Specifications 124 Submit Documentation Feedback

T T DDR2/mDDRController F OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Figure 6-25 shows the routing for the DQGATE net class. Table 6-37 contains the routing specification. Figure 6-25. DQGATE Routing Table 6-37. DQGATE Routing Specification No. Parameter Min Typ Max Unit Notes DQGATE Length F CKB0B1 See Note (1) Center to center DQGATE to any other trace spacing DQS/D nominal trace length DQLM-50 DQLM DQLM+50 Mils DQGATE Skew 100 Mils See Note (2) (1) CKB0B1 is the sum of the length of the CK net plus the average length of the DQS0 and DQS1 nets. (2) Skew from CKB0B1 Submit Documentation Feedback Peripheral Information and Electrical Specifications 125

6.12 MMC SD SDIO (MMCSD0, MMCSD1) 6.12.1 MMCSD Peripheral 6.12.2 MMCSD Peripheral Register Description(s) OMAP-L138 Low-Power www.ti.com The device includes an two MMCSD controllers which are compliant with MMC V3.31, Secure Digital Part Physical Layer Specification V1.1 and Secure Digital Input Output (SDIO) V2.0 specifications. The MMC/SD Controller have following features: MultiMediaCard (MMC). Secure Digital (SD) Memory Card. MMC/SD protocol support. SDIO protocol support. Programmable clock frequency. 512 bit Read/Write FIFO to lower system overhead. Slave EDMA transfer capability. The device MMC/SD Controller does not support SPI mode. Table 6-38. Multimedia Card/Secure Digital (MMC/SD) Card Controller Registers MMCSD0 MMCSD1 ACRONYM REGISTER DESCSRIPTION BYTE ADDRESS BYTE ADDRESS 0x01C4 0000 0x01E1 B000 MMCCTL MMC Control Register 0x01C4 0004 0x01E1 B004 MMCCLK MMC Memory Clock Control Register 0x01C4 0008 0x01E1 B008 MMCST0 MMC Status Register 0x01C4 000C 0x01E1 B00C MMCST1 MMC Status Register 0x01C4 0010 0x01E1 B010 MMCIM MMC Interrupt Mask Register 0x01C4 0014 0x01E1 B014 MMCTOR MMC Response Time-Out Register 0x01C4 0018 0x01E1 B018 MMCTOD MMC Data Read Time-Out Register 0x01C4 001C 0x01E1 B01C MMCBLEN MMC Block Length Register 0x01C4 0020 0x01E1 B020 MMCNBLK MMC Number of Blocks Register 0x01C4 0024 0x01E1 B024 MMCNBLC MMC Number of Blocks Counter Register 0x01C4 0028 0x01E1 B028 MMCDRR MMC Data Receive Register 0x01C4 002C 0x01E1 B02C MMCDXR MMC Data Transmit Register 0x01C4 0030 0x01E1 B030 MMCCMD MMC Command Register 0x01C4 0034 0x01E1 B034 MMCARGHL MMC Argument Register 0x01C4 0038 0x01E1 B038 MMCRSP01 MMC Response Register and 0x01C4 003C 0x01E1 B03C MMCRSP23 MMC Response Register and 0x01C4 0040 0x01E1 B040 MMCRSP45 MMC Response Register and 0x01C4 0044 0x01E1 B044 MMCRSP67 MMC Response Register and 0x01C4 0048 0x01E1 B048 MMCDRSP MMC Data Response Register 0x01C4 0050 0x01E1 B050 MMCCIDX MMC Command Index Register 0x01C4 0064 0x01E1 B064 SDIOCTL SDIO Control Register 0x01C4 0068 0x01E1 B068 SDIOST0 SDIO Status Register 0x01C4 006C 0x01E1 B06C SDIOIEN SDIO Interrupt Enable Register 0x01C4 0070 0x01E1 B070 SDIOIST SDIO Interrupt Status Register 0x01C4 0074 0x01E1 B074 MMCFIFOCTL MMC FIFO Control Register Peripheral Information and Electrical Specifications 126 Submit Documentation Feedback

6.12.3 MMC/SD Electrical Data/Timing ST ART XMIT V alid Valid Valid END MMCSD_CLK MMCSD_CMD 13 13 13 ST ART XMIT V alid Valid Valid END MMCSD_CLK MMCSD_CMD 1097 ST ART D0 D1 Dx END MMCSD_CLK MMCSD_DATx 1414 14 14 OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 6-39 through Table 6-40 assume testing over recommended operating conditions. Table 6-39. Timing Requirements for MMC/SD (see Figure 6-27 and Figure 6-29 1.2V 1.1V 1.0V NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX t su(CMDV-CLKH) Setup time, MMCSD_CMD valid before MMCSD_CLK high ns t h(CLKH-CMDV) Hold time, MMCSD_CMD valid after MMCSD_CLK high 2.5 2.5 2.5 ns t su(DATV-CLKH) Setup time, MMCSD_DATx valid before MMCSD_CLK high 4.5 ns t h(CLKH-DATV) Hold time, MMCSD_DATx valid after MMCSD_CLK high 2.5 2.5 2.5 ns Table 6-40. Switching Characteristics for MMC/SD (see Figure 6-26 through Figure 6-29 1.2V 1.1V 1.0V NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX f (CLK) Operating frequency, MMCSD_CLK MHz f (CLK_ID) Identification mode frequency, MMCSD_CLK 400 400 400 KHz t W(CLKL) Pulse width, MMCSD_CLK low 6.5 6.5 ns t W(CLKH) Pulse width, MMCSD_CLK high 6.5 6.5 ns t r(CLK) Rise time, MMCSD_CLK ns t f(CLK) Fall time, MMCSD_CLK ns t d(CLKL-CMD) Delay time, MMCSD_CLK low to MMCSD_CMD transition 2.5 ns t d(CLKL-DAT) Delay time, MMCSD_CLK low to MMCSD_DATx transition 3.3 3.5 ns Figure 6-26. MMC/SD Host Command Timing Figure 6-27. MMC/SD Card Response Timing Figure 6-28. MMC/SD Host Write Timing Submit Documentation Feedback Peripheral Information and Electrical Specifications 127

MMCSD_CLK MMCSD_DA Tx 3 3 OMAP-L138 Low-Power www.ti.com Figure 6-29. MMC/SD Host Read and Card CRC Status Timing Peripheral Information and Electrical Specifications 128 Submit Documentation Feedback

6.13 Serial ATA Controller (SATA) 6.13.1 SATA Register Descriptions OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 The Serial ATA Controller (SATA) provides a single HBA port operating in AHCI mode and is used to interface to data storage devices at both 1.5 Gbits/second and 3.0 Gbits/second line speeds. AHCI describes a system memory structure that contains a generic area for control and status, and a table of entries describing a command list where each command list entry contains information necessary to program an SATA device, and a pointer to a descriptor table for transferring data between system memory and the device. The SATA Controller supports the following features: Serial ATA 1.5 Gbps (Gen 1i) and Gbps (Gen 2i) line speeds Support for the AHCI controller spec 1.1 Integrated SERDES PHY Integrated Rx and Tx data buffers Supports all SATA power management (NCQ) for up to entries 32-bit addressing Supports port multiplier with command-based switching Activity LED support Mechanical presence switch Cold presence detect Table 6-41 is a list of the SATA Controller registers. Table 6-41. SATA Controller Registers BYTE ADDRESS ACRONYM REGISTER CCC_CTL Command Completion Coalescing Control Register 0x01E1 8018 CCC_PORTS Command Completion Coalescing Ports Register 0x01E1 80A0 BISTAFR BIST Active FIS Register 0x01E1 80A4 BISTCR BIST Control Register 0x01E1 80A8 BISTFCTR BIST FIS Count Register 0x01E1 80AC BISTSR BIST Status Register 0x01E1 80B0 BISTDECR BIST DWORD Error Count Register 0x01E1 80E0 TIMER1MS BIST DWORD Error Count Register 0x01E1 80E8 GPARAM1R Global Parameter Register 0x01E1 80EC GPARAM2R Global Parameter Register 0x01E1 80F0 PPARAMR Port Parameter Register 0x01E1 80F4 TESTR Test Register 0x01E1 80F8 VERSIONR Version Register 0x01E1 80FC IDR ID Register 0x01E1 8100 P0CLB Port Command List Base Address Register 0x01E1 8108 P0FB Port FIS Base Address Register 0x01E1 8110 P0IS Port Interrupt Status Register Submit Documentation Feedback Peripheral Information and Electrical Specifications 129

6.13.2 SATA Design Considerations OMAP-L138 Low-Power www.ti.com Table 6-41. SATA Controller Registers (continued) BYTE ADDRESS ACRONYM REGISTER datasheet. A future revision of this datasheet will include design and layout recommendations to meet the SATA specification requirements. 130 Peripheral Information and Electrical Specifications Submit Documentation Feedback

6.14 Multichannel Audio Serial Port (McASP) Receive□Logic C lock/Fram e G enerator State□Machine Clock□Check□and Serializer□0 Serializer□1 Serializer□y GIO Control DIT□RAM 384□C 384□U Optional Transm it Form atter Receive Form atter Transm it Logic C lock/Fram e G enerator State□Machine McASP Peripheral Configuration Bus McASP DMA Bus (Dedicated) AHCLKRx ACLKRx AFSRx AMUTEINx AMUTEx AFSXx ACLKXx AHCLKXx AXRx[0] AXRx[1] AXRx[y] Pins Function Receive□Master□Clock Receive□Bit□Clock R eceive Left/R ight C lock or Fram e Sync Transm it M aster C lock Transm it B it C lock Transm it Left/R ight C lock or Fram e Sync Transm it/R eceive Serial D ata Pin Transm it/R eceive Serial D ata Pin Transm it/R eceive Serial D ata Pin Error□Detection The□McASP DOES□NOT□have□a dedicated AMUTEIN□pin. OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 The McASP serial port is specifically designed for multichannel audio applications. Its key are: Flexible clock and frame sync generation logic and on-chip dividers Up to sixteen transmit or receive data pins and serializers Large number of serial data format options, including: TDM Frames with to time slots per frame (periodic) or slot per frame (burst) Time slots of 8,12,16, 20, 24, 28, and bits First bit delay or clocks MSB or LSB first bit order Left- or right-aligned data words within time slots DIT Mode with 384-bit Channel Status and 384-bit User Data registers Extensive error checking and mute generation logic All unused pins GPIO-capable Transmit Receive FIFO Buffers allow the McASP to operate at a higher sample rate by making it more tolerant to DMA latency. Dynamic Adjustment of Clock Dividers Clock Divider Value may be changed without resetting the McASP Figure 6-30. McASP Block Diagram Submit Documentation Feedback Peripheral Information and Electrical Specifications 131

6.14.1 McASP Peripheral Registers Description(s) OMAP-L138 Low-Power www.ti.com Registers for the McASP are summarized in Table 6-42 The registers are accessed through the peripheral configuration port. The receive buffer registers (RBUF) and transmit buffer registers (XBUF) can also be accessed through the DMA port, as listed in Table 6-43 Registers for the McASP Audio FIFO (AFIFO) are summarized in Table 6-44 Note that the AFIFO Write FIFO (WFIFO) and Read FIFO (RFIFO) have independent control and status registers. The AFIFO control registers are accessed through the peripheral configuration port. Table 6-42. McASP Registers Accessed Through Peripheral Configuration Port BYTE ADDRESS ACRONYM REGISTER returns: Pin data input register 0x01D0 001C PDSET Writes affect: Pin data set register (alternate write address: PDOUT) 0x01D0 0020 PDCLR Pin data clear register (alternate write address: PDOUT) 0x01D0 0044 GBLCTL Global control register 0x01D0 0048 AMUTE Audio mute control register 0x01D0 004C DLBCTL Digital loopback control register 0x01D0 0050 DITCTL DIT mode control register 0x01D0 0060 Receiver global control register: Alias of GBLCTL, only receive bits are RGBLCTL affected allows receiver to be reset independently from transmitter 0x01D0 0064 RMASK Receive format unit bit mask register 0x01D0 0068 RFMT Receive bit stream format register 0x01D0 006C AFSRCTL Receive frame sync control register 0x01D0 0070 ACLKRCTL Receive clock control register 0x01D0 0074 AHCLKRCTL Receive high-frequency clock control register 0x01D0 0078 RTDM Receive TDM time slot 0-31 register 0x01D0 007C RINTCTL Receiver interrupt control register 0x01D0 0080 RSTAT Receiver status register 0x01D0 0084 RSLOT Current receive TDM time slot register 0x01D0 0088 RCLKCHK Receive clock check control register 0x01D0 008C REVTCTL Receiver DMA event control register 0x01D0 00A0 Transmitter global control register. Alias of GBLCTL, only transmit bits are XGBLCTL affected allows transmitter to be reset independently from receiver 0x01D0 00A4 XMASK Transmit format unit bit mask register 0x01D0 00A8 XFMT Transmit bit stream format register 0x01D0 00AC AFSXCTL Transmit frame sync control register 0x01D0 00B0 ACLKXCTL Transmit clock control register 0x01D0 00B4 AHCLKXCTL Transmit high-frequency clock control register 0x01D0 00B8 XTDM Transmit TDM time slot 0-31 register 0x01D0 00BC XINTCTL Transmitter interrupt control register 0x01D0 00C0 XSTAT Transmitter status register 0x01D0 00C4 XSLOT Current transmit TDM time slot register 0x01D0 00C8 XCLKCHK Transmit clock check control register 0x01D0 00CC XEVTCTL Transmitter DMA event control register 0x01D0 0100 DITCSRA0 Left (even TDM time slot) channel status register (DIT mode) 0x01D0 0104 DITCSRA1 Left (even TDM time slot) channel status register (DIT mode) Peripheral Information and Electrical Specifications 132 Submit Documentation Feedback

www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 6-42. McASP Registers Accessed Through Peripheral Configuration Port (continued) BYTE ADDRESS ACRONYM REGISTER (even TDM time slot) channel status register (DIT mode) 0x01D0 010C DITCSRA3 Left (even TDM time slot) channel status register (DIT mode) 0x01D0 0110 DITCSRA4 Left (even TDM time slot) channel status register (DIT mode) 0x01D0 0114 DITCSRA5 Left (even TDM time slot) channel status register (DIT mode) 0x01D0 0118 DITCSRB0 Right (odd TDM time slot) channel status register (DIT mode) 0x01D0 011C DITCSRB1 Right (odd TDM time slot) channel status register (DIT mode) 0x01D0 0120 DITCSRB2 Right (odd TDM time slot) channel status register (DIT mode) 0x01D0 0124 DITCSRB3 Right (odd TDM time slot) channel status register (DIT mode) 0x01D0 0128 DITCSRB4 Right (odd TDM time slot) channel status register (DIT mode) 0x01D0 012C DITCSRB5 Right (odd TDM time slot) channel status register (DIT mode) 0x01D0 0130 DITUDRA0 Left (even TDM time slot) channel user data register (DIT mode) 0x01D0 0134 DITUDRA1 Left (even TDM time slot) channel user data register (DIT mode) 0x01D0 0138 DITUDRA2 Left (even TDM time slot) channel user data register (DIT mode) 0x01D0 013C DITUDRA3 Left (even TDM time slot) channel user data register (DIT mode) 0x01D0 0140 DITUDRA4 Left (even TDM time slot) channel user data register (DIT mode) 0x01D0 0144 DITUDRA5 Left (even TDM time slot) channel user data register (DIT mode) 0x01D0 0148 DITUDRB0 Right (odd TDM time slot) channel user data register (DIT mode) 0x01D0 014C DITUDRB1 Right (odd TDM time slot) channel user data register (DIT mode) 0x01D0 0150 DITUDRB2 Right (odd TDM time slot) channel user data register (DIT mode) 0x01D0 0154 DITUDRB3 Right (odd TDM time slot) channel user data register (DIT mode) 0x01D0 0158 DITUDRB4 Right (odd TDM time slot) channel user data register (DIT mode) 0x01D0 015C DITUDRB5 Right (odd TDM time slot) channel user data register (DIT mode) 0x01D0 0180 SRCTL0 Serializer control register 0x01D0 0184 SRCTL1 Serializer control register 0x01D0 0188 SRCTL2 Serializer control register 0x01D0 018C SRCTL3 Serializer control register 0x01D0 0190 SRCTL4 Serializer control register 0x01D0 0194 SRCTL5 Serializer control register 0x01D0 0198 SRCTL6 Serializer control register 0x01D0 019C SRCTL7 Serializer control register 0x01D0 01A0 SRCTL8 Serializer control register 0x01D0 01A4 SRCTL9 Serializer control register 0x01D0 01A8 SRCTL10 Serializer control register 0x01D0 01AC SRCTL11 Serializer control register 0x01D0 01B0 SRCTL12 Serializer control register 0x01D0 01B4 SRCTL13 Serializer control register 0x01D0 01B8 SRCTL14 Serializer control register 0x01D0 01BC SRCTL15 Serializer control register 0x01D0 0200 XBUF0 (1) Transmit buffer register for serializer 0x01D0 0204 XBUF1 (1) Transmit buffer register for serializer 0x01D0 0208 XBUF2 (1) Transmit buffer register for serializer 0x01D0 020C XBUF3 (1) Transmit buffer register for serializer 0x01D0 0210 XBUF4 (1) Transmit buffer register for serializer 0x01D0 0214 XBUF5 (1) Transmit buffer register for serializer 0x01D0 0218 XBUF6 (1) Transmit buffer register for serializer 0x01D0 021C XBUF7 (1) Transmit buffer register for serializer (1) Writes to XRBUF originate from peripheral configuration port only when XBUSEL in XFMT. Submit Documentation Feedback Peripheral Information and Electrical Specifications 133

www.ti.com Table 6-42. McASP Registers Accessed Through Peripheral Configuration Port (continued) BYTE ADDRESS ACRONYM REGISTER (1) Transmit buffer register for serializer 0x01D0 0224 XBUF9 (1) Transmit buffer register for serializer 0x01D0 0228 XBUF10 (1) Transmit buffer register for serializer 0x01D0 022C XBUF11 (1) Transmit buffer register for serializer 0x01D0 0230 XBUF12 (1) Transmit buffer register for serializer 0x01D0 0234 XBUF13 (1) Transmit buffer register for serializer 0x01D0 0238 XBUF14 (1) Transmit buffer register for serializer 0x01D0 023C XBUF15 (1) Transmit buffer register for serializer 0x01D0 0280 RBUF0 (2) Receive buffer register for serializer 0x01D0 0284 RBUF1 (2) Receive buffer register for serializer 0x01D0 0288 RBUF2 (2) Receive buffer register for serializer 0x01D0 028C RBUF3 (2) Receive buffer register for serializer 0x01D0 0290 RBUF4 (2) Receive buffer register for serializer 0x01D0 0294 RBUF5 (2) Receive buffer register for serializer 0x01D0 0298 RBUF6 (2) Receive buffer register for serializer 0x01D0 029C RBUF7 (2) Receive buffer register for serializer 0x01D0 02A0 RBUF8 (2) Receive buffer register for serializer 0x01D0 02A4 RBUF9 (2) Receive buffer register for serializer 0x01D0 02A8 RBUF10 (2) Receive buffer register for serializer 0x01D0 02AC RBUF11 (2) Receive buffer register for serializer 0x01D0 02B0 RBUF12 (2) Receive buffer register for serializer 0x01D0 02B4 RBUF13 (2) Receive buffer register for serializer 0x01D0 02B8 RBUF14 (2) Receive buffer register for serializer 0x01D0 02BC RBUF15 (2) Receive buffer register for serializer (2) Reads from XRBUF originate on peripheral configuration port only when RBUSEL in RFMT. Table 6-43. McASP Registers Accessed Through DMA Port ACCESS TYPE BYTE ADDRESS ACRONYM REGISTER address. Cycles through receive serializers, skipping over transmit serializers and inactive serializers. Starts at the lowest serializer at the beginning of each time slot. Reads from DMA port only if XBUSEL in XFMT. Write Accesses 0x01D0 2000 XBUF Transmit buffer DMA port address. Cycles through transmit serializers, skipping over receive and inactive serializers. Starts at the lowest serializer at the beginning of each time slot. Writes to DMA port only if RBUSEL in RFMT. Table 6-44. McASP AFIFO Registers Accessed Through Peripheral Configuration Port BYTE ADDRESS ACRONYM REGISTER

6.14.2 McASP Electrical Data/Timing 6.14.2.1 Multichannel Audio Serial Port (McASP0) Timing OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 6-45 and Table 6-47 assume testing over recommended operating conditions (see Figure 6-31 and Figure 6-32 Table 6-45. Timing Requirements for McASP0 (1.2V, 1.1V) (1) (2) 1.2V 1.1V NO. PARAMETER UNIT MIN MAX MIN MAX t c(AHCLKRX) Cycle time, AHCLKR/X ns t w(AHCLKRX) Pulse duration, AHCLKR/X high or low ns t c(ACLKRX) Cycle time, ACLKR/X AHCLKR/X ext (3) (3) ns t w(ACLKRX) Pulse duration, ACLKR/W high or low AHCLKR/X ext ns AHCLKR/X int 11.5 ns Setup time, t su(AFSRX-ACLKRX) AHCLKR/X ext input ns AFSR/X input to ACLKR/X (4) AHCLKR/X ext output ns AHCLKR/X int ns Hold time, t h(ACLKRX-AFSRX) AHCLKR/X ext input 0.4 ns AFSR/X input after ACLKR/X (4) AHCLKR/X ext output 0.4 ns AHCLKR/X int 11.5 ns Setup time, t su(AXR-ACLKRX) AXR0[n] input to ACLKR/X (4) (5) AHCLKR/X ext ns AHCLKR/X int ns Hold time, t h(ACLKRX-AXR) AHCLKR/X ext input 0.4 ns AXR0[n] input after ACLKR/X (4) (5) AHCLKR/X ext output 0.4 ns (1) ACLKX0 internal McASP0 ACLKXCTL.CLKXM PDIR.ACLKX ACLKX0 external input McASP0 ACLKXCTL.CLKXM PDIR.ACLKX ACLKX0 external output McASP0 ACLKXCTL.CLKXM PDIR.ACLKX ACLKR0 internal McASP0 ACLKRCTL.CLKRM PDIR.ACLKR ACLKR0 external input McASP0 ACLKRCTL.CLKRM PDIR.ACLKR ACLKR0 external output McASP0 ACLKRCTL.CLKRM PDIR.ACLKR (2) P SYSCLK2 period (3) This timing is limited by the timing shown or 2P, whichever is greater. (4) McASP0 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR0 (5) McASP0 ACLKXCTL.ASYNC=0: Receiver is clocked by transmitter's ACLKX0 Submit Documentation Feedback Peripheral Information and Electrical Specifications 135

www.ti.com Table 6-46. Timing Requirements for McASP0 (1.0V) (1) (2) 1.0V NO. PARAMETER UNIT MIN MAX t c(AHCLKRX) Cycle time, AHCLKR/X 26.6 ns t w(AHCLKRX) Pulse duration, AHCLKR/X high or low 13.3 ns t c(ACLKRX) Cycle time, ACLKR/X AHCLKR/X ext 26.6 (3) ns t w(ACLKRX) Pulse duration, ACLKR/W high or low AHCLKR/X ext 13.3 ns AHCLKR/X int ns Setup time, t su(AFSRX-ACLKRX) AHCLKR/X ext input 5.5 ns AFSR/X input to ACLKR/X (4) AHCLKR/X ext output 5.5 ns AHCLKR/X int ns Hold time, t h(ACLKRX-AFSRX) AHCLKR/X ext input ns AFSR/X input after ACLKR/X (4) AHCLKR/X ext output ns AHCLKR/X int ns Setup time, t su(AXR-ACLKRX) AXR0[n] input to ACLKR/X (4) (5) AHCLKR/X ext 5.5 ns AHCLKR/X int ns Hold time, t h(ACLKRX-AXR) AHCLKR/X ext input ns AXR0[n] input after ACLKR/X (4) (5) AHCLKR/X ext output ns (1) ACLKX0 internal McASP0 ACLKXCTL.CLKXM PDIR.ACLKX ACLKX0 external input McASP0 ACLKXCTL.CLKXM PDIR.ACLKX ACLKX0 external output McASP0 ACLKXCTL.CLKXM PDIR.ACLKX ACLKR0 internal McASP0 ACLKRCTL.CLKRM PDIR.ACLKR ACLKR0 external input McASP0 ACLKRCTL.CLKRM PDIR.ACLKR ACLKR0 external output McASP0 ACLKRCTL.CLKRM PDIR.ACLKR (2) P SYSCLK2 period (3) This timing is limited by the timing shown or 2P, whichever is greater. (4) McASP0 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR0 (5) McASP0 ACLKXCTL.ASYNC=0: Receiver is clocked by transmitter's ACLKX0 Peripheral Information and Electrical Specifications 136 Submit Documentation Feedback

www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 6-47. Switching Characteristics for McASP0 (1.2V, 1.1V) (1) 1.2V 1.1V NO. PARAMETER UNIT MIN MAX MIN MAX t c(AHCLKRX) Cycle time, AHCLKR/X ns t w(AHCLKRX) Pulse duration, AHCLKR/X high or low AH 2.5 (2) AH 2.5 (2) ns t c(ACLKRX) Cycle time, ACLKR/X ACLKR/X int (3) (4) (3) (4) ns t w(ACLKRX) Pulse duration, ACLKR/X high or low ACLKR/X int A 2.5 (5) A 2.5 (5) ns ACLKR/X int ns Delay time, ACLKR/X transmit edge to t d(ACLKRX-AFSRX) ACLKR/X ext input 13.5 14.5 ns AFSX/R output valid (6) ACLKR/X ext output 13.5 14.5 ns ACLKR/X int ns Delay time, ACLKX transmit edge to t d(ACLKX-AXRV) ACLKR/X ext input 13.5 14.5 ns AXR output valid ACLKR/X ext output 13.5 14.5 ns Disable time, ACLKR/X transmit edge to ACLKR/X int ns t dis(ACLKX-AXRHZ) AXR high impedance following last data ACLKR/X ext 13.5 14.5 ns bit (1) McASP0 ACLKX0 internal ACLKXCTL.CLKXM PDIR.ACLKX ACLKX0 external input McASP0 ACLKXCTL.CLKXM PDIR.ACLKX ACLKX0 external output McASP0ACLKXCTL.CLKXM PDIR.ACLKX ACLKR0 internal McASP0 ACLKR0CTL.CLKRM PDIR.ACLKR ACLKR0 external input McASP0 ACLKRCTL.CLKRM PDIR.ACLKR ACLKR0 external output McASP0 ACLKRCTL.CLKRM PDIR.ACLKR (2) AH (AHCLKR/X period)/2 in ns. For example, when AHCLKR/X period is ns, use AH 12.5 ns. (3) P SYSCLK2 period (4) This timing is limited by the timing shown or 2P, whichever is greater. (5) A (ACLKR/X period)/2 in ns. For example, when AHCLKR/X period is ns, use AH 12.5 ns. (6) McASP0 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR0 Table 6-48. Switching Characteristics for McASP0 (1.0V) (1) 1.0V NO. PARAMETER UNIT MIN MAX t c(AHCLKRX) Cycle time, AHCLKR/X 26.6 ns t w(AHCLKRX) Pulse duration, AHCLKR/X high or low AH 2.5 (2) ns t c(ACLKRX) Cycle time, ACLKR/X ACLKR/X int 26.6 (3) (4) ns t w(ACLKRX) Pulse duration, ACLKR/X high or low ACLKR/X int A 2.5 (5) ns ACLKR/X int ns t d(ACLKRX-AFSRX) Delay time, ACLKR/X transmit edge to AFSX/R output valid (6) ACLKR/X ext input ns ACLKR/X ext output ns ACLKR/X int ns t d(ACLKX-AXRV) Delay time, ACLKX transmit edge to AXR output valid ACLKR/X ext input ns ACLKR/X ext output ns ACLKR/X int ns Disable time, ACLKR/X transmit edge to AXR high t dis(ACLKX-AXRHZ) impedance following last data bit ACLKR/X ext ns (1) McASP0 ACLKX0 internal ACLKXCTL.CLKXM PDIR.ACLKX ACLKX0 external input McASP0 ACLKXCTL.CLKXM PDIR.ACLKX ACLKX0 external output McASP0ACLKXCTL.CLKXM PDIR.ACLKX ACLKR0 internal McASP0 ACLKR0CTL.CLKRM PDIR.ACLKR ACLKR0 external input McASP0 ACLKRCTL.CLKRM PDIR.ACLKR ACLKR0 external output McASP0 ACLKRCTL.CLKRM PDIR.ACLKR (2) AH (AHCLKR/X period)/2 in ns. For example, when AHCLKR/X period is ns, use AH 12.5 ns. (3) P SYSCLK2 period (4) This timing is limited by the timing shown or 2P, whichever is greater. (5) A (ACLKR/X period)/2 in ns. For example, when AHCLKR/X period is ns, use AH 12.5 ns. (6) McASP0 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR0 Submit Documentation Feedback Peripheral Information and Electrical Specifications 137

A0 A1 B0 B1 A30 A31 B30 B31 C0 C1 C2 C3 C31 AHCLKR/X (Falling Edge Polarity) AHCLKR/X (Rising Edge Polarity) AFSR/X (Bit Width, 0 Bit Delay) AFSR/X (Bit Width, 1 Bit Delay) AFSR/X (Bit Width, 2 Bit Delay) AFSR/X (Slot Width, 0 Bit Delay) AFSR/X (Slot Width, 1 Bit Delay) AFSR/X (Slot Width, 2 Bit Delay) AXR[n] (Data In/Receive) ACLKR/X (CLKRP = CLKXP = 0)(A) ACLKR/X (CLKRP = CLKXP = 1)(B) OMAP-L138 Low-Power www.ti.com For CLKRP CLKXP the McASP transmitter is configured for rising edge (to shift data out) and the McASP receiver is configured for falling edge (to shift data in). For CLKRP CLKXP the McASP transmitter is configured for falling edge (to shift data out) and the McASP receiver is configured for rising edge (to shift data in). Figure 6-31. McASP Input Timings 138 Peripheral Information and Electrical Specifications Submit Documentation Feedback

A0 A1 B0 B1 A30 A31 B30 B31 C0 C1 C2 C3 C31 AHCLKR/X (Falling Edge Polarity) AHCLKR/X (Rising Edge Polarity) AFSR/X (Bit Width, 0 Bit Delay) AFSR/X (Bit Width, 1 Bit Delay) AFSR/X (Bit Width, 2 Bit Delay) AFSR/X (Slot Width, 0 Bit Delay) AFSR/X (Slot Width, 1 Bit Delay) AFSR/X (Slot Width, 2 Bit Delay) AXR[n] (Data Out/Transmit) ACLKR/X (CLKRP = CLKXP = 0)(B) ACLKR/X (CLKRP = CLKXP = 1)(A) OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 For CLKRP CLKXP the McASP transmitter is configured for falling edge (to shift data out) and the McASP receiver is configured for rising edge (to shift data in). For CLKRP CLKXP the McASP transmitter is configured for rising edge (to shift data out) and the McASP receiver is configured for falling edge (to shift data in). Figure 6-32. McASP Output Timings Submit Documentation Feedback Peripheral Information and Electrical Specifications 139

6.15 Multichannel Buffered Serial Port (McBSP) 6.15.1 McBSP Peripheral Register Description(s) OMAP-L138 Low-Power www.ti.com The McBSP provides these functions: Full-duplex communication Double-buffered data registers, which allow a continuous data stream Independent framing and clocking for receive and transmit Direct interface to industry-standard codecs, analog interface chips (AICs), and other serially connected analog-to-digital (A/D) and digital-to-analog (D/A) devices External shift clock or an internal, programmable frequency shift clock for data transfer Transmit Receive FIFO Buffers allow the McBSP to operate at a higher sample rate by making it more tolerant to DMA latency If internal clock source is used, the CLKGDV field of the Sample Rate Generator Register (SRGR) must always be set to a value of or greater. Table 6-49. McBSP/FIFO Registers McBSP0 McBSP1 BYTE BYTE ACRONYM REGISTER (read-only) 0x01D1 0004 0x01D1 1004 DXR McBSP Data Transmit Register 0x01D1 0008 0x01D1 1008 SPCR McBSP Serial Port Control Register 0x01D1 000C 0x01D1 100C RCR McBSP Receive Control Register 0x01D1 0010 0x01D1 1010 XCR McBSP Transmit Control Register 0x01D1 0014 0x01D1 1014 SRGR McBSP Sample Rate Generator register 0x01D1 0018 0x01D1 1018 MCR McBSP Multichannel Control Register 0x01D1 001C 0x01D1 101C RCERE0 McBSP Enhanced Receive Channel Enable Register Partition A/B 0x01D1 0020 0x01D1 1020 XCERE0 McBSP Enhanced Transmit Channel Enable Register Partition A/B 0x01D1 0024 0x01D1 1024 PCR McBSP Pin Control Register 0x01D1 0028 0x01D1 1028 RCERE1 McBSP Enhanced Receive Channel Enable Register Partition C/D 0x01D1 002C 0x01D1 102C XCERE1 McBSP Enhanced Transmit Channel Enable Register Partition C/D 0x01D1 0030 0x01D1 1030 RCERE2 McBSP Enhanced Receive Channel Enable Register Partition E/F 0x01D1 0034 0x01D1 1034 XCERE2 McBSP Enhanced Transmit Channel Enable Register Partition E/F 0x01D1 0038 0x01D1 1038 RCERE3 McBSP Enhanced Receive Channel Enable Register Partition G/H 0x01D1 003C 0x01D1 103C XCERE3 McBSP Enhanced Transmit Channel Enable Register Partition G/H McBSP FIFO Control and Status Registers 0x01D1 0800 0x01D1 1800 BFIFOREV BFIFO Revision Identification Register 0x01D1 0810 0x01D1 1810 WFIFOCTL Write FIFO Control Register 0x01D1 0814 0x01D1 1814 WFIFOSTS Write FIFO Status Register 0x01D1 0818 0x01D1 1818 RFIFOCTL Read FIFO Control Register 0x01D1 081C 0x01D1 181C RFIFOSTS Read FIFO Status Register McBSP FIFO Data Registers 0x01F1 0000 0x01F1 1000 RBUF McBSP FIFO Receive Buffer 0x01F1 0000 0x01F1 1000 XBUF McBSP FIFO Transmit Buffer Peripheral Information and Electrical Specifications 140 Submit Documentation Feedback

6.15.2 McBSP Electrical Data/Timing 6.15.2.1 Multichannel Buffered Serial Port (McBSP) Timing OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 The following assume testing over recommended operating conditions. Table 6-50. Timing Requirements for McBSP0 [1.2V, 1.1V] (1) (see Figure 6-33 1.2V 1.1V NO. PARAMETER UNIT MIN MAX MIN MAX t c(CKRX) Cycle time, CLKR/X CLKR/X ext or (2) (3) or (2) (3) ns t w(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X ext P (4) P (4) ns CLKR int 15.5 Setup time, external FSR high before CLKR t su(FRH-CKRL) ns low CLKR ext CLKR int t h(CKRL-FRH) Hold time, external FSR high after CLKR low ns CLKR ext CLKR int 15.5 t su(DRV-CKRL) Setup time, DR valid before CLKR low ns CLKR ext CLKR int t h(CKRL-DRV) Hold time, DR valid after CLKR low ns CLKR ext CLKX int 15.5 t su(FXH-CKXL) Setup time, external FSX high before CLKX low ns CLKX ext CLKX int t h(CKXL-FXH) Hold time, external FSX high after CLKX low ns CLKX ext (1) CLKRP CLKXP FSRP FSXP If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. (2) P AYNC3 period in ns. For example, when the ASYNC clock domain is running at 100 MHz, use ns. (3) Use whichever value is greater. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. The minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements. (4) This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of duty cycle. Submit Documentation Feedback Peripheral Information and Electrical Specifications 141

www.ti.com Table 6-51. Timing Requirements for McBSP0 [1.0V] (1) (see Figure 6-33 1.0V NO. PARAMETER UNIT MIN MAX or t c(CKRX) Cycle time, CLKR/X CLKR/X ext ns 26.6 (2) (3) t w(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X ext P (4) ns CLKR int t su(FRH-CKRL) Setup time, external FSR high before CLKR low ns CLKR ext CLKR int t h(CKRL-FRH) Hold time, external FSR high after CLKR low ns CLKR ext CLKR int t su(DRV-CKRL) Setup time, DR valid before CLKR low ns CLKR ext CLKR int t h(CKRL-DRV) Hold time, DR valid after CLKR low ns CLKR ext CLKX int t su(FXH-CKXL) Setup time, external FSX high before CLKX low ns CLKX ext CLKX int t h(CKXL-FXH) Hold time, external FSX high after CLKX low ns CLKX ext (1) CLKRP CLKXP FSRP FSXP If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. (2) P AYNC3 period in ns. For example, when the ASYNC clock domain is running at 100 MHz, use ns. (3) Use whichever value is greater. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. The minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements. (4) This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of duty cycle. Peripheral Information and Electrical Specifications 142 Submit Documentation Feedback

www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 6-52. Switching Characteristics for McBSP0 [1.2V, 1.1V] (1) (2) (see Figure 6-33 1.2V 1.1V NO. PARAMETER UNIT MIN MAX MIN MAX Delay time, CLKS high to CLKR/X high for internal t d(CKSH-CKRXH) 14.5 ns CLKR/X generated from CLKS input or or t c(CKRX) Cycle time, CLKR/X CLKR/X int ns (3) (4) (5) (3) (4) (5) Pulse duration, CLKR/X high or t w(CKRX) CLKR/X int C (6) C (6) C (6) C (6) ns CLKR/X low CLKR int 5.5 5.5 ns Delay time, CLKR high to internal FSR t d(CKRH-FRV) valid CLKR ext 14.5 CLKX int 5.5 5.5 Delay time, CLKX high to internal FSX t d(CKXH-FXV) ns valid CLKX ext 14.5 CLKX int 7.5 -5.5 7.5 Disable time, DX high impedance t dis(CKXH-DXHZ) ns following last data bit from CLKX high CLKX ext -22 CLKX int (7) 5.5 (7) (7) 5.5 (7) t d(CKXH-DXV) Delay time, CLKX high to DX valid ns CLKX ext (7) 14.5 (7) (7) (7) Delay time, FSX high to DX valid FSX int (8) (8) (8) (8) t d(FXH-DXV) ns ONLY applies when in data FSX ext (8) 14.5 (8) (8) (8) delay (XDATDLY 00b) mode (1) CLKRP CLKXP FSRP FSXP If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. (2) Minimum delay times also represent minimum output hold times. (3) Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. Minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements. (4) P AYNC3 period in ns. For example, when the ASYNC clock domain is running at 100 MHz, use ns. (5) Use whichever value is greater. (6) C H or L S sample rate generator input clock P if CLKSM ASYNC period) S sample rate generator input clock P_clks if CLKSM (P_clks CLKS period) H CLKX high pulse width (CLKGDV/2 S if CLKGDV is even H (CLKGDV 1)/2 S if CLKGDV is odd L CLKX low pulse width (CLKGDV/2) S if CLKGDV is even L (CLKGDV 1)/2 S if CLKGDV is odd CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see (4) above). (7) Extra delay from CLKX high to DX valid applies only to the first data bit of a device if and only if DXENA in SPCR. if DXENA then if DXENA then 6P, 12P (8) Extra delay from FSX high to DX valid applies only to the first data bit of a device if and only if DXENA in SPCR. if DXENA then if DXENA then 6P, 12P Submit Documentation Feedback Peripheral Information and Electrical Specifications 143

www.ti.com Table 6-53. Switching Characteristics for McBSP0 [1.0V] (1) (2) (see Figure 6-33 1.0V NO. PARAMETER UNIT MIN MAX Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from t d(CKSH-CKRXH) 21.5 ns CLKS input or t c(CKRX) Cycle time, CLKR/X CLKR/X int ns 26.6 (3) (4) (5) t w(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X int C (6) C (6) ns CLKR int ns t d(CKRH-FRV) Delay time, CLKR high to internal FSR valid CLKR ext 2.5 21.5 CLKX int t d(CKXH-FXV) Delay time, CLKX high to internal FSX valid ns CLKX ext 2.5 21.5 CLKX int Disable time, DX high impedance following last data bit from CLKX t dis(CKXH-DXHZ) ns high CLKX ext 21.5 CLKX int (7) (7) t d(CKXH-DXV) Delay time, CLKX high to DX valid ns CLKX ext 2.5 (7) 21.5 (7) Delay time, FSX high to DX valid FSX int (8) (8) t d(FXH-DXV) ns ONLY applies when in data FSX ext (8) 21.5 (8) delay (XDATDLY 00b) mode (1) CLKRP CLKXP FSRP FSXP If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. (2) Minimum delay times also represent minimum output hold times. (3) Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. Minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements. (4) P AYNC3 period in ns. For example, when the ASYNC clock domain is running at 100 MHz, use ns. (5) Use whichever value is greater. (6) C H or L S sample rate generator input clock P if CLKSM ASYNC period) S sample rate generator input clock P_clks if CLKSM (P_clks CLKS period) H CLKX high pulse width (CLKGDV/2 S if CLKGDV is even H (CLKGDV 1)/2 S if CLKGDV is odd L CLKX low pulse width (CLKGDV/2) S if CLKGDV is even L (CLKGDV 1)/2 S if CLKGDV is odd CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see (4) above). (7) Extra delay from CLKX high to DX valid applies only to the first data bit of a device if and only if DXENA in SPCR. if DXENA then if DXENA then 6P, 12P (8) Extra delay from FSX high to DX valid applies only to the first data bit of a device if and only if DXENA in SPCR. if DXENA then if DXENA then 6P, 12P Table 6-54. Timing Requirements for McBSP1 [1.2V, 1.1V] (1) (see Figure 6-33 1.2V 1.1V NO. PARAMETER UNIT MIN MAX MIN MAX t c(CKRX) Cycle time, CLKR/X CLKR/X ext or (2) (3) or (2) (4) ns t w(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X ext P (5) P (6) ns CLKR int Setup time, external FSR high before CLKR t su(FRH-CKRL) ns low CLKR ext (1) CLKRP CLKXP FSRP FSXP If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. (2) P AYNC3 period in ns. For example, when the ASYNC clock domain is running at 100 MHz, use ns. (3) Use whichever value is greater. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. The minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements. (4) Use whichever value is greater. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. The minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements. (5) This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of duty cycle. (6) This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of duty cycle. 144 Peripheral Information and Electrical Specifications Submit Documentation Feedback

www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 6-54. Timing Requirements for McBSP1 [1.2V, 1.1V] (see Figure 6-33 (continued) 1.2V 1.1V NO. PARAMETER UNIT MIN MAX MIN MAX CLKR int t h(CKRL-FRH) Hold time, external FSR high after CLKR low ns CLKR ext CLKR int t su(DRV-CKRL) Setup time, DR valid before CLKR low ns CLKR ext CLKR int t h(CKRL-DRV) Hold time, DR valid after CLKR low ns CLKR ext CLKX int t su(FXH-CKXL) Setup time, external FSX high before CLKX low ns CLKX ext CLKX int t h(CKXL-FXH) Hold time, external FSX high after CLKX low ns CLKX ext Submit Documentation Feedback Peripheral Information and Electrical Specifications 145

www.ti.com Table 6-55. Timing Requirements for McBSP1 [1.0V] (1) (see Figure 6-33 1.0V NO. PARAMETER UNIT MIN MAX or t c(CKRX) Cycle time, CLKR/X CLKR/X ext ns 26.6 (2) (3) t w(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X ext P (4) ns CLKR int t su(FRH-CKRL) Setup time, external FSR high before CLKR low ns CLKR ext CLKR int t h(CKRL-FRH) Hold time, external FSR high after CLKR low ns CLKR ext CLKR int t su(DRV-CKRL) Setup time, DR valid before CLKR low ns CLKR ext CLKR int t h(CKRL-DRV) Hold time, DR valid after CLKR low ns CLKR ext CLKX int t su(FXH-CKXL) Setup time, external FSX high before CLKX low ns CLKX ext CLKX int t h(CKXL-FXH) Hold time, external FSX high after CLKX low ns CLKX ext (1) CLKRP CLKXP FSRP FSXP If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. (2) P AYNC3 period in ns. For example, when the ASYNC clock domain is running at 100 MHz, use ns. (3) Use whichever value is greater. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. The minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements. (4) This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of duty cycle. Peripheral Information and Electrical Specifications 146 Submit Documentation Feedback

www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 6-56. Switching Characteristics for McBSP1 [1.2V, 1.1V] (1) (2) (see Figure 6-33 1.2V 1.1V NO. PARAMETER UNIT MIN MAX MIN MAX Delay time, CLKS high to CLKR/X high for internal t d(CKSH-CKRXH) 2.5 16.5 ns CLKR/X generated from CLKS input or or t c(CKRX) Cycle time, CLKR/X CLKR/X int ns (3) (4) (5) (3) (4) (5) Pulse duration, CLKR/X high or t w(CKRX) CLKR/X int C (6) C (6) C (6) C (6) ns CLKR/X low CLKR int 6.5 ns Delay time, CLKR high to internal FSR t d(CKRH-FRV) valid CLKR ext 2.5 16.5 2.5 CLKX int 6.5 Delay time, CLKX high to internal FSX t d(CKXH-FXV) ns valid CLKX ext 2.5 16.5 2.5 CLKX int 6.5 Disable time, DX high impedance t dis(CKXH-DXHZ) ns following last data bit from CLKX high CLKX ext 16.5 CLKX int (7) 6.5 (7) (7) (7) t d(CKXH-DXV) Delay time, CLKX high to DX valid ns CLKX ext 2.5 (7) 16.5 (7) 2.5 (7) (7) Delay time, FSX high to DX valid FSX int (8) 6.5 (8) (8) (8) t d(FXH-DXV) ns ONLY applies when in data FSX ext (8) 16.5 (8) (8) (9) delay (XDATDLY 00b) mode (1) CLKRP CLKXP FSRP FSXP If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. (2) Minimum delay times also represent minimum output hold times. (3) Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. Minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements. (4) P AYNC3 period in ns. For example, when the ASYNC clock domain is running at 100 MHz, use ns. (5) Use whichever value is greater. (6) C H or L S sample rate generator input clock P if CLKSM ASYNC period) S sample rate generator input clock P_clks if CLKSM (P_clks CLKS period) H CLKX high pulse width (CLKGDV/2 S if CLKGDV is even H (CLKGDV 1)/2 S if CLKGDV is odd L CLKX low pulse width (CLKGDV/2) S if CLKGDV is even L (CLKGDV 1)/2 S if CLKGDV is odd CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see (4) above). (7) Extra delay from CLKX high to DX valid applies only to the first data bit of a device if and only if DXENA in SPCR. if DXENA then if DXENA then 6P, 12P (8) Extra delay from FSX high to DX valid applies only to the first data bit of a device if and only if DXENA in SPCR. if DXENA then if DXENA then 6P, 12P (9) Extra delay from FSX high to DX valid applies only to the first data bit of a device if and only if DXENA in SPCR. if DXENA then if DXENA then 6P, 12P Submit Documentation Feedback Peripheral Information and Electrical Specifications 147

www.ti.com Table 6-57. Switching Characteristics for McBSP1 [1.0V] (1) (2) (see Figure 6-33 1.0V NO. PARAMETER UNIT MIN MAX Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from t d(CKSH-CKRXH) ns CLKS input or t c(CKRX) Cycle time, CLKR/X CLKR/X int ns 26.6 (3) (4) (5) t w(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X int C (6) C (6) ns CLKR int ns t d(CKRH-FRV) Delay time, CLKR high to internal FSR valid CLKR ext 2.5 CLKX int t d(CKXH-FXV) Delay time, CLKX high to internal FSX valid ns CLKX ext 2.5 CLKX int Disable time, DX high impedance following last data bit from CLKX t dis(CKXH-DXHZ) ns high CLKX ext CLKX int (7) (8) t d(CKXH-DXV) Delay time, CLKX high to DX valid ns CLKX ext 2.5 (8) (8) Delay time, FSX high to DX valid FSX int (9) (9) t d(FXH-DXV) ns ONLY applies when in data FSX ext (9) (9) delay (XDATDLY 00b) mode (1) CLKRP CLKXP FSRP FSXP If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. (2) Minimum delay times also represent minimum output hold times. (3) Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. Minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements. (4) P AYNC3 period in ns. For example, when the ASYNC clock domain is running at 100 MHz, use ns. (5) Use whichever value is greater. (6) C H or L S sample rate generator input clock P if CLKSM ASYNC period) S sample rate generator input clock P_clks if CLKSM (P_clks CLKS period) H CLKX high pulse width (CLKGDV/2 S if CLKGDV is even H (CLKGDV 1)/2 S if CLKGDV is odd L CLKX low pulse width (CLKGDV/2) S if CLKGDV is even L (CLKGDV 1)/2 S if CLKGDV is odd CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see (4) above). (7) Extra delay from CLKX high to DX valid applies only to the first data bit of a device if and only if DXENA in SPCR. if DXENA then if DXENA then 6P, 12P (8) Extra delay from CLKX high to DX valid applies only to the first data bit of a device if and only if DXENA in SPCR. if DXENA then if DXENA then 6P, 12P (9) Extra delay from FSX high to DX valid applies only to the first data bit of a device if and only if DXENA in SPCR. if DXENA then if DXENA then 6P, 12P Peripheral Information and Electrical Specifications 148 Submit Documentation Feedback

Bit(n1) (n2) (n3) Bit□0 Bit(n1) (n2) (n3) CLKS CLKR FSR□(int) FSR□(ext) DR CLKX FSX□(int) FSX□(ext) FSX□(XDATDLY=00b) DX 13 (A) 13 (A) CLKS FSR□external CLKR/X□(no□need□to□resync) CLKR/X□(needs□resync) OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Figure 6-33. McBSP Timing (B) Table 6-58. Timing Requirements for McBSP0 FSR When GSYNC (see Figure 6-34 1.2V 1.1V 1.0V NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX t su(FRH-CKSH) Setup time, FSR high before CLKS high 4.5 ns t h(CKSH-FRH) Hold time, FSR high after CLKS high ns Table 6-59. Timing Requirements for McBSP1 FSR When GSYNC (see Figure 6-34 1.2V 1.1V 1.0V NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX t su(FRH-CKSH) Setup time, FSR high before CLKS high ns t h(CKSH-FRH) Hold time, FSR high after CLKS high ns Figure 6-34. FSR Timing When GSYNC Submit Documentation Feedback Peripheral Information and Electrical Specifications 149

6.16 Serial Peripheral Interface Ports SPI0, SPI1) Peripheral Configuration Bus Interrupt and DMA Requests 16-Bit Shift Register 16-Bit Buffer GPIO Control (all pins) State Machine Clock Control SPIx_SIMO SPIx_SOMI SPIx_ENA SPIx_SCS SPIx_CLK OMAP-L138 Low-Power www.ti.com Figure 6-35 is a block diagram of the SPI module, which is a simple shift register and buffer plus control logic. Data is written to the shift register before transmission occurs and is read from the buffer at the end of transmission. The SPI can operate either as a master, in which case, it initiates a transfer and drives the SPIx_CLK pin, or as a slave. Four clock phase and polarity options are supported as well as many data formatting options. Figure 6-35. Block Diagram of SPI Module The SPI supports 3-, 4-, and 5-pin operation with three basic pins (SPIx_CLK, SPIx_SIMO, and SPIx_SOMI) and two optional pins SPIx_SCS SPIx_ENA The optional SPIx_SCS (Slave Chip Select) pin is most useful to enable in slave mode when there are other slave devices on the same SPI port. The device will only shift data and drive the SPIx_SOMI pin when SPIx_SCS is held low. In slave mode, SPIx_ENA is an optional output and can be driven in either a push-pull or open-drain manner. The SPIx_ENA output provides the status of the internal transmit buffer (SPIDAT0/1 registers). In four-pin mode with the enable option, SPIx_ENA is asserted only when the transmit buffer is full, indicating that the slave is ready to begin another transfer. In five-pin mode, the SPIx_ENA is additionally qualified by SPIx_SCS being asserted. This allows a single handshake line to be shared by multiple slaves on the same SPI bus. In master mode, the SPIx_ENA pin is an optional input and the master can be configured to delay the start of the next transfer until the slave asserts SPIx_ENA The addition of this handshake signal simplifies SPI communications and, on average, increases SPI bus throughput since the master does not need to delay each transfer long enough to allow for the worst-case latency of the slave device. Instead, each transfer can begin as soon as both the master and slave have actually serviced the previous SPI transfer. 150 Peripheral Information and Electrical Specifications Submit Documentation Feedback

Optional − Slave Chip Select Optional Enable (Ready) SLA VE SPIMASTER SPI SPIx_SIMOSPIx_SIMO SPIx_SOMI SPIx_SOMI SPIx_CLK SPIx_CLK SPIx_ENA SPIx_ENA SPIx_SCS SPIx_SCS OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Figure 6-36. Illustration of SPI Master-to-SPI Slave Connection Submit Documentation Feedback Peripheral Information and Electrical Specifications 151

6.16.1 SPI Peripheral Registers Description(s) OMAP-L138 Low-Power www.ti.com Table 6-60 is a list of the SPI registers. Table 6-60. SPIx Configuration Registers SPI0 SPI1 REGISTER NAME (Pin Function) 0x01C4 1018 0x01F0 E018 SPIPC1 Pin Control Register (Pin Direction) 0x01C4 101C 0x01F0 E01C SPIPC2 Pin Control Register (Pin Data In) 0x01C4 1020 0x01F0 E020 SPIPC3 Pin Control Register (Pin Data Out) 0x01C4 1024 0x01F0 E024 SPIPC4 Pin Control Register (Pin Data Set) 0x01C4 1028 0x01F0 E028 SPIPC5 Pin Control Register (Pin Data Clear) 0x01C4 102C 0x01F0 E02C Reserved Reserved Do not write to this register 0x01C4 1030 0x01F0 E030 Reserved Reserved Do not write to this register 0x01C4 1034 0x01F0 E034 Reserved Reserved Do not write to this register 0x01C4 1038 0x01F0 E038 SPIDAT0 Shift Register (without format select) 0x01C4 103C 0x01F0 E03C SPIDAT1 Shift Register (with format select) 0x01C4 1040 0x01F0 E040 SPIBUF Buffer Register 0x01C4 1044 0x01F0 E044 SPIEMU Emulation Register 0x01C4 1048 0x01F0 E048 SPIDELAY Delay Register 0x01C4 104C 0x01F0 E04C SPIDEF Default Chip Select Register 0x01C4 1050 0x01F0 E050 SPIFMT0 Format Register 0x01C4 1054 0x01F0 E054 SPIFMT1 Format Register 0x01C4 1058 0x01F0 E058 SPIFMT2 Format Register 0x01C4 105C 0x01F0 E05C SPIFMT3 Format Register 0x01C4 1060 0x01F0 E060 INTVEC0 Interrupt Vector for SPI INT0 0x01C4 1064 0x01F0 E064 INTVEC1 Interrupt Vector for SPI INT1 Peripheral Information and Electrical Specifications 152 Submit Documentation Feedback

6.16.2 SPI Electrical Data/Timing 6.16.2.1 Serial Peripheral Interface (SPI) Timing OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 6-61 through Table 6-76 assume testing over recommended operating conditions (see Figure 6-37 through Figure 6-40 Table 6-61. General Timing Requirements for SPI0 Master Modes (1) 1.2V 1.1V 1.0V NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX Cycle Time, SPI0_CLK, All Master t c(SPC)M (2) 256P (2) 256P (2) 256P ns Modes Pulse Width High, SPI0_CLK, All t w(SPCH)M 0.5M-1 0.5M-1 0.5M-1 ns Master Modes Pulse Width Low, SPI0_CLK, All t w(SPCL)M 0.5M-1 0.5M-1 0.5M-1 ns Master Modes Delay, Polarity Phase initial to SPI0_CLK rising data bit Polarity Phase -0.5M+5 -0.5M+5 -0.5M+6 valid on to SPI0_CLK rising SPI0_SI t d(SIMO_SPC)M ns Polarity Phase MO after to SPI0_CLK falling initial edge on Polarity Phase SPI0_CL -0.5M+5 -0.5M+5 -0.5M+6 to SPI0_CLK falling K (3) Delay, Polarity Phase subsequ from SPI0_CLK rising ent bits Polarity Phase valid on from SPI0_CLK falling SPI0_SI t d(SPC_SIMO)M ns Polarity Phase MO after from SPI0_CLK falling transmit edge of Polarity Phase SPI0_CL from SPI0_CLK rising K Output Polarity Phase 0.5M-3 0.5M-3 0.5M-3 hold from SPI0_CLK falling time, Polarity Phase 0.5M-3 0.5M-3 0.5M-3 SPI0_SI from SPI0_CLK rising MO valid t oh(SPC_SIMO)M ns Polarity Phase after 0.5M 0.5M 0.5M from SPI0_CLK rising receive edge of Polarity Phase SPI0_CL 0.5M 0.5M 0.5M from SPI0_CLK falling K Input Polarity Phase 1.5 1.5 1.5 Setup to SPI0_CLK falling Time, Polarity Phase 1.5 1.5 1.5 SPI0_S to SPI0_CLK rising OMI Polarity Phase t su(SOMI_SPC)M valid ns 1.5 1.5 1.5 to SPI0_CLK rising before receive edge of Polarity Phase 1.5 1.5 1.5 SPI0_CL to SPI0_CLK falling K (1) P SYSCLK2 period; M t c(SPC)M (SPI master bit clock period) (2) This timing is limited by the timing shown or 2P, whichever is greater. (3) First bit may be MSB or LSB depending upon SPI configuration. MO(0) refers to first bit and MO(n) refers to last bit output on SPI0_SIMO. MI(0) refers to the first bit input and MI(n) refers to the last bit input on SPI0_SOMI. Submit Documentation Feedback Peripheral Information and Electrical Specifications 153

www.ti.com Table 6-61. General Timing Requirements for SPI0 Master Modes (continued) 1.2V 1.1V 1.0V NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX Input Polarity Phase Hold from SPI0_CLK falling Time, Polarity Phase SPI0_S from SPI0_CLK rising OMI Polarity Phase t ih(SPC_SOMI)M valid ns from SPI0_CLK rising after receive edge of Polarity Phase SPI0_CL from SPI0_CLK falling K Table 6-62. General Timing Requirements for SPI0 Slave Modes (1) 1.2V 1.1V 1.0V NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX t c(SPC)S Cycle Time, SPI0_CLK, All Slave Modes (2) 256P (2) 256P (2) 256P ns t w(SPCH)S Pulse Width High, SPI0_CLK, All Slave Modes ns t w(SPCL)S Pulse Width Low, SPI0_CLK, All Slave Modes ns Polarity Phase to SPI0_CLK rising Setup time, transmit Polarity Phase data written to SPI to SPI0_CLK rising t su(SOMI_SPC)S before initial clock ns Polarity Phase edge from to SPI0_CLK falling master. (3) (4) Polarity Phase to SPI0_CLK falling Polarity Phase from SPI0_CLK rising Delay, subsequent Polarity Phase bits valid on from SPI0_CLK falling t d(SPC_SOMI)S SPI0_SOMI after ns Polarity Phase transmit edge of from SPI0_CLK falling SPI0_CLK Polarity Phase from SPI0_CLK rising Polarity Phase 0.5S-6 0.5S-16 0.5S-20 from SPI0_CLK falling Output hold time, Polarity Phase 0.5S-6 0.5S-16 0.5S-20 SPI0_SOMI valid from SPI0_CLK rising t oh(SPC_SOMI)S after ns Polarity Phase receive edge of 0.5S-6 0.5S-16 0.5S-20 from SPI0_CLK rising SPI0_CLK Polarity Phase 0.5S-6 0.5S-16 0.5S-20 from SPI0_CLK falling Polarity Phase 1.5 1.5 1.5 to SPI0_CLK falling Input Setup Time, Polarity Phase 1.5 1.5 1.5 SPI0_SIMO valid to SPI0_CLK rising t su(SIMO_SPC)S before ns Polarity Phase receive edge of 1.5 1.5 1.5 to SPI0_CLK rising SPI0_CLK Polarity Phase 1.5 1.5 1.5 to SPI0_CLK falling (1) P SYSCLK2 period; S t c(SPC)S (SPI slave bit clock period) (2) This timing is limited by the timing shown or 2P, whichever is greater. (3) First bit may be MSB or LSB depending upon SPI configuration. SO(0) refers to first bit and SO(n) refers to last bit output on SPI0_SOMI. SI(0) refers to the first bit input and SI(n) refers to the last bit input on SPI0_SIMO. (4) Measured from the termination of the write of new data to the SPI module, In analyzing throughput requirements, additional internal bus cycles must be accounted for to allow data to be written to the SPI module by the DSP CPU. Peripheral Information and Electrical Specifications 154 Submit Documentation Feedback

www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 6-62. General Timing Requirements for SPI0 Slave Modes (continued) 1.2V 1.1V 1.0V NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX Polarity Phase from SPI0_CLK falling Input Hold Time, Polarity Phase SPI0_SIMO valid from SPI0_CLK rising t ih(SPC_SIMO)S after ns Polarity Phase receive edge of from SPI0_CLK rising SPI0_CLK Polarity Phase from SPI0_CLK falling Submit Documentation Feedback Peripheral Information and Electrical Specifications 155

www.ti.com Table 6-63. Additional SPI0 Master Timings, 4-Pin Enable Option (1) (2) (3) 1.2V 1.1V 1.0V NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX Polarity Phase 3P+5 3P+5 3P+6 to SPI0_CLK rising Polarity Phase 0.5M+3P+5 0.5M+3P+5 0.5M+3P+6 to SPI0_CLK rising Delay from slave assertion of SPI0_ENA active to first t d(ENA_SPC)M ns SPI0_CLK from master. (4) Polarity Phase 3P+5 3P+5 3P+6 to SPI0_CLK falling Polarity Phase 0.5M+3P+5 0.5M+3P+5 0.5M+3P+6 to SPI0_CLK falling Polarity Phase 0.5M+P+5 0.5M+P+5 0.5M+P+6 from SPI0_CLK falling Polarity Phase P+5 P+5 P+6 from SPI0_CLK falling Max delay for slave to deassert SPI0_ENA after final SPI0_CLK t d(SPC_ENA)M ns edge to ensure master does not begin the next transfer. (5) Polarity Phase 0.5M+P+5 0.5M+P+5 0.5M+P+6 from SPI0_CLK rising Polarity Phase P+5 P+5 P+6 from SPI0_CLK rising (1) These parameters are in addition to the general timings for SPI master modes Table 6-61 (2) P SYSCLK2 period; M t c(SPC)M (SPI master bit clock period) (3) Figure shows only Polarity Phase as an example. Table gives parameters for all four master clocking modes. (4) In the case where the master SPI is ready with new data before SPI0_ENA assertion. (5) In the case where the master SPI is ready with new data before SPI0_EN A deassertion. 156 Peripheral Information and Electrical Specifications Submit Documentation Feedback

www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 6-64. Additional SPI0 Master Timings, 4-Pin Chip Select Option (1) (2) (3) 1.2V 1.1V 1.0V NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX Polarity Phase 2P-1 2P-2 2P-3 to SPI0_CLK rising Polarity Phase 0.5M+2P-1 0.5M+2P-2 0.5M+2P-3 to SPI0_CLK rising t d(SCS_SPC)M Delay from SPI0_SCS active to first SPI0_CLK (4) (5) ns Polarity Phase 2P-1 2P-2 2P-3 to SPI0_CLK falling Polarity Phase 0.5M+2P-1 0.5M+2P-2 0.5M+2P-3 to SPI0_CLK falling Polarity Phase 0.5M+P-1 0.5M+P-2 0.5M+P-3 from SPI0_CLK falling Polarity Phase P-1 P-2 P-3 from SPI0_CLK falling Delay from final SPI0_CLK edge to master deasserting t d(SPC_SCS)M ns SPI0_SCS (6) (7) Polarity Phase 0.5M+P-1 0.5M+P-2 0.5M+P-3 from SPI0_CLK rising Polarity Phase P-1 P-2 P-3 from SPI0_CLK rising (1) These parameters are in addition to the general timings for SPI master modes Table 6-61 (2) P SYSCLK2 period; M t c(SPC)M (SPI master bit clock period) (3) Figure shows only Polarity Phase as an example. Table gives parameters for all four master clocking modes. (4) In the case where the master SPI is ready with new data before SPI0_SCS assertion. (5) This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0]. (6) Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI0_SCS will remain asserted. (7) This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0]. Submit Documentation Feedback Peripheral Information and Electrical Specifications 157

www.ti.com Table 6-65. Additional SPI0 Master Timings, 5-Pin Option (1) (2) (3) 1.2V 1.1V 1.0V NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX Polarity Phase 0.5M+P+5 0.5M+P+5 0.5M+P+6 from SPI0_CLK falling Polarity Phase Max delay for slave to deassert P+5 P+5 P+6 from SPI0_CLK falling SPI0_ENA after final SPI0_CLK edge t d(SPC_ENA)M ns to ensure master does not begin the Polarity Phase 0.5M+P+5 0.5M+P+5 0.5M+P+6 next transfer. (4) from SPI0_CLK rising Polarity Phase P+5 P+5 P+6 from SPI0_CLK rising Polarity Phase 0.5M+P-2 0.5M+P-2 0.5M+P-3 from SPI0_CLK falling Polarity Phase P-2 P-2 P-3 from SPI0_CLK falling Delay from final SPI0_CLK edge to t d(SPC_SCS)M ns master deasserting SPI0_SCS (5) (6) Polarity Phase 0.5M+P-2 0.5M+P-2 0.5M+P-3 from SPI0_CLK rising Polarity Phase P-2 P-2 P-3 from SPI0_CLK rising Max delay for slave SPI to drive SPI0_ENA valid after master t d(SCSL_ENAL)M asserts SPI0_SCS to delay the master from beginning the next C2TDELAY+P C2TDELAY+P C2TDELAY+P ns transfer, Polarity Phase 2P-2 2P-2 2P-3 to SPI0_CLK rising Polarity Phase 0.5M+2P-2 0.5M+2P-2 0.5M+2P-3 to SPI0_CLK rising Delay from SPI0_SCS active to first t d(SCS_SPC)M ns SPI0_CLK (7) (8) (9) Polarity Phase 2P-2 2P-2 2P-3 to SPI0_CLK falling Polarity Phase 0.5M+2P-2 0.5M+2P-2 0.5M+2P-3 to SPI0_CLK falling (1) These parameters are in addition to the general timings for SPI master modes Table 6-62 (2) P SYSCLK2 period; M t c(SPC)M (SPI master bit clock period) (3) Figure shows only Polarity Phase as an example. Table gives parameters for all four master clocking modes. (4) In the case where the master SPI is ready with new data before SPI0_ENA deassertion. (5) Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI0_SCS will remain asserted. (6) This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0]. (7) If SPI0_ENA is asserted immediately such that the transmission is not delayed by SPI0_ENA (8) In the case where the master SPI is ready with new data before SPI0_SCS assertion. (9) This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0]. Peripheral Information and Electrical Specifications 158 Submit Documentation Feedback

www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 6-65. Additional SPI0 Master Timings, 5-Pin Option (continued) 1.2V 1.1V 1.0V NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX Polarity Phase 3P+5 3P+5 3P+6 to SPI0_CLK rising Polarity Phase 0.5M+3P+5 0.5M+3P+5 0.5M+3P+6 to SPI0_CLK rising Delay from assertion of SPI0_ENA t d(ENA_SPC)M ns low to first SPI0_CLK edge. (10) Polarity Phase 3P+5 3P+5 3P+6 to SPI0_CLK falling Polarity Phase 0.5M+3P+5 0.5M+3P+5 0.5M+3P+6 to SPI0_CLK falling (10) If SPI0_ENA was initially deasserted high and SPI0_CLK is delayed. Submit Documentation Feedback Peripheral Information and Electrical Specifications 159

www.ti.com Table 6-66. Additional SPI0 Slave Timings, 4-Pin Enable Option (1) (2) (3) 1.2V 1.1V 1.0V NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX Polarity Phase 1.5P-3 2.5P+17.5 1.5P-3 2.5P+20 1.5P-3 2.5P+27 from SPI0_CLK falling Polarity Phase Delay from final 0.5M+1.5P-3 0.5M+2.5P+17. 0.5M+1.5P-3 0.5M+1.5P-3 from SPI0_CLK falling 0.5M+2.5P+20 0.5M+2.5P+27 SPI0_CLK edge to t d(SPC_ENAH)S ns slave deasserting Polarity Phase SPI0_ENA 1.5P-3 2.5P+17.5 1.5P-3 2.5P+20 1.5P-3 2.5P+27 from SPI0_CLK rising Polarity Phase 0.5M+1.5P-3 0.5M+1.5P-3 0.5+2.5P+20 0.5M+1.5P-3 0.5+2.5P+27 from SPI0_CLK rising 0.5+2.5P+17.5 (1) These parameters are in addition to the general timings for SPI slave modes Table 6-62 (2) P SYSCLK2 period; M t c(SPC)M (SPI master bit clock period) (3) Figure shows only Polarity Phase as an example. Table gives parameters for all four slave clocking modes. 160 Peripheral Information and Electrical Specifications Submit Documentation Feedback

www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 6-67. Additional SPI0 Slave Timings, 4-Pin Chip Select Option (1) (2) (3) 1.2V 1.1V 1.0V NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX t d(SCSL_SPC)S Required delay from SPI0_SCS asserted at slave to first SPI0_CLK edge at slave. P 1.5 P 1.5 P 1.5 ns Polarity Phase 0.5M+P+4 0.5M+P+4 0.5M+P+5 from SPI0_CLK falling Polarity Phase P+4 P+4 P+5 from SPI0_CLK falling Required delay from final SPI0_CLK edge before SPI0_SCS is t d(SPC_SCSH)S ns deasserted. Polarity Phase 0.5M+P+4 0.5M+P+4 0.5M+P+5 from SPI0_CLK rising Polarity Phase P+4 P+4 P+5 from SPI0_CLK rising P+17. t ena(SCSL_SOMI)S Delay from master asserting SPI0_SCS to slave driving SPI0_SOMI valid P+20 P+27 ns P+17. t dis(SCSH_SOMI)S Delay from master deasserting SPI0_SCS to slave 3-stating SPI0_SOMI P+20 P+27 ns (1) These parameters are in addition to the general timings for SPI slave modes Table 6-62 (2) P SYSCLK2 period; M t c(SPC)M (SPI master bit clock period) (3) Figure shows only Polarity Phase as an example. Table gives parameters for all four slave clocking modes. Submit Documentation Feedback Peripheral Information and Electrical Specifications 161

www.ti.com Table 6-68. Additional SPI0 Slave Timings, 5-Pin Option (1) (2) (3) 1.2V 1.1V 1.0V NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX t d(SCSL_SPC)S Required delay from SPI0_SCS asserted at slave to first SPI0_CLK edge at slave. P 1.5 P 1.5 P 1.5 ns Polarity Phase 0.5M+P 0.5M+P 0.5M+P from SPI0_CLK falling Polarity Phase P+4 P+4 P+5 from SPI0_CLK falling Required delay from final SPI0_CLK edge before SPI0_SCS is t d(SPC_SCSH)S ns deasserted. Polarity Phase 0.5M+P 0.5M+P 0.5M+P from SPI0_CLK rising Polarity Phase P+4 P+4 P+5 from SPI0_CLK rising t ena(SCSL_SOMI)S Delay from master asserting SPI0_SCS to slave driving SPI0_SOMI valid P+17.5 P+20 P+27 ns t dis(SCSH_SOMI)S Delay from master deasserting SPI0_SCS to slave 3-stating SPI0_SOMI P+17.5 P+20 P+27 ns t ena(SCSL_ENA)S Delay from master deasserting SPI0_SCS to slave driving SPI0_ENA valid 17.5 ns Polarity Phase 2.5P+17 2.5P+20 2.5P+27 from SPI0_CLK falling Polarity Phase 2.5P+17 2.5P+20 2.5P+27 from SPI0_CLK rising Delay from final clock receive edge on SPI0_CLK to slave 3-stating t dis(SPC_ENA)S ns or driving high SPI0_ENA (4) Polarity Phase 2.5P+17 2.5P+20 2.5P+27 from SPI0_CLK rising Polarity Phase 2.5P+17 2.5P+20 2.5P+27 from SPI0_CLK falling (1) These parameters are in addition to the general timings for SPI slave modes Table 6-62 (2) P SYSCLK2 period; M t c(SPC)M (SPI master bit clock period) (3) Figure shows only Polarity Phase as an example. Table gives parameters for all four slave clocking modes. (4) SPI0_ENA is driven low after the transmission completes if the SPIINT0.ENABLE_HIGHZ bit is programmed to Otherwise it is tri-stated. If tri-stated, an external pullup resistor should be used to provide a valid level to the master. This option is useful when tying several SPI slave devices to a single master. 162 Peripheral Information and Electrical Specifications Submit Documentation Feedback

www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 6-69. General Timing Requirements for SPI1 Master Modes (1) 1.2V 1.1V 1.0V NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX t c(SPC)M Cycle Time, SPI1_CLK, All Master Modes (2) 256P (2) 256P (2) 256P ns Pulse Width High, SPI1_CLK, All Master t w(SPCH)M 0.5M-1 0.5M-1 0.5M-1 ns Modes Pulse Width Low, SPI1_CLK, All Master t w(SPCL)M 0.5M-1 0.5M-1 0.5M-1 ns Modes Polarity Phase to SPI1_CLK rising Polarity Phase Delay, initial data -0.5M+5 -0.5M+5 -0.5M+6 bit valid on to SPI1_CLK rising 4,5 t d(SIMO_SPC)M SPI1_SIMO to ns Polarity Phase initial edge on SPI1_CLK (3) to SPI1_CLK falling Polarity Phase -0.5M+5 -0.5M+5 -0.5M+6 to SPI1_CLK falling Polarity Phase from SPI1_CLK rising Polarity Phase Delay, subsequent from SPI1_CLK bits valid on falling t d(SPC_SIMO)M SPI1_SIMO after ns Polarity Phase transmit edge of SPI1_CLK from SPI1_CLK falling Polarity Phase from SPI1_CLK rising Polarity Phase 0.5M-3 0.5M-3 0.5M-3 from SPI1_CLK falling Polarity Phase 0.5M-3 0.5M-3 0.5M-3 Output hold time, from SPI1_CLK SPI1_SIMO valid rising t oh(SPC_SIMO)M after ns Polarity Phase receive edge of SPI1_CLK 0.5M-3 0.5M-3 0.5M-3 from SPI1_CLK rising Polarity Phase 0.5M-3 0.5M-3 0.5M-3 from SPI1_CLK falling (1) P SYSCLK2 period; M t c(SPC)M (SPI master bit clock period) (2) This timing is limited by the timing shown or 2P, whichever is greater. (3) First bit may be MSB or LSB depending upon SPI configuration. MO(0) refers to first bit and MO(n) refers to last bit output on SPI1_SIMO. MI(0) refers to the first bit input and MI(n) refers to the last bit input on SPI1_SOMI. Submit Documentation Feedback Peripheral Information and Electrical Specifications 163

www.ti.com Table 6-69. General Timing Requirements for SPI1 Master Modes (continued) 1.2V 1.1V 1.0V NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX Polarity Phase 1.5 1.5 1.5 to SPI1_CLK falling Polarity Phase Input Setup Time, 1.5 1.5 1.5 SPI1_SOMI valid to SPI1_CLK rising t su(SOMI_SPC)M before ns Polarity Phase receive edge of 1.5 1.5 1.5 SPI1_CLK to SPI1_CLK rising Polarity Phase 1.5 1.5 1.5 to SPI1_CLK falling Polarity Phase from SPI1_CLK falling Polarity Phase Input Hold Time, from SPI1_CLK SPI1_SOMI valid rising t ih(SPC_SOMI)M after ns Polarity Phase receive edge of SPI1_CLK from SPI1_CLK rising Polarity Phase from SPI1_CLK falling Peripheral Information and Electrical Specifications 164 Submit Documentation Feedback

www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 6-70. General Timing Requirements for SPI1 Slave Modes (1) 1.2V 1.1V 1.0V NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX t c(SPC)S Cycle Time, SPI1_CLK, All Slave Modes (2) 256P (2) 256P (2) 256P ns t w(SPCH)S Pulse Width High, SPI1_CLK, All Slave Modes ns t w(SPCL)S Pulse Width Low, SPI1_CLK, All Slave Modes ns Polarity Phase to SPI1_CLK rising Polarity Phase Setup time, transmit data to SPI1_CLK rising written to SPI before initial t su(SOMI_SPC)S ns clock edge from Polarity Phase master. (3) (4) to SPI1_CLK falling Polarity Phase to SPI1_CLK falling Polarity Phase from SPI1_CLK rising Polarity Phase Delay, subsequent bits valid from SPI1_CLK falling t d(SPC_SOMI)S on SPI1_SOMI after ns Polarity Phase transmit edge of SPI1_CLK from SPI1_CLK falling Polarity Phase from SPI1_CLK rising Polarity Phase 0.5S-4 0.5S-10 0.5S-12 from SPI1_CLK falling Polarity Phase 0.5S-4 0.5S-10 0.5S-12 Output hold time, from SPI1_CLK rising t oh(SPC_SOMI)S SPI1_SOMI valid after ns Polarity Phase receive edge of SPI1_CLK 0.5S-4 0.5S-10 0.5S-12 from SPI1_CLK rising Polarity Phase 0.5S-4 0.5S-10 0.5S-12 from SPI1_CLK falling Polarity Phase 1.5 1.5 1.5 to SPI1_CLK falling Polarity Phase 1.5 1.5 1.5 Input Setup Time, to SPI1_CLK rising t su(SIMO_SPC)S SPI1_SIMO valid before ns Polarity Phase receive edge of SPI1_CLK 1.5 1.5 1.5 to SPI1_CLK rising Polarity Phase 1.5 1.5 1.5 to SPI1_CLK falling Polarity Phase from SPI1_CLK falling Polarity Phase Input Hold Time, from SPI1_CLK rising t ih(SPC_SIMO)S SPI1_SIMO valid after ns Polarity Phase receive edge of SPI1_CLK from SPI1_CLK rising Polarity Phase from SPI1_CLK falling (1) P SYSCLK2 period; S t c(SPC)S (SPI slave bit clock period) (2) This timing is limited by the timing shown or 2P, whichever is greater. (3) First bit may be MSB or LSB depending upon SPI configuration. SO(0) refers to first bit and SO(n) refers to last bit output on SPI1_SOMI. SI(0) refers to the first bit input and SI(n) refers to the last bit input on SPI1_SIMO. (4) Measured from the termination of the write of new data to the SPI module, In analyzing throughput requirements, additional internal bus cycles must be accounted for to allow data to be written to the SPI module by the DSP CPU. Submit Documentation Feedback Peripheral Information and Electrical Specifications 165

www.ti.com Table 6-71. Additional (1) SPI1 Master Timings, 4-Pin Enable Option (2) (3) 1.2V 1.1V 1.0V NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX Polarity Phase 3P+5 3P+5 3P+6 to SPI1_CLK rising Delay from slave Polarity Phase 0.5M+3P+5 0.5M+3P+5 0.5M+3P+6 assertion of SPI1_ENA to SPI1_CLK rising t d(EN A_SPC)M active to first ns Polarity Phase SPI1_CLK from 3P+5 3P+5 3P+6 to SPI1_CLK falling master. (4) Polarity Phase 0.5M+3P+5 0.5M+3P+5 0.5M+3P+6 to SPI1_CLK falling Polarity Phase 0.5M+P+5 0.5M+P+5 0.5M+P+6 from SPI1_CLK falling Max delay for slave to Polarity Phase deassert SPI1_ENA P+5 P+5 P+6 from SPI1_CLK falling after final SPI1_CLK t d(SPC_ENA)M ns edge to ensure master Polarity Phase 0.5M+P+5 0.5M+P+5 0.5M+P+6 does not begin the from SPI1_CLK rising next transfer. (5) Polarity Phase P+5 P+5 P+6 from SPI1_CLK rising (1) These parameters are in addition to the general timings for SPI master modes Table 6-69 (2) P SYSCLK2 period; M t c(SPC)M (SPI master bit clock period) (3) Figure shows only Polarity Phase as an example. Table gives parameters for all four master clocking modes. (4) In the case where the master SPI is ready with new data before SPI1_ENA assertion. (5) In the case where the master SPI is ready with new data before SPI1_ENA deassertion. Table 6-72. Additional (1) SPI1 Master Timings, 4-Pin Chip Select Option (2) (3) 1.2V 1.1V 1.0V NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX Polarity Phase 2P-1 2P-5 2P-6 to SPI1_CLK rising Polarity Phase Delay from 0.5M+2P-1 0.5M+2P-5 0.5M+2P-6 to SPI1_CLK rising SPI1_SCS active t d(SCS_SPC)M ns to first Polarity Phase 2P-1 2P-5 2P-6 SPI1_CLK (4) (5) to SPI1_CLK falling Polarity Phase 0.5M+2P-1 0.5M+2P-5 0.5M+2P-6 to SPI1_CLK falling Polarity Phase 0.5M+P-1 0.5M+P-5 0.5M+P-6 from SPI1_CLK falling Delay from final Polarity Phase P-1 P-5 P-6 SPI1_CLK edge to from SPI1_CLK falling t d(SPC_SCS)M master ns Polarity Phase deasserting 0.5M+P-1 0.5M+P-5 0.5M+P-6 from SPI1_CLK rising SPI1_SCS (6) (7) Polarity Phase P-1 P-5 P-6 from SPI1_CLK rising (1) These parameters are in addition to the general timings for SPI master modes Table 6-69 (2) P SYSCLK2 period; M t c(SPC)M (SPI master bit clock period) (3) Figure shows only Polarity Phase as an example. Table gives parameters for all four master clocking modes. (4) In the case where the master SPI is ready with new data before SPI1_SCS assertion. (5) This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0]. (6) Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI1_SCS will remain asserted. (7) This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0]. Peripheral Information and Electrical Specifications 166 Submit Documentation Feedback

www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 6-73. Additional (1) SPI1 Master Timings, 5-Pin Option (2) (3) 1.2V 1.1V 1.0V NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX Polarity Phase 0.5M+P+5 0.5M+P+5 0.5M+P+6 from SPI1_CLK falling Polarity Phase P+5 P+5 P+6 Max delay for slave to deassert SPI1_ENA after final from SPI1_CLK falling t d(SPC_ENA)M SPI1_CLK edge to ensure master does not begin the next ns Polarity Phase transfer. (4) 0.5M+P+5 0.5M+P+5 0.5M+P+6 from SPI1_CLK rising Polarity Phase P+5 P+5 P+6 from SPI1_CLK rising Polarity Phase 0.5M+P-1 0.5M+P-5 0.5M+P-6 from SPI1_CLK falling Polarity Phase P-1 P-5 P-6 from SPI1_CLK falling Delay from final SPI1_CLK edge to t d(SPC_SCS)M ns master deasserting SPI1_SCS (5) (6) Polarity Phase 0.5M+P-1 0.5M+P-5 0.5M+P-6 from SPI1_CLK rising Polarity Phase P-1 P-5 P-6 from SPI1_CLK rising Max delay for slave SPI to drive SPI1_ENA valid after master asserts SPI1_SCS to t d(SCSL_ENAL)M delay the C2TDELAY+P C2TDELAY+P C2TDELAY+P ns master from beginning the next transfer, Polarity Phase 2P-1 2P-5 2P-6 to SPI1_CLK rising Polarity Phase 0.5M+2P-1 0.5M+2P-5 0.5M+2P-6 to SPI1_CLK rising t d(SCS_SPC)M Delay from SPI1_SCS active to first SPI1_CLK (7) (8) (9) ns Polarity Phase 2P-1 2P-5 2P-6 to SPI1_CLK falling Polarity Phase 0.5M+2P-1 0.5M+2P-5 0.5M+2P-6 to SPI1_CLK falling (1) These parameters are in addition to the general timings for SPI master modes Table 6-70 (2) P SYSCLK2 period; M t c(SPC)M (SPI master bit clock period) (3) Figure shows only Polarity Phase as an example. Table gives parameters for all four master clocking modes. (4) In the case where the master SPI is ready with new data before SPI1_ENA deassertion. (5) Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI1_SCS will remain asserted. (6) This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0]. (7) If SPI1_ENA is asserted immediately such that the transmission is not delayed by SPI1_ENA (8) In the case where the master SPI is ready with new data before SPI1_SCS assertion. (9) This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0]. Submit Documentation Feedback Peripheral Information and Electrical Specifications 167

www.ti.com Table 6-73. Additional SPI1 Master Timings, 5-Pin Option (continued) 1.2V 1.1V 1.0V NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX Polarity Phase 3P+5 3P+5 3P+6 to SPI1_CLK rising Polarity Phase 0.5M+3P+5 0.5M+3P+5 0.5M+3P+6 to SPI1_CLK rising Delay from assertion of SPI1_ENA low to first SPI1_CLK t d(ENA_SPC)M ns edge. (10) Polarity Phase 3P+5 3P+5 3P+6 to SPI1_CLK falling Polarity Phase 0.5M+3P+5 0.5M+3P+5 0.5M+3P+6 to SPI1_CLK falling (10) If SPI1_ENA was initially deasserted high and SPI1_CLK is delayed. 168 Peripheral Information and Electrical Specifications Submit Documentation Feedback

www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 6-74. Additional (1) SPI1 Slave Timings, 4-Pin Enable Option (2) (3) 1.2V 1.1V 1.0V NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX Polarity Phase 1.5P-3 2.5P+15 1.5P-10 2.5P+17 1.5P-12 2.5P+19 from SPI1_CLK falling Polarity Phase 0.5M+1.5P-3 0.5M+2.5P+15 0.5M+1.5P-10 0.5M+2.5P+17 0.5M+1.5P-12 0.5M+2.5P+19 Delay from final from SPI1_CLK falling t d(SPC_ENAH)S SPI1_CLK edge to slave ns Polarity Phase deasserting SPI1_ENA 1.5P-3 2.5P+15 1.5P-10 2.5P+17 1.5P-12 2.5P+19 from SPI1_CLK rising Polarity Phase 0.5M+1.5P-3 0.5M+2.5P+15 0.5M+1.5P-10 0.5M+2.5P+17 0.5M+1.5P-12 0.5M+2.5P+19 from SPI1_CLK rising (1) These parameters are in addition to the general timings for SPI slave modes Table 6-70 (2) P SYSCLK2 period; M t c(SPC)M (SPI master bit clock period) (3) Figure shows only Polarity Phase as an example. Table gives parameters for all four slave clocking modes. Submit Documentation Feedback Peripheral Information and Electrical Specifications 169

www.ti.com Table 6-75. Additional (1) SPI1 Slave Timings, 4-Pin Chip Select Option (2) (3) 1.2V 1.1V 1.0V NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX t d(SCSL_SPC)S Required delay from SPI1_SCS asserted at slave to first SPI1_CLK edge at slave. P+1.5 P+1.5 P+1.5 ns Polarity Phase 0.5M+P+4 0.5M+P+5 0.5M+P+6 from SPI1_CLK falling Polarity Phase P+4 P+5 P+6 from SPI1_CLK falling Required delay from final SPI1_CLK edge before t d(SPC_SCSH)S ns SPI1_SCS is deasserted. Polarity Phase 0.5M+P+4 0.5M+P+5 0.5M+P+6 from SPI1_CLK rising Polarity Phase P+4 P+5 P+6 from SPI1_CLK rising t ena(SCSL_SOMI)S Delay from master asserting SPI1_SCS to slave driving SPI1_SOMI valid P+15 P+17 P+19 ns t dis(SCSH_SOMI)S Delay from master deasserting SPI1_SCS to slave 3-stating SPI1_SOMI P+15 P+17 P+19 ns (1) These parameters are in addition to the general timings for SPI slave modes Table 6-70 (2) P SYSCLK2 period; M t c(SPC)M (SPI master bit clock period) (3) Figure shows only Polarity Phase as an example. Table gives parameters for all four slave clocking modes. 170 Peripheral Information and Electrical Specifications Submit Documentation Feedback

www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 6-76. Additional (1) SPI1 Slave Timings, 5-Pin Option (2) (3) 1.2V 1.1V 1.0V NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX t d(SCSL_SPC)S Required delay from SPI1_SCS asserted at slave to first SPI1_CLK edge at slave. P+1.5 P+1.5 P+1.5 ns Polarity Phase 0.5M+P+4 0.5M+P+5 0.5M+P+6 from SPI1_CLK falling Polarity Phase P+4 P+5 P+6 from SPI1_CLK falling Required delay from final SPI1_CLK edge before t d(SPC_SCSH)S ns SPI1_SCS is deasserted. Polarity Phase 0.5M+P+4 0.5M+P+5 0.5M+P+6 from SPI1_CLK rising Polarity Phase P+4 P+5 P+6 from SPI1_CLK rising t ena(SCSL_SOMI)S Delay from master asserting SPI1_SCS to slave driving SPI1_SOMI valid P+15 P+17 P+19 ns t dis(SCSH_SOMI)S Delay from master deasserting SPI1_SCS to slave 3-stating SPI1_SOMI P+15 P+17 P+19 ns t ena(SCSL_ENA)S Delay from master deasserting SPI1_SCS to slave driving SPI1_ENA valid ns Polarity Phase 2.5P+15 2.5P+17 2.5P+19 from SPI1_CLK falling Polarity Phase 2.5P+15 2.5P+17 2.5P+19 from SPI1_CLK rising Delay from final clock receive edge on SPI1_CLK to slave t dis(SPC_ENA)S ns 3-stating or driving high SPI1_ENA (4) Polarity Phase 2.5P+15 2.5P+17 2.5P+19 from SPI1_CLK rising Polarity Phase 2.5P+15 2.5P+17 2.5P+19 from SPI1_CLK falling (1) These parameters are in addition to the general timings for SPI slave modes Table 6-70 (2) P SYSCLK2 period; M t c(SPC)M (SPI master bit clock period) (3) Figure shows only Polarity Phase as an example. Table gives parameters for all four slave clocking modes. (4) SPI1_ENA is driven low after the transmission completes if the SPIINT0.ENABLE_HIGHZ bit is programmed to Otherwise it is tri-stated. If tri-stated, an external pullup resistor should be used to provide a valid level to the master. This option is useful when tying several SPI slave devices to a single master. Submit Documentation Feedback Peripheral Information and Electrical Specifications 171

SPIx_CLK SPIx_SIMO SPIx_SOMI SPIx_CLK SPIx_SIMO SPIx_SOMI SPIx_CLK SPIx_SIMO SPIx_SOMI SPIx_CLK SPIx_SIMO SPIx_SOMI MO(0) MO(1) MO(n−1) MO(n) MI(0) MI(1) MI(n−1) MI(n) MO(0) MO(1) MO(n−1) MO(n) MI(0) MI(1) MI(n−1) MI(n) MO(0) MO(1) MO(n−1) MO(n) MI(0) MI(1) MI(n−1) MI(n) MO(0) MO(1) MO(n−1) MO(n) MI(0) MI(1) MI(n−1) MI(n) 4 5 5 6 MASTER MODE POLARITY = 0 PHASE = 0 MASTER MODE POLARITY = 0 PHASE = 1 MASTER MODE POLARITY = 1 PHASE = 0 MASTER MODE POLARITY = 1 PHASE = 1 OMAP-L138 Low-Power www.ti.com Figure 6-37. SPI Timings Master Mode 172 Peripheral Information and Electrical Specifications Submit Documentation Feedback

SPIx_CLK SPIx_SIMO SPIx_SOMI SPIx_CLK SPIx_SIMO SPIx_SOMI SPIx_CLK SPIx_SIMO SPIx_SOMI SPIx_CLK SPIx_SIMO SPIx_SOMI SI(0) SI(1) SI(n−1) SI(n) SO(0) SO(1) SO(n−1) SO(n) SI(0) SI(1) SI(n−1) SI(n) SO(0) SO(1) SO(n−1) SO(n) SI(0) SI(1) SI(n−1) SI(n) SO(0) SO(1) SO(n−1) SO(n) SI(0) SI(1) SI(n−1) SI(n) SO(0) SO(1) SO(n−1) SO(n) 1110 SLA VE MODE POLARITY = 0 PHASE = 0 SLA VE MODE POLARITY = 0 PHASE = 1 SLA VE MODE POLARITY = 1 PHASE = 0 SLA VE MODE POLARITY = 1 PHASE = 1 OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Figure 6-38. SPI Timings Slave Mode Submit Documentation Feedback Peripheral Information and Electrical Specifications 173

MASTER MODE 4 PIN WITH CHIP SELECT SPIx_CLK SPIx_SIMO SPIx_SOMI SPIx_ENA SPIx_CLK SPIx_SIMO SPIx_SOMI SPIx_SCS SPIx_CLK SPIx_SIMO SPIx_SOMI SPIx_ENA SPIx_SCS MO(0) MO(1) MO(n−1) MO(n) MI(0) MI(1) MI(n−1) MI(n) MO(0) MO(1) MO(n−1) MO(n) MI(0) MI(1) MI(n−1) MI(n) MO(0) MO(1) MO(n−1) MO(n) MI(0) MI(1) MI(n−1) MI(n) MASTER MODE 4 PIN WITH ENABLE MASTER MODE 5 PIN A. DESELECTED IS PROGRAMMABLE EITHER HIGH OR 3−STATE (REQUIRES EXTERNAL PULLUP) DESEL (A) DESEL (A) OMAP-L138 Low-Power www.ti.com Figure 6-39. SPI Timings Master Mode (4-Pin and 5-Pin) 174 Peripheral Information and Electrical Specifications Submit Documentation Feedback

SPIx_CLK SPIx_SOMI SPIx_SIMO SPIx_ENA SPIx_CLK SPIx_SOMI SPIx_SIMO SPIx_SCS SPIx_CLK SPIx_SOMI SPIx_SIMO SPIx_ENA SPIx_SCS SO(0) SO(1) SO(n−1) SO(n) SI(0) SI(1) SI(n−1) SI(n) SO(0) SO(1) SO(n−1) SO(n) SI(0) SI(1) SI(n−1) SI(n) SO(0) SO(1) SO(n−1) SO(n) SI(0) SI(1) SI(n−1) SI(n) SLA VE MODE 4 PIN WITH ENABLE SLA VE MODE 4 PIN WITH CHIP SELECT SLA VE MODE 5 PIN DESEL (A) DESEL (A) A. DESELECTED IS PROGRAMMABLE EITHER HIGH OR 3−STATE (REQUIRES EXTERNAL PULLUP) OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Figure 6-40. SPI Timings Slave Mode (4-Pin and 5-Pin) Submit Documentation Feedback Peripheral Information and Electrical Specifications 175

6.17 Inter-Integrated Circuit Serial Ports (I2C) 6.17.1 I2C Device-Specific Information Peripheral Configuration Bus Noise Filter Noise Filter Clock Prescaler I2CPSCx Prescaler Register Bit Clock Generator I2CCLKHx Clock Divide High Register I2CCLKLx Clock Divide Low Register Control I2CCOARx Own Address Register I2CSARx Slave Address Register I2CCMDRx Mode Register I2CEMDRx Extended Mode Register I2CCNTx Data Count Register I2CPID1 Peripheral ID Register 1 I2CPID2 Peripheral ID Register 2 Transmit I2CXSRx Transmit Shift Register I2CDXRx T ransmit Buffer Receive I2CDRRx Receive Buffer I2CRSRx Receive Shift Register I2Cx_SCL I2Cx_SDA Control Interrupt/DMA I2CIERx Interrupt Enable Register I2CSTRx Interrupt Status Register I2CSRCx Interrupt Source Register Control I2CPFUNC Pin Function Register I2CPDIR Pin Direction Register I2CPDIN Pin Data In Register I2CPDOUT Pin Data Out Register I2CPDSET Pin Data Set Register I2CPDCLR Pin Data Clear Register Interrupt DMA Requests OMAP-L138 Low-Power www.ti.com Each I2C port supports: Compatible with Philips I2C Specification Revision 2.1 (January 2000) Fast Mode up to 400 Kbps (no fail-safe I/O buffers) Noise Filter to Remove Noise ns or less Seven- and Ten-Bit Device Addressing Modes Master (Transmit/Receive) and Slave (Transmit/Receive) Functionality Events: DMA, Interrupt, or Polling General-Purpose I/O Capability if not used as I2C Figure 6-41 is block diagram of the device I2C Module. Figure 6-41. I2C Module Block Diagram 176 Peripheral Information and Electrical Specifications Submit Documentation Feedback

6.17.2 I2C Peripheral Registers Description(s) OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 6-77 is the list of the I2C registers. Table 6-77. Inter-Integrated Circuit (I2C) Registers I2C0 I2C1 ACRONYM REGISTER

6.17.3 I2C Electrical Data/Timing 6.17.3.1 Inter-Integrated Circuit (I2C) Timing OMAP-L138 Low-Power www.ti.com Table 6-78 and Table 6-79 assume testing over recommended operating conditions (see Figure 6-42 and Figure 6-43 Table 6-78. Timing Requirements for I2C Input 1.2V, 1.1V, 1.0V NO. PARAMETER Standard Mode Fast Mode UNIT MIN MAX MIN MAX t c(SCL) Cycle time, I2Cx_SCL 2.5 µ s t su(SCLH-SDAL) Setup time, I2Cx_SCL high before I2Cx_SDA low 4.7 0.6 µ s t h(SCLL-SDAL) Hold time, I2Cx_SCL low after I2Cx_SDA low 0.6 µ s t w(SCLL) Pulse duration, I2Cx_SCL low 4.7 1.3 µ s t w(SCLH) Pulse duration, I2Cx_SCL high 0.6 µ s t su(SDA-SCLH) Setup time, I2Cx_SDA before I2Cx_SCL high 250 100 ns t h(SDA-SCLL) Hold time, I2Cx_SDA after I2Cx_SCL low 0.9 µ s t w(SDAH) Pulse duration, I2Cx_SDA high 4.7 1.3 µ s t r(SDA) Rise time, I2Cx_SDA 1000 0.1C b 300 ns t r(SCL) Rise time, I2Cx_SCL 1000 0.1C b 300 ns t f(SDA) Fall time, I2Cx_SDA 300 0.1C b 300 ns t f(SCL) Fall time, I2Cx_SCL 300 0.1C b 300 ns t su(SCLH-SDAH) Setup time, I2Cx_SCL high before I2Cx_SDA high 0.6 µ s t w(SP) Pulse duration, spike (must be suppressed) N/A ns C b Capacitive load for each bus line 400 400 pF Table 6-79. Switching Characteristics for I2C (1) 1.2V, 1.1V, 1.0V NO. PARAMETER Standard Mode Fast Mode UNIT MIN MAX MIN MAX t c(SCL) Cycle time, I2Cx_SCL 2.5 µ s t su(SCLH-SDAL) Setup time, I2Cx_SCL high before I2Cx_SDA low 4.7 0.6 µ s t h(SDAL-SCLL) Hold time, I2Cx_SCL low after I2Cx_SDA low 0.6 µ s t w(SCLL) Pulse duration, I2Cx_SCL low 4.7 1.3 µ s t w(SCLH) Pulse duration, I2Cx_SCL high 0.6 µ s t su(SDAV-SCLH) Setup time, I2Cx_SDA valid before I2Cx_SCL high 250 100 ns t h(SCLL-SDAV) Hold time, I2Cx_SDA valid after I2Cx_SCL low 0.9 µ s t w(SDAH) Pulse duration, I2Cx_SDA high 4.7 1.3 µ s t su(SCLH-SDAH) Setup time, I2Cx_SCL high before I2Cx_SDA high 0.6 µ s (1) I2C must be configured correctly to meet the timings in Table 6-79 Peripheral Information and Electrical Specifications 178 Submit Documentation Feedback

I2Cx_SDA I2Cx_SCL 11 9 Stop Start Repeated Start Stop I2Cx_SDA I2Cx_SCL 26 24 OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Figure 6-42. I2C Receive Timings Figure 6-43. I2C Transmit Timings Submit Documentation Feedback Peripheral Information and Electrical Specifications 179

6.18 Universal Asynchronous Receiver/Transmitter (UART) 6.18.1 UART Peripheral Registers Description(s) OMAP-L138 Low-Power www.ti.com Each UART has the following features: 16-byte storage space for both the transmitter and receiver FIFOs or byte selectable receiver FIFO trigger level for autoflow control and DMA DMA signaling capability for both received and transmitted data Programmable auto-rts and auto-cts for autoflow control Programmable Baud Rate up to 3MBaud Programmable Oversampling Options of x13 and x16 Frequency pre-scale values from to 65,535 to generate appropriate baud rates Prioritized interrupts Programmable serial data formats or 8-bit characters Even, odd, or no parity bit generation and detection 1.5, or stop bit generation False start bit detection Line break generation and detection Internal diagnostic capabilities Loopback controls for communications link fault isolation Break, parity, overrun, and framing error simulation Modem control functions (CTS, RTS) The UART registers are listed in Section 6.18.1 Table 6-80 is the list of UART registers. Table 6-80. UART Registers UART0 UART1 UART2 ACRONYM REGISTER (read only) 0x01C4 2000 0x01D0 C000 0x01D0 D000 THR Transmitter Holding Register (write only) 0x01C4 2004 0x01D0 C004 0x01D0 D004 IER Interrupt Enable Register 0x01C4 2008 0x01D0 C008 0x01D0 D008 IIR Interrupt Identification Register (read only) 0x01C4 2008 0x01D0 C008 0x01D0 D008 FCR FIFO Control Register (write only) 0x01C4 200C 0x01D0 C00C 0x01D0 D00C LCR Line Control Register 0x01C4 2010 0x01D0 C010 0x01D0 D010 MCR Modem Control Register 0x01C4 2014 0x01D0 C014 0x01D0 D014 LSR Line Status Register 0x01C4 2018 0x01D0 C018 0x01D0 D018 MSR Modem Status Register 0x01C4 201C 0x01D0 C01C 0x01D0 D01C SCR Scratchpad Register 0x01C4 2020 0x01D0 C020 0x01D0 D020 DLL Divisor LSB Latch 0x01C4 2024 0x01D0 C024 0x01D0 D024 DLH Divisor MSB Latch 0x01C4 2028 0x01D0 C028 0x01D0 D028 REVID1 Revision Identification Register 0x01C4 2030 0x01D0 C030 0x01D0 D030 PWREMU_MGMT Power and Emulation Management Register 0x01C4 2034 0x01D0 C034 0x01D0 D034 MDR Mode Definition Register Peripheral Information and Electrical Specifications 180 Submit Documentation Feedback

6.18.2 UART Electrical Data/Timing Start Bit Data Bits UART_TXDn UART_RXDn Data Bits Bit Start OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 6-81. Timing Requirements for UART Receive (1) (see Figure 6-44 1.2V, 1.1V, 1.0V NO. PARAMETER UNIT MIN MAX t w(URXDB) Pulse duration, receive data bit (RXDn) 0.96U 1.05U ns t w(URXSB) Pulse duration, receive start bit 0.96U 1.05U ns (1) U UART baud time 1/programmed baud rate. Table 6-82. Switching Characteristics Over Recommended Operating Conditions for UARTx Transmit (1) (see Figure 6-44 1.2V, 1.1V, 1.0V NO. PARAMETER UNIT MIN MAX f (baud) Maximum programmable baud rate MBaud t w(UTXDB) Pulse duration, transmit data bit (TXDn) U U ns t w(UTXSB) Pulse duration, transmit start bit U U ns (1) U UART baud time 1/programmed baud rate. Figure 6-44. UART Transmit/Receive Timing Submit Documentation Feedback Peripheral Information and Electrical Specifications 181

6.19 Universal Serial Bus OTG Controller (USB0) [USB2.0 OTG] OMAP-L138 Low-Power www.ti.com The USB2.0 peripheral supports the following features: USB 2.0 peripheral at speeds high speed (HS: 480 Mb/s C6747 only) and full speed (FS: Mb/s) USB 2.0 host at speeds HS, FS, and low speed (LS: 1.5 Mb/s) All transfer modes (control, bulk, interrupt, and isochronous) Transmit (TX) and Receive (RX) endpoints in addition to endpoint FIFO RAM endpoint Programmable size Integrated USB 2.0 High Speed PHY Connects to a standard Charge Pump for VBUS V generation RNDIS mode for accelerating RNDIS type protocols using short packet termination over USB Table 6-83 is the list of USB OTG registers. Table 6-83. Universal Serial Bus OTG (USB0) Registers BYTE ADDRESS ACRONYM REGISTER 2.0 Test Modes Peripheral Information and Electrical Specifications 182 Submit Documentation Feedback

www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 6-83. Universal Serial Bus OTG (USB0) Registers (continued) BYTE ADDRESS ACRONYM REGISTER (Index register set to select Endpoints 1-4 only) 0x01E0 0412 PERI_CSR0 Control Status Register for Endpoint in Peripheral Mode. (Index register set to select Endpoint HOST_CSR0 Control Status Register for Endpoint in Host Mode. (Index register set to select Endpoint PERI_TXCSR Control Status Register for Peripheral Transmit Endpoint. (Index register set to select Endpoints 1-4) HOST_TXCSR Control Status Register for Host Transmit Endpoint. (Index register set to select Endpoints 1-4) 0x01E0 0414 RXMAXP Maximum Packet Size for Peripheral/Host Receive Endpoint (Index register set to select Endpoints 1-4 only) 0x01E0 0416 PERI_RXCSR Control Status Register for Peripheral Receive Endpoint. (Index register set to select Endpoints 1-4) HOST_RXCSR Control Status Register for Host Receive Endpoint. (Index register set to select Endpoints 1-4) 0x01E0 0418 COUNT0 Number of Received Bytes in Endpoint FIFO. (Index register set to select Endpoint RXCOUNT Number of Bytes in Host Receive Endpoint FIFO. (Index register set to select Endpoints 0x01E0 041A HOST_TYPE0 Defines the speed of Endpoint HOST_TXTYPE Sets the operating speed, transaction protocol and peripheral endpoint number for the host Transmit endpoint. (Index register set to select Endpoints 1-4 only) 0x01E0 041B HOST_NAKLIMIT0 Sets the NAK response timeout on Endpoint (Index register set to select Endpoint HOST_TXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host Transmit endpoint. (Index register set to select Endpoints 1-4 only) 0x01E0 041C HOST_RXTYPE Sets the operating speed, transaction protocol and peripheral endpoint number for the host Receive endpoint. (Index register set to select Endpoints 1-4 only) 0x01E0 041D HOST_RXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host Receive endpoint. (Index register set to select Endpoints 1-4 only) 0x01E0 041F CONFIGDATA Returns details of core configuration. (Index register set to select Endpoint FIFO 0x01E0 0420 FIFO0 Transmit and Receive FIFO Register for Endpoint 0x01E0 0424 FIFO1 Transmit and Receive FIFO Register for Endpoint 0x01E0 0428 FIFO2 Transmit and Receive FIFO Register for Endpoint 0x01E0 042C FIFO3 Transmit and Receive FIFO Register for Endpoint 0x01E0 0430 FIFO4 Transmit and Receive FIFO Register for Endpoint OTG Device Control 0x01E0 0460 DEVCTL Device Control Register Dynamic FIFO Control 0x01E0 0462 TXFIFOSZ Transmit Endpoint FIFO Size (Index register set to select Endpoints 1-4 only) 0x01E0 0463 RXFIFOSZ Receive Endpoint FIFO Size (Index register set to select Endpoints 1-4 only) 0x01E0 0464 TXFIFOADDR Transmit Endpoint FIFO Address (Index register set to select Endpoints 1-4 only) 0x01E0 0464 HWVERS Hardware Version Register 0x01E0 0466 RXFIFOADDR Receive Endpoint FIFO Address (Index register set to select Endpoints 1-4 only) Target Endpoint Control Registers, Valid Only in Host Mode Submit Documentation Feedback Peripheral Information and Electrical Specifications 183

www.ti.com Table 6-83. Universal Serial Bus OTG (USB0) Registers (continued) BYTE ADDRESS ACRONYM REGISTER Endpoint. 0x01E0 0482 TXHUBADDR Address of the hub that has to be accessed through the associated Transmit Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub. 0x01E0 0483 TXHUBPORT Port of the hub that has to be accessed through the associated Transmit Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub. 0x01E0 0484 RXFUNCADDR Address of the target function that has to be accessed through the associated Receive Endpoint. 0x01E0 0486 RXHUBADDR Address of the hub that has to be accessed through the associated Receive Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub. 0x01E0 0487 RXHUBPORT Port of the hub that has to be accessed through the associated Receive Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub. Target Endpoint Control Registers, Valid Only in Host Mode 0x01E0 0488 TXFUNCADDR Address of the target function that has to be accessed through the associated Transmit Endpoint. 0x01E0 048A TXHUBADDR Address of the hub that has to be accessed through the associated Transmit Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub. 0x01E0 048B TXHUBPORT Port of the hub that has to be accessed through the associated Transmit Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub. 0x01E0 048C RXFUNCADDR Address of the target function that has to be accessed through the associated Receive Endpoint. 0x01E0 048E RXHUBADDR Address of the hub that has to be accessed through the associated Receive Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub. 0x01E0 048F RXHUBPORT Port of the hub that has to be accessed through the associated Receive Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub. Target Endpoint Control Registers, Valid Only in Host Mode 0x01E0 0490 TXFUNCADDR Address of the target function that has to be accessed through the associated Transmit Endpoint. 0x01E0 0492 TXHUBADDR Address of the hub that has to be accessed through the associated Transmit Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub. 0x01E0 0493 TXHUBPORT Port of the hub that has to be accessed through the associated Transmit Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub. 0x01E0 0494 RXFUNCADDR Address of the target function that has to be accessed through the associated Receive Endpoint. 0x01E0 0496 RXHUBADDR Address of the hub that has to be accessed through the associated Receive Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub. 0x01E0 0497 RXHUBPORT Port of the hub that has to be accessed through the associated Receive Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub. Target Endpoint Control Registers, Valid Only in Host Mode 0x01E0 0498 TXFUNCADDR Address of the target function that has to be accessed through the associated Transmit Endpoint. 0x01E0 049A TXHUBADDR Address of the hub that has to be accessed through the associated Transmit Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub. 0x01E0 049B TXHUBPORT Port of the hub that has to be accessed through the associated Transmit Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub. 0x01E0 049C RXFUNCADDR Address of the target function that has to be accessed through the associated Receive Endpoint. 0x01E0 049E RXHUBADDR Address of the hub that has to be accessed through the associated Receive Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub. 0x01E0 049F RXHUBPORT Port of the hub that has to be accessed through the associated Receive Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub. Target Endpoint Control Registers, Valid Only in Host Mode 0x01E0 04A0 TXFUNCADDR Address of the target function that has to be accessed through the associated Transmit Endpoint. Peripheral Information and Electrical Specifications 184 Submit Documentation Feedback

www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 6-83. Universal Serial Bus OTG (USB0) Registers (continued) BYTE ADDRESS ACRONYM REGISTER Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub. 0x01E0 04A3 TXHUBPORT Port of the hub that has to be accessed through the associated Transmit Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub. 0x01E0 04A4 RXFUNCADDR Address of the target function that has to be accessed through the associated Receive Endpoint. 0x01E0 04A6 RXHUBADDR Address of the hub that has to be accessed through the associated Receive Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub. 0x01E0 04A7 RXHUBPORT Port of the hub that has to be accessed through the associated Receive Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub. Control and Status Register for Endpoint 0x01E0 0502 PERI_CSR0 Control Status Register for Endpoint in Peripheral Mode HOST_CSR0 Control Status Register for Endpoint in Host Mode 0x01E0 0508 COUNT0 Number of Received Bytes in Endpoint FIFO 0x01E0 050A HOST_TYPE0 Defines the Speed of Endpoint 0x01E0 050B HOST_NAKLIMIT0 Sets the NAK Response Timeout on Endpoint 0x01E0 050F CONFIGDATA Returns details of core configuration. Control and Status Register for Endpoint 0x01E0 0510 TXMAXP Maximum Packet Size for Peripheral/Host Transmit Endpoint 0x01E0 0512 PERI_TXCSR Control Status Register for Peripheral Transmit Endpoint (peripheral mode) HOST_TXCSR Control Status Register for Host Transmit Endpoint (host mode) 0x01E0 0514 RXMAXP Maximum Packet Size for Peripheral/Host Receive Endpoint 0x01E0 0516 PERI_RXCSR Control Status Register for Peripheral Receive Endpoint (peripheral mode) HOST_RXCSR Control Status Register for Host Receive Endpoint (host mode) 0x01E0 0518 RXCOUNT Number of Bytes in Host Receive endpoint FIFO 0x01E0 051A HOST_TXTYPE Sets the operating speed, transaction protocol and peripheral endpoint number for the host Transmit endpoint. 0x01E0 051B HOST_TXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host Transmit endpoint. 0x01E0 051C HOST_RXTYPE Sets the operating speed, transaction protocol and peripheral endpoint number for the host Receive endpoint. 0x01E0 051D HOST_RXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host Receive endpoint. Control and Status Register for Endpoint 0x01E0 0520 TXMAXP Maximum Packet Size for Peripheral/Host Transmit Endpoint 0x01E0 0522 PERI_TXCSR Control Status Register for Peripheral Transmit Endpoint (peripheral mode) HOST_TXCSR Control Status Register for Host Transmit Endpoint (host mode) 0x01E0 0524 RXMAXP Maximum Packet Size for Peripheral/Host Receive Endpoint 0x01E0 0526 PERI_RXCSR Control Status Register for Peripheral Receive Endpoint (peripheral mode) HOST_RXCSR Control Status Register for Host Receive Endpoint (host mode) 0x01E0 0528 RXCOUNT Number of Bytes in Host Receive endpoint FIFO 0x01E0 052A HOST_TXTYPE Sets the operating speed, transaction protocol and peripheral endpoint number for the host Transmit endpoint. 0x01E0 052B HOST_TXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host Transmit endpoint. 0x01E0 052C HOST_RXTYPE Sets the operating speed, transaction protocol and peripheral endpoint number for the host Receive endpoint. Submit Documentation Feedback Peripheral Information and Electrical Specifications 185

www.ti.com Table 6-83. Universal Serial Bus OTG (USB0) Registers (continued) BYTE ADDRESS ACRONYM REGISTER HOST_RXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host Receive endpoint. Control and Status Register for Endpoint 0x01E0 0530 TXMAXP Maximum Packet Size for Peripheral/Host Transmit Endpoint 0x01E0 0532 PERI_TXCSR Control Status Register for Peripheral Transmit Endpoint (peripheral mode) HOST_TXCSR Control Status Register for Host Transmit Endpoint (host mode) 0x01E0 0534 RXMAXP Maximum Packet Size for Peripheral/Host Receive Endpoint 0x01E0 0536 PERI_RXCSR Control Status Register for Peripheral Receive Endpoint (peripheral mode) HOST_RXCSR Control Status Register for Host Receive Endpoint (host mode) 0x01E0 0538 RXCOUNT Number of Bytes in Host Receive endpoint FIFO 0x01E0 053A HOST_TXTYPE Sets the operating speed, transaction protocol and peripheral endpoint number for the host Transmit endpoint. 0x01E0 053B HOST_TXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host Transmit endpoint. 0x01E0 053C HOST_RXTYPE Sets the operating speed, transaction protocol and peripheral endpoint number for the host Receive endpoint. 0x01E0 053D HOST_RXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host Receive endpoint. Control and Status Register for Endpoint 0x01E0 0540 TXMAXP Maximum Packet Size for Peripheral/Host Transmit Endpoint 0x01E0 0542 PERI_TXCSR Control Status Register for Peripheral Transmit Endpoint (peripheral mode) HOST_TXCSR Control Status Register for Host Transmit Endpoint (host mode) 0x01E0 0544 RXMAXP Maximum Packet Size for Peripheral/Host Receive Endpoint 0x01E0 0546 PERI_RXCSR Control Status Register for Peripheral Receive Endpoint (peripheral mode) HOST_RXCSR Control Status Register for Host Receive Endpoint (host mode) 0x01E0 0548 RXCOUNT Number of Bytes in Host Receive endpoint FIFO 0x01E0 054A HOST_TXTYPE Sets the operating speed, transaction protocol and peripheral endpoint number for the host Transmit endpoint. 0x01E0 054B HOST_TXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host Transmit endpoint. 0x01E0 054C HOST_RXTYPE Sets the operating speed, transaction protocol and peripheral endpoint number for the host Receive endpoint. 0x01E0 054D HOST_RXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host Receive endpoint. DMA Registers 0x01E0 1000 DMAREVID DMA Revision Register 0x01E0 1004 TDFDQ DMA Teardown Free Descriptor Queue Control Register 0x01E0 1008 DMAEMU DMA Emulation Control Register 0x01E0 1800 TXGCR[0] Transmit Channel Global Configuration Register 0x01E0 1808 RXGCR[0] Receive Channel Global Configuration Register 0x01E0 180C RXHPCRA[0] Receive Channel Host Packet Configuration Register A 0x01E0 1810 RXHPCRB[0] Receive Channel Host Packet Configuration Register B 0x01E0 1820 TXGCR[1] Transmit Channel Global Configuration Register 0x01E0 1828 RXGCR[1] Receive Channel Global Configuration Register 0x01E0 182C RXHPCRA[1] Receive Channel Host Packet Configuration Register A 0x01E0 1830 RXHPCRB[1] Receive Channel Host Packet Configuration Register B 0x01E0 1840 TXGCR[2] Transmit Channel Global Configuration Register Peripheral Information and Electrical Specifications 186 Submit Documentation Feedback

www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 6-83. Universal Serial Bus OTG (USB0) Registers (continued) BYTE ADDRESS ACRONYM REGISTER RXGCR[2] Receive Channel Global Configuration Register 0x01E0 184C RXHPCRA[2] Receive Channel Host Packet Configuration Register A 0x01E0 1850 RXHPCRB[2] Receive Channel Host Packet Configuration Register B 0x01E0 1860 TXGCR[3] Transmit Channel Global Configuration Register 0x01E0 1868 RXGCR[3] Receive Channel Global Configuration Register 0x01E0 186C RXHPCRA[3] Receive Channel Host Packet Configuration Register A 0x01E0 1870 RXHPCRB[3] Receive Channel Host Packet Configuration Register B 0x01E0 2C00 DMA_SCHED_CTRL DMA Scheduler Control Register 0x01E0 2D00 ENTRY[0] DMA Scheduler Table Word 0x01E0 2D04 ENTRY[1] DMA Scheduler Table Word 0x01E0 2DFC ENTRY[63] DMA Scheduler Table Word Queue Manager Registers 0x01E0 4000 QMGRREVID Queue Manager Revision Register 0x01E0 4008 DIVERSION Queue Diversion Register 0x01E0 4020 FDBSC0 Free Descriptor/Buffer Starvation Count Register 0x01E0 4024 FDBSC1 Free Descriptor/Buffer Starvation Count Register 0x01E0 4028 FDBSC2 Free Descriptor/Buffer Starvation Count Register 0x01E0 402C FDBSC3 Free Descriptor/Buffer Starvation Count Register 0x01E0 4080 LRAM0BASE Linking RAM Region Base Address Register 0x01E0 4084 LRAM0SIZE Linking RAM Region Size Register 0x01E0 4088 LRAM1BASE Linking RAM Region Base Address Register 0x01E0 4090 PEND0 Queue Pending Register 0x01E0 4094 PEND1 Queue Pending Register 0x01E0 5000 QMEMRBASE[0] Memory Region Base Address Register 0x01E0 5004 QMEMRCTRL[0] Memory Region Control Register 0x01E0 5010 QMEMRBASE[1] Memory Region Base Address Register 0x01E0 5014 QMEMRCTRL[1] Memory Region Control Register 0x01E0 5070 QMEMRBASE[7] Memory Region Base Address Register 0x01E0 5074 QMEMRCTRL[7] Memory Region Control Register 0x01E0 600C CTRLD[0] Queue Manager Queue Control Register D 0x01E0 601C CTRLD[1] Queue Manager Queue Control Register D 0x01E0 63FC CTRLD[63] Queue Manager Queue Status Register D 0x01E0 6800 QSTATA[0] Queue Manager Queue Status Register A 0x01E0 6804 QSTATB[0] Queue Manager Queue Status Register B 0x01E0 6808 QSTATC[0] Queue Manager Queue Status Register C 0x01E0 6810 QSTATA[1] Queue Manager Queue Status Register A 0x01E0 6814 QSTATB[1] Queue Manager Queue Status Register B 0x01E0 6818 QSTATC[1] Queue Manager Queue Status Register C 0x01E0 6BF0 QSTATA[63] Queue Manager Queue Status Register A 0x01E0 6BF4 QSTATB[63] Queue Manager Queue Status Register B 0x01E0 6BF8 QSTATC[63] Queue Manager Queue Status Register C Submit Documentation Feedback Peripheral Information and Electrical Specifications 187

6.19.1 USB0 [USB2.0] Electrical Data/Timing tr tf VCRS 90% VOH 10% VOL USB_DM USB_DP tper − tjr OMAP-L138 Low-Power www.ti.com Table 6-84. Switching Characteristics Over Recommended Operating Conditions for USB0 [USB2.0] (see Figure 6-45 1.2V, 1.1V, 1.0V LOW SPEED FULL SPEED HIGH SPEED NO. PARAMETER UNIT 1.5 Mbps Mbps 480 Mbps MIN MAX MIN MAX MIN MAX t r(D) Rise time, USB_DP and USB_DM signals (1) 300 0.5 ns t f(D) Fall time, USB_DP and USB_DM signals (1) 300 0.5 ns t rfM Rise/Fall time, matching (2) 120 111 V CRS Output signal cross-over voltage (1) 1.3 1.3 V t jr(source)NT Source (Host) Driver jitter, next transition (3) ns t jr(FUNC)NT Function Driver jitter, next transition (3) ns t jr(source)PT Source (Host) Driver jitter, paired transition (4) (3) ns t jr(FUNC)PT Function Driver jitter, paired transition (3) ns t w(EOPT) Pulse duration, EOP transmitter 1250 1500 160 175 ns t w(EOPR) Pulse duration, EOP receiver 670 ns t (DRATE) Data Rate 1.5 480 Mb/s Z DRV Driver Output Resistance 40.5 49.5 40.5 49.5 Ω Z INP Receiver Input Impedance 100k 100k Ω (1) Low Speed: C L 200 pF, Full Speed: C L pF, High Speed: C L pF (2) t RFM r f x 100. [Excluding the first transaction from the Idle state.] (3) For more detailed information, see the Universal Serial Bus Specification Revision 2.0, Chapter Electrical. (4) t jr t px(1) t px(0) Figure 6-45. USB2.0 Integrated Transceiver Interface Timing 188 Peripheral Information and Electrical Specifications Submit Documentation Feedback

6.20 Universal Serial Bus Host Controller (USB1) [USB1.1 OHCI] OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 All the USB interfaces for this device are compliant with Universal Serial Bus Specifications, Revision 1.1. Table 6-85 is the list of USB Host Controller registers. Table 6-85. USB Host Controller Registers USB1 ACRONYM REGISTER (1) 0x01E2 501C HCPERIODCURRENTED HC Current Periodic Register (1) 0x01E2 5020 HCCONTROLHEADED HC Head Control Register (1) 0x01E2 5024 HCCONTROLCURRENTED HC Current Control Register (1) 0x01E2 5028 HCBULKHEADED HC Head Bulk Register (1) 0x01E2 502C HCBULKCURRENTED HC Current Bulk Register (1) 0x01E2 5030 HCDONEHEAD HC Head Done Register (1) 0x01E2 5034 HCFMINTERVAL HC Frame Interval Register 0x01E2 5038 HCFMREMAINING HC Frame Remaining Register 0x01E2 503C HCFMNUMBER HC Frame Number Register 0x01E2 5040 HCPERIODICSTART HC Periodic Start Register 0x01E2 5044 HCLSTHRESHOLD HC Low-Speed Threshold Register 0x01E2 5048 HCRHDESCRIPTORA HC Root Hub A Register 0x01E2 504C HCRHDESCRIPTORB HC Root Hub B Register 0x01E2 5050 HCRHSTATUS HC Root Hub Status Register 0x01E2 5054 HCRHPORTSTATUS1 HC Port Status and Control Register (2) 0x01E2 5058 HCRHPORTSTATUS2 HC Port Status and Control Register (3) (1) Restrictions apply to the physical addresses used in these registers. (2) Connected to the integrated USB1.1 phy pins (USB1_DM, USB1_DP). (3) Although the controller implements two ports, the second port cannot be used. Table 6-86. Switching Characteristics Over Recommended Operating Conditions for USB1 [USB1.1] 1.2V, 1.1V, 1.0V NO. PARAMETER LOW SPEED FULL SPEED UNIT MIN MAX MAX MAX t r Rise time, USB.DP and USB.DM signals (1) (1) 300 (1) (1) (1) ns t f Fall time, USB.DP and USB.DM signals (1) (1) 300 (1) (1) (1) ns t RFM Rise/Fall time matching (2) (2) 120 (2) (2) 110 (2) V CRS Output signal cross-over voltage (1) 1.3 (1) (1) 1.3 (1) (1) V t j Differential propagation jitter (3) -25 (3) (3) (3) (3) ns f op Operating frequency (4) 1.5 MHz (1) Low Speed: C L 200 pF. High Speed: C L 50pF (2) t RFM t r f x 100 (3) t jr t px(1) t px(0) (4) f op 1/t per Submit Documentation Feedback Peripheral Information and Electrical Specifications 189

6.21 Ethernet Media Access Controller (EMAC) 6.21.1 EMAC Peripheral Register Description(s) OMAP-L138 Low-Power www.ti.com The Ethernet Media Access Controller (EMAC) provides an efficient interface between device and the network. The EMAC supports both 10Base-T and 100Base-TX, or Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS) support. The EMAC controls the flow of packet data from the device to the PHY. The MDIO module controls PHY configuration and status monitoring. Both the EMAC and the MDIO modules interface to the device through a custom interface that allows efficient data transmission and reception. This custom interface is referred to as the EMAC control module, and is considered integral to the EMAC/MDIO peripheral. The control module is also used to multiplex and control interrupts. Table 6-87. Ethernet Media Access Controller (EMAC) Registers BYTE ADDRESS ACRONYM REGISTER (Unmasked) Register 0x01E2 3084 TXINTSTATMASKED Transmit Interrupt Status (Masked) Register 0x01E2 3088 TXINTMASKSET Transmit Interrupt Mask Set Register 0x01E2 308C TXINTMASKCLEAR Transmit Interrupt Clear Register 0x01E2 3090 MACINVECTOR MAC Input Vector Register 0x01E2 3094 MACEOIVECTOR MAC End Of Interrupt Vector Register 0x01E2 30A0 RXINTSTATRAW Receive Interrupt Status (Unmasked) Register 0x01E2 30A4 RXINTSTATMASKED Receive Interrupt Status (Masked) Register 0x01E2 30A8 RXINTMASKSET Receive Interrupt Mask Set Register 0x01E2 30AC RXINTMASKCLEAR Receive Interrupt Mask Clear Register 0x01E2 30B0 MACINTSTATRAW MAC Interrupt Status (Unmasked) Register 0x01E2 30B4 MACINTSTATMASKED MAC Interrupt Status (Masked) Register 0x01E2 30B8 MACINTMASKSET MAC Interrupt Mask Set Register 0x01E2 30BC MACINTMASKCLEAR MAC Interrupt Mask Clear Register 0x01E2 3100 RXMBPENABLE Receive Multicast/Broadcast/Promiscuous Channel Enable Register 0x01E2 3104 RXUNICASTSET Receive Unicast Enable Set Register 0x01E2 3108 RXUNICASTCLEAR Receive Unicast Clear Register 0x01E2 310C RXMAXLEN Receive Maximum Length Register 0x01E2 3110 RXBUFFEROFFSET Receive Buffer Offset Register 0x01E2 3114 RXFILTERLOWTHRESH Receive Filter Low Priority Frame Threshold Register 0x01E2 3120 RX0FLOWTHRESH Receive Channel Flow Control Threshold Register 0x01E2 3124 RX1FLOWTHRESH Receive Channel Flow Control Threshold Register 0x01E2 3128 RX2FLOWTHRESH Receive Channel Flow Control Threshold Register 0x01E2 312C RX3FLOWTHRESH Receive Channel Flow Control Threshold Register 0x01E2 3130 RX4FLOWTHRESH Receive Channel Flow Control Threshold Register 0x01E2 3134 RX5FLOWTHRESH Receive Channel Flow Control Threshold Register 0x01E2 3138 RX6FLOWTHRESH Receive Channel Flow Control Threshold Register 0x01E2 313C RX7FLOWTHRESH Receive Channel Flow Control Threshold Register Peripheral Information and Electrical Specifications 190 Submit Documentation Feedback

www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 6-87. Ethernet Media Access Controller (EMAC) Registers (continued) BYTE ADDRESS ACRONYM REGISTER (see Table 6-88 EMAC Statistics Registers 0x01E2 3500 MACADDRLO MAC Address Low Bytes Register, Used in Receive Address Matching 0x01E2 3504 MACADDRHI MAC Address High Bytes Register, Used in Receive Address Matching 0x01E2 3508 MACINDEX MAC Index Register 0x01E2 3600 TX0HDP Transmit Channel DMA Head Descriptor Pointer Register 0x01E2 3604 TX1HDP Transmit Channel DMA Head Descriptor Pointer Register 0x01E2 3608 TX2HDP Transmit Channel DMA Head Descriptor Pointer Register 0x01E2 360C TX3HDP Transmit Channel DMA Head Descriptor Pointer Register 0x01E2 3610 TX4HDP Transmit Channel DMA Head Descriptor Pointer Register 0x01E2 3614 TX5HDP Transmit Channel DMA Head Descriptor Pointer Register 0x01E2 3618 TX6HDP Transmit Channel DMA Head Descriptor Pointer Register 0x01E2 361C TX7HDP Transmit Channel DMA Head Descriptor Pointer Register 0x01E2 3620 RX0HDP Receive Channel DMA Head Descriptor Pointer Register 0x01E2 3624 RX1HDP Receive Channel DMA Head Descriptor Pointer Register 0x01E2 3628 RX2HDP Receive Channel DMA Head Descriptor Pointer Register 0x01E2 362C RX3HDP Receive Channel DMA Head Descriptor Pointer Register 0x01E2 3630 RX4HDP Receive Channel DMA Head Descriptor Pointer Register 0x01E2 3634 RX5HDP Receive Channel DMA Head Descriptor Pointer Register 0x01E2 3638 RX6HDP Receive Channel DMA Head Descriptor Pointer Register 0x01E2 363C RX7HDP Receive Channel DMA Head Descriptor Pointer Register 0x01E2 3640 TX0CP Transmit Channel Completion Pointer Register 0x01E2 3644 TX1CP Transmit Channel Completion Pointer Register 0x01E2 3648 TX2CP Transmit Channel Completion Pointer Register 0x01E2 364C TX3CP Transmit Channel Completion Pointer Register 0x01E2 3650 TX4CP Transmit Channel Completion Pointer Register Submit Documentation Feedback Peripheral Information and Electrical Specifications 191

www.ti.com Table 6-87. Ethernet Media Access Controller (EMAC) Registers (continued) BYTE ADDRESS ACRONYM REGISTER 6-88. EMAC Statistics Registers BYTE ADDRESS ACRONYM REGISTER (Total number of good broadcast frames received) Multicast Receive Frames Register 0x01E2 3208 RXMCASTFRAMES (Total number of good multicast frames received) 0x01E2 320C RXPAUSEFRAMES Pause Receive Frames Register Receive CRC Errors Register (Total number of frames received with 0x01E2 3210 RXCRCERRORS CRC errors) Receive Alignment/Code Errors Register 0x01E2 3214 RXALIGNCODEERRORS (Total number of frames received with alignment/code errors) Receive Oversized Frames Register 0x01E2 3218 RXOVERSIZED (Total number of oversized frames received) Receive Jabber Frames Register 0x01E2 321C RXJABBER (Total number of jabber frames received) Receive Undersized Frames Register 0x01E2 3220 RXUNDERSIZED (Total number of undersized frames received) 0x01E2 3224 RXFRAGMENTS Receive Frame Fragments Register 0x01E2 3228 RXFILTERED Filtered Receive Frames Register 0x01E2 322C RXQOSFILTERED Received QOS Filtered Frames Register Receive Octet Frames Register 0x01E2 3230 RXOCTETS (Total number of received bytes in good frames) Good Transmit Frames Register 0x01E2 3234 TXGOODFRAMES (Total number of good frames transmitted) 0x01E2 3238 TXBCASTFRAMES Broadcast Transmit Frames Register 0x01E2 323C TXMCASTFRAMES Multicast Transmit Frames Register 0x01E2 3240 TXPAUSEFRAMES Pause Transmit Frames Register 0x01E2 3244 TXDEFERRED Deferred Transmit Frames Register 0x01E2 3248 TXCOLLISION Transmit Collision Frames Register 0x01E2 324C TXSINGLECOLL Transmit Single Collision Frames Register 0x01E2 3250 TXMULTICOLL Transmit Multiple Collision Frames Register 0x01E2 3254 TXEXCESSIVECOLL Transmit Excessive Collision Frames Register 0x01E2 3258 TXLATECOLL Transmit Late Collision Frames Register 0x01E2 325C TXUNDERRUN Transmit Underrun Error Register 0x01E2 3260 TXCARRIERSENSE Transmit Carrier Sense Errors Register 0x01E2 3264 TXOCTETS Transmit Octet Frames Register 0x01E2 3268 FRAME64 Transmit and Receive Octet Frames Register Peripheral Information and Electrical Specifications 192 Submit Documentation Feedback

www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 6-88. EMAC Statistics Registers (continued) BYTE ADDRESS ACRONYM REGISTER 6-89. EMAC Control Module Registers BYTE ADDRESS ACRONYM REGISTER

www.ti.com Table 6-90. EMAC Control Module RAM BYTE ADDRESS

6.21.1.1 EMAC Electrical Data/Timing MII_RXCLK 2 3 MII_TXCLK 2 3 MII_RXCLK□(Input) MII_RXD[3]-MII_RXD[0], MII_RXDV,□MII_RXER□(Inputs) OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 6-91. Timing Requirements for MII_RXCLK (see Figure 6-46 1.2V, 1.1V 1.0V NO. Mbps 100 Mbps Mbps UNIT MIN MAX MIN MAX MIN MAX t c(MII_RXCLK) Cycle time, MII_RXCLK 400 400 ns t w(MII_RXCLKH) Pulse duration, MII_RXCLK high 140 140 ns t w(MII_RXCLKL) Pulse duration, MII_RXCLK low 140 140 ns Figure 6-46. MII_RXCLK Timing (EMAC Receive) Table 6-92. Timing Requirements for MII_TXCLK (see Figure 6-46 1.2V, 1.1V 1.0V NO. PARAMETER Mbps 100 Mbps Mbps UNIT MIN MAX MIN MAX MIN MAX t c(MII_TXCLK) Cycle time, MII_TXCLK 400 400 ns t w(MII_TXCLKH) Pulse duration, MII_TXCLK high 140 140 ns t w(MII_TXCLKL) Pulse duration, MII_TXCLK low 140 140 ns Figure 6-47. MII_TXCLK Timing (EMAC Transmit) Table 6-93. Timing Requirements for EMAC MII Receive Mbit/s (1) (see Figure 6-48 1.2V, 1.1V, 1.0V NO. PARAMETER UNIT MIN MAX t su(MRXD-MII_RXCLKH) Setup time, receive selected signals valid before MII_RXCLK high ns t h(MII_RXCLKH-MRXD) Hold time, receive selected signals valid after MII_RXCLK high ns (1) Receive selected signals include: MII_RXD[3]-MII_RXD[0], MII_RXDV, and MII_RXER. Figure 6-48. EMAC Receive Interface Timing Submit Documentation Feedback Peripheral Information and Electrical Specifications 195

MII_TCLK□(Input) MII_TXD[3]-MII_TXD[0], MII_TXEN□(Outputs) OMAP-L138 Low-Power www.ti.com Table 6-94. Switching Characteristics Over Recommended Operating Conditions for EMAC MII Transmit Mbit/s (1) (see Figure 6-49 1.2V, 1.1V 1.0V NO. PARAMETER UNIT MIN MAX MIN MAX t d(MII_TXCLKH- Delay time, MII_TXCLK high to transmit selected signals valid ns MTXD) (1) Transmit selected signals include: MTXD3-MTXD0, and MII_TXEN. Figure 6-49. EMAC Transmit Interface Timing Peripheral Information and Electrical Specifications 196 Submit Documentation Feedback

RMII_MHz_50_CLK RMII_TXEN RMII_TXD[1:0] RMII_RXD[1:0] RMII_CRS_DV RMII_RXER 2 3 5 5 8 9 OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 6-95. Timing Requirements for EMAC RMII 1.2V, 1.1V (1) NO. PARAMETER UNIT MIN TYP MAX tc(REFCLK) Cycle Time, REF_CLK ns tw(REFCLKH) Pulse Width, REF_CLK High ns tw(REFCLKL) Pulse Width, REF_CLK Low ns tsu(RXD-REFCLK) Input Setup Time, RXD Valid before REF_CLK High ns th(REFCLK-RXD) Input Hold Time, RXD Valid after REF_CLK High ns tsu(CRSDV-REFCLK) Input Setup Time, CRSDV Valid before REF_CLK High ns th(REFCLK-CRSDV) Input Hold Time, CRSDV Valid after REF_CLK High ns tsu(RXER-REFCLK) Input Setup Time, RXER Valid before REF_CLK High ns th(REFCLKR-RXER) Input Hold Time, RXER Valid after REF_CLK High ns (1) RMII is not supported at operating points below 1.1V nominal. Table 6-96. Switching Characteristics Over Recommended Operating Conditions for EMAC RMII 1.2V, 1.1V (1) NO. PARAMETER UNIT MIN TYP MAX td(REFCLK-TXD) Output Delay Time, REF_CLK High to TXD Valid 2.5 ns td(REFCLK-TXEN) Output Delay Time, REF_CLK High to TXEN Valid 2.5 ns (1) RMII is not supported at operating points below 1.1V nominal. Figure 6-50. RMII Timing Diagram Submit Documentation Feedback Peripheral Information and Electrical Specifications 197

6.22 Management Data Input/Output (MDIO) 6.22.1 MDIO Registers OMAP-L138 Low-Power www.ti.com The Management Data Input/Output (MDIO) module continuously polls all MDIO addresses in order to enumerate all PHY devices in the system. The Management Data Input/Output (MDIO) module implements the 802.3 serial management interface to interrogate and control Ethernet PHY(s) using a shared two-wire bus. Host software uses the MDIO module to configure the auto-negotiation parameters of each PHY attached to the EMAC, retrieve the negotiation results, and configure required parameters in the EMAC module for correct operation. The module is designed to allow almost transparent operation of the MDIO interface, with very little maintenance from the core processor. Only one PHY may be connected at any given time. For a list of supported MDIO registers see Table 6-97 [MDIO Registers]. Table 6-97. MDIO Register Memory Map BYTE ADDRESS ACRONYM REGISTER NAME 0x01E2 4000 REV Revision Identification Register 0x01E2 4004 CONTROL MDIO Control Register 0x01E2 4008 ALIVE MDIO PHY Alive Status Register 0x01E2 400C LINK MDIO PHY Link Status Register 0x01E2 4010 LINKINTRAW MDIO Link Status Change Interrupt (Unmasked) Register 0x01E2 4014 LINKINTMASKED MDIO Link Status Change Interrupt (Masked) Register 0x01E2 4018 Reserved 0x01E2 4020 USERINTRAW MDIO User Command Complete Interrupt (Unmasked) Register 0x01E2 4024 USERINTMASKED MDIO User Command Complete Interrupt (Masked) Register 0x01E2 4028 USERINTMASKSET MDIO User Command Complete Interrupt Mask Set Register 0x01E2 402C USERINTMASKCLEAR MDIO User Command Complete Interrupt Mask Clear Register 0x01E2 4030 0x01E2 407C Reserved 0x01E2 4080 USERACCESS0 MDIO User Access Register 0x01E2 4084 USERPHYSEL0 MDIO User PHY Select Register 0x01E2 4088 USERACCESS1 MDIO User Access Register 0x01E2 408C USERPHYSEL1 MDIO User PHY Select Register 0x01E2 4090 0x01E2 47FF Reserved Peripheral Information and Electrical Specifications 198 Submit Documentation Feedback

6.22.2 Management Data Input/Output (MDIO) Electrical Data/Timing MDCLK MDIO (input) 3 3 MDCLK MDIO (output) OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 6-98. Timing Requirements for MDIO Input (see Figure 6-51 and Figure 6-52 1.2V, 1.1V, 1.0V NO. UNIT MIN MAX t c(MDCLK) Cycle time, MDCLK 400 ns t w(MDCLK) Pulse duration, MDCLK high/low 180 ns t t(MDCLK) Transition time, MDCLK ns t su(MDIO-MDCLKH) Setup time, MDIO data input valid before MDCLK high ns t h(MDCLKH-MDIO) Hold time, MDIO data input valid after MDCLK high ns Figure 6-51. MDIO Input Timing Table 6-99. Switching Characteristics Over Recommended Operating Conditions for MDIO Output (see Figure 6-52 NO. UNIT MIN MAX t d(MDCLKL-MDIO) Delay time, MDCLK low to MDIO data output valid 100 ns Figure 6-52. MDIO Output Timing Submit Documentation Feedback Peripheral Information and Electrical Specifications 199

6.23 LCD Controller (LCDC) OMAP-L138 Low-Power www.ti.com Table 6-100 lists the LCD Controller registers. Table 6-100. LCD Controller Registers BYTE ADDRESS ACRONYM REGISTER LCD_CTRL LCD Control Register 0x01E1 3008 LCD_STAT LCD Status Register 0x01E1 300C LIDD_CTRL LCD LIDD Control Register 0x01E1 3010 LIDD_CS0_CONF LCD LIDD CS0 Configuration Register 0x01E1 3014 LIDD_CS0_ADDR LCD LIDD CS0 Address Read/Write Register 0x01E1 3018 LIDD_CS0_DATA LCD LIDD CS0 Data Read/Write Register 0x01E1 301C LIDD_CS1_CONF LCD LIDD CS1 Configuration Register 0x01E1 3020 LIDD_CS1_ADDR LCD LIDD CS1 Address Read/Write Register 0x01E1 3024 LIDD_CS1_DATA LCD LIDD CS1 Data Read/Write Register 0x01E1 3028 RASTER_CTRL LCD Raster Control Register 0x01E1 302C RASTER_TIMING_0 LCD Raster Timing Register 0x01E1 3030 RASTER_TIMING_1 LCD Raster Timing Register 0x01E1 3034 RASTER_TIMING_2 LCD Raster Timing Register 0x01E1 3038 RASTER_SUBPANEL LCD Raster Subpanel Display Register 0x01E1 3040 LCDDMA_CTRL LCD DMA Control Register 0x01E1 3044 LCDDMA_FB0_BASE LCD DMA Frame Buffer Base Address Register 0x01E1 3048 LCDDMA_FB0_CEILING LCD DMA Frame Buffer Ceiling Address Register 0x01E1 304C LCDDMA_FB1_BASE LCD DMA Frame Buffer Base Address Register 0x01E1 3050 LCDDMA_FB1_CEILING LCD DMA Frame Buffer Ceiling Address Register Peripheral Information and Electrical Specifications 200 Submit Documentation Feedback

6.23.1 LCD Interface Display Driver (LIDD Mode) LCD_AC_ENB_CS LCD_PCLK

1 W_SU

(0 to 31) W_STROBE (1 to 63) W_HOLD (1 to 15) CS_DELAY (0 to 3) R_SU (0 to 31) R_STROBE (1 to 63) R_HOLD (1 to 15) CS_DELAY (0 to 3) LCD_CLK (SYSCLK2) Write Data 5 14 Data[7:0] Not Used 8 9 10 11 RS R/W LCD_D[15:0] LCD_VSYNC LCD_HSYNC Read Status OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 6-101. Timing Requirements for LCD LIDD Mode (1) 1.2V, 1.1V 1.0V NO. PARAMETER UNIT MIN MAX MIN MAX t su(LCD_D) Setup time, LCD_D[15:0] valid before LCD_CLK (SYSCLK2) high ns t h(LCD_D) Hold time, LCD_D[15:0] valid after LCD_CLK (SYSCLK2) high ns (1) Over operating free-air temperature range (unless otherwise noted) Table 6-102. Switching Characteristics Over Recommended Operating Conditions for LCD LIDD Mode 1.2V, 1.1V 1.0V NO. PARAMETER UNIT MIN MAX MIN MAX t d(LCD_D_V) Delay time, LCD_CLK (SYSCLK2) high to LCD_D[15:0] valid (write) ns t d(LCD_D_I) Delay time, LCD_CLK (SYSCLK2) high to LCD_D[15:0] invalid (write) ns t d(LCD_E_A Delay time, LCD_CLK (SYSCLK2) high to LCD_AC_ENB_CS low ns t d(LCD_E_I) Delay time, LCD_CLK (SYSCLK2) high to LCD_AC_ENB_CS high ns t d(LCD_A_A) Delay time, LCD_CLK (SYSCLK2) high to LCD_VSYNC low ns t d(LCD_A_I) Delay time, LCD_CLK (SYSCLK2) high to LCD_VSYNC high ns t d(LCD_W_A) Delay time, LCD_CLK (SYSCLK2) high to LCD_HSYNC low ns t d(LCD_W_I) Delay time, LCD_CLK (SYSCLK2) high to LCD_HSYNC high ns t d(LCD_STRB_A) Delay time, LCD_CLK (SYSCLK2) high to LCD_PCLK high ns t d(LCD_STRB_I) Delay time, LCD_CLK (SYSCLK2) high to LCD_PCLK low ns t d(LCD_D_Z) Delay time, LCD_CLK (SYSCLK2) high to LCD_D[15:0] in 3-state ns t d(Z_LCD_D) Delay time, LCD_CLK (SYSCLK2) high to LCD_D[15:0] (valid from 3-state) ns Figure 6-53. Character Display HD44780 Write Submit Documentation Feedback Peripheral Information and Electrical Specifications 201

LCD_AC_ENB_CS LCD_PCLK LCD_VSYNC LCD_HSYNC R_SU R_STROBE R_HOLD (0–31) (1–63) (1–5) CS_DELA Y (0−3) Not Used RS R/W LCD_CLK (SYSCLK2) 2 3 W_SU W_STROBE W_HOLD (0–31) (1–63) (1–15) CS_DELA Y (0 − 3) 8 9 12 13 10 11 Not Used LCD_D[7:0] 14 1716 Read Data 15 4 5 12 13 Data[7:0]W rite Instruction OMAP-L138 Low-Power www.ti.com Figure 6-54. Character Display HD44780 Read 202 Peripheral Information and Electrical Specifications Submit Documentation Feedback

LCD_D[15:0] LCD_AC_ENB_CS (async mode) LCD_VSYNC LCD_HSYNC LCD_CLK (SYSCLK2) LCD_PCLK W_SU W_STROBE W_HOLD (0−31) (1−63) (1−15) CS_DELA Y (0−3) CS0 CS1 R/W E Clock 2 3 W_SU W_STROBE W_HOLD (0−31) (1−63) (1−15) CS_DELA Y (0−3) 5 4 5 6 7 6 7 8 9 12 13 W rite Address W rite Data 12 13 10 11 10 11 Data[15:0] OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Figure 6-55. Micro-Interface Graphic Display 6800 Write Submit Documentation Feedback Peripheral Information and Electrical Specifications 203

LCD_D[15:0] LCD_AC_ENB_CS (async mode) LCD_VSYNC LCD_HSYNC LCD_CLK (SYSCLK2) LCD_PCLK W_SU W_STROBE W_HOLD (0−31) (1−63) (1−15) CS_DELA Y (0−3) CS0 CS1 R/W E Clock 2 3 R_SU R_STROBE R_HOLD (0−31) (1−63 (1−15) CS_DELA Y (0−3) 5 14 15 6 7 6 7 8 9 12 13 1716 W rite Address Read Data 10 11 1213 Data[15:0] OMAP-L138 Low-Power www.ti.com Figure 6-56. Micro-Interface Graphic Display 6800 Read 204 Peripheral Information and Electrical Specifications Submit Documentation Feedback

LCD_D[15:0] LCD_AC_ENB_CS (async mode) LCD_VSYNC LCD_HSYNC LCD_CLK (SYSCLK2) LCD_PCLK R_SU R_STROBE R_HOLD (0−31) (1−63) (1−15) CS_DELA Y (0−3) CS0 CS1 R/W E Clock 2 3 R_STROBE R_HOLD (1−63) (1−15) CS_DELA Y (0−3) 14 15 6 7 6 7 8 9 12 13 171614 1716 15 12 13 Data[15:0] R_SU (0−31) Read Status OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Figure 6-57. Micro-Interface Graphic Display 6800 Status Submit Documentation Feedback Peripheral Information and Electrical Specifications 205

LCD_D[15:0] LCD_AC_ENB_CS (async mode) LCD_VSYNC LCD_HSYNC LCD_CLK (SYSCLK2) LCD_PCLK W_SU W_STROBE W_HOLD (0−31) (1−63) (1−15) CS_DELA Y (0−3) DATA[15:0] CS0 CS1 WR RD Clock 2 3 W_SU W_STROBE W_HOLD (0−31) (1−63) (1−15) CS_DELA Y (0 − 3) 5 4 5 6 7 6 7 8 9 10 11 W rite Address W rite Data 10 11 OMAP-L138 Low-Power www.ti.com Figure 6-58. Micro-Interface Graphic Display 8080 Write 206 Peripheral Information and Electrical Specifications Submit Documentation Feedback

LCD_D[15:0] LCD_AC_ENB_CS (async mode) LCD_VSYNC LCD_HSYNC LCD_CLK (SYSCLK2) LCD_PCLK W_SU W_STROBE W_HOLD (0−31) (1−63) (1−15) CS_DELA Y (0−3) CS0 CS1 WR RD Clock 2 3 R_SU R_STROBE R_HOLD (0−31) (1−63) (1−15) CS_DELA Y (0−3) 5 14 15 6 7 6 7 8 9 12 13 1716 Read Data 10 11 Data[15:0]W rite Address OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Figure 6-59. Micro-Interface Graphic Display 8080 Read Submit Documentation Feedback Peripheral Information and Electrical Specifications 207

LCD_D[15:0] LCD_AC_ENB_CS LCD_VSYNC LCD_HSYNC LCD_CLK (SYSCLK2) LCD_PCLK R_SU R_STROBE R_HOLD (0−31) (1−63) (1−15) CS_DELA Y (0−3) CS0 CS1 WR RD Clock R_STROBE R_HOLD (1−63) (1−15) CS_DELA Y (0−3) 14 15 6 7 6 12 13 1716 Read Status 14 1716 Read Data 12 13 Data[15:0] R_SU (0−31) OMAP-L138 Low-Power www.ti.com Figure 6-60. Micro-Interface Graphic Display 8080 Status Peripheral Information and Electrical Specifications 208 Submit Documentation Feedback

6.23.2 LCD Raster Mode OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 6-103. Switching Characteristics Over Recommended Operating Conditions for LCD Raster Mode See Figure 6-61 through Figure 6-65 1.2V, 1.1V 1.0V NO. PARAMETER UNIT MIN MAX MIN MAX f clock(PIXEL_CLK) Clock frequency, pixel clock F/2 (1) F/2 (1) MHz t c(PIXEL_CLK) Cycle time, pixel clock 26.66 33.33 ns t w(PIXEL_CLK_H) Pulse duration, pixel clock high ns t w(PIXEL_CLK_L) Pulse duration, pixel clock low ns t d(LCD_D_V) Delay time, LCD_PCLK high to LCD_D[15:0] valid (write) ns t d(LCD_D_IV) Delay time, LCD_PCLK high to LCD_D[15:0] invalid (write) ns t LCD_AC_ENB_CS_A Delay time, LCD_PCLK low to LCD_AC_ENB_CS high ns t LCD_AC_ENB_CS_I) Delay time, LCD_PCLK low to LCD_AC_ENB_CS high ns t d(LCD_VSYNC_A) Delay time, LCD_PCLK low to LCD_VSYNC high ns t d(LCD_VSYNC_I) Delay time, LCD_PCLK low to LCD_VSYNC low ns t d(LCD_HSYNC_A) Delay time, LCD_PCLK high to LCD_HSYNC high ns t d(LCD_HSYNC_I) Delay time, LCD_PCLK high to LCD_HSYNC low ns (1) F frequency of LCD_PCLK in ns Frame-to-frame timing is derived through the following parameters in the LCD (RASTER_TIMING_1) register: Vertical front porch (VFP) Vertical sync pulse width (VSW) Vertical back porch (VBP) Lines per panel (LPP) Line-to-line timing is derived through the following parameters in the LCD (RASTER_TIMING_0) register: Horizontal front porch (HFP) Horizontal sync pulse width (HSW) Horizontal back porch (HBP) Pixels per panel (PPL) LCD_AC_ENB_CS timing is derived through the following parameter in the LCD (RASTER_TIMING_2) register: AC bias frequency (ACB) The display format produced in raster mode is shown in Figure 6-61 An entire frame is delivered one line at a time. The first line delivered starts at data pixel (1, and ends at data pixel (P, 1). The last line delivered starts at data pixel (1, and ends at data pixel (P, L). The beginning of each new frame is denoted by the activation of I/O signal LCD_VSYNC. The beginning of each new line is denoted by the activation of I/O signal LCD_HSYNC. Submit Documentation Feedback Peripheral Information and Electrical Specifications 209

1, 1 2, 1 3, 1 1, 2 2, 2 1, 3 P, 1P−1, P−2, P, 2P−1, P, 3 1, L L−1 L−2 3, L2, L L−1 P, L P−1, L−1 L−1 P−1, L L−2 P−2, L Data Pixels (From 1 to P) Data Lines (From 1 to L) OMAP-L138 Low-Power www.ti.com Figure 6-61. LCD Raster-Mode Display Format Peripheral Information and Electrical Specifications 210 Submit Documentation Feedback

LCD_HSYNC Hsync LCD_VSYNC (1 to 64) VSW (1 to 64) VSW (0 to 255) VFP (1 to 1024) Frame Time ~ 70Hz LPP (0 to 255) LCD_D[15:0] 1, 1 P, 1 1, 2 P, 2 1, L P, L 1, L−1 P, L−1 Line Time LCD_HSYNC Hsync 10 11 LCD_PCLK PLL 16 /C0121 (1 to 1024) HBP (1 to 256) Line 1 (1 to 256) HFP (1 to 64) HSW PLL 16 /C0121 (1 to 1024) Line 2 Vsync Data Data Active TFT ACB (0 to 255) LCD_AC_ENB_CS Enable ACB (0 to 255) VBP OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Figure 6-62. LCD Raster-Mode Active Submit Documentation Feedback Peripheral Information and Electrical Specifications 211

LCD_HSYNC LP LCD_VSYNC VSW = 1 (1 to 1024) Frame Time ~ 70Hz LPP LCD_D[7:0] 1, L−2 P, L−2 1, L−4 P, L−4 Line Time LCD_HSYNC LP 10 11 LCD_PCLK PPL 16 /C0121 (1 to 1024) HBP (1 to 256) Line 5 HFP (1 to 64) HSW PPL 16 /C0121 (1 to 2024) Line 6 1, 1: P, 1 1, 5: P, 5 1, L−1 P, L−1 1, L 1, L−1 P, L−1 1, L−3 P, L−3 (1 to 64) VSW = 1 (1 to 64) VFP = 0 VBP = 0 VFP = 0 VBP = 0 FP Data CP Data Passive STN LCD_AC_ENB_CS M ACB (0 to 255) ACB (0 to 255) 1, 4: P, 4 1, 3: P, 3 1, 2: P, 2 1, L: P, L 1, 6: P, 6 1, 2 P, 2 1, 1 P, 1 1, L P, L (1 to 256) OMAP-L138 Low-Power www.ti.com Figure 6-63. LCD Raster-Mode Passive 212 Peripheral Information and Electrical Specifications Submit Documentation Feedback

LCD_HSYNC LCD_PCLK (active mode) LCD_D[15:0] (active mode) 1,□L P,□L2,□L PPL 16 ×(1□to□1024) HBP (1□to□256 Line□L (1□to□256) HFP (1□to□64) HSW PPL 16 ×(1□to□1024) Line□1□(Passive□Only) LCD_VSYNC LCD_PCLK (passive mode) LCD_AC_ENB_CS LCD_D[7:0] (passive mode) 1,□L 2,□1 P,□1P,□L2,□L 1,□1 10 11 2 3 2 3 VSW = 1 VFP =□0 VBP =□0 OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Figure 6-64. LCD Raster-Mode Control Signal Activation Submit Documentation Feedback Peripheral Information and Electrical Specifications 213

LCD_HSYNC LCD_PCLK (active mode) LCD_D[15:0] (active mode) PPL 16 ×(1□to□1024) HBP (1□to□256 Line□1□for□passive (1□to□256) HFP (1□to□64) HSW PPL 16 ×(1□to□1024) Line□1□for□active LCD_VSYNC LCD_PCLK (passive mode) LCD_AC_ENB_CS LCD_D[7:0] (passive mode) 1,□1 2,□2 P,□2P,□12,□1 1,□2 10 11 4 5 2 3 VSW = 1 VFP =□0 VBP =□0 P,□11,□1 2,□1 4 5 Line□2□for□passive OMAP-L138 Low-Power www.ti.com Figure 6-65. LCD Raster-Mode Control Signal Deactivation 214 Peripheral Information and Electrical Specifications Submit Documentation Feedback

6.24 Host-Port Interface (UHPI) 6.24.1 HPI Device-Specific Information 6.24.2 HPI Peripheral Register Description(s) OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 The device includes a user-configurable 16-bit Host-port interface (HPI16). Table 6-104. HPI Control Registers BYTE ADDRESS ACRONYM REGISTER PWREMU_MGMT HPI power and emulation management register to the PWREMU_MGMT register. 0x01E1 0008 Reserved 0x01E1 000C GPIO_EN General Purpose IO Enable Register 0x01E1 0010 GPIO_DIR1 General Purpose IO Direction Register 0x01E1 0014 GPIO_DAT1 General Purpose IO Data Register 0x01E1 0018 GPIO_DIR2 General Purpose IO Direction Register 0x01E1 001C GPIO_DAT2 General Purpose IO Data Register 0x01E1 0020 GPIO_DIR3 General Purpose IO Direction Register 0x01E1 0024 GPIO_DAT3 General Purpose IO Data Register 01E1 0028 Reserved 01E1 002C Reserved The Host and the CPU both have 01E1 0030 HPIC HPI control register read/write access to the HPIC register. HPIA HPI address register The Host has read/write access 01E1 0034 (HPIAW) (1) (Write) to the HPIA registers. The CPU has only read access to the HPIA HPIA HPI address register 01E1 0038 registers. (HPIAR) (1) (Read) 01E1 000C 01E1 07FF Reserved (1) There are two 32-bit HPIA registers: HPIAR for read operations and HPIAW for write operations. The HPI can be configured such that HPIAR and HPIAW act as a single 32-bit HPIA (single-HPIA mode) or as two separate 32-bit HPIAs (dual-HPIA mode) from the perspective of the Host. The CPU can access HPIAW and HPIAR independently. Submit Documentation Feedback Peripheral Information and Electrical Specifications 215

6.24.3 HPI Electrical Data/Timing OMAP-L138 Low-Power www.ti.com Table 6-105. Timing Requirements for Host-Port Interface [1.2V, 1.1V] (1) (2) 1.2V, 1.1V, 1.0V NO. UNIT MIN MAX t su(SELV-HSTBL) Setup time, select signals (3) valid before UHPI_HSTROBE low ns t h(HSTBL-SELV) Hold time, select signals (3) valid after UHPI_HSTROBE low ns t w(HSTBL) Pulse duration, UHPI_HSTROBE active low ns t w(HSTBH) Pulse duration, UHPI_HSTROBE inactive high between consecutive accesses ns t su(SELV-HASL) Setup time, selects signals valid before UHPI_HAS low t h(HASL-SELV) Hold time, select signals valid after UHPI_HAS low t su(HDV-HSTBH) Setup time, host data valid before UHPI_HSTROBE high ns t h(HSTBH-HDV) Hold time, host data valid after UHPI_HSTROBE high ns Hold time, UHPI_HSTROBE high after UHPI_HRDY low. UHPI_HSTROBE t h(HRDYL-HSTBH) should not be inactivated until UHPI_HRDY is active (low); otherwise, HPI writes ns will not complete properly. t su(HASL-HSTBL) Setup time, UHPI_HAS low before UHPI_HSTROBE low t h(HSTBL-HASH) Hold time, UHPI_HAS low after UHPI_HSTROBE low (1) UHPI_HSTROBE refers to the following logical operation on UHPI_HCS UHPI_HDS1 and UHPI_HDS2 [NOT( UHPI_HDS1 XOR UHPI_HDS2 OR UHPI_HCS (2) M=SYSCLK2 period in ns. (3) Select signals include: HCNTL[1:0], HR/ W and HHWIL. Peripheral Information and Electrical Specifications 216 Submit Documentation Feedback

www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 6-106. Switching Characteristics Over Recommended Operating Conditions for Host-Port Interface [1.2V, 1.1V] (1) (2) (3) 1.2V 1.1V NO. PARAMETER UNIT MIN MAX MIN MAX For HPI Write, HRDY can go high not ready for these HPI Write conditions; otherwise, HRDY stays low ready Case Back-to-back HPIA writes (can be either first or second half-word) Case HPIA write following a PREFETCH command (can be either first or second half-word) Case HPID write when FIFO is full or flushing (can be either first or second half-word) Case HPIA write and Write FIFO not empty For HPI Read, HRDY can go high not ready for these HPI Read conditions: Case HPID read (with Delay time, HSTROBE low to t d(HSTBL-HRDYV) ns auto-increment) and data not in Read HRDY valid FIFO (can only happen to first half-word of HPID access) Case First half-word access of HPID Read without auto-increment For HPI Read, HRDY stays low ready for these HPI Read conditions: Case HPID read with auto-increment and data is already in Read FIFO (applies to either half-word of HPID access) Case HPID read without auto-increment and data is already in Read FIFO (always applies to second half-word of HPID access) Case HPIC or HPIA read (applies to either half-word access) t d(HASL-HRDYV) Delay time, HAS low to HRDY valid t en(HSTBL-HDLZ) Enable time, HD driven from HSTROBE low 1.5 1.5 ns t d(HRDYL-HDV) Delay time, HRDY low to HD valid ns t oh(HSTBH-HDV) Output hold time, HD valid after HSTROBE high 1.5 1.5 ns t dis(HSTBH-HDHZ) Disable time, HD high-impedance from HSTROBE high ns For HPI Read. Applies to conditions where data is already residing in HPID/FIFO: Case HPIC or HPIA read Delay time, HSTROBE low to t d(HSTBL-HDV) Case First half-word of HPID read ns HD valid with auto-increment and data is already in Read FIFO Case Second half-word of HPID read with or without auto-increment For HPI Write, HRDY can go high not ready for these HPI Write conditions; otherwise, HRDY stays low ready Case HPID write when Write FIFO is Delay time, HSTROBE high to full (can happen to either half-word) t d(HSTBH-HRDYV) ns HRDY valid Case HPIA write (can happen to either half-word) Case HPID write without auto-increment (only happens to second half-word) (1) M=SYSCLK2 period in ns. (2) HSTROBE refers to the following logical operation on HCS HDS1 and HDS2 [NOT( HDS1 XOR HDS2 OR HCS (3) By design, whenever HCS is driven inactive (high), HPI will drive HRDY active (low). Submit Documentation Feedback Peripheral Information and Electrical Specifications 217

www.ti.com Table 6-107. Switching Characteristics Over Recommended Operating Conditions for Host-Port Interface [1.0V] (1) (2) (3) 1.0V NO. PARAMETER UNIT MIN MAX For HPI Write, HRDY can go high not ready for these HPI Write conditions; otherwise, HRDY stays low ready Case Back-to-back HPIA writes (can be either first or second half-word) Case HPIA write following a PREFETCH command (can be either first or second half-word) Case HPID write when FIFO is full or flushing (can be either first or second half-word) Case HPIA write and Write FIFO not empty For HPI Read, HRDY can go high not ready for these HPI Read conditions: Delay time, HSTROBE low to HRDY Case HPID read (with auto-increment) and t d(HSTBL-HRDYV) ns valid data not in Read FIFO (can only happen to first half-word of HPID access) Case First half-word access of HPID Read without auto-increment For HPI Read, HRDY stays low ready for these HPI Read conditions: Case HPID read with auto-increment and data is already in Read FIFO (applies to either half-word of HPID access) Case HPID read without auto-increment and data is already in Read FIFO (always applies to second half-word of HPID access) Case HPIC or HPIA read (applies to either half-word access) t d(HASL-HRDYV) Delay time, HAS low to HRDY valid t en(HSTBL-HDLZ) Enable time, HD driven from HSTROBE low 1.5 ns t d(HRDYL-HDV) Delay time, HRDY low to HD valid ns t oh(HSTBH-HDV) Output hold time, HD valid after HSTROBE high 1.5 ns t dis(HSTBH-HDHZ) Disable time, HD high-impedance from HSTROBE high ns For HPI Read. Applies to conditions where data is already residing in HPID/FIFO: Case HPIC or HPIA read Delay time, HSTROBE low to HD Case First half-word of HPID read with t d(HSTBL-HDV) ns valid auto-increment and data is already in Read FIFO Case Second half-word of HPID read with or without auto-increment For HPI Write, HRDY can go high not ready for these HPI Write conditions; otherwise, HRDY stays low ready Case HPID write when Write FIFO is full (can Delay time, HSTROBE high to HRDY t d(HSTBH-HRDYV) happen to either half-word) ns valid Case HPIA write (can happen to either half-word) Case HPID write without auto-increment (only happens to second half-word) (1) M=SYSCLK2 period in ns. (2) HSTROBE refers to the following logical operation on HCS HDS1 and HDS2 [NOT( HDS1 XOR HDS2 OR HCS (3) By design, whenever HCS is driven inactive (high), HPI will drive HRDY active (low). Peripheral Information and Electrical Specifications 218 Submit Documentation Feedback

UHPI_HCS UHPI_HAS (D) UHPI_HCNTL[1:0] UHPI_HR/W UHPI_HHWIL UHPI_HSTROBE (A)(C) UHPI_HD[15:0] (output) UHPI_HRDY (B) 1st Half-Word 2nd Half-Word A. UHPI_HSTROBE refers to the following logical operation on UHPI_HCS, UHPI_HDS1, and UHPI_HDS2: [NOT(HDS1 XOR HDS2)] OR UHPI_HCS. B. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with auto-incrementing) and the state of the FIFO, transitions on UHPI_HRDY may or may not occur. C. UHPI_HCS reflects typical UHPI_HCS behavior when UHPI_HSTROBE assertion is caused by UHPI_HDS1 or UHPI_HDS2 . UHPI_HCS timing requirements are reflected by parameters for UHPI_HSTROBE. D The diagram above assumes UHPI_HAS has been pulled high. OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Figure 6-66. UHPI Read Timing HAS Not Used, Tied High) Submit Documentation Feedback Peripheral Information and Electrical Specifications 219

UHPI_HAS (A) UHPI_HCNTL[1:0] UHPI_HR/W UHPI_HHWIL UHPI_HSTROBE (B) UHPI_HCS UHPI_HD[15:0] (output) UHPI_HRDY 1st half-word 2nd half-word75a 815 10910 9 17 17 1616 OMAP-L138 Low-Power www.ti.com For correct operation, strobe the UHPI_HAS signal only once per UHPI_HSTROBE active cycle. UHPI_HSTROBE refers to the following logical operation on UHPI_HCS UHPI_HDS1 and UHPI_HDS2 [NOT( UHPI_HDS1 XOR UHPI_HDS2 OR UHPI_HCS Figure 6-67. UHPI Read Timing HAS Used) 220 Peripheral Information and Electrical Specifications Submit Documentation Feedback

UHPI_HAS (D) UHPI_HCNTL[1:0] UHPI_HR/W UHPI_HHWIL UHPI_HSTROBE (A)(C) UHPI_HCS UHPI_HD[15:0] (input) UHPI_HRDY (B) 2 1 21 1 2 1 2 3 4 3 11 12 1813 185 11 12 2nd Half-Word1st Half-Word A. UHPI_HSTROBE refers to the following logical operation on UHPI_HCS, UHPI_HDS1, and UHPI_HDS2: [NOT(HDS1 XOR HDS2 )] OR UHPI_HCS . B. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with auto-incrementing) and the state of the FIFO, transitions on UHPI_HRDY may or may not occur. C. UHPI_HCS reflects typical UHPI_HCS behavior when UHPI_HSTROBE assertion is caused by UHPI_HDS1 or UHPI_HDS2. UHPI_HCS timing requirements are reflected by parameters for UHPI_HSTROBE. D The diagram above assumes UHPI_HAS has been pulled high. OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Figure 6-68. UHPI Write Timing HAS Not Used, Tied High) Submit Documentation Feedback Peripheral Information and Electrical Specifications 221

1st half-word 2nd half-word 12111211 UHPI_HAS † UHPI_HCNTL[1:0] UHPI_HR/W UHPI_HHWIL UHPI_HSTROBE ‡ UHPI_HCS UHPI_HD[15:0] (input) UHPI_HRDY 1717 16 16 OMAP-L138 Low-Power www.ti.com For correct operation, strobe the UHPI_HAS signal only once per UHPI_HSTROBE active cycle. UHPI_HSTROBE refers to the following logical operation on UHPI_HCS UHPI_HDS1 and UHPI_HDS2 [NOT( UHPI_HDS1 XOR UHPI_HDS2 OR UHPI_HCS Figure 6-69. UHPI Write Timing HAS Used) 222 Peripheral Information and Electrical Specifications Submit Documentation Feedback

6.25 Universal Parallel Port (uPP) OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 The Universal Parallel Port (uPP) peripheral is a multichannel, high-speed parallel interface with dedicated data lines and minimal control signals. It is designed to interface cleanly with high-speed analog-to-digital converters (ADCs) or digital-to-analog converters (DACs) with up to 16-bit data width (per channel). It may also be interconnected with field-programmable gate arrays (FPGAs) or other uPP devices to achieve high-speed digital data transfer. It can operate in receive mode, transmit mode, or duplex mode, in which its individual channels operate in opposite directions. The uPP peripheral includes an internal DMA controller to maximize throughput and minimize CPU overhead during high-speed data transmission. All uPP transactions use the internal DMA to provide data to or retrieve data from the I/O channels. The DMA controller includes two DMA channels, which typically service separate I/O channels. The uPP peripheral also supports data interleave mode, in which all DMA resources service a single I/O channel. In this mode, only one I/O channel may be used. The include: Programmable data width per channel (from to bits inclusive) Programmable data justification Right-justify with zero extend Right-justify with sign extend Left-justify with zero fill Supports multiplexing of interleaved data during SDR transmit Optional frame START signal with programmable polarity Optional data ENABLE signal with programmable polarity Optional synchronization WAIT signal with programmable polarity Single Data Rate (SDR) or Double data Rate (DDR, interleaved) interface Supports multiplexing of interleaved data during SDR transmit Supports demultiplexing and multiplexing of interleaved data during DDR transfers Submit Documentation Feedback Peripheral Information and Electrical Specifications 223

6.25.1 uPP Register Descriptions OMAP-L138 Low-Power www.ti.com Table 6-108 shows the uPP registers. Table 6-108. Universal Parallel Port (uPP) Registers BYTE ADDRESS ACRONYM REGISTER I Descriptor Register 0x01E1 6044 UPID1 uPP DMA Channel I Descriptor Register 0x01E1 6048 UPID2 uPP DMA Channel I Descriptor Register 0x01E1 6050 UPIS0 uPP DMA Channel I Status Register 0x01E1 6054 UPIS1 uPP DMA Channel I Status Register 0x01E1 6058 UPIS2 uPP DMA Channel I Status Register 0x01E1 6060 UPQD0 uPP DMA Channel Q Descriptor Register 0x01E1 6064 UPQD1 uPP DMA Channel Q Descriptor Register 0x01E1 6068 UPQD2 uPP DMA Channel Q Descriptor Register 0x01E1 6070 UPQS0 uPP DMA Channel Q Status Register 0x01E1 6074 UPQS1 uPP DMA Channel Q Status Register 0x01E1 6078 UPQS2 uPP DMA Channel Q Status Register Peripheral Information and Electrical Specifications 224 Submit Documentation Feedback

6.25.2 uPP Electrical Data/Timing OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 6-109. Timing Requirements for uPP (see Figure TBD 1.2V 1.1V 1.0V NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX SDR mode 13.33 26.66 ns t c(INCLK) Cycle time, CH n _CLK DDR mode 26.66 53.33 SDR mode ns t w(INCLKH) Pulse width, CH n _CLK high DDR mode SDR mode ns t w(INCLKL) Pulse width, CH n _CLK low DDR mode t su(STV-INCLKH) Setup time, CH n _START valid before CH n _CLK high 5.5 6.5 ns t h(INCLKH-STV) Hold time, CH n _START valid after CH n _CLK high 0.8 0.8 0.8 ns t su(ENV-INCLKH) Setup time, CH n _ENABLE valid before CH n _CLK high 5.5 6.5 ns t h(INCLKH-ENV) Hold time, CH n _ENABLE valid after CH n _CLK high 0.8 0.8 0.8 ns Setup time, CH n _DATA/XDATA valid before CH n _CLK t su(DV-INCLKH) 5.5 6.5 ns high t h(INCLKH-DV) Hold time, CH n _DATA/XDATA valid after CH n _CLK high 0.8 0.8 0.8 ns t su(DV-INCLKL) Setup time, CH n _DATA/XDATA valid before CH n _CLK low 5.5 6.5 ns t h(INCLKL-DV) Hold time, CH n _DATA/XDATA valid after CH n _CLK low 0.8 0.8 0.8 ns t su(WTV-INCLKL) Setup time, CH n _WAIT valid before CH n _CLK high 5.5 6.5 ns t h(INCLKL-WTV) Hold time, CH n _WAIT valid after CH n _CLK high 0.8 0.8 0.8 ns t c(2xTXCLK) Cycle time, 2xTXCLK input clock (1) 6.66 13.33 ns (1) 2xTXCLK is an alternate transmit clock source that must be at least times the required uPP transmit clock rate (as it is is divided down by inside the uPP). 2xTXCLK has no specified skew relationship to the CH n _CLOCK and therefore is not shown in the timing diagram. Table 6-110. Switching Characteristics Over Recommended Operating Conditions for uPP (see Figure TBD) 1.2V 1.1V 1.0V NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX SDR mode 13.33 26.66 ns t c(OUTCLK) Cycle time, CH n _CLK DDR mode 26.66 53.33 SDR mode ns t w(OUTCLKH) Pulse width, CH n _CLK high DDR mode SDR mode ns t w(OUTCLKL) Pulse width, CH n _CLK low DDR mode t d(OUTCLKH-STV) Delay time, CH n _START valid after CH n _CLK high ns t d(OUTCLKH-ENV) Delay time, CH n _ENABLE valid after CH n _CLK high ns t d(OUTCLKH-DV) Delay time, CH n _DATA/XDATA valid after CH n _CLK high ns t d(OUTCLKL-DV) Delay time, CH n _DATA/XDATA valid after CH n _CLK low ns Submit Documentation Feedback Peripheral Information and Electrical Specifications 225

CHx_CLK CHx_ST ART CHx_ENABLE CHx_DA T A[n:0] CHx_XDA T A[n:0] Data2Data1 Data3 Data4 CHx_WAIT Data5 Data6 Data7 Data8 Data9 21 3 Q1 I2 I3 I4 I5 I6 I7 I8 I9Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 CHx_CLK CHx_ST ART CHx_ENABLE CHx_DA T A[n:0] CHx_XDA T A[n:0] CHx_WAIT OMAP-L138 Low-Power www.ti.com Figure 6-70. uPP Single Data Rate (SDR) Receive Timing Figure 6-71. uPP Double Data Rate (DDR) Receive Timing 226 Peripheral Information and Electrical Specifications Submit Documentation Feedback

CHx_CLK CHx_ST ART CHx_ENABLE CHx_DA T A[n:0] CHx_XDA T A[n:0] CHx_WAIT 12 14 2019 Q1 I2 I3 I4 I5 I6 I7 I8 I9Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 CHx_CLK CHx_ST ART CHx_ENABLE CHx_DA T A[n:0] CHx_XDA T A[n:0] CHx_WAIT OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Figure 6-72. uPP Single Data Rate (SDR) Transmit Timing Figure 6-73. uPP Double Data Rate (DDR) Transmit Timing Submit Documentation Feedback Peripheral Information and Electrical Specifications 227

6.26 Video Port Interface (VPIF) OMAP-L138 Low-Power www.ti.com The Video Port Interface (VPIF) allows the capture and display of digital video streams. include: Up to Video Capture Channels (Channel and Channel Two 8-bit Standard-Definition (SD) Video with embedded timing codes (BT.656) Single 16-bit High-Definition (HD) Video with embedded timing codes (BT.1120) Single Raw Video (8-/10-/12-bit) Up to Video Display Channels (Channel and Channel Two 8-bit SD Video Display with embedded timing codes (BT.656) Single 16-bit HD Video Display with embedded timing codes (BT.1120) The VPIF capture channel input data format is selectable based on the settings of the specific Channel Control Register (Channels 3). The VPIF Raw Video data-bus width is selectable based on the settings of the Channel Control Register. 228 Peripheral Information and Electrical Specifications Submit Documentation Feedback

6.26.1 VPIF Register Descriptions OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 6-111 shows the VPIF registers. Table 6-111. Video Port Interface (VPIF) Registers BYTE ADDRESS ACRONYM REGISTER CH0_CTRL Channel control register 0x01E1 7008 CH1_CTRL Channel control register 0x01E1 700C CH2_CTRL Channel control register 0x01E1 7010 CH3_CTRL Channel control register 0x01E1 7014 0x01E1 701F Reserved 0x01E1 7020 INTEN Interrupt enable 0x01E1 7024 INTENSET Interrupt enable set 0x01E1 7028 INTENCLR Interrupt enable clear 0x01E1 702C INTSTAT Interrupt status 0x01E1 7030 INTSTATCLR Interrupt status clear 0x01E1 7034 EMU_CTRL Emulation control 0x01E1 7038 DMA_SIZE DMA size control 0x01E1 703C 0x01E1 703F Reserved CAPTURE CHANNEL REGISTERS 0x01E1 7040 CH0_TY_STRTADR Channel Top Field luma buffer start address 0x01E1 7044 CH0_BY_STRTADR Channel Bottom Field luma buffer start address 0x01E1 7048 CH0_TC_STRTADR Channel Top Field chroma buffer start address 0x01E1 704C CH0_BC_STRTADR Channel Bottom Field chroma buffer start address 0x01E1 7050 CH0_THA_STRTADR Channel Top Field horizontal ancillary data buffer start address 0x01E1 7054 CH0_BHA_STRTADR Channel Bottom Field horizontal ancillary data buffer start address 0x01E1 7058 CH0_TVA_STRTADR Channel Top Field vertical ancillary data buffer start address 0x01E1 705C CH0_BVA_STRTADR Channel Bottom Field vertical ancillary data buffer start address 0x01E1 7060 CH0_SUBPIC_CFG Channel sub-picture configuration 0x01E1 7064 CH0_IMG_ADD_OFST Channel image data address offset 0x01E1 7068 CH0_HA_ADD_OFST Channel horizontal ancillary data address offset 0x01E1 706C CH0_HSIZE_CFG Channel horizontal data size configuration 0x01E1 7070 CH0_VSIZE_CFG0 Channel vertical data size configuration (0) 0x01E1 7074 CH0_VSIZE_CFG1 Channel vertical data size configuration (1) 0x01E1 7078 CH0_VSIZE_CFG2 Channel vertical data size configuration (2) 0x01E1 707C CH0_VSIZE Channel vertical image size CAPTURE CHANNEL REGISTERS 0x01E1 7080 CH1_TY_STRTADR Channel Top Field luma buffer start address 0x01E1 7084 CH1_BY_STRTADR Channel Bottom Field luma buffer start address 0x01E1 7088 CH1_TC_STRTADR Channel Top Field chroma buffer start address 0x01E1 708C CH1_BC_STRTADR Channel Bottom Field chroma buffer start address 0x01E1 7090 CH1_THA_STRTADR Channel Top Field horizontal ancillary data buffer start address 0x01E1 7094 CH1_BHA_STRTADR Channel Bottom Field horizontal ancillary data buffer start address 0x01E1 7098 CH1_TVA_STRTADR Channel Top Field vertical ancillary data buffer start address 0x01E1 709C CH1_BVA_STRTADR Channel Bottom Field vertical ancillary data buffer start address 0x01E1 70A0 CH1_SUBPIC_CFG Channel sub-picture configuration 0x01E1 70A4 CH1_IMG_ADD_OFST Channel image data address offset 0x01E1 70A8 CH1_HA_ADD_OFST Channel horizontal ancillary data address offset 0x01E1 70AC CH1_HSIZE_CFG Channel horizontal data size configuration Submit Documentation Feedback Peripheral Information and Electrical Specifications 229

www.ti.com Table 6-111. Video Port Interface (VPIF) Registers (continued) BYTE ADDRESS ACRONYM REGISTER CH1_VSIZE_CFG0 Channel vertical data size configuration (0) 0x01E1 70B4 CH1_VSIZE_CFG1 Channel vertical data size configuration (1) 0x01E1 70B8 CH1_VSIZE_CFG2 Channel vertical data size configuration (2) 0x01E1 70BC CH1_VSIZE Channel vertical image size DISPLAY CHANNEL REGISTERS 0x01E1 70C0 CH2_TY_STRTADR Channel Top Field luma buffer start address 0x01E1 70C4 CH2_BY_STRTADR Channel Bottom Field luma buffer start address 0x01E1 70C8 CH2_TC_STRTADR Channel Top Field chroma buffer start address 0x01E1 70CC CH2_BC_STRTADR Channel Bottom Field chroma buffer start address 0x01E1 70D0 CH2_THA_STRTADR Channel Top Field horizontal ancillary data buffer start address 0x01E1 70D4 CH2_BHA_STRTADR Channel Bottom Field horizontal ancillary data buffer start address 0x01E1 70D8 CH2_TVA_STRTADR Channel Top Field vertical ancillary data buffer start address 0x01E1 70DC CH2_BVA_STRTADR Channel Bottom Field vertical ancillary data buffer start address 0x01E1 70E0 CH2_SUBPIC_CFG Channel sub-picture configuration 0x01E1 70E4 CH2_IMG_ADD_OFST Channel image data address offset 0x01E1 70E8 CH2_HA_ADD_OFST Channel horizontal ancillary data address offset 0x01E1 70EC CH2_HSIZE_CFG Channel horizontal data size configuration 0x01E1 70F0 CH2_VSIZE_CFG0 Channel vertical data size configuration (0) 0x01E1 70F4 CH2_VSIZE_CFG1 Channel vertical data size configuration (1) 0x01E1 70F8 CH2_VSIZE_CFG2 Channel vertical data size configuration (2) 0x01E1 70FC CH2_VSIZE Channel vertical image size 0x01E1 7100 CH2_THA_STRTPOS Channel Top Field horizontal ancillary data insertion start position 0x01E1 7104 CH2_THA_SIZE Channel Top Field horizontal ancillary data size 0x01E1 7108 CH2_BHA_STRTPOS Channel Bottom Field horizontal ancillary data insertion start position 0x01E1 710C CH2_BHA_SIZE Channel Bottom Field horizontal ancillary data size 0x01E1 7110 CH2_TVA_STRTPOS Channel Top Field vertical ancillary data insertion start position 0x01E1 7114 CH2_TVA_SIZE Channel Top Field vertical ancillary data size 0x01E1 7118 CH2_BVA_STRTPOS Channel Bottom Field vertical ancillary data insertion start position 0x01E1 711C CH2_BVA_SIZE Channel Bottom Field vertical ancillary data size 0x01E1 7120 0x01E1 713F Reserved DISPLAY CHANNEL REGISTERS 0x01E1 7140 CH3_TY_STRTADR Channel Field luma buffer start address 0x01E1 7144 CH3_BY_STRTADR Channel Field luma buffer start address 0x01E1 7148 CH3_TC_STRTADR Channel Field chroma buffer start address 0x01E1 714C CH3_BC_STRTADR Channel Field chroma buffer start address 0x01E1 7150 CH3_THA_STRTADR Channel Field horizontal ancillary data buffer start address 0x01E1 7154 CH3_BHA_STRTADR Channel Field horizontal ancillary data buffer start address 0x01E1 7158 CH3_TVA_STRTADR Channel Field vertical ancillary data buffer start address 0x01E1 715C CH3_BVA_STRTADR Channel Field vertical ancillary data buffer start address 0x01E1 7160 CH3_SUBPIC_CFG Channel sub-picture configuration 0x01E1 7164 CH3_IMG_ADD_OFST Channel image data address offset 0x01E1 7168 CH3_HA_ADD_OFST Channel horizontal ancillary data address offset 0x01E1 716C CH3_HSIZE_CFG Channel horizontal data size configuration 0x01E1 7170 CH3_VSIZE_CFG0 Channel vertical data size configuration (0) 0x01E1 7174 CH3_VSIZE_CFG1 Channel vertical data size configuration (1) 0x01E1 7178 CH3_VSIZE_CFG2 Channel vertical data size configuration (2) 0x01E1 717C CH3_VSIZE Channel vertical image size Peripheral Information and Electrical Specifications 230 Submit Documentation Feedback

www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 6-111. Video Port Interface (VPIF) Registers (continued) BYTE ADDRESS ACRONYM REGISTER CH3_THA_STRTPOS Channel Top Field horizontal ancillary data insertion start position 0x01E1 7184 CH3_THA_SIZE Channel Top Field horizontal ancillary data size 0x01E1 7188 CH3_BHA_STRTPOS Channel Bottom Field horizontal ancillary data insertion start position 0x01E1 718C CH3_BHA_SIZE Channel Bottom Field horizontal ancillary data size 0x01E1 7190 CH3_TVA_STRTPOS Channel Top Field vertical ancillary data insertion start position 0x01E1 7194 CH3_TVA_SIZE Channel Top Field vertical ancillary data size 0x01E1 7198 CH3_BVA_STRTPOS Channel Bottom Field vertical ancillary data insertion start position 0x01E1 719C CH3_BVA_SIZE Channel Bottom Field vertical ancillary data size 0x01E1 71A0 0x01E1 71FF Reserved Submit Documentation Feedback Peripheral Information and Electrical Specifications 231

6.26.2 VPIF Electrical Data/Timing VP_CLKINx 2 3 1 4 OMAP-L138 Low-Power www.ti.com Table 6-112. Timing Requirements for VPIF VP_CLKINx Inputs (1) (see Figure 6-74 1.2V 1.1V 1.0V NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX Cycle time, VP_CLKIN0 13.3 26.6 ns t c(VKI) Cycle time, VP_CLKIN1/2/3 13.3 26.6 ns t w(VKIH) Pulse duration, VP_CLKINx high 0.4C 0.4C 0.4C ns t w(VKIL) Pulse duration, VP_CLKINx low 0.4C 0.4C 0.4C ns t t(VKI) Transition time, VP_CLKINx ns (1) C VP_CLKINx period in ns. Figure 6-74. Video Port Capture VP_CLKINx Timing Peripheral Information and Electrical Specifications 232 Submit Documentation Feedback

VP_CLKIN0/1 VP_DINx/FIELD/ HSYNC/VSYNC VP_CLKOUTx (Positive□Edge Clocking) VP_CLKOUTx (Negative□Edge Clocking) VP_DOUTx 11 12 OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 6-113. Timing Requirements for VPIF Channels Video Capture Data and Control Inputs (see Figure 6-75 1.2V 1.1V 1.0V NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX t su(VDINV-VKIH) Setup time, VP_DINx valid before VP_CLKIN0/1 high ns t h(VKIH-VDINV) Hold time, VP_DINx valid after VP_CLKIN0/1 high ns Figure 6-75. VPIF Channels Video Capture Data and Control Input Timing Table 6-114. Switching Characteristics Over Recommended Operating Conditions for Video Data Shown With Respect to VP_CLKOUT2/3 (1) (see Figure 6-76 1.2V 1.1V 1.0V NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX t c(VKO) Cycle time, VP_CLKOUT2/3 13.3 26.6 ns t w(VKOH) Pulse duration, VP_CLKOUT2/3 high 0.4C 0.4C 0.4C ns t w(VKOL) Pulse duration, VP_CLKOUT2/3 low 0.4C 0.4C 0.4C ns t t(VKO) Transition time, VP_CLKOUT2/3 ns Delay time, t d(VKOH-VPDOUTV) 8.5 ns VP_CLKOUT2/3 high to VP_DOUTx valid Delay time, t d(VCLKOH-VPDOUTIV) 1.5 1.5 1.5 ns VP_CLKOUT2/3 high to VP_DOUTx invalid (1) C VP_CLKO2/3 period in ns. Figure 6-76. VPIF Channels Video Display Data Output Timing With Respect to VP_CLKOUT2/3 Submit Documentation Feedback Peripheral Information and Electrical Specifications 233

6.27 Enhanced Capture (eCAP) Peripheral OMAP-L138 Low-Power www.ti.com The device contains up to three enhanced capture (eCAP) modules. Figure 6-77 shows a functional block diagram of a module. Uses for ECAP include: Speed measurements of rotating machinery (e.g. toothed sprockets sensed via Hall sensors) Elapsed time measurements between position sensor triggers Period and duty cycle measurements of pulse train signals Decoding current or voltage amplitude derived from duty cycle encoded current/voltage sensors The ECAP module described in this specification includes the following features: bit time base event time-stamp registers (each bits) Edge polarity selection for up to sequenced time-stamp capture events Interrupt on either of the events Single shot capture of up to event time-stamps Continuous mode capture of time-stamps in a deep circular buffer Absolute time-stamp capture Difference mode time-stamp capture All the above resources are dedicated to a single input pin The eCAP modules are clocked at the ASYNC3 clock domain rate. The clock enable bits (ECAP1/2/3/4ENCLK) in the PCLKCR1 register are used to turn off the eCAP modules individually (for low power operation). Upon reset, ECAP1ENCLK, ECAP2ENCLK, ECAP3ENCLK, and ECAP4EN CLK are set to low, indicating that the peripheral clock is off. 234 Peripheral Information and Electrical Specifications Submit Documentation Feedback

(counter−32 bit) RST CAP1 (APRD active) LD CAP2 (ACMP active) LD CAP3 (APRD shadow) LD CAP4 (ACMP shadow) LD Continuous / Oneshot Capture Control LD1 LD2 LD3 LD4 PRD [0−31] CMP [0−31] CTR [0−31] eCAPx Interrupt Trigger and Flag control to Interrupt Controller CTR=CMP ACMP shadow Event Pre-scale CTRPHS (phase register−32 bit) SYNCOut SYNCIn Event qualifier Polarity select Polarity select Polarity select Polarity select CTR=PRD CTR_OVF PWM compare logic CTR [0−31] PRD [0−31] CMP [0−31] CTR=CMP CTR=PRD CTR_OVFOVF APWM mode Delta−mode SYNC 4Capture events CEVT[1:4] APRD shadow MODE SELECT OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Figure 6-77. eCAP Functional Block Diagram Submit Documentation Feedback Peripheral Information and Electrical Specifications 235

www.ti.com Table 6-115 is the list of the ECAP registers. Table 6-115. ECAPx Configuration Registers ECAP0 ECAP1 ECAP2 REGISTER NAME characteristics. Table 6-116. Timing Requirements for Enhanced Capture (eCAP) PARAMETER TEST CONDITIONS 1.2V, 1.1V, 1.0V MIN MAX UNIT t w(CAP) Capture input pulse width Asynchronous c(SCO) cycles Synchronous c(SCO) cycles Table 6-117. Switching Characteristics Over Recommended Operating Conditions for eCAP PARAMETER 1.2V 1.1V 1.0V UNIT MIN MAX MIN MAX MIN MAX t w(APWM) Pulse duration, APWMx output high/low ns Peripheral Information and Electrical Specifications 236 Submit Documentation Feedback

6.28 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Peripheral□Bus ePWM0 module ePWM1 module EPWM0SYNCI EPWM1SYNCI EPWM1SYNCO GPIO MUX EPWMSYNCI EPWM1A EPWM1B EPWM0A EPWM0B EPWM0INT EPWM1INT TZ TZ EPWM0SYNCOInterrupt Controllers EPWMSYNCOTo□eCAP0 module (sync□in) OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 The device contains two enhanced PWM Modules (eHRPWM). Figure 6-78 shows a block diagram of multiple eHRPWM modules. Figure 4-4 shows the signal interconnections with the eHRPWM. Figure 6-78. Multiple PWM Modules in a OMAP-L138 System Submit Documentation Feedback Peripheral Information and Electrical Specifications 237

CTR=PRD TBPRD shadow (16) TBPRD active (16) Counter up/down (16 bit) TBCNT active (16) TBCTL[CNTLDE] TBCTL[SWFSYNC] (software forced sync) EPWMSYNCI CTR=ZERO CTR_Dir CTR=CMPB Disabled Sync in/out select Mux TBCTL[SYNCOSEL] EPWMSYNCO TBPHS active (24) 16 8 TBPHSHR (8) Phase control Time−base (TB) CTR=CMPA CMP A active (24) CMP A shadow (24) Action qualifier (AQ) Counter compare (CC) CMPB active (16) CTR=CMPB CMPB shadow (16) CMP AHR (8) EPWMA EPWMB Dead band (DB) (PC) chopper PWM zone (TZ) Trip CTR = ZERO EPWMxA EPWMxB EPWMxTZINT TZ HiRes PWM (HRPWM) CTR = PRD CTR = ZERO CTR = CMPB CTR = CMP A CTR_Dir Event trigger and interrupt (ET) EPWMxINT CTR=ZERO OMAP-L138 Low-Power www.ti.com Figure 6-79. eHRPWM Sub-Modules Showing Critical Internal Signal Interconnections Peripheral Information and Electrical Specifications 238 Submit Documentation Feedback

www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 6-118. eHRPWM Module Control and Status Registers Grouped by Submodule eHRPWM0 eHRPWM1 BYTE ADDRESS BYTE ADDRESS Acronym Shadow Register (1) 0x01F0 0006 0x01F0 2006 TBPHS No Time-Base Phase Register 0x01F0 0008 0x01F0 2008 TBCNT No Time-Base Counter Register 0x01F0 000A 0x01F0 200A TBPRD Yes Time-Base Period Register Counter-Compare Submodule Registers 0x01F0 000E 0x01F0 200E CMPCTL No Counter-Compare Control Register 0x01F0 0010 0x01F0 2010 CMPAHR No Extension for HRPWM Counter-Compare A Register (1) 0x01F0 0012 0x01F0 2012 CMPA Yes Counter-Compare A Register 0x01F0 0014 0x01F0 2014 CMPB Yes Counter-Compare B Register Action-Qualifier Submodule Registers 0x01F0 0016 0x01F0 2016 AQCTLA No Action-Qualifier Control Register for Output A (eHRPWMxA) 0x01F0 0018 0x01F0 2018 AQCTLB No Action-Qualifier Control Register for Output B (eHRPWMxB) 0x01F0 001A 0x01F0 201A AQSFRC No Action-Qualifier Software Force Register 0x01F0 001C 0x01F0 201C AQCSFRC Yes Action-Qualifier Continuous S/W Force Register Set Dead-Band Generator Submodule Registers 0x01F0 001E 0x01F0 201E DBCTL No Dead-Band Generator Control Register 0x01F0 0020 0x01F0 2020 DBRED No Dead-Band Generator Rising Edge Delay Count Register 0x01F0 0022 0x01F0 2022 DBFED No Dead-Band Generator Falling Edge Delay Count Register PWM-Chopper Submodule Registers 0x01F0 003C 0x01F0 203C PCCTL No PWM-Chopper Control Register Trip-Zone Submodule Registers 0x01F0 0024 0x01F0 2024 TZSEL No Trip-Zone Select Register 0x01F0 0028 0x01F0 2028 TZCTL No Trip-Zone Control Register 0x01F0 002A 0x01F0 202A TZEINT No Trip-Zone Enable Interrupt Register 0x01F0 002C 0x01F0 202C TZFLG No Trip-Zone Flag Register 0x01F0 002E 0x01F0 202E TZCLR No Trip-Zone Clear Register 0x01F0 0030 0x01F0 2030 TZFRC No Trip-Zone Force Register Event-Trigger Submodule Registers 0x01F0 0032 0x01F0 2032 ETSEL No Event-Trigger Selection Register 0x01F0 0034 0x01F0 2034 ETPS No Event-Trigger Pre-Scale Register 0x01F0 0036 0x01F0 2036 ETFLG No Event-Trigger Flag Register 0x01F0 0038 0x01F0 2038 ETCLR No Event-Trigger Clear Register 0x01F0 003A 0x01F0 203A ETFRC No Event-Trigger Force Register High-Resolution PWM (HRPWM) Submodule Registers 0x01F0 1020 0x01F0 3020 HRCNFG No HRPWM Configuration Register (1) (1) These registers are only available on eHRPWM instances that include the high-resolution PWM (HRPWM) extension; otherwise, these locations are reserved. Submit Documentation Feedback Peripheral Information and Electrical Specifications 239

6.28.1 Enhanced Pulse Width Modulator (eHRPWM) Timing OMAP-L138 Low-Power www.ti.com PWM refers to PWM outputs on eHRPWM1-6. Table 6-119 shows the PWM timing requirements and Table 6-120 switching characteristics. Table 6-119. Timing Requirements for eHRPWM PARAMETER TEST CONDITIONS 1.2V, 1.1V, 1.0V UNIT MIN MAX t w(SYNCIN) Sync input pulse width Asynchronous c(SCO) cycles Synchronous c(SCO) cycles Table 6-120. Switching Characteristics Over Recommended Operating Conditions for eHRPWM PARAMETER TEST 1.2V 1.1V 1.0V UNIT CONDITIONS MIN MAX MIN MAX MIN MAX t w(PWM) Pulse duration, PWMx output ns TBD TBD high/low t w(SYNCOUT) Sync output pulse width c(SCO) c(SCO) c(SCO) cycles t d(PWM)TZA Delay time, trip input active to no pin load ns PWM forced high TBD TBD Delay time, trip input active to PWM forced low t d(TZ-PWM)HZ Delay time, trip input active to ns TBD TBD PWM Hi-Z Peripheral Information and Electrical Specifications 240 Submit Documentation Feedback

6.28.2 Trip-Zone Input Timing PWM (A) TZ tw(TZ) td(TZ-PWM)HZ OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM recovery software. Figure 6-80. PWM Hi-Z Characteristics Table 6-121. Trip-Zone input Timing Requirements PARAMETER TEST CONDITIONS 1.2V, 1.1V, 1.0V MIN MAX UNIT t w(TZ) Pulse duration, TZx input low Asynchronous c(SCO) cycles Synchronous c(SCO) cycles Table 6-122 shows the high-resolution PWM switching characteristics. Table 6-122. High Resolution PWM Characteristics at SYSCLKOUT (60 100 MHz) PARAMETER 1.2V 1.1V 1.0V MIN TYP MAX MIN TYP MAX MIN TYP MAX UNIT Micro Edge Positioning (MEP) step size (1) 200 TBD TBD ps (1) Maximum MEP step size is based on worst-case process, maximum temperature and maximum voltage. MEP step size will increase with low voltage and high temperature and decrease with voltage and cold temperature. (SFO) estimation software functions. See the TI software libraries for details of using SFO function in end applications. SFO functions help to estimate the number of MEP steps per SYSCLKOUT period dynamically while the HRPWM is in operation. Submit Documentation Feedback Peripheral Information and Electrical Specifications 241

6.29 Timers OMAP-L138 Low-Power www.ti.com The timers support the following features: Configurable as single 64-bit timer or two 32-bit timers Period timeouts generate interrupts, DMA events or external pin events 32-bit compare registers Compare matches generate interrupt events Capture capability 64-bit Watchdog capability (Timer64P1 only) Table 6-123 lists the timer registers. Table 6-123. Timer Registers TIMER64P TIMER64P TIMER64P TIMER64P ACRONYM REGISTER

6.29.1 Timer Electrical Data/Timing TM64P0_IN12 TM64P0_OUT12 5 6 OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 6-124. Timing Requirements for Timer Input (1) (2) (see Figure 6-81 1.2V, 1.1V, 1.0V NO. PARAMETER UNIT MIN MAX t c(TM64Px_IN12) Cycle time, TM64Px_IN12 ns t w(TINPH) Pulse duration, TM64Px_IN12 high 0.45C 0.55C ns t w(TINPL) Pulse duration, TM64Px_IN12 low 0.45C 0.55C ns t t(TM64Px_IN12) Transition time, TM64Px_IN12 0.05C ns (1) P OSCIN cycle time in ns. For example, when OSCIN frequency is MHz, use P 37.0 ns. (2) C TM64P0_IN12 cycle time in ns. For example, when TM64Px_IN12 frequency is MHz, use C 37.0 ns Figure 6-81. Timer Timing Table 6-125. Switching Characteristics Over Recommended Operating Conditions for Timer Output (1) 1.2V, 1.1V, 1.0V NO. PARAMETER UNIT MIN MAX t w(TOUTH) Pulse duration, TM64P0_OUT12 high ns t w(TOUTL) Pulse duration, TM64P0_OUT12 low ns (1) P OSCIN cycle time in ns. For example, when OSCIN frequency is MHz, use P 37.0 ns. Figure 6-82. Timer Timing Submit Documentation Feedback Peripheral Information and Electrical Specifications 243

6.30 Real Time Clock (RTC) Seconds Minutes Hours Days Months Years Alarm Timer Alarm Interrupts Periodic Interrupts Counter 32□kHz Oscillator Compensation Week Days Oscillator RTC_XI XTAL RTC_XO OMAP-L138 Low-Power www.ti.com The RTC provides a time reference to an application running on the device. The current date and time is tracked in a set of counter registers that update once per second. The time can be represented in 12-hour or 24-hour mode. The calendar and time registers are buffered during reads and writes so that updates do not interfere with the accuracy of the time and date. Alarms are available to interrupt the CPU at a particular time, or at periodic time intervals, such as once per minute or once per day. In addition, the RTC can interrupt the CPU every time the calendar and time registers are updated, or at programmable periodic intervals. The real-time clock (RTC) provides the following features: 100-year calendar (xx00 to xx99) Counts seconds, minutes, hours, day of the week, date, month, and year with leap year compensation Binary-coded-decimal (BCD) representation of time, calendar, and alarm 12-hour clock mode (with AM and PM) or 24-hour clock mode Alarm interrupt Periodic interrupt Single interrupt to the CPU Supports external 32.768-kHz crystal or external clock source of the same frequency Separate isolated power supply Figure 6-83 shows a block diagram of the RTC. Figure 6-83. Real-Time Clock Block Diagram 244 Peripheral Information and Electrical Specifications Submit Documentation Feedback

6.30.1 Clock Source XTAL 32.768 kHz RTC_X1 RTC_X0 RTC_VSS 32K OSC Real Time Clock (RTC) Module Isolated□RTC Power□Domain Switch□for□Device Core□Power Real□Time□Clock +1.2V CV DD RTC_CVDD OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 The clock reference for the RTC is an external 32.768-kHz crystal or an external clock source of the same frequency. The RTC also has a separate power supply that is isolated from the rest of the system. When the CPU and other peripherals are without power, the RTC can remain powered to preserve the current time and calendar information. Even if the RTC is not used, it must remain powered when the rest of the device is powered. The source for the RTC reference clock may be provided by a crystal or by an external clock source. The RTC has an internal oscillator buffer to support direct operation with a crystal. The crystal is connected between pins RTC_XI and RTC_XO. RTC_XI is the input to the on-chip oscillator and RTC_XO is the output from the oscillator back to the crystal. An external 32.768-kHz clock source may be used instead of a crystal. In such a case, the clock source is connected to RTC_XI, and RTC_XO is left unconnected. If the RTC is not used, the RTC_XI pin should be held either low or high, RTC_XO should be left unconnected, RTC_CVDD should be connected to the device CVDD and RTC_VSS should remain grounded. Figure 6-84. Clock Source Submit Documentation Feedback Peripheral Information and Electrical Specifications 245

6.30.2 Registers OMAP-L138 Low-Power www.ti.com Table 6-126 lists the memory-mapped registers for the RTC. See the device-specific data manual for the memory address of these registers. Table 6-126. Real-Time Clock (RTC) Registers BYTE ADDRESS ACRONYM REGISTER (LSB) Register 0x01C2 3050 COMPMSB Compensation (MSB) Register 0x01C2 3054 OSC Oscillator Register 0x01C2 3060 SCRATCH0 Scratch (General-Purpose) Register 0x01C2 3064 SCRATCH1 Scratch (General-Purpose) Register 0x01C2 3068 SCRATCH2 Scratch (General-Purpose) Register 0x01C2 306C KICK0 Kick (Write Protect) Register 0x01C2 3070 KICK1 Kick (Write Protect) Register Peripheral Information and Electrical Specifications 246 Submit Documentation Feedback

6.31 General-Purpose Input/Output (GPIO) OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 The GPIO peripheral provides general-purpose pins that can be configured as either inputs or outputs. When configured as an output, a write to an internal register can control the state driven on the output pin. When configured as an input, the state of the input is detectable by reading the state of an internal register. In addition, the GPIO peripheral can produce CPU interrupts and EDMA events in different interrupt/event generation modes. The GPIO peripheral provides generic connections to external devices. The GPIO pins are grouped into banks of pins per bank (i.e., bank consists of GPIO [0:15]). The device GPIO peripheral supports the following: Up to 144 Pins configurable as GPIO External Interrupt and DMA request Capability Every GPIO pin may be configured to generate an interrupt request on detection of rising and/or falling edges on the pin. The interrupt requests within each bank are combined (logical or) to create eight unique bank level interrupt requests. The bank level interrupt service routine may poll the INTSTATx register for its bank to determine which pin(s) have triggered the interrupt. GPIO Banks and Interrupts assigned to ARM INTC Interrupt Requests 42, 43, 44, 45, 46, 47, 48, and respectively GPIO Banks and Interrupts assigned to DSP Events 65, 41, 49, 52, 54, 59, 62, and respectively GPIO Banks and are assigned to EDMA events 22, 23, 28, 29, and respectively on Channel Controller and GPIO Banks and are assigned to EDMA events 16, 17, and respectively on Channel Controller Set/clear functionality: Firmware writes to corresponding bit position(s) to set or to clear GPIO signal(s). This allows multiple firmware processes to toggle GPIO output signals without critical section protection (disable interrupts, program GPIO, re-enable interrupts, to prevent context switching to anther process during GPIO programming). Separate Input/Output registers Output register in addition to set/clear so that, if preferred by firmware, some GPIO output signals can be toggled by direct write to the output register(s). Output register, when read, reflects output drive status. This, in addition to the input register reflecting pin status and open-drain I/O cell, allows wired logic be implemented. The memory map for the GPIO registers is shown in Table 6-127 Submit Documentation Feedback Peripheral Information and Electrical Specifications 247

6.31.1 GPIO Register Description(s) OMAP-L138 Low-Power www.ti.com Table 6-127. GPIO Registers BYTE ADDRESS ACRONYM REGISTER OUT_DATA01 GPIO Banks and Output Data Register 0x01E2 6018 SET_DATA01 GPIO Banks and Set Data Register 0x01E2 601C CLR_DATA01 GPIO Banks and Clear Data Register 0x01E2 6020 IN_DATA01 GPIO Banks and Input Data Register 0x01E2 6024 SET_RIS_TRIG01 GPIO Banks and Set Rising Edge Interrupt Register 0x01E2 6028 CLR_RIS_TRIG01 GPIO Banks and Clear Rising Edge Interrupt Register 0x01E2 602C SET_FAL_TRIG01 GPIO Banks and Set Falling Edge Interrupt Register 0x01E2 6030 CLR_FAL_TRIG01 GPIO Banks and Clear Falling Edge Interrupt Register 0x01E2 6034 INTSTAT01 GPIO Banks and Interrupt Status Register GPIO Banks and 0x01E2 6038 DIR23 GPIO Banks and Direction Register 0x01E2 603C OUT_DATA23 GPIO Banks and Output Data Register 0x01E2 6040 SET_DATA23 GPIO Banks and Set Data Register 0x01E2 6044 CLR_DATA23 GPIO Banks and Clear Data Register 0x01E2 6048 IN_DATA23 GPIO Banks and Input Data Register 0x01E2 604C SET_RIS_TRIG23 GPIO Banks and Set Rising Edge Interrupt Register 0x01E2 6050 CLR_RIS_TRIG23 GPIO Banks and Clear Rising Edge Interrupt Register 0x01E2 6054 SET_FAL_TRIG23 GPIO Banks and Set Falling Edge Interrupt Register 0x01E2 6058 CLR_FAL_TRIG23 GPIO Banks and Clear Falling Edge Interrupt Register 0x01E2 605C INTSTAT23 GPIO Banks and Interrupt Status Register GPIO Banks and 0x01E2 6060 DIR45 GPIO Banks and Direction Register 0x01E2 6064 OUT_DATA45 GPIO Banks and Output Data Register 0x01E2 6068 SET_DATA45 GPIO Banks and Set Data Register 0x01E2 606C CLR_DATA45 GPIO Banks and Clear Data Register 0x01E2 6070 IN_DATA45 GPIO Banks and Input Data Register 0x01E2 6074 SET_RIS_TRIG45 GPIO Banks and Set Rising Edge Interrupt Register 0x01E2 6078 CLR_RIS_TRIG45 GPIO Banks and Clear Rising Edge Interrupt Register 0x01E2 607C SET_FAL_TRIG45 GPIO Banks and Set Falling Edge Interrupt Register 0x01E2 6080 CLR_FAL_TRIG45 GPIO Banks and Clear Falling Edge Interrupt Register 0x01E2 6084 INTSTAT45 GPIO Banks and Interrupt Status Register GPIO Banks and 0x01E2 6088 DIR67 GPIO Banks and Direction Register 0x01E2 608C OUT_DATA67 GPIO Banks and Output Data Register 0x01E2 6090 SET_DATA67 GPIO Banks and Set Data Register 0x01E2 6094 CLR_DATA67 GPIO Banks and Clear Data Register 0x01E2 6098 IN_DATA67 GPIO Banks and Input Data Register 0x01E2 609C SET_RIS_TRIG67 GPIO Banks and Set Rising Edge Interrupt Register 0x01E2 60A0 CLR_RIS_TRIG67 GPIO Banks and Clear Rising Edge Interrupt Register 0x01E2 60A4 SET_FAL_TRIG67 GPIO Banks and Set Falling Edge Interrupt Register Peripheral Information and Electrical Specifications 248 Submit Documentation Feedback

www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 6-127. GPIO Registers (continued) BYTE ADDRESS ACRONYM REGISTER CLR_FAL_TRIG67 GPIO Banks and Clear Falling Edge Interrupt Register 0x01E2 60AC INTSTAT67 GPIO Banks and Interrupt Status Register GPIO Bank 0x01E2 60B0 DIR8 GPIO Bank Direction Register 0x01E2 60B4 OUT_DATA8 GPIO Bank Output Data Register 0x01E2 60B8 SET_DATA8 GPIO Bank Set Data Register 0x01E2 60BC CLR_DATA8 GPIO Bank Clear Data Register 0x01E2 60C0 IN_DATA8 GPIO Bank Input Data Register 0x01E2 60C4 SET_RIS_TRIG8 GPIO Bank Set Rising Edge Interrupt Register 0x01E2 60C8 CLR_RIS_TRIG8 GPIO Bank Clear Rising Edge Interrupt Register 0x01E2 60CC SET_FAL_TRIG8 GPIO Bank Set Falling Edge Interrupt Register 0x01E2 60D0 CLR_FAL_TRIG8 GPIO Bank Clear Falling Edge Interrupt Register 0x01E2 60D4 INTSTAT8 GPIO Bank Interrupt Status Register Submit Documentation Feedback Peripheral Information and Electrical Specifications 249

6.31.2 GPIO Peripheral Input/Output Electrical Data/Timing GP [ ] as□input n m GPn m[ ] as□output 6.31.3 GPIO Peripheral External Interrupts Electrical Data/Timing GP [ ] as□input n m OMAP-L138 Low-Power www.ti.com Table 6-128. Timing Requirements for GPIO Inputs (1) (see Figure 6-85 1.2V, 1.1V, 1.0V NO. UNIT MIN MAX t w(GPIH) Pulse duration, GP n m as input high (1) (2) ns t w(GPIL) Pulse duration, GP n m as input low (1) (2) ns (1) The pulse width given is sufficient to generate a CPU interrupt or an EDMA event. However, if a user wants to have the device recognize the GPIx changes through software polling of the GPIO register, the GPIx duration must be extended to allow the device enough time to access the GPIO register through the internal bus. (2) C=SYSCLK4 period in ns. Table 6-129. Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs (see Figure 6-85 1.2V, 1.1V, 1.0V NO. PARAMETER UNIT MIN MAX t w(GPOH) Pulse duration, GP n m as output high (1) (2) ns t w(GPOL) Pulse duration, GP n m as output low (1) (2) ns (1) This parameter value should not be used as a maximum performance specification. Actual performance of back-to-back accesses of the GPIO is dependent upon internal bus activity. (2) C=SYSCLK4 period in ns. Figure 6-85. GPIO Port Timing Table 6-130. Timing Requirements for External Interrupts (1) (see Figure 6-86 1.2V, 1.1V, 1.0V NO. UNIT MIN MAX t w(ILOW) Width of the external interrupt pulse low (1) (2) ns t w(IHIGH) Width of the external interrupt pulse high (1) (2) ns (1) The pulse width given is sufficient to generate an interrupt or an EDMA event. However, if a user wants to have the device recognize the GPIO changes through software polling of the GPIO register, the GPIO duration must be extended to allow the device enough time to access the GPIO register through the internal bus. (2) C=SYSCLK4 period in ns. Figure 6-86. GPIO External Interrupt Timing 250 Peripheral Information and Electrical Specifications Submit Documentation Feedback

6.32 Programmable Real-Time Unit Subsystem (PRUSS) OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 The Programmable Real-Time Unit Subsystem (PRUSS) consists of Two Programmable Real-Time Units (PRU0 and PRU1) and their associated memories An Interrupt Controller (INTC) for handling system interrupt events. The INTC also supports posting events back to the device level host CPU. A Switched Central Resource (SCR) for connecting the various internal and external masters to the resources inside the PRUSS. The two PRUs can operate completely independently or in coordination with each other. The PRUs can also work in coordination with the device level host CPU. This is determined by the nature of the program which is loaded into the PRUs instruction memory. Several different signaling mechanisms are available between the two PRUs and the device level host CPU. The PRUs are optimized for performing embedded tasks that require manipulation of packed memory mapped data structures, handling of system events that have tight realtime constraints and interfacing with systems external to the device. The PRUSS comprises various distinct addressable regions. Externally the subsystem presents a single 64Kbyte range of addresses. The internal interconnect bus (also called switched central resource, or SCR) of the PRUSS decodes accesses for each of the individual regions. The PRUSS memory map is documented in Table 6-131 and in Table 6-132 Note that these two memory maps are implemented inside the PRUSS and are local to the components of the PRUSS. Table 6-131. Programmable Real-Time Unit Subsystem (PRUSS) Local Instruction Space Memory Map BYTE ADDRESS PRU0 PRU1 0x0000 0000 0x0000 0FFF PRU0 Instruction RAM PRU1 Instruction RAM Table 6-132. Programmable Real-Time Unit Subsystem (PRUSS) Local Data Space Memory Map BYTE ADDRESS PRU0 PRU1 0x0000 0000 0x0000 01FF Data RAM (1) Data RAM (1) 0x0000 0200 0x0000 1FFF Reserved Reserved 0x0000 2000 0x0000 21FF Data RAM (1) Data RAM (1) 0x0000 2200 0x0000 3FFF Reserved Reserved 0x0000 4000 0x0000 6FFF INTC Registers INTC Registers 0x0000 7000 0x0000 73FF PRU0 Control Registers PRU0 Control Registers 0x0000 7400 0x0000 77FF Reserved Reserved 0x0000 7800 0x0000 7BFF PRU1 Control Registers PRU1 Control Registers 0x0000 7C00 0xFFFF FFFF Reserved Reserved (1) Note that PRU0 accesses Data RAM at address 0x0000 0000, also PRU1 accesses Data RAM at address 0x0000 0000. Data RAM0 is intended to be the primary data memory for PRU0 and Data RAM1 is intended to be the primary data memory for PRU1. However for passing information between PRUs, each PRU can access the data ram of the other PRU through address 0x0000 2000. The global view of the PRUSS internal memories and control ports is documented in Table 6-133 The offset addresses of each region are implemented inside the PRUSS but the global device memory mapping places the PRUSS slave port in the address range 0x01C3 0000-0x01C3 FFFF. The PRU0 and PRU1 can use either the local or global addresses to access their internal memories, but using the local addresses will provide access time several cycles faster than using the global addresses. This is because when accessing via the global address the access needs to be routed through the switch fabric outside PRUSS and back in through the PRUSS slave port. Submit Documentation Feedback Peripheral Information and Electrical Specifications 251

6.32.1 PRUSS Register Descriptions OMAP-L138 Low-Power www.ti.com Table 6-133. Programmable Real-Time Unit Subsystem (PRUSS) Global Memory Map BYTE ADDRESS REGION 0x01C3 0000 0x01C3 01FF Data RAM 0x01C3 0200 0x01C3 1FFF Reserved 0x01C3 2000 0x01C3 21FF Data RAM 0x01C3 2200 0x01C3 3FFF Reserved 0x01C3 4000 0x01C3 6FFF INTC Registers 0x01C3 7000 0x01C3 73FF PRU0 Control Registers 0x01C3 7400 0x01C3 77FF PRU0 Debug Registers 0x01C3 7800 0x01C3 7BFF PRU1 Control Registers 0x01C3 7C00 0x01C3 7FFF PRU1 Debug Registers 0x01C3 8000 0x01C3 8FFF PRU0 Instruction RAM 0x01C3 9000 0x01C3 BFFF Reserved 0x01C3 C000 0x01C3 CFFF PRU1 Instruction RAM 0x01C3 D000 0x01C3 FFFF Reserved Each of the PRUs can access the rest of the device memory (including memory mapped peripheral and configuration registers) using the global memory space addresses Table 6-134. Programmable Real-Time Unit Subsystem (PRUSS) Control Status Registers PRU0 BYTE ADDRESS PRU1 BYTE ADDRESS ACRONYM REGISTER (for Debug) PRU Internal General Purpose 0x01C37480 0x01C374FC 0x01C3 7C80 0x01C3 7CFC INTCTER0 INTCTER31 Register (for Debug) Table 6-135. Programmable Real-Time Unit Subsystem Interrupt Controller (PRUSS INTC) Registers BYTE ADDRESS ACRONYM REGISTER

www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 6-135. Programmable Real-Time Unit Subsystem Interrupt Controller (PRUSS INTC) Registers (continued) BYTE ADDRESS ACRONYM REGISTER

6.33 Emulation Logic OMAP-L138 Low-Power www.ti.com This section describes the steps to use a third party debugger on the ARM926EJ-S within the device. The debug capabilities and below. DSP: Basic Debug Execution Control System Visibility Real-Time Debug Interrupts serviced while halted Low/non-intrusive system visibility while running Advanced Debug Global Start Global Stop Specify targeted memory level(s) during memory accesses HSRTDX (High Speed Real Time Data eXchange) Advanced System Control Subsystem reset via debug Peripheral notification of debug events Cache-coherent debug accesses Analysis Actions Stop program execution Generate debug interrupt Benchmarking with counters External trigger generation Debug state machine state transition Combinational and Sequential event generation Analysis Events Program event detection Data event detection External trigger Detection System event detection (i.e. cache miss) Debug state machine state detection Analysis Configuration Application access Debugger access Table 6-136. DSP Debug HWBPs, including: Basic Debug precise (1) HWBPs inside DSP core and one of them is associated with a counter. Hardware breakpoint imprecise (1) HWBPs from AET. imprecise (1) HWBPs from AET which are shared for watch point. (1) Precise hardware breakpoints will halt the processor immediately prior to the execution of the selected instruction. Imprecise breakpoints will halt the processor some number of cycles after the selected instruction depending on device conditions. Peripheral Information and Electrical Specifications 254 Submit Documentation Feedback

www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 6-136. DSP Debug (continued) Category Hardware Feature Availability Up to watch points, which are shared with HWBPs, and can also be used as watch Watch point points with data (32 bits) Watch point with Data Up to Which can also be used as watch points. Analysis Counters/timers 1x64-bits (cycle only) 2x32-bits (water mark counters) External Event Trigger In External Event Trigger Out ARM: Basic Debug Execution Control System Visibility Advanced Debug Global Start Global Stop Advanced System Control Subsystem reset via debug Peripheral notification of debug events Cache-coherent debug accesses Program Trace Program flow corruption Code coverage Path coverage Thread/interrupt synchronization problems Data Trace Memory corruption Timing Trace Profiling Analysis Actions Stop program execution Control trace streams Generate debug interrupt Benchmarking with counters External trigger generation Debug state machine state transition Combinational and Sequential event generation Analysis Events Program event detection Data event detection External trigger Detection System event detection (i.e. cache miss) Debug state machine state detection Analysis Configuration Application access Debugger access Submit Documentation Feedback Peripheral Information and Electrical Specifications 255

6.33.1 JTAG Port www.ti.com Table 6-137. ARM Debug HWBPs, including: precise (1) HWBP inside ARM core which are shared with watch points. Basic Debug Hardware breakpoint imprecise (1) HWBPs from ETM s address comparators, which are shared with trace function, and can be used as watch points. imprecise (1) HWBPs from ICECrusher. Up to watch points, including: from ARM core which is shared with HWBPs and can be associated with a data. Watch point from ETM s address comparators, which are shared with trace function, and HWBPs. from ARM core which is shared with HWBPs. Watch point with Data Analysis watch points from ETM can be associated with a data comparator, and ETM has total data comparators. Counters/timers 3x32-bit cycle event) External Event Trigger In External Event Trigger Out Internal Cross-Triggering Signals One between ARM and DSP Address range for trace Data qualification for trace System events for trace control Trace Control Counters/Timers for trace control 2x16-bit State Machines/Sequencers 1x3-State State Machine Context/Thread ID Comparator Independent trigger control units Capture depth PC bytes ETB On-chip Trace Capture depth PC Timing bytes ETB Capture Application accessible Y (1) Precise hardware breakpoints will halt the processor immediately prior to the execution of the selected instruction. Imprecise breakpoints will halt the processor some number of cycles after the selected instruction depending on device conditions. The device target debug interface uses the five standard IEEE 1149.1(JTAG) signals TRST TCK, TMS, TDI, and TDO) a return clock (RTCK) due to the clocking requirements of the ARM926EJ-S and emulation signals EMU0 and EMU1 TRST holds the debug and boundary scan logic in reset (normal DSP operation) when pulled low (its default state). Since TRST has an internal pull-down resistor, this ensures that at power up the device functions in its normal (non-test) operation mode if TRST is not connected. Otherwise, TRST should be driven inactive by the emulator or boundary scan controller. Boundary scan test cannot be performed while the TRST pin is pulled low. Table 6-138. JTAG Port (active low) causes all test and debug logic in the device to be reset TRST I Test Logic Reset along with the IEEE 1149.1 interface This is the test clock used to drive an IEEE 1149.1 TAP state machine and logic. TCK I Test Clock Depending on the emulator attached to this is a free running clock or a gated clock depending on RTCK monitoring. Synchronized TCK. Depending on the emulator attached to, the JTAG signals are RTCK O Returned Test Clock clocked from RTCK or RTCK is monitored by the emulator to gate TCK. TMS I Test Mode Select Directs the next state of the IEEE 1149.1 test access port state machine Peripheral Information and Electrical Specifications 256 Submit Documentation Feedback

6.33.2 Scan Chain Configuration Parameters 6.33.3 Initial Scan Chain Configuration 6.33.3.1 Adding TAPS to the Scan Chain TDO Router TDI StepsCLK TMS Router ARM926EJ-S/ETM OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Table 6-138. JTAG Port (continued) PIN TYPE NAME I Test Data Input Scan data input to the device TDO O Test Data Output Scan data output of the device EMU0 I/O Emulation Channel trigger HSRTDX EMU1 I/O Emulation Channel trigger HSRTDX Table 6-139 shows the TAP configuration details required to configure the router/emulator for this device. Table 6-139. JTAG Port C and has a 6-bit IR length. The first level of debug interface that sees the scan controller is the TAP router module. The debugger can configure the TAP router for serially linking up to TAP controllers or individually scanning one of the TAP controllers without disrupting the IR state of the other TAPs. The TAP router must be programmed to add additional TAPs to the scan chain. The following JTAG scans must be completed to add the ARM926EJ-S to the scan chain. A Power-On Reset (POR) or the JTAG Test-Logic Reset state configures the TAP router to contain only the router s TAP. Figure 6-87. Adding ARM926EJ-S to the scan chain Pre-amble The device whose data reaches the emulator first is listed first in the board configuration file. This device is a pre-amble for all the other devices. This device has the lowest device ID. Post-amble The device whose data reaches the emulator last is listed last in the board configuration file. This device is a post-amble for all the other devices. This device has the highest device ID. Function Update the JTAG preamble and post-amble counts. Parameter The IR pre-amble count is '0'. Parameter The IR post-amble count is '0'. Parameter The DR pre-amble count is '0'. Submit Documentation Feedback Peripheral Information and Electrical Specifications 257

www.ti.com Parameter The DR post-amble count is '0'. Parameter The IR main count is '6'. Parameter The DR main count is '1'. Function Do a send-only JTAG IR/DR scan. Parameter The route to JTAG shift state is 'shortest transition'. Parameter The JTAG shift state is 'shift-ir'. Parameter The JTAG destination state is 'pause-ir'. Parameter The bit length of the command is '6'. Parameter The send data value is '0x00000007'. Parameter The actual receive data is 'discarded'. Function Do a send-only JTAG IR/DR scan. Parameter The route to JTAG shift state is 'shortest transition'. Parameter The JTAG shift state is 'shift-dr'. Parameter The JTAG destination state is 'pause-dr'. Parameter The bit length of the command is '8'. Parameter The send data value is '0x00000089'. Parameter The actual receive data is 'discarded'. Function Do a send-only JTAG IR/DR scan. Parameter The route to JTAG shift state is 'shortest transition'. Parameter The JTAG shift state is 'shift-ir'. Parameter The JTAG destination state is 'pause-ir'. Parameter The bit length of the command is '6'. Parameter The send data value is '0x00000002'. Parameter The actual receive data is 'discarded'. Function Embed the port address in next command. Parameter The port address field is '0x0f000000'. Parameter The port address value is '3'. Function Do a send-only JTAG IR/DR scan. Parameter The route to JTAG shift state is 'shortest transition'. Parameter The JTAG shift state is 'shift-dr'. Parameter The JTAG destination state is 'pause-dr'. Parameter The bit length of the command is '32'. Parameter The send data value is '0xa2002108'. Parameter The actual receive data is 'discarded'. Function Do a send-only all-ones JTAG IR/DR scan. Parameter The JTAG shift state is 'shift-ir'. Parameter The JTAG destination state is 'run-test/idle'. Parameter The bit length of the command is '6'. Parameter The send data value is 'all-ones'. Parameter The actual receive data is 'discarded'. Function Wait for a minimum number of TCLK pulses. Parameter The count of TCLK pulses is '10'. Function Update the JTAG preamble and post-amble counts. Parameter The IR pre-amble count is '0'. Parameter The IR post-amble count is '6'. Parameter The DR pre-amble count is '0'. Parameter The DR post-amble count is '1'. Peripheral Information and Electrical Specifications 258 Submit Documentation Feedback

www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 Parameter The IR main count is '4'. Parameter The DR main count is '1'. The initial scan chain contains only the TAP router module. The following steps must be completed in order to add ETB TAP to the scan chain. Figure 6-88. Adding ETB to the scan chain Function Do a send-only JTAG IR/DR scan. Parameter The route to JTAG shift state is 'shortest transition'. Parameter The JTAG shift state is 'shift-ir'. Parameter The JTAG destination state is 'pause-ir'. Parameter The bit length of the command is '6'. Parameter The send data value is '0x00000007'. Parameter The actual receive data is 'discarded'. Function Do a send-only JTAG IR/DR scan. Parameter The route to JTAG shift state is 'shortest transition'. Parameter The JTAG shift state is 'shift-dr'. Parameter The JTAG destination state is 'pause-dr'. Parameter The bit length of the command is '8'. Parameter The send data value is '0x00000089'. Parameter The actual receive data is 'discarded'. Function Do a send-only JTAG IR/DR scan. Parameter The route to JTAG shift state is 'shortest transition'. Parameter The JTAG shift state is 'shift-ir'. Parameter The JTAG destination state is 'pause-ir'. Parameter The bit length of the command is '6'. Parameter The send data value is '0x00000002'. Parameter The actual receive data is 'discarded'. Function Embed the port address in next command. Parameter The port address field is '0x0f000000'. Parameter The port address value is '3'. Function Do a send-only JTAG IR/DR scan. Parameter The route to JTAG shift state is 'shortest transition'. Parameter The JTAG shift state is 'shift-dr'. Parameter The JTAG destination state is 'pause-dr'. Parameter The bit length of the command is '32'. Parameter The send data value is '0xa3302108'. Parameter The actual receive data is 'discarded'. Submit Documentation Feedback Peripheral Information and Electrical Specifications 259

www.ti.com Function Do a send-only all-ones JTAG IR/DR scan. Parameter The JTAG shift state is 'shift-ir'. Parameter The JTAG destination state is 'run-test/idle'. Parameter The bit length of the command is '6'. Parameter The send data value is 'all-ones'. Parameter The actual receive data is 'discarded'. Function Wait for a minimum number of TCLK pulses. Parameter The count of TCLK pulses is '10'. Function Update the JTAG preamble and post-amble counts. Parameter The IR pre-amble count is '0'. Parameter The IR post-amble count is 4'. Parameter The DR pre-amble count is '0'. Parameter The DR post-amble count is 1'. Parameter The IR main count is '4'. Parameter The DR main count is '1'. Peripheral Information and Electrical Specifications 260 Submit Documentation Feedback

7.1 Device Support 7.1.1 Development Support 7.1.2 Device and Development-Support Tool Nomenclature OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 This section describes the device orderable part numbers, packaging options, materials, thermal and mechanical parameters. TI offers an extensive line of development tools for the device platform, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. The tool's support documentation is electronically available within the Code Composer Studio Integrated Development Environment (IDE). The following products support development of the device applications: Software Development Tools: Code Composer Studio Integrated Development Environment (IDE): including Editor C/C++/Assembly Code Generation, and Debug plus additional development tools Scalable, Real-Time Foundation Software (DSP/BIOS which provides the basic run-time target software needed to support any application. Hardware Development Tools: Extended Development System (XDS Emulator For a complete listing of development-support tools for the device, visit the Texas Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL). For information on pricing and availability, contact the nearest TI field sales office or authorized distributor. To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all DSP devices and support tools. Each DSP commercial family member has one of three prefixes: TMX, TMP, or TMS (e.g., TMS320C6745). Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS). Device development evolutionary flow: X Experimental device that is not necessarily representative of the final device's electrical specifications. P Final silicon die that conforms to the device's electrical specifications but has not completed quality and reliability verification. NULL Fully-qualified production device. Support tool development evolutionary flow: TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing. TMDS Fully qualified development-support product. TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer: "Developmental product is intended for internal evaluation purposes." TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies. Submit Documentation Feedback Mechanical Packaging and Orderable Information 261

X OMAPL138 (□□) ZWT (□□) 3 PREFIX X□=□Experimental□Device P =□Prototype□Device Blank□=□Production□Device DEVICE SILICON□REVISION Blank□=□Silicon□Revision□1.0 3□=□300□Mhz =□0°C□to□90°C□(Commercial□Grade) A = –40°C□to□105°C□(Industrial□Grade) Blank PACKAGE□TYPE 361□Pin□Plastic□BGA,□with□Pb-free Soldered□Balls□[Green],□0.65□mm□Ball□Pitch ZCE□□= ZWT =□361□Pin□Plastic□BGA,□with□Pb-free Soldered□Balls□[Green],□0.8□mm□Ball□Pitch DEVICE□SPEED□RANGE TEMPERATURE□RANGE□(JUNCTION) OMAP-L138 Low-Power www.ti.com Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, ZWT), the temperature range (for example, "Blank" is the commercial temperature range), and the device speed range in megahertz (for example, "Blank" is the default). Figure 7-1 provides a legend for reading the complete device. BGA Ball Grid Array The device speed range symbolization indicates the maximum CPU frequency when the core voltage CV DD is set to 1.2 Figure 7-1. Device Nomenclature 262 Mechanical Packaging and Orderable Information Submit Documentation Feedback

7.2 Thermal Data for ZCE Package OMAP-L138 Low-Power www.ti.com SPRS586A JUNE 2009 REVISED AUGUST 2009 The following table(s) show the thermal resistance characteristics for the PBGA ZCE mechanical package. Table 7-1. Thermal Resistance Characteristics (PBGA Package) [ZCE] NO. C/W (1) AIR FLOW (m/s) (2) R Θ JC Junction-to-case 7.6 N/A R Θ JB Junction-to-board 11.3 N R Θ JA Junction-to-free air 23.9 0.00 21.2 0.50 20.3 1.00 R Θ JMA Junction-to-moving air 19.5 2.00 18.6 4.00 0.2 0.00 0.3 0.50 Psi JT Junction-to-package top 0.3 1.00 0.4 2.00 0.5 4.00 11.2 0.00 11.1 0.50 Psi JB Junction-to-board 11.1 1.00 11.0 2.00 10.9 4.00 (1) These measurements were conducted in a JEDEC defined 2S2P system and will change based on environment as well as application. For more information, see these EIA/JEDEC standards EIA/JESD51-2, Integrated Circuits Thermal Test Method Environment Conditions Natural Convection (Still Air) and JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages Power dissipation of 500 mW and ambient temp of 70C assumed. PCB with 2oz (70um) top and bottom copper thickness and 1.5oz (50um) inner copper thickness (2) m/s meters per second Submit Documentation Feedback Mechanical Packaging and Orderable Information 263

7.3 Thermal Data for ZWT Package OMAP-L138 Low-Power www.ti.com The following table(s) show the thermal resistance characteristics for the PBGA ZWT mechanical package. Table 7-2. Thermal Resistance Characteristics (PBGA Package) [ZWT] NO. C/W (1) AIR FLOW (m/s) (2) R Θ JC Junction-to-case 7.3 N/A R Θ JB Junction-to-board 12.4 N R Θ JA Junction-to-free air 23.7 0.00 21.0 0.50 20.1 1.00 R Θ JMA Junction-to-moving air 19.3 2.00 18.4 4.00 0.2 0.00 0.3 0.50 Psi JT Junction-to-package top 0.3 1.00 0.4 2.00 0.5 4.00 12.3 0.00 12.2 0.50 Psi JB Junction-to-board 12.1 1.00 12.0 2.00 11.9 4.00 (1) These measurements were conducted in a JEDEC defined 2S2P system and will change based on environment as well as application. For more information, see these EIA/JEDEC standards EIA/JESD51-2, Integrated Circuits Thermal Test Method Environment Conditions Natural Convection (Still Air) and JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages Power dissipation of and ambient temp of 70C assumed. PCB with 2oz (70um) top and bottom copper thickness and 1.5oz (50um) inner copper thickness (2) m/s meters per second 264 Mechanical Packaging and Orderable Information Submit Documentation Feedback

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) OMAPL138AZCE3 ACTIVE NFBGA ZCE 361 160 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR OMAPL138AZWT3 ACTIVE NFBGA ZWT 361 90 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 31-Mar-2010 Addendum-Page 1

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