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Technical content

Features

 Frequency range: 20 GHz–45 GHz  High gain: 25 dB  Gain flatness: ±1.5 dB  Return loss: Input: 17 dB, Output: 11dB  Output power: P -1dB = 21 dBm at 38 GHz P-3dB = 22.5 dBm at 38 GHz

Applications

 Broadband gain block  Broadband driver amplifier  Point-to-point radio  LMDS  EW  Instrumentation  Frequency Multiplier (X2 and X3) Chip Size: 1720 μm × 760 μm (67.7 mils × 29.9 mils) Chip Size Tolerance: ±10 μm (±0.4 mils) Chip Thickness: 100 μm ± 10 μm (4 mils ± 0.4 mils) Pad Dimensions: 75 μm × 75 μm (3 mils ±0.4 mils) AMMC-5040 20-GHz to 45-GHz GaAs Amplifier Data Sheet

  • 2 - AMMC-5040 Data Sheet Absolute Maximum Ratings (See Note) NOTE Operation in excess of any one of these conditions may result in permanent damage to this device. Functional operation at or near these limitations may significantly reduce the lifetime of the device. DC Specifications/Physical Properties (See Note) NOTE Assume conductive epoxy to an evaluation RF board at 85°C base plate temperature. Symbol Parameters Units Minimum Values Maximum Values Notes Vd-Vg Drain to Gate Voltage V — 8 Vd Positive Supply Voltagea a. Combinations of supply voltage, drain current, in put power, and output power shall not exceed PD. V— 5 IDD Total Drain Current a mA — 550 a Vg Gate Supply Voltage V –3 0.5 PD Power Dissipationa, b b. When operated at this condition with a base plate temperature of 85°C, the median time to failure (MTTF) is significantly reduced. W — 2.09 a, b Pin CW Input Power a dBm — 21 a Tch Operating Channel Tempc, d c. These ratings apply to each individual FET. d. The operating channel temperature will directly affect the devi ce MTTF. For maximum life, it is recommended that junction temperatures be maintained at the lowest possible levels. °C — +150 c, d Tstg Storage Case Temp. °C — –65 to +150 Tmax Maximum Assembly Temp (30s maximum) °C — +300 Symbol Parameters and Test Conditions Units Min. Typ. Max. VD1,2-3-4 Drain Supply Operating Voltage V 2 4.5 5 ID1 First Stage Drain Supply Current (VDD = 4.5 V, VG1 = –0.5 V) mA — 50 — ID2-3-4 Total Drain Supply Current for Stages 2, 3, and 4 (VDD = 4.5 V, VGG = –0.5 V) mA — 225 — VG1,2-3-4 Gate Supply Operating Voltages (IDD = 300 mA) V — –0.45 — VP Pinch-off Voltage (VDD = 4.5 V, IDD < 10 mA) V — –1.5 — ch-b Thermal Resistancea (Channel-to-Backside) a. Measured in wafer form with Tchuck = 25°C (except ch-bs.) °C/W — 31 —
  • 3 - AMMC-5040 Data Sheet Thermal Properties RF Specifications (VDD = 4.5V, IDD (Q) = 300 mA, Z0 = 50) (See Notes) NOTE 1. Data measured in wafer form, T chuck = 25°C. 2. 100% on-wafer RF test is done at frequency = 24 GHz, 27 GHz, 29 GHz, 37 GHz, and 40 GHz, except as noted. Parameters Test Conditions Value Maximum Power Dissipation Tbaseplate = 85°C PD = 2.09W, Tchannel = 150°C Thermal Resistance (jc) Vd = 4.5V, Idd = 300 mA, PD = 1.35W, Tbaseplate = 85°C jc = 31°C/W, Tchannel = 126.85°C Thermal Resistance (jc) Under RF Drive Vd = 4.5V, Idd = 306 mA, Pout = 22 dBm, Pd = 1.25W, Tbaseplate = 85°C jc = 31°C/W, Tchannel = 123°C Symbol Parameters and Test Conditions Units GHz Broadband Narrow Band Typical Performance 23–40 21–24 27–29 37–40 40–45 Min. Typ. Typical |S21|2 Small-signal Gain dB 20 25 25.5 25 22.4 21.3 RLin Input Return Loss dB 15 17 17 18 21 17 RLout O u t p u t R e t u r n L o s s d B 8 1 11 01 41 31 3 P-1dB Output Power @ 1 dB Gain Compression, f = 22 GHz dBm — 20 20 22.5 21 20 P-3dB Output Power @ 3 dB Gain Compression, f = 22 GHz dBm — 21 21.6 23.5 22.5 21.5 OIP3 Output 3rd Order Intercept Point, f = 2 MHz, Pin = –8 dBm, f = 22 GHz dBm — 30 29 29 31 27 |S12|2 I s o l a t i o n d B 4 05 55 55 55 55 5
  • 6 - AMMC-5040 Data Sheet AMMC-5040 RF Performance for Frequency Multiplier Applications Typical Performance as a X2 Frequency Multiplier, Input Power Optimized for Conversion Gain (See Note) NOTE T = 25°C. See Frequency Multiplier Biasing and Operation for bias conditions for operation as a multiplier. Typical Performance as a X2 Frequency Multiplier, Input Power Optimized for Output Power (See Note) NOTE T = 25°C. See Frequency Multiplier Biasing and Operation for bias conditions for operation as a multiplier. Input Frequency (GHz) Input Power (dBm) Output Frequency (GHz) Output Power (dBm) Conversion Gain (dB) 10 6 20 18.2 12.2 11 6 22 18.9 12.9 12 6.5 24 20.5 14.0 13 6.5 26 20.8 14.3 14 7.5 28 20.0 12.4 15 7.5 30 19.6 12.1 16 7.5 32 18.0 10.5 17 7.5 34 16.0 8.5 18 7 36 11.7 4.7 19 7 38 7.1 0.1 20 3 40 7.0 4.0 21 5 42 10.7 5.7 22 5 44 11.3 6.3 23 5 46 11.7 6.7 Input Frequency (GHz) Input Power (dBm) Output Frequency (GHz) Output Power (dBm) Conversion Gain (dB) 10 10 20 20.2 10.2 11 10 22 20.9 10.9 12 10 24 22.0 12.0 13 9.5 26 22.2 12.7 14 9.5 28 20.8 11.3 15 9.5 30 20.6 11.1 16 9.5 32 19.0 9.5
  • 7 - AMMC-5040 Data Sheet Typical Performance as a X3 Frequency Multiplier (See Note) NOTE T = 25°C. See Frequency Multiplier Biasing and Operation for bias conditions for operation as a multiplier. AMMC-5040 Typical Scattering Parameters (See Note) (Tchuck = 25°C, VDD = 4.5V, IDD = 300 mA, Zin = Zout = 50) Input Frequency (GHz) Input Power (dBm) Output Frequency (GHz) Output Power (dBm) Conversion Gain (dB) 7 14.3 21 19.6 5.3 8 14.2 24 20.6 6.4 9 15.1 27 20.0 4.9 10 15.9 30 18.6 2.6 11 15.8 33 16.0 0.2 12 15.8 36 14.7 –1.0 13 15.7 39 12.9 –2.7 14 15.6 42 10.0 –5.5 Table 1 AMMC-5040 Typical Scattering Parameters, I DD = 300 mA Freq. S11 S21 S12 S22 GHz dB Mag Ang dB Mag Ang dB Mag Ang dB Mag Ang
  • 8 - AMMC-5040 Data Sheet NOTE Data obtained from on-wafer measurements. Table 1 AMMC-5040 Typical Scattering Parameters, I DD = 300 mA (Continued) Freq. S11 S21 S12 S22 GHz dB Mag Ang dB Mag Ang dB Mag Ang dB Mag Ang
  • 9 - AMMC-5040 Data Sheet AMMC-5040 Typical Scattering Parameters (See Note) (Tchuck = 25°C, VDD = 4.5V, IDD = 350 mA, Zin = Zout = 50) NOTE Data obtained from on-wafer measurements. Freq. S11 S21 S12 S22 GHz dB Mag Ang dB Mag Ang dB Mag Ang dB Mag Ang
  • 10 - AMMC-5040 Data Sheet Biasing and Operation The recommended DC bias condition for the AMMC-5040 is with all four drains connected to a single 4.5V supply and all four gates connected to an adjustable negative voltage supply as shown in Figure 15. The gate voltage is adjusted for a total drain supply current of typically 300 mA. Figure 1 thorugh Figure 12 can be used to help estimate the minimum drain voltage and current necessary for a given RF gain and output power. As shown in Figure 13, the second, third, and fourth stage DC drain bias lines are connected internally and therefore require only a single bond wire. An additional bond wire is needed for the first stage DC drain bias, Vd1. Only the third and fourth stage DC gate bias lines are connected internally. A total of three DC gate bond wires are required: one for Vg1, one for Vg2, and one for the Vg3/Vg4 connection. The internal matching circuitry at the RF input creates a 50- DC and RF path to ground. A blocking capacitor should be used at the RF input. Any DC voltage applied to the RF input must be maintained below 1V. The RF output is AC coupled. No ground bond wires are needed since the ground connection is made by means of plated through via holes to the backside of the chip. Frequency Multiplier Biasing and Operation The AMMC-5040 can also be used as a frequency doubler, tripler or quadrupler. As a frequency doubler, the AMMC-5040 provides ­conversion gain for input signals in the 10 GHz–23 GHz frequency range for output frequencies of 20 GHz–46 GHz. Similarly, 5GHz–10 GHz signals can be ­quadrupled up to 20 GHz–40 GHz with some conversion loss. Optimum conversion efficiency as a doubler is ­obtained with an input power level of 3 dBm–8 dBm. For use as a frequency tripler, an input power level of 14 dBm–16 dBm is recommended. Frequency multiplication is achieved by reducing the bias on the first stage FET to efficiently generate harmonics. The remaining three stages are then used to provide amplification. While many bias schemes may be used to generate and amplify the desired harmonics within the AMMC-5040, the following information is suggested as a starting point for multiplier applications. Frequency doubling or quadrupling (generation of even harmonics) is accomplished by biasing the first stage FET at pinch-off by setting Vg1 = Vp ≈ –1.1 volts. The remaining three stages are biased for normal amplification, for example, Vgg is ­ adjusted such that Id2 + Id3 + Id4 ≈ 250 mA. The drain voltage, Vdd, for all four stages should be 3.5V–4.5V. The assembly diagram shown in Figure 16 can be used as a guideline. To operate the AMMC-5040 as a frequency tripler (odd harmonic), the device is biased as shown in Figure 17. The drain voltage for the first stage FET is biased separately with Vd1 reduced to 1.1V–1.2V. The drain voltage for the remaining three stages, Vd2, Vd3, and Vd4, should be 3.5V–V. All four gate voltages, Vgg, are set to approximately –0.6 V. If desired, Vgg can be adjusted to minimize second harmonics. Improved multiplier performance can be obtained by biasing both the gate and drain voltages for the first stage separately from stages 2–4. In all cases, Cb > 100 nF to assure stability. Assembly Techniques The chip should be attached directly to the ground plane using electrically conductive epoxy1. For conductive epoxy, the amount should be just enough to provide a thin fillet around the bottom perimeter of the die. The ground plane should be free of any residue that may jeopardize electrical or mechanical attachment. Caution should be taken to not exceed the Absolute Maximum Rating for assembly temperature and time. Thermo-sonic wedge bonding is the preferred method for wire attachment to the bond pads. The RF connections should be kept as short as possible to minimize inductance. 0.7-mil gold wire is recommended. The recommended wire bonding stage temperature is 150°C ± 2°C. The chip is 100-μm thick and should be handled with care. This MMIC has exposed air bridges on the top surface. Handle at the edges or with a custom collet (do not pick up die with vacuum on die center). This MMIC is also static sensitive and ESD handling precautions should be taken. For more detailed information, refer to Broadcom Application Note 54, GaAs MMIC ESD, Die Attach and Bonding Guidelines. NOTE Eutectic attach is not recommended and may jeopardize reliability of the device. 1. Sumitomo 1295SA silver epoxy is recommended.

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