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30 KHz – 40 GHz
Description
Agilent’s AMMC-5024 is a broad- band PHEMT GaAs MMIC TWA designed for medium output power and high gain over the full
30 KHz to 40 GHz frequency
range. The design employs a 9-stage, cascade-connected FET structure to ensure flat gain and power as well as uniform group delay. E-beam lithography is used to produce uniform gate lengths of 0.15 mm and MBE technology assures precise semiconductor layer control.
Features
- Wide frequency range:
- High gain: 16 dB
- Gain flatness: ± 0.75 dB Return loss: Input: 13 dB, Output: 13 dB
- Medium power: P-1dB = 22.5 dBm at 22 GHz
- Low noise figure: 4.6 dB at 26 GHz
Applications
- Communication systems
- Microwave instrumentation
- Optical systems
- Broadband applications requiring flat gain and group delay with excellent input and output port matches over the 30 KHz and
40 GHz frequency range
[1] Symbol Parameters/Conditions Units Min. Max. Vdd Positive Drain Voltage V 10 Idd T otal Drain Current mA 340 Vg1 First Gate Voltage V -9.5 0 Ig1 First Gate Current mA -38 +1 Vg2 Second Gate Voltage V -3.5 +4 Ig2 Second Gate Current mA -20 Pin CW Input Power dBm 17 Tch Operating Channel Temperature °C +150 Tb Operating Backside Temperature °C -55 Tstg Storage T emperature °C -65 +165 Tmax Max. Assembly T emp (60 sec max) °C +300 Notes: 1. Absolute maximum ratings for continuous operation unless otherwise noted. Chip Size: 2350 x 1050 µm (92.5 x 41.3 mils) Chip Size Tolerance: ±10 µm (±0.4 mils) Chip Thickness: 100 ± 10 µm (4 ± 0.4 mils) Pad Dimensions: 80 x 80 µm (2.95 x 0.4 mils)
AMMC-5024 DC Specifications/Physical Properties[1] Symbol Parameters and Test Conditions Units Min. Typ. Max. Idss Saturated Drain Current (Vdd=7 V , Vg1=0 V , Vg2=open circuit) mA 250 304 350 Vp First Gate Pinch-off Voltage (Vdd=7 V , Idd=30 mA, Vg2=open circuit) V -8.2 Vg2 Second Gate Self-bias Voltage (Vdd=7 V , Idd = 200 mA, Vg2=open circuit) V 2.75 Idsmin First Gate Minimum Drain Current mA 47 68 (Vg1)( V dd =7 V , Vg1 = -7 V, Vg2=open circuit) Idsmin Second Gate Minimum Drain Current mA 105 128 (Vg2)( V dd =7 V , Vg1 =0 V , Vg2= -3.5 V) θch-b Thermal Resistance[2] (Backside temperature, Tb = 25°C) °C/W 52 RF Specifications for High Power Applications[3,4] (Vdd=7 V , Idd(Q)=200 mA, Zin=Z o=50Ω Symbol Parameters and Test Conditions Units Min. Typ. Max. |S21|2 Small-signal Gain dB 14 16 18 ∆|S21|2 Small-signal Gain Flatness dB ±0.75 ±1.5 RLin Input Return Loss dB 12 16.9 RLout Output Return Loss dB 10 16.8 |S12|2 Isolation dB 26 28 P-1dB Output Power @ 1 dB Gain Compression f = 22 GHz dBm 21 22.5 Psat Saturated Output Power f = 22 GHz dBm 23 24.5 OIP3 Output 3 rd Order Intercept Point, dBm 27 30 Rfin1 = Rfin2 = 2 dBm, f = 22 GHz, ∆f = 2 MHz NF Noise Figure (V ds = 3V, Ids = 140 mA) f = 26 GHz dB 4.6 6.5 f = 40 GHz dB 7.2 9 RF Specifications for High Gain and Low Power Applications[3,4] (Vdd=4 V , Idd(Q)=160 mA, Z in=Z o=50Ω Symbol Parameters and Test Conditions Units Min. Typ. Max. |S21|2 Small-signal Gain dB 17.5 ∆|S21|2 Small-signal Gain Flatness dB ±1.5 RLin Minimum Input Return Loss dB 13 RLout Minimum Output Return Loss dB 13 |S12|2 Isolation dB 30 P-1dB Output Power @ 1 dB Gain Compression f = 22 GHz dBm 17.3 Psat Saturated Output Power f = 22 GHz dBm 20.5 OIP3 Output 3 rd Order Intercept Point, dBm 22.5 Rfin1 = Rfin2 = 2 dBm, f = 22 GHz, ∆f = 2 MHz NF Noise Figure f = 26 GHz dB 3.7 f = 40 GHz dB 5.5 Notes: 1. Backside temperature Tb = 25°C unless otherwise noted. 2. Channel-to-backside Thermal Resistance (θch-b) = 61°C/W at Tchannel (Tc) = 150°C as measured using the liquid crystal method. Thermal Resistance at backside temperature (Tb) = 25°C calculated from measured data. 3. Data measured in wafer form, T chuck = 25°C 4. 100% on-wafer RF test is done at frequency = 2, 10, 20, 30 and 40 GHz, except as noted.
AMMC-5024 Typical Scattering Parameters[1] (Tchuck = 25°C, VDD = 7V, IDD = 200 mA, Zin = Zout = 50Ω) Freq. S 11 S21 S12 S22 GHz dB Mag Phase dB Mag Phase dB Mag Phase dB Mag Phase Note: 1. Data obtained from on-wafer measurements.
AMMC-5024 Typical Scattering Parameters[1] (Tchuck = 25°C, VDD = 4V, IDD = 160 mA, Zin = Zout = 50Ω) Freq. S 11 S21 S12 S22 GHz dB Mag Phase dB Mag Phase dB Mag Phase dB Mag Phase Note: 1. Data obtained from on-wafer measurements.
AMMC-5024 is biased with a single positive drain supply (Vdd) a negative gate supply (Vg1) and has a positive control gate supply (Vg2). For best overall performance the recommended bias condition for the AMMC-5024 is V dd =7V and Idd = 200 mA. To achieve this drain current level, Vg1 is typi- cally between –2.5 to –3.5V. Typically, DC current flow for Vg1 is –10 mA. Open circuit is the default setting for Vg2 when not utilizing gain control. Using the simplest form of assembly (Figure 20), the device is capable of delivering flat gain over a 2– 50 GHz range with a minimum of gain slope and ripple. However, this device is designed with DC coupled RF I/O ports, and operation may be extended to lower frequencies (<2 GHz) through the use of off- chip low-frequency extension circuitry and proper external biasing components. With low frequency bias extension it may be used in a variety of time- domain applications (through 40 Gb/s). Figure 21 shows a typical assem- bly configuration. When bypass capacitors are connected to the AUX pads, the low frequency limit is extended down to the corner frequency determined by the bypass capaci- tor and the combination of the on-chip 50 ohm load and small de-queing resistor. At this fre- quency the small signal gain will increase in magnitude and stay at this elevated level down to the point where the C aux bypass capacitor acts as an open circuit, effectively rolling off the gain completely. The low frequency limit can be approximated from the following equation: fCaux = 1 2πCaux(Ro + RDEQ) where: Ro is the 50Ω gate or drain line termination resistor. RDEQ is the small series de- queing resistor and 10Ω. Caux is the capacitance of the bypass capacitor connected to the AUX Drain and AUX Gate pad in farads. With the external bypass capaci- tors connected to the AUX gate and AUX drain pads, gain will show a slight increase between 1.0 and 1.5 GHz. This is due to a series combination of C aux and the on chip resistance but is exaggerated by the parasitic inductance (L c) of the bypass capacitor and the inductance of the bond wire (L d). Therefore the bond wire from the Aux pads to the bypass capacitors should be made as short as possible. Input and output RF ports are DC coupled; therefore, DC decoupling capacitors are required if there are DC paths. (Do not attempt to apply bias to these pads.) RF bond connections should be kept as short as possible to reduce RF lead inductance which will degrade performance above 20 GHz. An optional output power detector network is also pro- vided. Detector sensitivity is optimized by biasing the diodes with typical drain voltage V dd = 7 volts. Simply connecting Det-Bias to the V dd supply is a convenient method of biasing this detector network. The differential voltage between the Det-Ref and Det-Out pads can be correlated with the RF power emerging from the RF output port. A >0.5 µF capacitor is required for the Det_Out pad to expand power detection perfor- mance below 100 MHz. Ground connections are made with plated through-holes to the backside of the device; therefore, ground wires are not needed. Assembly T echniques The chip should be attached directly to the ground plane using either a fluxless AuSn solder preform or electrically conductive epoxy [1]. For conduc- tive epoxy, the amount should be just enough to provide a thin fillet around the bottom perim- eter of the die. The ground plane should be free of any residue that may jeopardize electrical or mechanical attachment. Caution should be taken to not exceed the Absolute Maximum Rating for assembly temperature and time. Thermosonic wedge bonding is the preferred method for wire attachment to the bond pads. The RF connections should be kept as short as possible to minimize inductance. Gold mesh [2] or double-bonding with 0.7 mil gold wire is recom- mended. Mesh can be attached using a 2 mil round tracking tool and a tool force of approximately 22 grams with an ultrasonic power of roughly 55 dB for a duration of 76 ± 8 mS. A guided wedge at an ultrasonic power level of 64 dB can be used for the 0.7 mil wire. The recommended wire bond stage temperature is 150 ± 2°C.
Figure 19. AMMC-5024 Schematic. should be handled with care.
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