AML8726-MX AMLOGIC | Alldatasheet
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AML8726-MX TTL Display User Guide Version 0.2 June 2012 1/21 AMLOGIC Proprietary Application Notes AML8726-MX TTL Display User Guide Revision 0.2 Preliminary AMLOGIC, Inc.
3930 Freedom Circle
Santa Clara, CA 95054 U.S.A. www.amlogic.com AMLOGIC reserves the right to change any information described herein at any time without notice. AMLOGIC assumes no responsibility or liability from use of such information. Distribute to Emdoor!
AML8726-MX TTL Display User Guide Version 0.2 June 2012 2/21 AMLOGIC Proprietary Table of Content Distribute to Emdoor!
AML8726-MX TTL Display User Guide Version 0.2 June 2012 3/21 AMLOGIC Proprietary
Revision History
0.1 April.10, 2012 Evoke Zhang 1st Draft Version 0.2 April.16, 2012 Evoke Zhang Update TCON Signals description Distribute to Emdoor!
AML8726-MX TTL Display User Guide Version 0.2 June 2012 4/21 AMLOGIC Proprietary
1 General Description
Amlogic AML8726-MX is a highly integrated multimedia application processor SoC for Multimedia Internet Device (MID), tablet and Set Top Box (STB). It integrates a powerful CPU, a 2D/3D graphics subsystem and a state-of-the-art video decoding engine together with all major peripherals. AML8726-MX integrates three LCD panel timing controllers: TTL, LVDS, and mLVDS. TTL should be used with TTL type LCD panel, LVDS is for LVDS type LCD panel, and mLVDS is for mini-LVDS type LCD panel. This document is a user guide of AML8726-MX TTL interface for TTL LCD panel timing control only. This document describes: RGB data output TCON signals LCD Basic LCD Timing LCD Effect Android Driver Register address mapping Register description Distribute to Emdoor!
2 RGB Data Output
AML8726-MX has 24 pins of TTL RGB data signals to output RGB888 data for supporting 8bits TTL LCD panel. Table 5. RGB data signals Multiplexing Table When required RGB666 data for a 6bits TTL panel, the RGB data signals must be connected bit[7:2] to panel. It will be display abnormal when connected wrong signals. The RGB data connection for 8bits and 6bits panel is illustrated in Figure 1. Figure 1. RGB Data Connection
3 LCD Panel Timing Controller(TCON)
AML8726-MX integrates a complex and flexible digital LCD panel timing controller (TCON) with TTL interface. timing requirements of various TTL LCD panels.
3.1 TCON Signal Pinmux
Table 1. About GPIO function sett ings, please refer to AML8726-MX GPIO User Guide for detailed
Table 1. TCON Signals Multiplexing Table
3.2 Frame Signal and Line Signal
signal cannot. For convenience, only the typical case will be described in the following sections. output HIGH again from the beginning of next line. This will introduce a glitch between two lines. The example signals are illustrated in Figure . Most of TCON signals can be configured as line signal or frame signal by setting TCON_MISC_ADDR register.
3.3 TCON Signal Timing Control
All register names and associated signal names are listed in Table 2.
Table 2. TCON Signal Timing Registers Note: Each register has 12 effective bits and valid value from 0 to 4095. The line has 1000 scan pixels and 800 valid pixels. The horizontal starting position is 4th pixel. The HS register should be set to 4 representing the 4th pixel. The HE register should be set to 4+800=804, representing the ACTIVE time of signal is 800 pixels. and HE registers. And VE register is used to define the position of last line. The line number is counted from 0. A frame has 660 scan lines and 600 valid lines. The vertical starting position is 3rd line. The VS register should be set to 3 representing the 3rd line. The VE register should be set to 3+600-1=602, representing the ACTIVE time of signal is 600 lines. The timing diagram of signal with HS/HE/VS/VE example values is illustrated in Figure . Figure 2. Signal Timing Diagram with HS/HE/VS/VE example value
4 LCD Basic
4.1 Display Area Definition
4.2 Panel Aspect Ratio
Set the right value of Panel Aspect Ratio to ensure the length-to-width ratio of OSD display.
4.3 Panel Interface
5 LCD Timing
5.1 Pixel Clock Calculate
Table 4. pixel clock parameter HHI_VIID_DIVIDER_CNTL. For details please see the registers description in Chapter 9.
5.2 Pixel Clock Spread Spectrum
.clk_ctrl=0x3111e, // ss_level=3, the clock spread spetrum width is 3%. Figure 3. Display Area Table 3. Timing horizontal and vertical total timing, they are applied to calculate line frequence and frame rate.
5.3 Panel Aspect Ratio
Set the right value of Panel Aspect Ratio to ensure the length-to-width ratio of OSD display.
5.4 Panel Interface
6 LCD Timing
6.1 Pixel Clock Calculate
HHI_VIID_DIVIDER_CNTL. For details please see the registers description in Chapter 9.
6.2 Pixel Clock Spread Spectrum
.clk_ctrl=0x3111e, // ss_level=3, the clock spread spetrum width is 3%.
6.3 TCON Signal Definition
according to display parameter VDIEO_ON_PIXEL and VIDEO_ON_LINE setting, and can not be modified.
6.4 Panel Aspect Ratio
Set the right value of Panel Aspect Ratio to ensure the length-to-width ratio of OSD display.
6.5 Panel Interface
7 LCD Timing
7.1 Pixel Clock Calculate
HHI_VIID_DIVIDER_CNTL. For details please see the registers description in Chapter 9.
7.2 Pixel Clock Spread Spectrum
.clk_ctrl=0x3111e, // ss_level=3, the clock spread spetrum width is 3%. Figure 4. TCON Signals We still use the timing defined in Table 3. Hsync – sth1, Vsync – stv1, DE – oeh.
registers description in Chapter 9.
7.3 Pixel Clock and CPH1/2/3 Signal
CPH3, are provided. CPH1/2/3 can be configured polarity to positive or negative edge to latch data. please see the registers description in Chapter 9.
7.4 RGB Swap
see the registers description in Chapter 9.
8 LCD Effect
characteristics and improve the display quality. color channel comparing to the 8-bit output to panel.
- Co-effective factor correction
- Gamma lookup table correction
The data correction data processing is illustrated in Figure . Figure 5. RGB Data Correction Process
AML8726-MX TTL Display User Guide Version 0.2 June 2012 14/21 AMLOGIC Proprietary Corrected Red Data Green Blue RGB_BASE_ADDR[9:0] RGB_COEFF_ADDR[10:0] Corrected Green Data Corrected Blue Data Red Blue Gamma Lookup Table Green Gamma Lookup Table Red Gamma Lookup Table
8.1 Base Shifting
Base shifting is the first step of gamma correction to correct the luminance of the image. Each pixel RGB data will add the value of the base shifting value in RGB_BASE_ADDR[9:0]. Please notice: 1. The effective values of RGB_BASE_ADDR[9:0] are from -512 to +511. 2. The values of RGB_BASE_ADDR[9:0] will be used for all RGB channels at the same time.
8.2 Co-effective factor correction
Co-effective factor correction is the second step to do linear gamma correction of the image. Each pixel RGB data will multiply the value of co-effective factor in RGB_COEFF_ADDR[10:0]. Please notice: 1. The effective value of RGB_COEFF_ADDR[10:0] is from 0 to 1.999023. 2. The value of RGB_COEFF_ADDR[10:0] will be used for all RGB channels at the same time.
8.3 Gamma lookup table correction
Gamma lookup table correction is the last step to do non -linear gamma correction based on color mapping using lookup table. AML8726-MX integrates 768 10-bit registers to store gamma lookup table used by step 3 of gamma correction. The registers are divided into 3 blocks. Each block has 256 10 -bit registers to store one color channel gamma lookup table values: Red lookup table registers (R_LUT) Green lookup table registers (G_LUT) Blue lookup table registers (B_LUT) The gamma table is set as below. static void t13_setup_gama_table(tcon_conf_t *pConf) int i; const unsigned short gamma_adjust[256] = { for (i=0; i<256; i++) { pConf->GammaTableR[i] = gamma_adjust[i] << 2; pConf->GammaTableG[i] = gamma_adjust[i] << 2; pConf->GammaTableB[i] = gamma_adjust[i] << 2; Distribute to Emdoor!
AML8726-MX TTL Display User Guide Version 0.2 June 2012 15/21 AMLOGIC Proprietary Gamma correction is controlled by the member of panel parameter named gamma_cntl_port. (set 1 to enable gamma correction) .gamma_cntl_port = (1 << LCD_GAMMA_EN), gamma correction can be enabled/disabled by editing the register GAMMA_CNTL_PORT real-time. For details please see the registers description in Chapter 9.
9 Android Driver
9.1 Uboot Driver
Amlogic provides Panel Parameter files for uboot. In Amlogic reference code, the directory is [uboot root]/board/amlogic/[board directory]/ It recommends that software creates a single C type source code file for each panel.
9.2 Kernel Driver
Amlogic provides Panel Parameter files for Kernel. In Amlogic reference code, the directory is [kernel root]/customer/boards/ It recommends that software creates a single C type source code file for each panel.
10 Register Address Mapping
10.1 Register address mapping
The register addresses in this document are provided as address offset. Address mapping is needed to convert register address offset to the physical register address. The basic formula of address mapping is: REG_ADDR = BASE_ADDR + (REG_OFFSET << 2) where: REG_ADDR: physical register address that software can access the register BASE_ADDR: the base address of the address bus REG_OFFSET: the register address offset Distribute to Emdoor!
AML8726-MX TTL Display User Guide Version 0.2 June 2012 16/21 AMLOGIC Proprietary The value of base address (BASE_ADDR) may be different in different software implementation. In Amlogic ported Linux kernel and the boot loader uBoot, the base addresses are: Linux Kernel: 0xF1100000 uboot: 0xC1100000 Software needs to choose BASE_ADDR according implementation environment.
10.2 Register operation for serial debugging
The register can be read or write for serial debugging. uboot: read: md REG_ADDR write: mw REG_ADDR REG_VAL Linux Kernel: read: echo “REG_OFFSET” > /sys/class/i2c/cbus_reg write: echo “w REG_OFFSET REG_VAL” > /sys/class/i2c/cbus_reg Distribute to Emdoor!
11 Register Descriptions
11.1 Video Clock
Table 5. HHI_VIID_CLK_DIV Register Definition 17:16 OD R/W 0 Video clock parameter OD, see Chapter 5.1 for detail. 13:9 N R/W 0 Video clock parameter N, see Chapter 5.1 for detail. 8:0 M R/W 0 Video clock parameter M, see Chapter 5.1 for detail. Table 6. HHI_VIID_CLK_DIV Register Definition 7:0 XD0 R/W 0 Video clock parameter XD-1, see Chapter 5.1 for detail. Table 7. HHI_VIID_DIVIDER_CNTL Register Definition 6:4 PRE_SEL R/W 0 Video clock parameter div, see Chapter 5.1 for detail. Table 8. POL_CNTL_ADDR Register Definition
8 CPH3_POL R/W 0 CPH3 Polarity Control
7 CPH2_POL R/W 0 CPH2 Polarity Control
6 CPH1_POL R/W 0 CPH1 Polarity Control
AML8726-MX TTL Display User Guide Version 0.2 June 2012 18/21 AMLOGIC Proprietary
11.2 TCON Signal
Table 9.STH1_HS_ADDR Register Definition Name STH1_HS_ADDR Offset 0x1490 Width 32-bit Bit Name R/W Default Description 31:12 - - - Reserved 11:0 STH1_HS_ADDR R/W 0 STH1 signal horizontal start pixel position. Table 10.STH1_HE_ADDR Register Definition Name STH1_HE_ADDR Offset 0x1491 Width 32-bit Bit Name R/W Default Description 31:12 - - - Reserved 11:0 STH1_HE_ADDR R/W 0 STH1 signal horizontal end pixel position. Table 11.STH1_VS_ADDR Register Definition Name STH1_VS_ADDR Offset 0x1492 Width 32-bit Bit Name R/W Default Description 31:12 - - - Reserved 11:0 STH1_VS_ADDR R/W 0 STH1 signal vertical start pixel position Table 12.STH1_VE_ADDR Register Definition Name STH1_VE_ADDR Offset 0x1493 Width 32-bit Bit Name R/W Default Description 31:12 - - - Reserved 11:0 STH1_VE_ADDR R/W 0 STH1 signal vertical end pixel position. Table 3.OEH_HS_ADDR Register Definition Name OEH_HS_ADDR Offset 0x1498 Width 32-bit Bit Name R/W Default Description 31:12 - - - Reserved 11:0 OEH_HS_ADDR R/W 0 OEH signal horizontal start pixel position. Table 4.OEH_HE_ADDR Register Definition Name OEH_HE_ADDR Offset 0x1499 Width 32-bit Bit Name R/W Default Description 31:12 - - - Reserved 11:0 OEH_HE_ADDR R/W 0 OEH signal horizontal end pixel position. Table 5.OEH_VS_ADDR Register Definition Name OEH_VS_ADDR Offset 0x149A Width 32-bit Bit Name R/W Default Description 31:12 - - - Reserved 11:0 OEH_VS_ADDR R/W 0 OEH signal vertical start pixel position Table 6.OEH_VE_ADDR Register Definition Name OEH_VE_ADDR Offset 0x149B Width 32-bit Bit Name R/W Default Description 31:12 - - - Reserved 11:0 OEH_VE_ADDR R/W 0 OEH signal vertical end pixel position. Table 7.VCOM_HSWITCH_ADDR Register Definition Name VCOM_HSWITCH_ADDR Offset 0x149C Width 32-bit Bit Name R/W Default Description 31:12 - - - Reserved 11:0 VCOM_HSWITCH_ADDR R/W 0 VCOM signal horizontal switch pixel position Table 18.VCOM_VS_ADDR Register Definition Name VCOM_VS_ADDR Offset 0x149D Width 32-bit Bit Name R/W Default Description 31:12 - - - Reserved 11:0 VCOM_VS_ADDR R/W 0 VCOM signal vertical start pixel position Distribute to Emdoor!
AML8726-MX TTL Display User Guide Version 0.2 June 2012 19/21 AMLOGIC Proprietary Table 19.VCOM_VE_ADDR Register Definition Name VCOM_VE_ADDR Offset 0x149E Width 32-bit Bit Name R/W Default Description 31:12 - - - Reserved 11:0 VCOM_VE_ADDR R/W 0 VCOM signal vertical end pixel position Table 20.CPV1_HS_ADDR Register Definition Name CPV1_HS_ADDR Offset 0x149F Width 32-bit Bit Name R/W Default Description 31:12 - - - Reserved 11:0 CPV1_HS_ADDR R/W 0 CPV1 signal horizontal start pixel position Table 21.CPV1_HE_ADDR Register Definition Name CPV1_HE_ADDR Offset 0x14A0 Width 32-bit Bit Name R/W Default Description 31:12 - - - Reserved 11:0 CPV1_HE_ADDR R/W 0 CPV1 signal horizontal end pixel position Table 22.CPV1_VS_ADDR Register Definition Name CPV1_VS_ADDR Offset 0x14A1 Width 32-bit Bit Name R/W Default Description 31:12 - - - Reserved 11:0 CPV1_VS_ADDR R/W 0 CPV1 signal vertical start pixel position Table 8.CPV1_VE_ADDR Register Definition Name CPV1_VE_ADDR Offset 0x14A2 Width 32-bit Bit Name R/W Default Description 31:12 - - - Reserved 11:0 CPV1_VE_ADDR R/W 0 CPV1 signal vertical end pixel position Table 9.STV1_HS_ADDR Register Definition Name STV1_HS_ADDR Offset 0x14A7 Width 32-bit Bit Name R/W Default Description 31:12 - - - Reserved 11:0 STV1_HS_ADDR R/W 0 STV1 signal horizontal start pixel position Table 10.STV1_HE_ADDR Register Definition Name STV1_HE_ADDR Offset 0x14A8 Width 32-bit Bit Name R/W Default Description 31:12 - - - Reserved 11:0 STV1_HE_ADDR R/W 0 STV1 signal horizontal end pixel position Table 11.STV1_VS_ADDR Register Definition Name STV1_VS_ADDR Offset 0x14A9 Width 32-bit Bit Name R/W Default Description 31:12 - - - Reserved 11:0 STV1_VS_ADDR R/W 0 STV1 signal vertical start pixel position Table 12.STV1_VE_ADDR Register Definition Name STV1_VE_ADDR Offset 0x14AA Width 32-bit Bit Name R/W Default Description 31:12 - - - Reserved 11:0 STV1_VE_ADDR R/W 0 STV1 signal vertical end pixel position Table 28.OEV1_HS_ADDR Register Definition Name OEV1_HS_ADDR Offset 0x14AF Width 32-bit Bit Name R/W Default Description 31:12 - - - Reserved 11:0 OEV1_HS_ADDR R/W 0 OEV1 signal horizontal start pixel position Distribute to Emdoor!
AML8726-MX TTL Display User Guide Version 0.2 June 2012 20/21 AMLOGIC Proprietary Table 29.OEV1_HE_ADDR Register Definition Name OEV1_HE_ADDR Offset 0x14B0 Width 32-bit Bit Name R/W Default Description 31:12 - - - Reserved 11:0 OEV1_HE_ADDR R/W 0 OEV1 signal horizontal end pixel position Table 30.OEV1_VS_ADDR Register Definition Name OEV1_VS_ADDR Offset 0x14B1 Width 32-bit Bit Name R/W Default Description 31:12 - - - Reserved 11:0 OEV1_VS_ADDR R/W 0 OEV1 signal vertical start pixel position Table 31.OEV1_VE_ADDR Register Definition Name OEV1_VE_ADDR Offset 0x14B2 Width 32-bit Bit Name R/W Default Description 31:12 - - - Reserved 11:0 OEV1_VE_ADDR R/W 0 OEV1 signal vertical end pixel position Table 32.TCON_MISC_ADDR Register Definition Name TCON_MISC_ADDR Offset 0x14C1 Width 32-bit Bit Name R/W Default Description 31:12 - - - Reserved
11 STH1_SEL R/W 0 0: STH1 is line signal
1: STH1 is frame signal
10 OEH_SEL R/W 0 0: OEH is line signal
1: OEH is frame signal
9 VCOM_SEL R/W 0 0: VCOM is line signal
1: VCOM is frame signal 8:7 - - 0 Reserved
6 CPV1_SEL R/W 0 0: CPV1 is line signal
1: CPV1 is frame signal 5 - - 1 Reserved
4 STV1_SEL R/W 1 0: STV1 is line signal
1: STV1 is frame signal 3:1 - - - Reserved
0 OEV1_SEL R/W 0 0: OEV1 is line signal
1: OEV1 is frame signal Table 13.DUAL_PORT_CNTL_ADDR Register Definition Name DUAL_PORT_CNTL_ADDR Offset 0x14C2 Width 32-bit Bit Name R/W Default Description 31:2 - - - Reserved 1 RGB_SWP R/W 0 Setting this bit to 1 swaps Red and Blue color output in data path. 0 BIT_SWP R/W 0 Setting this bit to 1 swaps the bit order in data path from 7:0 to 0:7. Distribute to Emdoor!
11.3 RGB Data Effect
Table 34. GAMMA_CNTL_PORT Register Definition
0 GAMMA_EN R/W 0 Gamma correction enable
Table 35. RGB_BASE_ADDR Register Definition Table 36. RGB_COEFF_ADDR Register Definition