AMIS-49200-XTD

AMIS-492X0 ONSEMI | Alldatasheet

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Technical content

©2008 SCILLC. All rights reserved. Publication Order Number: June 2008 – Rev. 6 492x0/D AMIS-492x0 Fieldbus MAU

1.0 Introduction

1.1 Overview

AMIS-492x0 Fieldbus MAU (media access unit) is a transceiv er chip for low speed FOUNDATION Fieldbus® and Profibus® PA devices. The AMIS-49200 was originally designed to be a near pin-for-pin replacement of the Yokogawa μSAA22Q MAU. “Near pin- for-pin” means that associated component values may change, but no board changes are required. A micro-leadframe package option (NQFP) is also available, the AMIS-49250.

1.2 Definitions, Acronyms and Abbreviations

ESD - Electrostatic discharge FF - FOUNDATION Fieldbus LQFP - Low profile quad flat pack Manchester - Communications encoding scheme implemented in FOUNDATION Fieldbus MAU - Medium attachment unit MDS - Medium dependent sub-layer NQFP - “Near chip-scale” quad flat pack μSAA22Q - Name of Yokogawa’s MAU IC

1.3 References

• Fieldbus Medium Attachment Unit (MAU) Chip, μSAA22Q, Yokogawa Electric Corporation, June 12, 1998, Document No.: SS-96-01 (Rev.3).
• Fieldbus Standard for Use in Industrial Control Systems Part 2: Physical Layer Specification and Service Definition, Amendment to Clause 22 ISA/SP50 –1996-544B, dS50.02, Part 2, Draft Standard.
• Profibus PA specifications EN 50170 (formerly DIN 19245) covers all of Profibus and includes P A (31.25 kbps Intrinsically Safe Physical Layer), references IEC 61158-2.

2.0 AMIS-492x0 Fieldbus MAU Description

2.1 Features

AMIS-492x0 Fieldbus MAU is a transceiver IC for low speed FOUNDA TION Fieldbus and Profibus PA devices. It incorporates the following features:

• All node power can be supplied by the bus, via the AMIS-492x0
• Current consumption 500uA (typ)
• VCC voltage: 6.2V to 4.75V
• VDD voltage: 5.5V to 2.7V
• Compatible to IEC 1158-2 and ISA 50.02
• Shunt regulator
• Voltage reference (internal only)
• Series regulator
• Band-pass filter
• Slew rate control
• Segment current control
• Low voltage detection
• Carrier detect
• Data rate: 31.25kbps voltage mode
• Dual voltage supply 3-6.2V
• 44-pin LQFP/NQFP package Rev. 6 | Page 2 of 22 | www.onsemi.com

2.2 Block Diagram

N_PFail1N_PFail2 Vmid Vref SHUNT SGNDSHSETIN SHSET SRSET SRTR SRAO SRSETIN Vmid CRT CCOUT CCINM CCINP TXE POL VSS SIGIN HPF Vref LPF FLTOUT FLT VO VDD TXS RXS CCD RXA VSSVSS MDS Interface Bandpass Filter Carrier Detector Series Regulator Shunt RegulatorLow Voltage Detectors Current Driver Vmid Reference BandgapBias Circuitry Zero-Cross Detector Receive Block Transmit Block Power Supply Block Tri-Level Modulator Slew Control 31 30 218 1096 7451511 1214 VSS42 VSS43 MDS_CTRL26 VSS VSS VSS VSS VSS VCC VCC VCC VCC VCC VCC VSS Figure 1: AMIS-492x0 Fieldbus MAU Block Diagram Rev. 6 | Page 3 of 22 | www.onsemi.com

2.3 Package Information

The IC is packaged as shown below. Figure 2: AMIS-49200 Package Dimensions (44-pin LQFP) Rev. 6 | Page 4 of 22 | www.onsemi.com

Rev. 6 | Page 5 of 22 | www.onsemi.com AMIS-492x0 Figure 3: AMIS-49250 Package Dimensions (44-pin NQFP)

Table 1: Pin Numbers and Signal Description Signal Name Pin No. I/O (Note 1) Description VSS 1 Ground Connect to ground VREF 2 AO Internal bandgap voltage (1.18V) VMID 3 AO 2V bias voltage for AC signals N_PFAIL1 4 AI/O Power fail alarm at VCC input. This pin is an open-drain output of negative logic. N_PFAIL2 5 AI/O Power fail alarm at VDD input. This pin is an open-drain output of negative logic. SHSETIN 6 AI Feedback (non-inverting) input for the shunt regulator SHSET 7 AO Divided voltage of VCC input. Feeding this voltage to SHSETIN pin results in 5V voltage at VCC. SHUNT 8 AI Control pin of the shunt regulator. Its sink current (25mA max) is controlled so that the voltage at SHSETIN is equal to VREF (1.18V). VSS/ SGND 9 Ground The current absorbed by SHUNT pin (25mA max) is fed to this pin, which must be connected to the ground level VSS 10 Ground Ground VSS 11 Ground Ground SRSETIN 12 AI Feedback (inverting) input for the series regulat or. The series regulator controls its output (SRAO) to make this input voltage is equal to VREF (1.18V). SRSET 13 AO Divided voltage of VO output. Feeding this voltage into SRSETIN pin results in 3V at VO pin. SRAO 14 AO Output pin of an operational amplifier for the series regulator SRTR 15 AI Gate of a PMOS transistor for the series regulator VO 16 AO Output pin of the series regulator (20mA max) VDD 17 Digital supply Supply voltage input for digital block VCC 18 Analog supply Analog supply voltage CRT 19 AI/O Current integration to limit output slew rate VSS 20 Ground Ground VDRV 21 AO Output of an operational amplifier for slew rate control. This signal can be fed to current driver. VSS 22 Ground Ground CCINP 23 AI Non-inverting input of an operational amplifier for transmission current driver CCINM 24 AI Inverting input of an operational amplifier for transmission current driver CCOUT 25 AO Output of an operational amplifier for transmission current driver MDS_CTRL 26 AI For POL = VDD MDS_CTRL should = VSS For POL = VSS MDS_CTRL can be tied to VDD or used as a not reset to control when transmit communications will be enabled SIGIN 27 AI Input pin of the band-pass filter. This pin is connected to VMID bias level with 270K resistor. HPF 28 AI Feedback signal of high-pass filter. This pin is connected to the output of an op-amp for high pass filter with 75K resistor. LPF 29 AI Non-inverting input of an operational amplifier for the low-pass filter FLT 30 AI Input pin of low-pass filter for feedback. This pin is connected to the output of the high-pass filter through 20kΩ and the non-inverting input of the low-pass filter through 54kΩ resisters. FLTOUT 31 AO Output of the operational amplifier for the low-pas s filter. This signal is internally connected to non-inverting input to form a voltage-follower. CCD 32 AO Current integration (for carrier detect circuit) VSS 33 Ground Ground Rev. 6 | Page 6 of 22 | www.onsemi.com

Table 1: Pin Numbers and Signal Description (Continued) Signal Name Pin No. I/O(Note 1) Description RXA 34 DO MDS-MAU interface signal for received signal activity. This pin is a push-pull output. RXS 35 DO MDS-MAU interface signal for received signal. This pin is a push-pull output. TXE 36 DIS MDS-MAU interface signal for enable signal transmission (Schmitt Trigger input) TXS 37 DIS MDS-MAU interface signal for signal to be transmitted (Schmitt Trigger input) POL 38 DIS Selects polarity of TxE input. When this pin is connected to GND, TxE is active high. When this pin is connected to VDD, TxE is active low. VSS 39 Ground Ground VSS 40 Ground Ground VSS 41 Ground Connect to ground VSS 42 Ground Connect to ground VSS 43 Ground Connect to ground VCC 44 Analog supply Analog supply voltage Note: 1. AI = Analog Input, AO = Analog Output, AI/O = Analog Input/Output, DIS = CMOS Digital Input (Schmitt Trigger), DO = CMOS Digital Output.

3.0 Electrical Characteristics

3.1 Operating Conditions

Unless otherwise noted, all block and sub-block specifications apply over the operating temperature (-40 to 85oC). Table 2: Absolute Maximum Ratings Parameter Symbol Min. Max. Units Conditions Analog block supply voltage VCC -0.3 6.5 V Digital block supply voltage VDD -0.3 6.0 V Digital input pin voltage VIN -0.3 VDD + 0.3 V (TxS, TxE and POL pins) Digital output pin voltage VOUT -0.3 VDD + 0.3 V (RxS and RxA pins) Input pin current IIN - ±5 mA Not for shunt pin Output pin current IOUT - 30 mA For shunt, SGND and VO ESD, Human Body Model 2,250 V ESD, Machine Model 250 V ESD, Charged Device Model 1,000 V Storage temperature TStorage -55 125 °C Table 3: Normal Operating Conditions Parameter Symbol Min. Typ. Max. Units Conditions Analog supply voltage VCC 4.75 5 6.2 V Digital supply voltage VDD 2.7 3 VCC - 1.1V V Supply voltages are configurable, or can be supplied from off-chip Storage temperature TOperating -40 85 °C Current consumption ICC 500 800 µA 25°C, SHUNT current = 1mA, No current from series regulator Rev. 6 | Page 7 of 22 | www.onsemi.com

Table 4: CMOS Input Specifications Parameter Symbol Min. Max. Units Input high voltage VIH 0.7•VDD VDD V Input low voltage VIL 0 0.3•VDD V Input high current IIH 1 μA Input low current IIL -1 μA Schmitt negative threshold Vt- 0.2•VDD V Schmitt positive threshold Vt+ 0.8•VDD V Schmitt hysteresis Vh 1 V

3.2 Power Supply Blocks

Table 5: Regulator Specifications Parameter Symbol Min. Typ. Max. Units Conditions Shunt Regulator Sink current ISH 0.001 25 mA Internal pass transistor N-ch and pad Load capacitance CSH 5 μF Load regulation 0 1.6 4 % ISH = 1 to 25mA Temperature coefficient TCVcc ±200 ppm/°C No load capacitance Series Regulator Input voltage VCC 4.75 6.2 V Internally tied to VCC pin 2.91 3.0 3.09 V Preset, ISR = 0 Output voltage VO 2.85 3.5 V External setting and N-JFET Output current ISR 20 mA Internal pass transistor P-ch and pad Load capacitance CSR 5 μF For stability use Cap w/ ESR Load regulation 0 2 4 % ISR = 0 to 20mA Temperature coefficient TCVo ±200 ppm/°C Low Voltage Detectors (applies to N_PFail1 and N_PFail2) Threshold V TH9 85 90 95 % Vref SxSETIN > VTH9 (output: L Æ H) Hysteresis VHYS5 .012 .025 .038 V SxSETIN < (VTH9 - VHYS5) (output: H Æ L ) Output sink current IOL 30 135 μA VOL= 0.4V (open drain) Output leakage current IL 1 μA VOH = 5V Table 6: Voltage Reference Specifications Parameter Symbol Min. Typ. Max. Units Conditions Bandgap Voltage Reference Output voltage tolerance VREF 1.157 1.185 1.205 V Equates to: +/- 2 percent Temperature drift 50 ppm/°C Hysteresis (1) V REFHYS - 100 - μV Note 1 Supply voltage VCCREF 4.75 5 6.2 V Load current IREFOUT - - 0 μA No load during operation VMID voltage reference Output voltage VMID 1.95 2.0 2.05 V Output current IMID -30 100 μA Load capacitance CMID 0.01 0.1 1 μF DVC6000F uses 1uF Temperature coefficient TCMID ± 200 ppm/°C Notes: 1. Hysteresis is defined as the change in the 25°C r eading after 85°C to 25°C cycle and –40°C to 25°C cycle. Rev. 6 | Page 8 of 22 | www.onsemi.com

3.3 Transmitter Blocks

Table 7: MDS-MAU Interface Parameter Symbol Min. Typ. Max. Units Conditions MDS-MAU Interface POL input pin POL V TxE input pin TxE V TxS input pin TxS See Schmitt Trigger input specs V Note: The associated MDS chip must handle the jabber detect function. Table 8: Tri-level Modulator Parameter Symbol Min. Typ. Max. Units Conditions Tri-level Modulator and Slew Control (Output is at VDRV) Output voltage VO V MID 3.02 V Load current IO -35 +120 μA |∆V| 10mV Output for silence (1) V S V MID+0.485 V MID+0.500 V MID+0.515 V TXE disabled Output for high level (1) VH VS+0.380 VS+0.400 VS+0.420 V TXE active Output for low level (1) V L V S-0.420 V S-0.400 V S-0.380 V TXE active Asymmetry of VH and VL ∆VHL -0.02 0.02 V Rise and fall times (2) tf, tr 4.7 μsec Note 2 (CRT= 22pF) Notes: 2. By adding an external capacitor between the CRT pin and ground, slew rate at VDRV output can be controlled. The controlling equation is tf or tr = 2us + should have a guard pattern around them to avoid unnecessary interference. Table 9: Current Control Amplifier Parameter Symbol Min. Typ. Max. Units Conditions Current Control Amplifier (Output is at CCOUT) Input common mode voltage range VCM 0 VCC – 1 V Output voltage swing VO 1 VCC – 0.5 V Load current Io -2300 100 μA Input offset voltage VOS -3 +3 mV Slew rate SR 0.54 V/μs Gain bandwidth product GBW 1.15 MHz Phase margin PM 66 Deg CL= 10pf RL= 200k Rev. 6 | Page 9 of 22 | www.onsemi.com

3.4 Receiver Block

Table 10: Receiver Sub-blocks Parameter Symbol Min. Typ. Max. Units Conditions Band Pass Filter Input voltage VBP 1 4 V SIGIN pin to GND Output voltage swing FLTOUT 1 4 V Output slew rate SR 0.6 V/μs Input offset voltage VOS ± 5 mV RF1 60 75 90 kΩ RF2 216 270 324 kΩ RF3 16 20 24 kΩ Filter resistors (1) RF4 43 54 65 kΩ Carrier Detector VTH+ 40 50 60 mV Threshold voltage VTH- -60 -50 -40 mV Relative to VMID Output high voltage VOH VDD-0.6 V IOH = 0mA Output low voltage VOL 0.3 V IOL = 0mA Output high current IOH 50 μA VDD-VO ≤ 0.6V Output low current IOL 50 μA V O ≤ 0.6V Output rising time tR 0.3 μs CL = 10pF Output leak current tF 0.3 μs CL = 10pF Zero-cross Detector VTH+ V MID+0.025 V MID+0.040 V MID+0.058 V No carrier Threshold voltage VTH- VMID VMID VMID V Carrier active Output high voltage VOH VDD-0.6 V IOH = 0mA Output low voltage VOL 0.3 V IOL = 0mA Output high current IOH 50 μA VDD-VO ≤ 0.6V Output low current IOL 50 μA V O ≤ 0.6V Output rising time tR 0.3 μs CL = 10pF Output leak current tF 0.3 μs CL = 10pF Note: 1. The band pass filter is made up of a two pole high pass filter in series with a tw o pole low pass filter. The filter consis ts of four resistors internal to AMIS-492x0, and four external capacitors. The active part of each filter is an amplifier connected in a follower configuration. Rev. 6 | Page 10 of 22 | www.onsemi.com

4.0 Theory of Operation

4.1 Overview

The AMIS-492x0 incorporates two different power supply circuits. Both derive their power from the bus. Using the internal configuration, the shunt regulator is set for 5V and the series regulator is set for 3V. Users can modify either power supply by adding external components. The AMIS-492x0 Fieldbus can also monitor these power supply voltages and generate power-fail signals if t hey fall below a specified value. Please refer to the AMIS-492x0 Fieldbus MAU Reference Design Application Note for ways to adjust the shunt and series voltage regulators. The AMIS-492x0 Fieldbus MAU transmits a Manchester-encoded si gnal provided from a standard MDS -MAU interface. The output driver makes it possible to design various signal circuits, whic h depend on the power requirements of your device. The slew ra te of the signal can be controlled to minimize unnecessary radiation as specified in IEC/ISA standards. The AMIS-492x0 Fieldbus MAU has a built-in ba nd pass filter which makes it easy to desi gn your own receiver. The receive block operates on a Manchester-encoded signal. It decodes the signal a nd verifies proper amplitude with a zero-cross and carrier det ect circuit, respectively. Detected signals are then passed on to a controller with the standard MDS-MAU interface.

4.2 Power Supply Block

The power supply block contains four sub-blocks: 1. A shunt regulator - for establishing a supply voltage of V CC (typ. = 5V) used by the analog circuitry 2. A series regulator - for establishing a supply voltage of V DD (typ. = 3V) used for digital circuitry 3. Two low voltage detectors - for monitoring the two supply voltages 4. A bandgap voltage reference - which is used internally for generating a bias level for AC signals 4.2.1. Shunt Regulator The shunt regulator controls its sink current to the SHUNT pin so that the voltage applied to the SHSETIN pin is equal to VREF. The VCC input is divided by an internal network to provide a voltage equa l to Vref at the SHSET pin. If SHSET and SHSETIN pins are tie d together, and VCC and SHUNT pins are connected to a power source of high impedance (e.g., current mirror circuit of signal driver), the shunt regulator provides 5V power to itself and external circuits. A capacitor of 5 μF or larger capacity is necessary to stabilize this regulator. Figure 13 shows C10 (22μF) connected to Pin 8 to accomplish stabilization. It is possible to increase the V CC voltage up to 6.2V by dividing V CC with an external network to supply the appropriate voltage to SHSETIN pin. In this case, SHSET pin must be kept open. The output voltage is determined by the following equation: VCC = VREF × (1 + R1 / R2) Rsh 3 . 25 Rsh 25 mA ( Max ) VCC SHUNT SGNDSHSETIN SHSET Shunt Regulator ( Internal Configuration ) 9 6 7 A 6 System VCC Rsh 3.25Rsh 25 mA ( Max ) VCC SHUNT SGND SHSETINSHSET Shunt Regulator (External Configuration ) 9 6 7 System VCC N/C VREF VREF Cfb 50 pF 16 Meg Cfb 50 pF 16Meg Figure 4: Shunt Regulator Rev. 6 | Page 11 of 22 | www.onsemi.com

4.3 Transmit Block

The transmit block contains four sub-blocks: 1. MDS-interface – decodes input signals to generate internal control signals. 2. Tri-level modulator – generates current sign als used as inputs to the slew-rate controller. 3. Slew rate controller – converts current to three distinct VDRV voltage levels (V S, VH, VL). 4. Current drive amplifier – op amp designed to driv e current drivers for 31.25kbps voltage-mode medium. 4.3.1. MDS-interface The MDS-interface decodes input signals to generate internal control signals. The POL pin is used to select the polarity of TxE (transmit enable). The TxE and TxS (transmit signal) are the MDS-MAU interfac e signals. These three signals are CMOS logic signals power ed by the V DD supply voltage. When POL is connected to GND, TxE is assumed to be active high (positive logic). Likewise, if POL is connected to V DD, TxE is assumed to be active low (negative logic). See Table 1 on page 7, Table 11, and Figure 8 to see how MDS_CTRL Pin 26 can be used to control MDS interface operati on. Table 11 shows the resulting VDRV output for the various combinations of interface signals. Table 11: MDS-interface Logic POL TxE TxS VDRV Low Low High VS Low VH Low High High VL Low V H Low High V L Low High High High VS Figure 8: MDS Interface 4.3.2. Tri-level Modulator The tri-level modulator switches current signals into a summing no de. The slew rate controller converts the current to a volt age signal, VDRV. The DC level of silence (VS) is nominally 2.5V. Transmission high (VH ) is nominally 2.9V and transmission low (VL) is nominally 2.1V, yielding an amplitude of 0.8V. Rev. 6 | Page 14 of 22 | www.onsemi.com

R 20K 20R 400K CRT Tri-Level Modulator Slew Control VCC N_VL VMID 1.2K 80K 80K Active Low Active Low N_Vs 1.2K 1.2K Figure 9: Tri-level Modulator 4.3.3. Slew Rate Controller Amplifier (A3), shown in the above figure, controls the slew rate . The amplifier converts the cu rrent signals from the tri-level modulator to a voltage signal, VDRV. It controls its slew rate with a capacitor (C RT) connected to the CRT pin. The waveform at the VDRV pin is symmetric and the fall/rise times are determined by the following equation: tF, tR = 2.0[μs] + 0.12 [μs/pF] × CRT The constant part comes from the internal capacitor (not shown). It is recommended to make a guard pattern on your circuit boa rd around the CRT pin and the hot side of CRT to avoid unnecessary interference. 4.3.4. Current Drive Amplifier The drive amplifier is an operational amp lifier optimized to drive current drivers for 31.25kbps voltage-mode medium. Its input and output signals are exposed to allow flexible design of the external driver. Note that this amplifier cannot directly sink the necessary current from the medium. In the following drive circuit the current (I BUS) through the current-detect resister (R F) is determined by the following equation. [ R3 Vmid (R12 + R11 ) ] - [ Vdrv (R2 R11 + R3 R11 ) ] - [ RF ( R2 R12 + R3 R12 ) ] I bus = A diode and/or a resistor connected to the emitter are necessary to shift the DC level of CCOUT and to suppress the loop gain. The resistance value depends on your design (overall gain and emitter current). Rev. 6 | Page 15 of 22 | www.onsemi.com

Figure 10: Current Control Circuit

4.4 Receive Block

The receive block contains three sub-blocks, which are internally connected: 1. A band pass filter – to filter the desired incoming communication signal. 2. Carrier detector – generates the RxA si gnal by detecting the signal amplitude. 3. Zero-cross detector generates the RxS signal by detec ting the high/low transitions of the Manchester code. 4.4.1. Band Pass Filter The band pass filter is a series connection of a high-pass and a lo w-pass filters each having two poles. Each filter is comprised of a voltage follower and on chip resisters, so only four external capacitors are necessary. The following figure shows an internal circuit and the connection of external capacitors. Cut-off frequency, fL, of the high-pass filter is determined by C1 and C2 while cut-off frequency, fH, of the low-pass filter is determined by C3 and C4. 2 1 2 F 1 FC * C * R * R Lf π= 1 F 2 F R R LQ = =0.95 4 3 4 F 3 FC * C * R * R Hf π= C C The possible ranges of f L and f H are 1kHz ~ 10kHz and 10kHz ~ 100kHz, respectively. The values in the following figure are recommended to obtain 1kHz and 47.6kHz cut-off frequencies. Rev. 6 | Page 16 of 22 | www.onsemi.com

5.0 AMIS-49200 as Replacement for Yokogawa μSAA22Q

The AMIS-49200 is a near pin-for-pin co mpatible replacement for the Yokogawa μSAA22Q Fieldbus MAU. There are some differences between the two chips both in the internal operation, the requir ed external connections and the value (or existence) of some of the external components. These differences are small and those who used the μSAA22Q would most likely be able to use the AMIS-49200 in designs with only some component value changes.

5.1 Functional Differences Between the μSAA22Q and the AMIS-492x0

5.1.1. Jabber Inhibit The AMIS-492x0 does not implement the Jabber Inhibit function in the μSAA22Q. Typically the AMIS-492x0 will be connected with a link controller chip such as the UFC100-F1 from Aniotek/Softing. This link controller has a Jabber Inhibit function so the absence of this function in the AMIS-492x0 should not be a problem. As can be seen in Table 12 , MDS_CTRL is only connected to ground if POL is connected to VDD. See Table 1 for a detailed description of the interaction between MDS_CTRL and POL. In Table 12, the μSAA22Q recommends that the JAB/ signal (Pin 39) be connect ed to ground if the signal is not used. On AMIS-492x0, Pin 39 must be connected to ground. 5.1.2. Low Power Mode The low power mode on the μSAA22Q allows the user to have a quiescent current draw of less than 10mA yet still communicate at the proper IEC 61158-2 signal levels. Very few, if any, Fieldbus devices are capable of operating at such a low current level so th is capability was not included in the AMIS-492x0. The pins affected by this are 41, 42 and 43. If the low power mode is not being used on the μSAA22Q, these three pins are grounded. On the AMIS-492x0 it is required that these pins be grounded.

5.2 Pin Differences Between the μSAA22Q and the AMIS-492x0

Table 12: Pin Connection Differences Between the µSAA22Q and the AMIS-492x0 μSAA22Q AMIS-492x0 Pin No. Signal Name Recommended Connection Signal Name Required Connection

1 NC Ground VSS Ground

11 NC Ground VSS Ground

22 NC Ground VSS Ground

26 NC Ground MDS_CTRL Ground*

33 NC Ground VSS Ground

39 JAB/ Ground if not used VSS Ground

41 CJB 1 μf cap VSS Ground

42 VTX Ground VSS Ground

43 VSL Ground VSS Ground

• MDS_CTRL is only connected to ground if POL is connected to VDD. See Table 1 for a detailed description of the interaction between MDS_CTRL and POL. Rev. 6 | Page 18 of 22 | www.onsemi.com

5.3 External Circuitry

Figure 13 shows the external circuitry required to connect the AMIS-492 x0 to an IEC 61158-2 conformant network. This schematic is the circuit that was used to pass the FOUNDATION Fieldbus Physic al Layer Conformance test as specified in FOUNDATION Fieldbus specification FF830, Rev 1.5. This circuit is similar but not identical to the circuit recommended by Yokogawa for the μSAA22Q. Figure 13: AMIS-492x0 Reference Circuit Implementation Table 13 lists the four external component values that need to be changed with using the AMIS -492x0 in a circuit that previously used the μSAA22Q. Table 13: Passive External Component Value Differences Between the µSAA22Q and the AMIS-492x0 Component μSAA22Q Value AMIS-492x0 Value C1 100pf 150pf C3 100pf 47pf C4 470pf 220pf C8 10nf 1μf C1 connects to signal CCD (Pin 32) and controls the carrier det ect assert and drop-out timing. Particular implementations may r equire that the value of C1 be changed to accommodate received signal level changes introduced by the addition of intrinsic safety components added to the external circuitry. C3 and C4 are par t of the receive filter and determine the band pass characteristic s of the receive filter. It is unlikely that these would need to be changed. C8 is a noise filter for VMID . It is important that VMID ha ve as little noise as possible as it is used as a reference for many sub-circ uits in the AMIS-492x0. C8 must be a large capacitor with maxi mum of 100nf. C8 recommended value is 1μf. Rev. 6 | Page 19 of 22 | www.onsemi.com

There is one other minor difference in the recommended external circuitry between the μSAA22Q and the AMIS-492x0. Figure 14 shows the start-up circuits recommended for the μSAA22Q and the AMIS-492x0. The circuit shown for the AMIS-492x0 is different from that shown for the μSAA22Q but either one will work. Both are current sources that turn on when power is applied to the H1 segment terminals so that the AMIS-492x0 can turn on without any turn-on transients on the network. 1 k 100 k

5.1 V V Shunt

μSAA22Q Startup Circuit AMIS 49200 Startup Circuit Figure 14: Recommended Start-up Circuits

5.4 Active Components

Transistors Q1 – Q4 are ordinary small signal transistors. Diodes D1 and D2 are similarly ordinary small signal diodes. Users d esiring to replace a μSAA22Q with the AMIS-49200 in an existing design should be able to use whatever transistors and diodes were used with the μSAA22Q. For new designs, the specified transistors can be used or other devices may be chosen.

5.5 Alternative Designs

Some users of the Yokogawa μSAA22Q did not use the exact recommended external circuit for the media interface circuit (see Figure 13). Using the AMIS-492x0 without the Yokogawa recommended external circuit ma y result in some compat ibility problems. There are many alternative designs and it is beyond the scope of this doc ument to identify all possible configurations and their associat ed design implications. Please refer to the AMIS-492x0 Fieldbus MAU Re ference Design Application Note for a recommended, FOUNDATION Fieldbus certifiable board design.

5.6 Verification

All designs using the AMIS-492x0 should re-run the entire physical layer conformance test as defined in FOUNDATION Fieldbus document FF-830, FOUNDATION™ Specific ation 31.25 kbit/s Physical Layer Conformance Test. Board layout can alter the behavior of all circuit implementations, even designs that follow the recommended implementation. Rev. 6 | Page 20 of 22 | www.onsemi.com

6.0 Ordering Information

Part Number Package Shipping Configuration Temperature Range AMIS-49200-XTD 44 LQFP 10x10mm (Green/RoHS Compliant) Tray -40°C to 85°C AMIS-49200-XTP 44 LQFP 10x10mm (Green/RoHS Compliant) Tape & Reel -40°C to 85°C AMIS-49250-XTD 44 NQFP 7x7mm (Green/RoHS Compliant) Tray -40°C to 85°C AMIS-49250-XTP 44 NQFP 7x7mm (Green/RoHS Compliant) Tape & Reel -40°C to 85°C

7.0 Appendix (A) – Manchester Encoding

All Fieldbus devices transmit the data onto the media as a Manc hester-encoded baseband signal. With Manchester encoding, zeros and ones are represented by transitions that occur in the middle of t he bit period (see below). For FOUNDATION Fieldbus H1 and Profibus PA, the nominal bit time is 32 μsec, with the transition occurring at 16 μsec. The Manchester encoding rules have been extended to include two additional symbols, non-data plus (N+) and non-data minus (N-). The symbol encoding rules are shown in Figure 15. Logical "0" T "N+" T "N-" T Logical "1" T 32 usec Figure 15: Manchester Encoding Rev. 6 | Page 21 of 22 | www.onsemi.com

Rev. 6 | Page 22 of 22 | www.onsemi.com AMIS-492x0

8.0 Revision History

Revision Date Modification

1 April 2006 Initial release

2 October 2006

3 January 2007

4 February 2008 Update to new AMIS template

5 May 2008 Update to new ON Semiconductor template; update OPN table

6 June 2008 Added AMIS-49250

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