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© Semiconductor Components Industries, LLC, 2010 November, 2010 − Rev. P0

1 Publication Order Number:

AMIS−30523/D AMIS-30523 Product Preview CAN Micro-Stepping Motor Driver Introduction The AMIS −30523 is a micro −stepping stepper motor driver for bipolar stepper motors with an embedded CAN transceiver. The motor driver is connected through I/O pins and a SPI interface with an external microcontroller. It has an on−chip voltage regulator, reset−output and watchdog reset, able to supply peripheral devices. It contains a current −translation table and takes the next micro −step depending on the clock signal on the “NXT” input pin and the status of the “DIR” (=direction) register or input pin. The CAN transceiver is the interface between a (CAN) protocol controller and the physical bus. It provides differential transmit capability to the bus and differential receive capability to the CAN controller. To cope with the long bus delay the communication speed needs to be low. The integrated transceiver allows low transmit data rates down 10 kbit/s or lower. The AMIS −30523 is ideally suited for general −purpose stepper motor applications in the automotive, industrial, medical, and marine environment. With the on−chip voltage regulator and embedded CAN transceiver it further reduces the BOM for mechatronic stepper applications. Key Features Motor Driver

  • Dual H−Bridge for 2−Phase Stepper Motors
  • Programmable Peak−Current up to 1.2 A Continuous (1.6 A for a Short Time)*
  • On−Chip Current Translator
  • SPI Interface
  • Seven Step Modes from Full Step up to 32 Micro−Steps
  • PWM Current Control with Automatic Selection of Fast and Slow Decay and Fully Integrated Current−Sense
  • Full Output Protection and Diagnosis
  • Thermal Warning and Shutdown
  • Integrated 5 V Regulator to Supply External Microcontroller CAN Transceiver
  • Compatible with the ISO 11898 Standard
  • Wide Range of Bus Communication Speed (0 up to 1 Mbit/s)
  • Allows Low Transmit Data Rate in Networks Exceeding 1 km
  • Extremely Low Current Standby Mode with Wake−up via the Bus
  • Low EME: Common−Mode Choke is No Longer Required
  • Differential Receiver with Wide common−mode range (/C003635 V)
  • V oltage Source via VSPLIT Pin for Stabilizing the Recessive Bus Level
  • No Disturbance of the Bus Lines with an Un−Powered Node
  • Logic Level Inputs Compatible with 3.3 V Devices
  • These are Pb−Free Devices *Output Current Level May be Limited by Ambient Temperature and Heat Sinking This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. http://onsemi.com See detailed ordering and shipping information in the package dimensions section on page 34 of this data sheet.

ORDERING INFORMATION

0C523−001 = Specific Device Code XXXX = Date Code WL = Wafer Lot Y = Assembly Location ZZ = Traceability Code AMIS30523 0C523−001 XXXXYZZ QFN52, 8x8 CASE 485M MARKING DIAGRAM

Figure 1. Block Diagram AMIS−30523

Figure 2. Pin Out AMIS−30523 Table 1. PIN DESCRIPTION

Table 2. ABSOLUTE MAXIMUM RATINGS

  1. For limited time < 0.5 s.
  2. For 0 < V CC < 5.25 V unlimited time
  3. Applied transient waveforms in accordance with ISO 7637 part 3, test pulses 1, 2, 3a, and 3b.
  4. Circuit functionality not guaranteed.
  5. Standardized Human body model (100 pF via 1.5 k /C0087, according to JEDEC EIA−JESD22−A114−B).
  6. Standardized human body model electrostatic discharge (ESD) pulses (100 pF via 1.5 k /C0087) stressed pin to ground.
  7. Standardized charged device model ESD pulses when tested according to ESD STM5.3.1 −1999.

Table 3. THERMAL RESISTANCE representations of the circuits used. Figure 3. In− and Output Equivalent Diagrams

  • Static environmental air (via the case)
  • PCB board copper area (via the exposed pad) The thermal resistances are presented in Table 5: DC Parameters Motor Driver. The major thermal resistances of the device are the Rth from the junction to the ambient (RthJ−A) and the overall Rth from the junction to exposed pad (RthJ−EP). In Table 3 one can find the values for the Rth J−A and Rth J−EP, simulated according to JESD−51: The Rth J−A for 2S2P is simulated conform JEDEC JESD−51 as follows:
  • A 4−layer printed circuit board with inner power planes and outer (top and bottom) signal layers is used
  • Board thickness is 1.46 mm (FR4 PCB material)
  • The 2 signal layers: 70 /C0109m thick copper with an area of 5500 mm2 copper and 20% conductivity
  • The 2 power internal planes: 36 /C0109m thick copper with an area of 5500 mm2 copper and 90% conductivity The Rth J−A for 1S0P is simulated conform JEDEC JESD−51 as follows:
  • A 1−layer printed circuit board with a single power and signal layer
  • Board thickness is 1.46 mm (FR4 PCB material)
  • The layer has a thickness of 70 /C0109m copper with an area of 5500 mm2 copper and 20% conductivity ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ DO DI CPN MOTXP GND GND MOTXP POR/WD CLK VDD CLR CS DIR NXT SLA GND GND MOTYP VBB TSTO CPP VCP VBB VBB VBB MOTYP ERR CANH CANL STB TxD GND VCC RxD VSPLIT GND MOTYN GND MOTYN MOTXN MOTXN

Figure 4. Example of QFN−52 PCB Ground Plane Layout in Top View (preferred layout at top and bottom) may affect device reliability. Table 4. OPERATING RANGES

  1. No more than 100 cumulative hours in life time above T tw.

Table 5. DC PARAMETERS MOTOR DRIVER Convention: Currents Flowing in the Circuit are Defined as Positive.

6 V /C0118 VBB < 8 V 15 mA

8 V /C0118 VBB v 30 V 40 mA

  1. Characterization Data Only, not tested in production

10.The coil current at a given junction temperature is calculated as: Icoil @ TJ = Icoil [1 + (TJ − 125) x ISET_TCi x 10−6]. See also paragraph Programmable Peak Current.

  1. Not valid for pins with internal Pull Down resistor.

12.No more than 100 cumulated hours in life time above Ttw. 13.Thermal shutdown is derived from Thermal Warning.

Convention: Currents Flowing in the Circuit are Defined as Positive.

15 V < VBB < 30 V VBB + 9 VBB +

30 K/W

0.95 K/W

  1. Characterization Data Only, not tested in production

10.The coil current at a given junction temperature is calculated as: Icoil @ TJ = Icoil [1 + (TJ − 125) x ISET_TCi x 10−6]. See also paragraph Programmable Peak Current.

  1. Not valid for pins with internal Pull Down resistor.

12.No more than 100 cumulated hours in life time above Ttw. 13.Thermal shutdown is derived from Thermal Warning.

Table 6. AC PARAMETERS MOTOR DRIVER (The AC Parameters are Given for VBB and Temperature in Their Operating Ranges) 14.Characterization Data Only, not tested in production.

Figure 5. NXT−Input Timing Diagram

0.5 VCC

Table 7. SPI TIMING PARAMETERS Figure 6. SPI Timing

0.8 VCC

Table 8. DC PARAMETERS CAN TRANSCEIVER specified) Convention: currents flowing in the circuit are defined as positive. 15.Characterization Data Only, not tested in production.

specified) Convention: currents flowing in the circuit are defined as positive. 15.Characterization Data Only, not tested in production.

Figure 12. EME Measurements

Figure 13. Typical Application Schematic AMIS−30523 Table 10. EXTERNAL COMPONENTS LIST AND DESCRIPTION

driver provides a so−called “speed and load angle” output. bit <MOTEN> disables all drivers (high −impedance). can flow in the motor stator windings. simultaneously (interlock delay). the transistor, the transistor is switched off. voltage slope control is implemented in the output switches. Table 15 SPI Control Parameter Overview EMC[1:0]). Motor driver, for more details. external components required to adjust the PWM frequency. parameters are required for operation. Figure 14. Forward and Slow/Fast Decay PWM

AMIS−30523 http://onsemi.com Automatic Duty Cycle Adaptation In case the supply voltage is lower than 2 * Bemf, then the duty cycle of the PWM is adapted automatically to >50% to maintain the requested average current in the coils. This process is completely automatic and requires no additional parameters for operation. The over −all current −ripple is divided by two if PWM frequency is doubled (see Table 15 SPI Control Parameter Overview PWMF) Actual value Duty Cycle <5 0 % Duty Cycle >50% Duty Cycle < 50% t Icoil Set value TPWM Figure 15. Automatic Duty Cycle Adaption Step Translator and Step Mode The step translator provides the control of the motor by means of SPI register Stepmode: SM[2:0], SPI register DIRCNTRL and input pins DIR and NXT. It is translating consecutive steps in corresponding currents in both motor coils for a given step mode. One out of seven possible stepping modes can be selected through SPI −bits SM[2:0] (see Table 15 SPI Control Parameter Overview ) After power −on or hard reset, the coil−current translator is set to the default 1/32 micro−stepping at position ‘0’. Upon changing the step mode, the translator jumps to position 0* of the corresponding stepping mode. When remaining in the same step mode, subsequent translator positions are all in the same column and increased or decreased with 1. Table 12 lists the output current vs. the translator position. As shown in Figure 16 the output current −pairs can be projected approximately on a circle in the (I x,Iy) plane. There are, however, two exceptions: uncompensated half step and full step. In these step modes the currents are not regulated to a fraction of I max but are in all intermediate steps regulated at 100%. In the (Ix,Iy) plane the current−pairs are projected on a square. Table 11 lists the output current vs. the translator position for these cases.

Table 11. SQUARE TRANSLATOR TABLE FOR FULL STEP AND UNCOMPENSATED HALF STEP Figure 16. Translator Table: Circular and Square

Table 12. CIRCULAR TRANSLATOR TABLE

<SLAG> (see Table 15 SPI Control Parameter Overview). sampling and hold moments of the coil voltage. Figure 21. Timing Diagram of SLA−Pin Crossing. SLA−pin is updated “real−time”. reading out Status Register 2. reading Status Register 1 or 2) to reactivate the drivers.

outputs other motor drivers. voltage level is derived from an internal bandgap reference. Figure 22. Power−on−Reset Timing Diagram

microcontroller is alive again. See Figure 23. Figure 23. Watchdog Timing Diagram NOTE: t DSPI is the time needed by the external microcontroller to shift−in the <WDEN> bit after a power−up.

Table 13. WATCHDOG TIMEOUT INTERVAL AS Logic 0 on CLR pin allows normal operation of the chip. CLR. (See Table 6 AC Parameters Motor Driver). resumes normal operation again. function is reset completely. current−consumption when the motor is not in operation.

  • The drivers are put in HiZ
  • All analog circuits are disabled and in low−power mode
  • All internal registers are maintaining their logic content
  • NXT and DIR inputs are forbidden
  • SPI communication remains possible (slight current increase during SPI communication)
  • Oscillator and digital clocks are silent, except during SPI communication The voltage regulator remains active but with reduced current−output capability (ILOADSLP). The watchdog timer stops running and it’s value is kept in the counter. Upon leaving sleep mode, this timer continues from the value it had before entering sleep mode. Normal operation is resumed after writing logic ‘0’ to bit <SLP>. A start−up time is needed for the charge pump to stabilize. After this time, (tcpu) NXT commands can be issued.
  • WRITE to SPI Register with address ADDR[4:0]: CMD2 = “1” READ Operation If the Master wants to read data from Status or Control Registers, it initiates the communication by sending a READ command. This READ command contains the address of the SPI register to be read out. At the falling edge of the eight clock pulse the data−out shift register is updated with the content of the corresponding internal SPI register. In the next 8−bit clock pulse train this data is shifted out via DO pin. At the same time the data shifted in from DI (Master) should be interpreted as the following successive command or dummy data.

Figure 26. Single READ Operation where DATA from SPI Register with Address 1 is Read by the Master noise and increases the consistency of the transmitted data. an additional READ command to obtain the status again. same routine. Control Registers don’t have a parity check. successive READ commands as illustrated in Figure 28. data stored in the last received address. unknown the data shifted out via DO is not valid.

Table 14. SPI CONTROL REGISTERS (All SPI control registers have Read/Write Access and default to ”0” after power−on or Table 15. SPI CONTROL PARAMETER OVERVIEW

00 Very Fast

01 Fast

10 Slow

11 Very Slow

100 Compensated Half Step

101 Uncompensated Half Step

110 Full Step

CUR[4:0] Selects IMCmax peak. This is the peak or amplitude of the regulated current waveform in the motor coils. Table 16. SPI CONTROL PARAMETER OVERVIEW CUR[4:0] 20.Reducing the current over different current ranges might trigger overcurrent detection. See application note AND8372/D for solutions. All 4 SPI status registers have Read Access and are default to “0” after power−on or hard reset. Table 17. SPI STATUS REGISTERS

Table 18. SPI STATUS FLAGS OVERVIEW does not reach the required voltage level.

1 Status Register 1 ‘0’ = no failure

1 Status Register 2 ‘0’ = no failure

excellent matching of the output signals. extreme low current in stand−by mode. transmit data rates down 10 kbit/s or lower. Table 19. OPERATING MODES transceiver to inform the controller of the wake−up request. circuit is particularly needed when a bus line short circuits. dissipation increases during this fault condition. Specifications Brochure, BRD8011/D.

AMIS−30523 http://onsemi.com PACKAGE DIMENSIONS ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ QFN52 8x8, 0.5P CASE 485M−01 ISSUE C C0.15 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. AD E B C0.08 A1 A3 A L NOTE 3 C0.15 SEATING PLANE C0.10 C 52 X e 14 26 4052 b52 X A0.10 BC 0.05 C DIM MIN MAX MILLIMETERS A 0.80 1.00 A1 0.00 0.05 A2 0.60 0.80 A3 0.20 REF b 0.18 0.30 D 8.00 BSC D2 6.50 6.80 E 8.00 BSC E2 6.50 6.80 e 0.50 BSC K 0.20 --- REF K52 X L 0.30 0.50 PIN ONE REFERENCE SOLDERING FOOTPRINT DIMENSIONS: MILLIMETERS 8.30 6.75 6.75 0.50 0.62 0.30 52X 52X PITCH 8.30 PKG OUTLINE RECOMMENDED *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 pubnumber/D LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative