AMIS-30521_10 ONSEMI | Alldatasheet
Document overview
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Technical content
Features
- Dual H−Bridge for 2 Phase Stepper Motors
- Programmable Peak−Current Up to 1.2 A Continuous (1.5 A Short Time), Using a 5−Bit Current DAC
- On−Chip Current Translator
- SPI Interface
- Speed and Load−Angle Output
- 7 Step Modes from Full Step−up to 32 Micro−Steps
- Fully Integrated Current−Sense
- PWM Current Control with Automatic Selection of Fast and Slow Decay
- Low EMC PWM with Selectable V oltage Slopes
- Active Flyback Diodes
- Full Output Protection and Diagnosis
- Thermal Warning and Shutdown
- Digital IO’s Compatible with 5 V and 3.3 V Microcontrollers
- NCV Prefix for Automotive and Other Applications Requiring Site and Control Changes
- These are Pb−Free Devices* *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com See detailed ordering and shipping information in the package dimensions section on page 26 of this data sheet.
ORDERING INFORMATION
PC20070309.2 CPN CPP VCP CLR VBB MOTYP MOTYP CS VDD DO TSTO VBB MOTXP MOTXP PINOUT
AMIS−30521, NCV70521 http://onsemi.com Table of Contents Page
Figure 1. Block Diagram AMIS−30521/NCV70521 Table 1. PIN DESCRIPTION
Table 2. ABSOLUTE MAXIMUM RATINGS
- Circuit functionality not guaranteed.
- Human Body Model (100 pF via 1.5 k /C0087, according to JEDEC EIA−JESD22−A114−B)
- HiV = High Voltage Pins MOTxx, V
Table 3. THERMAL RESISTANCE representations of the circuits used. Figure 2. In− and Output Equivalent Diagrams
example for good power distribution solutions.
- Static environmental air (via the case)
- PCB board copper area (via the exposed pad) The thermal resistances are presented in Table 5: DC Parameters. The major thermal resistances of the device are the Rth from the junction to the ambient (Rthja) and the overall Rth from the junction to exposed pad (Rthjp). In Table 3 one can find the values for the R thja simulated according to JESD−51. The Rthja for 2S2P is simulated conform JEDEC JESD−51 as follows:
- A 4−layer printed circuit board with inner power planes and outer (top and bottom) signal layers is used
- Board thickness is 1.46 mm (FR4 PCB material)
- The 2 signal layers: 70 /C0109m thick copper with an area of 5500 mm2 copper and 20% conductivity
- The 2 power internal planes: 36 /C0109m thick copper with an area of 5500 mm2 copper and 90% conductivity The Rthja for 1S0P is simulated conform JEDEC JESD−51 as follows:
- A 1−layer printed circuit board with only 1 layer
- Board thickness is 1.46 mm (FR4 PCB material)
- The layer has a thickness of 70 /C0109m copper with an area of 5500 mm2 copper and 20% conductivity ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ
Figure 3. Example of NQFP−32 PCB Ground Plane Layout in Top View (Preferred Layout at Top and Bottom) may affect device reliability. Table 4. OPERATING RANGES
- No more than 100 cumulative hours in life time above T tw
Table 5. DC PARAMETERS
- Current with oscillator running, all analogue cells active, SPI communication and NXT pulses applied. No floating inputs. Guaranteed by
- Current with all analogue cells in power down. Logic is powered but no clocks running. All outputs unloaded, no inputs floati ng.
- Not valid for pins with internal Pulldown resistor
- Characterization Data Only
10.POR is derived from VDD. For proper POR operation VBB needs to be minimal VBB_min.
6 V /C0118 VBB /C0118 14 V 2 * VBB
14 V < VBB /C0118 30 V VBB +
- No more than 100 cumulative hours in life time above Ttw
Table 6. AC PARAMETERS (AC Parameters are Given for VBB and Temperature in Their Operating Ranges)
0.5 VCC
Figure 4. NXT−Input Timing Diagram
Table 7. SPI TIMING PARAMETERS
0.2 VCC
0.8 VCC
Figure 5. SPI Timing
Figure 6. Typical Application Schematic AMIS−30521/NCV70521 Table 8. EXTERNAL COMPONENTS LIST AND DESCRIPTION bit <MOTEN> disables all drivers (High −Impedance). can flow in the motor stator windings. simultaneously (interlock delay). the transistor, the transistor is switched−off. voltage slope control is implemented in the output switches. Table 12 SPI Control Parameter Overview EMC[1:0]).
through SPI−bits SM[2:0] (Table 12). is set to the default 1/32 micro −stepping at position ’0’. translator position for these cases. Table 9. SQUARE TRANSLATOR TABLE FOR FULL STEP AND UNCOMPENSATED HALF STEP
Table 10. CIRCULAR TRANSLATOR TABLE
Figure 13. Principle of Bemf measurement sampling and hold moments of the coil voltage.
Figure 14. Timing Diagram of SLA−Pin VBEMF sampling @ coil current zero crossing. SLA−pin is updated “real−time”. VBEMF sampling @ coil current zero crossing. SLA−pin is updated when leaving current−less state. the SPI status register is set (<OPENX> or <OPENY>).
AMIS−30521, NCV70521 http://onsemi.com Charge Pump Failure The charge pump is an important circuit that guarantees low R DS(on) for all drivers, especially for low supply voltages. If the supply voltage is too low or external components are not properly connected to guarantee R DS(on) of the drivers, then the bit <CPFAIL> is set in the SPI status register 0. Also after power −on−reset the charge pump voltage will need some time to exceed the required threshold. During that time <CPFAIL> will be set to “1”. Error Output This is an open drain digital output to flag a problem to the external microcontroller. The signal on this output is active low and the logic combination of: NOT(ERR) = <TW> OR <TSD> OR <OVCXij> OR < OVCYij> OR <OPENi> OR <CPFAIL> CLR Pin (=Hard Reset) Logic 0 on CLR pin allows normal operation of the chip. To reset the complete digital inside the AMIS−30521/ NCV70521, the input CLR needs to be pulled to logic 1 during minimum time given by t CLR. (See AC Parameters) This reset function clears all internal registers without the need of a power−cycle except in sleep mode. The operation of all analog circuits is depending on the reset state of the digital, charge pump remains active. Logic 0 on CLR pin resumes normal operation again. Sleep Mode The bit <SLP> in SPI control register 2 is provided to enter a so−called “sleep mode”. This mode allows reduction of current−consumption when the motor is not in operation. The effect of sleep mode is as follows:
- The Drivers are Put in HiZ
- All Analog Circuits are Disabled and in Low−Power Mode
- All Internal Registers are Maintaining Their Logic Content
- NXT and DIR Inputs are Ignored
- SPI Communication Remains Possible (Slight Current Increase During SPI Communication)
- Oscillator and Digital Clocks are Silent, Except During SPI Communication Normal operation is resumed after writing logic ’0’ to bit <SLP>. A startup time is needed for the charge pump to stabilize. After this time, NXT commands can be issued. When the device is in sleep mode and V BB becomes lower than VBB_min the device might reset. SPI INTERFACE The serial peripheral interface (SPI) allows an external microcontroller (Master) to communicate with the AMIS−30521/NCV70521. The implemented SPI block is designed to interface directly with numerous microcontrollers from several manufacturers. The AMIS−30521/NCV70521 acts always as a Slave and cannot initiate any transmission. The operation of the device is configured and controlled by means of SPI registers which are observable for read and/or write from the Master. SPI Transfer Format and Pin Signals During a SPI transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). A serial clock line (CLK) synchronizes shifting and sampling of the information on the two serial data lines (DO and DI). DO signal is the output from the Slave (AMIS−30521/NCV70521), and DI signal is the output from the Master. A chip select line (CS ) allows individual selection of a Slave SPI device in a multiple−slave system. The CS line is active low. If the AMIS−30521/NCV70521 is not selected, DO is pulled up with the external pull up resistor. Since AMIS−30521/NCV70521 operates as a Slave in MODE 0 (CPOL = 0; CPHA = 0) it always clocks data out on the falling edge and samples data in on rising edge of clock. The Master SPI port must be configured in MODE 0 too, to match this operation. The SPI clock idles low between the transferred bytes. The diagram below is both a Master and a Slave timing diagram since CLK, DO and DI pins are directly connected between the Master and the Slave.
noise and increases the consistency of the transmitted data. an additional READ command to obtain the status again. same routine. Control Registers don’t have a parity check. successive READ commands as illustrated in Figure 19. the CS line high always when the SPI bus is idle. unknown the data shifted out via DO is not valid. Figure 18. Single WRITE Operation Where DATA from the Master is Written in SPI Register with Address 3
Table 12. SPI CONTROL PARAMETER OVERVIEW
00 Very Fast
01 Fast
10 Slow
11 Very Slow
100 Compensated Half Step
101 Uncompensated half Step
110 Full Step
CUR[4:0] Selects IMCmax peak. This is the peak or amplitude of the regulated current waveform in the motor coils. Table 13. SPI CONTROL PARAMETER OVERVIEW: CURRENT AMPLITUDE CUR[4:0] 16.Typical current amplitude at TJ = 125. 17.Reducing the current over different current ranges might trigger overcurrent detection, please refer to dedicated application note for solutions. All 4 SPI Status Registers have Read Access and are default to ”0” after Power−on or hard reset. Table 14. SPI STATUS REGISTERS
Table 15. SPI STATUS FLAGS OVERVIEW not reach the required voltage level.
1 Status Register 1
1 Status Register 2
AMIS−30521, NCV70521 http://onsemi.com DEVICE ORDERING INFORMATION Part Number Temperature Range Package Type Peak Current Shipping† AMIS30521C5212RG −40°C − 125°C NQFP−32 (Pb−Free) 1600 mA Tape & Reel AMIS30521C5212G −40°C − 125°C NQFP−32 (Pb−Free) 1600 mA Tube / Tray NCV70521MN003R2G* −40°C − 125°C NQFP−32 (Pb−Free) 1600 mA Tape & Reel NCV70521MN003G* −40°C − 125°C NQFP−32 (Pb−Free) 1600 mA Tube / Tray †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *Qualified for automotive applications.
AMIS−30521, NCV70521 http://onsemi.com PACKAGE DIMENSIONS NQFP−32, 7x7 CASE 560AA−01 ISSUE O
AMIS−30521, NCV70521 http://onsemi.com NQFP−32, 7x7 CASE 560AA−01 ISSUE O ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 AMIS−30521/D LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative