AMIS-30512

AMIS-30512 ONSEMI | Alldatasheet

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© Semiconductor Components Industries, LLC, 2008 September, 2008 − Rev. 1

1 Publication Order Number:

AMIS−30512/D AMIS-30512 Micro-Stepping Motor Driver Introduction The AMIS −30512 is a micro −stepping stepper motor driver for bipolar stepper motors. The chip is connected through I/O pins and a SPI interface with an external microcontroller. It has an on −chip voltage regulator, reset −output and watchdog reset, able to supply peripheral devices. The AMIS −30512 contains a current −translation table and takes the next micro−step depending on the clock signal on the “NXT” input pin and the status of the “DIR” (=direction) register or input pin. The chip provides a so −called “speed and load angle” output. This allows the creation of stall detection algorithms and control loops based on load −angle to adjust torque and speed. It is using a proprietary PWM algorithm for reliable current control. The AMIS−30512 is implemented in I2T100 technology, enabling both high −voltage analog circuitry and digital functionality on the same chip. The chip is fully compatible with the automotive voltage requirements. The AMIS −30512 is ideally suited for general −purpose stepper motor applications in the automotive, industrial, medical, and marine environment. Key Features

• Dual H−Bridge for 2−phase Stepper Motors
• Programmable Peak−current up to 800 mA Using a 5−bit Current DAC
• On−chip Current Translator
• SPI Interface
• Speed and Load Angle Output
• Seven Step Modes from Full−step up to 32 Micro−steps
• Fully Integrated Current−sense
• PWM Current Control with Automatic Selection of Fast and Slow Decay
• Low EMC PWM with Selectable V oltage Slopes
• Active Fly−back Diodes
• Full Output Protection and Diagnosis
• Thermal Warning and Shutdown
• Compatible with 3.3 V Microcontrollers, 5 V Tolerant Inputs
• Integrated 5 V Regulator to Supply External Microcontroller
• Integrated Reset Function to Reset External Microcontroller
• Integrated Watchdog Function http://onsemi.com Device Package Shipping

ORDERING INFORMATION

AMIS30512 SOIC 24 Tape & Reel PIN ASSIGNMENT (Top View) TSTO MOTXP VBB GND MOTXN MOTYN GND MOTYP VBB CS CLR DO DI GND CLK NXT DIR ERR SLA CPN CPP VCP VDD AMIS30512 POR/WD

Figure 1. Block Diagram

Table 1. Pin List and Descriptions Table 2. Absolute Maximum Ratings

1. For limited time < 0.5 s.
2. Human body model (100 pF via 1.5 k /C0087, according to JEDEC EIA−JESD22−A114−B).

Table 3. Recommended Operating Conditions periods of time may affect device reliability.

Table 4. DC Parameters (The DC parameters are given for VBB and temperature in their operating ranges unless otherwise

8 V < VBB < 30 V 50 mA

1. Not valid for pins with internal pull −down resistor
2. No more than 100 cumulated hours in life time above Tt w
3. Thermal shutdown and low temperature warning are derived from thermal warning.

1. Not valid for pins with internal pull −down resistor
2. No more than 100 cumulated hours in life time above Tt w
3. Thermal shutdown and low temperature warning are derived from thermal warning.

Table 5. AC Parameters (The AC parameters are given for VBB and temperature in their operating ranges.)

Figure 2. NXT−input Timing Diagram

Table 6. SPI Timing Parameters Figure 5. SPI Timing

Figure 6. Typical Application Schematic Table 7. External Components List and Description

bit <MOTEN> disables all drivers (high −impedance). can flow in the motor stator windings. simultaneously (interlock delay). the transistor, the transistor is switched−off. voltage slope control is implemented in the output switches. (Table 25: SPI Control Parameter Overview EMC[1:0]). through the inherent parasitic drain−bulk diode. frequency will not vary with changes in the supply voltage. required to adjust the PWM frequency. parameters are required for operation. Figure 7. Forward and Slow/Fast Decay PWM

Figure 8. Automatic Duty Cycle Adaptation coils for a given step mode. output current versus the translator position. There is, however, one exception: uncompensated half step. translator position for this case. Table 8. Square Translator Table for Full Step and Uncompensated Half Step

Table 9. Circular Translator Table

Figure 11. NXT−Step Mode Synchronization resolution was programmed. The right−hand side diagram shows the effect of subsequent NXT commands on the micro−step position. resolution was programmed. The right−hand side diagram shows the effect of subsequent NXT commands on the half−step position. parameter “CUR[4:0]” (Table 13: SPI Control Register 0). range: See Table 4: DC Parameters. Table 10. Programmable Peak Current CUR[4:0] NOTE: Changing the current over different current ranges might lead to false over current triggering.

observation points per electrical period. Figure 12. Principle of Bemf Measurement the sampling and hold moments of the coil voltage.

Figure 13. Timing Diagram of SLA−pin updated when leaving current−less state. Crossing. SLA−pin is updated “real−time”. warning bit <TW> is set (Table 27: SPI Status Register 0). the status bits to reactivate the drivers. lead to false over current triggering. low Rdson for all drivers, especially for low supply voltages.

threshold. During that time <CPFAIL> will be set to “1”. chip, some low-voltage analog blocks and external circuitry. The voltage is derived from an internal bandgap reference. loads connected to logic outputs. See DC parameters. Figure 14. Power−on−Reset Timing Diagram

Figure 15. Watchdog Timing Diagram NOTE: t DSPI is the time needed by the external microcontroller to shift-in the <WDEN> bit after a power-up. Control Register WR). The timing is given in Table 11. Table 11. Watchdog Timeout Interval as Function of Logic 0 on CLR pin allows normal operation of the chip.

• The drivers are put in HiZ
• All analog circuits are disabled and in low−power mode
• All internal registers are maintaining their logic content
• Pulses on NXT and DIR inputs are ignored
• SPI communication remains possible (slight current increase during SPI communication)
• Reset of chip is possible through CLR pin
• Oscillator and digital clocks are silent, except during SPI communication Normal operation is resumed after writing logic ‘0’ to bit <SLP>. A start−up time t CPU is needed for the charge pump to stabilize. After this time, NXT commands can be issued.

from AMIS−30512 in a READ operation.

• READ from SPI Register with address ADDR[4:0]: CMD2 = “0”
• WRITE to SPI Register with address ADDR[4:0]: CMD2 = “1” READ Operation If the Master wants to read data from Status or Control Registers, it initiates the communication by sending a READ command. This READ command contains the address of the SPI register to be read out. At the falling edge of the eight clock pulse the data−out shift register is updated with the content of the corresponding internal SPI register. In the next 8−bit clock pulse train this data is shifted out via DO pin. At the same time the data shifted in from DI (Master) should be interpreted as the following successive command or is dummy data.

Figure 18. Single READ operation where DATA from SPI register with noise and increases the consistency of the transmitted data. an additional READ command to obtain the status again. successive READ commands as illustrated in Figure 18. data stored in the last received address. unknown the data shifted out via DO is not valid.

All SPI control registers have Read/Write access and default to “0” after power−on or hard reset. Table 12. SPI Control Register WR this timer (if already enabled). Writing “0” to this bit will clear WD bit (SPI Status Register 0). Table 13. SPI Control Register 0 Table 14. SPI Control Register 1

Table 15. SPI Control Register 2 Table 16. SPI Control Parameter Overview SLAT Table 17. SPI Control Parameter Overview SLAG Table 18. SPI Control Parameter Overview PWMF Table 19. SPI Control Parameter Overview PWMJ Table 20. SPI Control Parameter Overview SLP Table 21. SPI Control Parameter Overview MOTEN Table 22. SPI Control Parameter Overview DIRCTRL Table 23. SPI Control Parameter Overview NXTP CUR[4:0] Selects IMCmax peak. This is the peak or amplitude of the regulated current waveform in the motor coils.

Table 24. SPI Control Parameter Overview CUR[4:0] EMC[1:0] Adjusts the dV/dt of the PWM voltage slopes on the motor pins. Table 25. SPI Control Parameter Overview EMC[1:0] SM[2:0] Selects the micro −stepping mode. Table 26. SPI Control Parameter Overview SM[2:0]

All four SPI status registers have Read Access and are default to “0” after power−on or hard reset. Table 27. Status Register 0 (SR0) Table 28. Status Register 1 (SR1) Table 29. SPI Status Register 2 (SR2)

Table 30. SPI Status Register 3 (SR3) Table 31. SPI Status Flags Overview not reach the required voltage level.

re-flow soldering is often used. heating in a conveyor type oven. should preferably be kept below 230°C. double-wave soldering method was specifically developed.

• Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave.
• For packages with leads on two sides and a pitch (e): 1. Larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the PCB; 2. Smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the PCB. The footprint must incorporate solder thieves at the downstream end.
• For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the PCB. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is four seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Manual Soldering Fix the component by first soldering two diagonally- opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300°C. When using a dedicated tool, all other leads can be soldered in one operation within two to five seconds between 270 and 320°C.

Table 32. Soldering Process

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect
2. These packages are not suitable for wave soldering as a solder joint between the PCB and heatsink (at bottom version) can not be achieved,

and as solder may stick to the heatsink (on top version).

1. If wave soldering is considered, then the package must be placed at a 45 ° angle to the solder wave direction. The package footprint must

incorporate solder thieves downstream and at the side corners. for packages with a pitch (e) equal to or smaller than 0.65 mm.

1. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable

for packages with a pitch (e) equal to or smaller than 0.5 mm.

AMIS−30512 http://onsemi.com PACKAGE DIMENSIONS

24 LEAD SOIC

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 AMIS−30512/D LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative