AMB0480XXRH

IDTAMB0480 IDT | Alldatasheet

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ADVANCED MEMORY BUFFER FOR FULLY BUFFERED DIMM COMMERCIAL TEMPERATURE RANGE APRIL 2006 2006 Integrated Device Technology, Inc. DSC - 7042/2c COMMERCIAL TEMPERATURE RANGE FEATURES:

• Advanced Memory Buffer for Fully buffered DIMMs  3.2 and 4 Gbit/s serial speeds (DDR2-533 and 667 DRAM)  Support for up to eight DIMMs per channel  Repeater Mode for extending FB-DIMM links  Northbound and Southbound single lane fail over and channel error detection  Voltage and Timing margin high-speed I/O test capability  Fully Supports the FB-DIMM configuration register set  Test features supported include: - Integrated thermal sensor and status indicator - Supports MEMBIST, IBIST and Virtual Host mode - Transparent mode and direct access mode for DRAM testing  Complies with JEDEC Architecture and Protocol Specification  Available in 655 ball FCBGA package EXPANDED FEATURES:  Wide range DDR Timing Control  Superfine adjustment for DDR timing  Wide range of DDR slew rate control  Slew rate controllable independent of output impedance  High speed SMBus in test mode  IBIST IDT PRBS Generator The IDT logo is a registered trademark of Integrated Device Technology, Inc. DESCRIPTION: The fully buffered dual in-line memory module (FB-DIMM) is the next generation memory architecture to meet the growing memory requirement of servers and workstations. The IDT Advanced Memory Buffer (AMB) chip is the essential building block located on each FB-DIMM. The IDT AMB receives commands and data from the host controller to control and write/read data to/ from the DRAMs on the DIMM. Commands and write data are sent southbound from the host controller to AMBs in a daisy chain fashion and interpreted by the target AMB. Status and read data are sent northbound from AMBs to the host controller also in a daisy chain fashion, passing through non-target AMBs. This unique channel structure alleviates buffer loading issues common in registered DIMM technology, enabling designers to use a large number of DIMMs within a single system. IDTAMB0480 complies with the latest JEDEC defined FB-DIMM Architecture and Protocol Specification and supports DDR2-533 and DDR2-667 DRAM. It also enables serial data transfer at 3.2 and 4.0Gbps. The IDTAMB0480 supports servers, workstations, storage devices and communication applications that support the next generation FB-DIMM architecture. IDTAMB0480 PRODUCT BRIEF ADVANCED MEMORY BUFFER FOR FULLY BUFFERED DIMM MODULES Host Memory Controller DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 Up to 8 modules DDR2 DDR2 DDR2 DDR2 IDT AMB DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 IDT AMB IDT AMB IDT AMB FDB MEMORY CHANNEL

COMMERCIAL TEMPERATURE RANGE IDTAMB0480 ADVANCED MEMORY BUFFER FOR FULLY BUFFERED DIMM CLK[3:0] A[15:0]A/BA[2:0]A Thermal Sensor SMBus Controller SA[2:0] SCL SDA Failover Link Init FSM and Control Cmnd Decode & CRC Check IBIST Rx IBIST Tx SB Link CSRs External MemBIST, DDR Calibration and DDR IOBIST Re-sync FIFO De-skew FIFO Re-skew FIFO SIPO PISO 10 x 12b 10 x 12b CLK[3:0] 32 x 144b DDR State Controller DDR Link CSRs Termination FSMFBDRES A[15:0]B/BA[2:0]B RASA/CASA/WEA RASB/CASB/WEB CS[1:0]A/CKE[1:0]A CS[1:0]B/CKE[1:0]B BFUNC Core Control and CSRs Reset ControlRESET SB clock CB[7:0]/DQ[63:0] DQS[17:0] Write Data FIFO DQS[17:0] Impedance Control FSM DDRC_B12 DDRC_C12 Sync and Idle Pattern Gen CRC Gen & Read FIFO Failover Northbound Lanes Re-sync FIFO De-skew FIFO Re-skew FIFO SIPOPISO 14 x 12b14 x 12b Link Init FSM and Control IBIST RxIBIST Tx NB Link CSRs SCK Phase-locked Loop Clock GeneratorPLLTSTO NB clock REF clock DDR clocks SCK DLL 10 x 2 10 x 2 Southbound LanesPS[9:0]/PS[9:0] SS[9:0]/SS[9:0] Vref ODTA ODTB 14 x 2 14 x 2 144b 144b168b DDRC_B18 DDRC_C18 DDRC_C14 FUNCTIONAL BLOCK DIAGRAM

ADVANCED MEMORY BUFFER FOR FULLY BUFFERED DIMM COMMERCIAL TEMPERATURE RANGE PIN CONFIGURATIONS A B C D E F G H J K L M N P R T U V W Y AA AB AC 1 2 3 4 5 6 7 8 9 1 01 11 21 31 41 5 NC NCNC NC NCNC NC NCNC NC NCNC NC NCNC NC NCNC NC NCNC NC NCNC NC NCNC NC NCNC NC NCNC NC NCNC NC NCNC NC NCNC NC NCNC NC NCNC NC NCNC NC NCNC NC NCNC NC NCNC NC NCNC NC NCNC VSS VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCC FBD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSSVSS VSS VSS VSS VSS VSS VSS VSS VSS VSS APLL VCC APLL A6A A4A PN0 PN1 PN2 PN3 PN4 PN0 PN1 PN2 PN3 PN4 RESET PN5 PN13 RFU (1) PN12 PN6 PN7 PN8 PN9 PN10 PN11FBD RES PLL TSTO PN5 PN13 RFU PN12 PN6 PN7 PN8 PN9 PN10 PN11 (1) SN0 SN1 SN2 SN0 SN1 SN2 SN3 SN4 SN5 SN13 SN12 SN6 SN7 SN8 SN9 SN10 SN3 SN4 SN5 SN13 SN12 SN6 SN7 SN8 SN9 SN10 A15A A14A A12A A9A A7A A5AA11A A2A A1A A3A A10ABA0A CASA BA2A A0A CKE 0A VSS WEA RASA CKE 1ABA1A DQ28 DQ30 DQS VSS DQS TEST LO TEST DQ19 DQ21 DQS DQ22 CLK2 CLK0 ODT CS1A CS0A DQS2 DQS2 DQ20 DQS CLK2 CLK0 RFU A8A A13A DQS3 DQ18 DQ17 DQ23 DQ26 DQS3 DQ16 DQ29 DQ31 DQ27 DQ25 DQ24 DQ4 DQS9 DQ14 DQ12 DQS DQS DQS9 DQ6 DQ13 DQ11 DQ15 DQ9 DQ7 DQ5 DQS1 DQ10 DQS1 DQ8 DQ3 DQS0 DQ1 DQS0 RFU (1) RFU (1) RFU DDRC _C12 DQ0 DQ2 BFUNC TEST LO TEST LO DQS8 CB1 RFU RFU RFU DDRC _B12 DDRC _C14 DQS8 CB2 CB0 CB3 DQS VDDVDD VDD VDD VDD VDD VDD VDDVDD VDDVDD VCCVCC VCCVCC VCCVCC VCCVCC VCCVCC VCCVCC VCCVCC VCC FBD VCC FBD VCC FBD VDD FCBGA TOP VIEW, LEFT SIDE NOTE: 1. These pin positions are reserved for forward clocks to be used in future implementations.

COMMERCIAL TEMPERATURE RANGE IDTAMB0480 ADVANCED MEMORY BUFFER FOR FULLY BUFFERED DIMM FCBGA TOP VIEW, RIGHT SIDE NOTE: 1. These pin positions are reserved for forward clocks to be used in future implementations. A B C D E F G H J K L M N P R T U V W Y AA AB AC 16 17 18 19 20 21 22 23 24 25 26 27 28 29 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Vcc FBD RFU VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSSVSS RFU (1) RFU (1) VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC NCNC NC NCNC NC NCNC NC NCNC NC NCNC NC NCNC NC NCNC NC NCNC NC NCNC NC NCNC NC NCNC NC NCNC NC NCNC NC NCNC NC NCNC NC NCNC NC NCNC NC NCNC NC NCNC NC NCNC NC NCNC VSS VSS PS6 PS5 PS6 PS5 SS8SS7SS6SS5SS9SS4SS3SS2SS1SS0 SS4SS3SS2SS1SS0 SS8SS7SS6SS5SS9 PS1 PS2 PS3 PS4PS0 PS1 PS2 PS3 PS4PS0 RFU (1) RFU (1) VDD SPD PS9PS9 SCK SCK SN11 SN11RFU TESTLO_ AB20 TESTLO_ AC20 PS8 PS7 PS8 PS7A13B A12B SA2 SA1 A8B A15B A14B SA0 SCL SDA A6B A11B A9B A2B A4B A1B A10B A3B A7B A5B BA0B BA2B CKE1B CKE0B CLK3 CLK1 CLK3 CLK1 CS0B A0B BA1B WEBCASB CS1BODT RASB DQS4 DQ34 DQ32 RFU DQS4TEST LO TEST RFU RFU CB4 DQ62 DQ60 DQS16 DQS17 TEST TEST LO TEST DDRC _B18 DDRC _C18 CB7CB6 CB5 DQS16 DQ63 DQ61 DQ54 DQ52 DQS15 DQS15 DQ49 DQS6 DQS6 DQ51 DQ59 DQ53 DQ55 DQ57 DQ39 DQ37 DQS7 DQ58 DQ35 DQ56 DQ36 DQ50 DQS7 DQ45 DQS5 DQ44 DQ33 DQ43 DQS5 DQ40 DQ42 DQ47 DQ41 DQS14 DQS14 DQS13DQS13 DQ38DQ48 DQ46 VCC VCCVCC Vcc FBD VDD VDD VDD VDDVDD VDD VDD VDDVDD VDD VDD VCC VCCVCC VCC VCCVCC VCC Vcc FBD Vcc FBD

ADVANCED MEMORY BUFFER FOR FULLY BUFFERED DIMM COMMERCIAL TEMPERATURE RANGE

655 BALL BGA PACKAGE ATTRIBUTES

16 17 18 19 20 21 22 23 24 25 26 27 28 29 A B C D E F G H J K L M N P R T U V W Y AA AB AC 123456789 1 0 1 1 1 2 1 3 1 4 1 5

COMMERCIAL TEMPERATURE RANGE IDTAMB0480 ADVANCED MEMORY BUFFER FOR FULLY BUFFERED DIMM ADVANCED MEMORY BUFFER SIGNALS BY BALL NUMBER Ball No. Signal A3 V SS A4 DQ26 A5 DQ12 A6 V DD A7 DQS10 A8 DQ13 A9 V DD A10 DQS1 A11 DQ10 A12 V DD A13 TESTLO A14 V DD A15 V DD A16 V DD A17 TEST A18 V DD A19 DQ52 A20 DQS15 A21 V DD A22 DQ49 A23 DQS6 A24 V DD A25 DQ48 A26 DQ38 A27 V DD B2 V DD B3 DQS3 B4 DQS3 B5 V SS B6 DQ14 B7 DQS10 B8 V SS B9 DQ11 B10 DQS1 B11 V SS B12 DDRC_B12 B13 TESTLO B14 V DD B15 V SS B16 V DD B17 TESTLO B 18 DDRC_B18 B19 V SS B20 DQS15 B21 DQ53 B22 V SS B23 DQS6 B24 DQ50 B25 V SS Ball No. Signal B26 DQS13 B27 DQS13 B28 V SS C1 V SS C2 DQS2 C3 DQ18 C4 V SS C5 DQ4 C6 DQS9 C7 V SS C8 DQ15 C9 DQ9 C10 V SS C11 DQ8 C12 DDRC_C12 C13 V SS C14 DDRC_C14 C15 DQS17 C16 DQS17 C17 V SS C18 DDRC_C18 C19 DQ54 C20 V SS C21 DQ55 C22 DQ51 C23 V SS C24 DQS7 C25 DQ56 C26 V SS C27 DQ46 C28 DQS14 C29 V DD D1 DQ19 D2 DQS2 D3 V SS D4 DQ16 D5 DQ24 D6 V SS D7 DQS9 D8 DQ7 D9 V SS D10 DQ3 D11 DQS0 D12 V SS D13 DQS8 D14 DQS8 D15 V DD D16 CB6 D17 CB7 Ball No. Signal D18 V SS D19 DQS16 D20 DQ63 D21 V SS D22 DQ59 D23 DQS7 D24 V SS D25 DQ36 D26 DQ44 D27 V SS D28 DQS14 D29 DQ47 E1 DQ21 E2 V SS E3 DQ17 E4 DQ29 E5 V SS E6 DQ25 E7 DQ6 E8 V SS E9 DQ5 E10 DQ1 E11 V SS E12 DQ0 E13 CB1 E14 V SS E15 CB2 E16 V SS E17 CB5 E18 DQS16 E19 V SS E20 DQ61 E21 DQ57 E22 V SS E23 DQ58 E24 DQ39 E25 V SS E26 DQ33 E27 DQ45 E28 V SS E29 DQ41 F1 V SS F2 DQ20 F3 DQ23 F4 V SS F5 DQ31 F6 DQ27 F7 V SS F8 TESTLO Ball No. Signal F9 TEST F10 V SS F11 DQS0 F12 DQ2 F13 V DD F14 CB0 F15 CB3 F16 CB4 F17 V DD F18 DQ62 F19 DQ60 F20 V SS F21 TEST F22 TEST F23 V SS F24 DQ37 F25 DQ35 F26 V SS F27 DQS5 F28 DQ43 F29 V SS G1 DQS11 G2 DQS11 G3 N C G4 N C G5 N C G6 V SS G7 DQS12 G8 DQS12 G9 N C G10 N C G11 N C G12 BFUNC G13 RFU G14 RFU G15 RFU G16 TESTLO G17 RFU G18 RFU G19 N C G20 N C G21 N C G22 DQS4 G23 DQS4 G24 V SS G25 N C G26 N C G27 N C G28 DQS5

ADVANCED MEMORY BUFFER FOR FULLY BUFFERED DIMM COMMERCIAL TEMPERATURE RANGE ADVANCED MEMORY BUFFER SIGNALS BY BALL NUMBER (CONT.) Ball No. Signal G29 DQ40 H1 DQ22 H2 V SS H3 N C H4 N C H5 N C H6 DQ28 H7 DQ30 H8 V SS H9 N C H10 N C H11 N C H12 V SS H13 V DD H14 V SS H15 V DD H16 V SS H17 V DD H18 V SS H19 N C H20 N C H21 N C H22 V SS H23 DQ34 H24 DQ32 H25 N C H26 N C H27 N C H28 V SS H29 DQ42 J1 V SS J2 CLK2 J3 N C J4 N C J5 N C J6 BA1A J7 V SS J8 CKE1A J9 N C J10 N C J11 N C J12 V DD J13 V SS J14 V DD J15 V SS J16 V DD J17 V SS J18 V DD J19 N C Ball No. Signal J20 N C J21 N C J22 RASB J23 V SS J24 RFU J25 N C J26 N C J27 N C J28 CLK3 J29 V SS K1 CLK2 K2 CLK0 K3 N C K4 N C K5 N C K6 V SS K7 WEA K8 RASA K9 N C K10 N C K11 N C K12 V SS K13 V CC K14 V SS K15 V CC K16 V SS K17 V CC K18 V SS K19 N C K20 N C K21 N C K22 ODT0B K23 CS1B K24 V SS K25 N C K26 N C K27 N C K28 CLK1 K29 CLK3 L1 CLK0 L2 V SS L3 N C L4 N C L5 N C L6 A0A L 7 CKE0A L8 V SS L9 N C L10 N C Ball No. Signal L11 N C L12 V CC L13 V SS L14 V CC L15 V SS L16 V CC L17 V SS L18 V CC L19 N C L20 N C L21 N C L22 V SS L23 CASB L24 WEB L25 N C L26 N C L27 N C L28 V SS L29 CLK1 M1 ODT0A M2 RFU M3 N C M4 N C M5 N C M6 CASA M7 V SS M8 BA2A M9 N C M10 N C M11 N C M12 V SS M13 V CC M14 V SS M15 V CC M16 V SS M17 V CC M18 V SS M19 N C M20 N C M21 N C M22 CS0B M23 V SS M24 BA1B M25 N C M26 N C M27 N C M28 CKE0B M29 V SS N1 CS1A Ball No. Signal N2 CS0A N3 N C N4 N C N5 N C N6 V SS N7 BA0A N8 A10A N9 N C N10 N C N11 N C N12 V CC N13 V SS N14 V CC N15 V SS N16 V CC N17 V SS N18 V CC N19 N C N20 N C N21 N C N22 A0B N23 A2B N24 V SS N25 N C N26 N C N27 N C N28 BA0B N29 BA2B P1 A6A P2 V SS P3 N C P4 N C P5 N C P6 A2A P7 A1A P8 A3A P9 N C P10 N C P11 N C P12 V SS P13 V CC P14 V SS P15 V CC P16 V SS P17 V CC P18 V SS P19 N C P20 N C P21 N C

COMMERCIAL TEMPERATURE RANGE IDTAMB0480 ADVANCED MEMORY BUFFER FOR FULLY BUFFERED DIMM ADVANCED MEMORY BUFFER SIGNALS BY BALL NUMBER (CONT.) Ball No. Signal P22 V SS P23 A4B P24 A1B P25 N C P26 N C P27 N C P28 V SS P29 CKE1B R1 V SS R2 A8A R3 N C R4 N C R5 N C R6 A11A R7 V SS R8 A5A R9 N C R10 N C R11 N C R12 V CC R13 V SS R14 V CC R15 V SS R16 V CC R17 V SS R18 V CC R19 N C R20 N C R21 N C R22 A6B R23 V SS R24 A10B R25 N C R26 N C R27 N C R28 A3B R29 V SS T 1 A4A T 2 A13A T3 N C T4 N C T5 N C T6 V SS T 7 A9A T 8 A7A T9 N C T10 N C T11 N C Ball No. Signal T12 V SS T13 V CC T14 V SS T15 V CC T16 V SS T17 V CC T18 V SS T19 N C T20 N C T21 N C T22 A11B T23 A9B T24 V SS T25 N C T26 N C T27 N C T28 A7B T29 A5B U1 PN0 U2 PN0 U3 N C U4 N C U5 N C U6 A15A U7 A14A U8 A12A U9 N C U10 N C U11 N C U12 RFU U13 V CCFBD U14 V SS U15 V SS U16 V SS U17 V CCFBD U18 RFU U19 N C U20 N C U21 N C U22 A8B U23 A15B U24 A14B U25 SA0 U26 SCL U27 SDA U28 PS8 U29 PS8 V1 PN1 Ball No. Signal V2 PN1 V3 V SS V4 SN0 V5 SN0 V6 V CCFBD V7 V SS V8 V CCFBD V9 V SS V10 RFU (1) V11 RFU (1) V12 V CCFBD V13 V SS V14 V SS V15 V SS V16 V CCFBD V17 V SS V18 V CCFBD V19 V SS V20 V CCFBD V21 RFU (1) V22 RFU (1) V23 V SS V24 A13B V25 A12B V26 SA2 V27 SA1 V28 PS7 V29 PS7 W1 PN2 W2 PS2 W3 V SS W4 SN1 W5 SN1 W6 SN3 W7 SN4 W8 SN5 W9 SN13 W10 SN12 W11 SN6 W12 SN7 W13 SN8 W14 SN9 W15 SN10 W16 V SS W17 SS0 W18 SS1 W19 SS2 W20 SS3 Ball No. Signal W21 SS4 W22 SS9 W23 SS5 W24 SS6 W25 SS7 W26 SS8 W27 V SS W28 PS6 W29 PS6 Y1 PN3 Y2 PN3 Y3 V SS Y4 SN2 Y5 SN2 Y6 SN3 Y7 SN4 Y8 SN5 Y9 SN13 Y10 SN12 Y11 SN6 Y12 SN7 Y13 SN8 Y14 SN9 Y15 SN10 Y16 V SS Y17 SS0 Y18 SS1 Y19 SS2 Y20 SS3 Y21 SS4 Y22 SS9 Y23 SS5 Y24 SS6 Y25 SS7 Y26 SS8 Y27 V SS Y28 PS5 Y29 PS5 AA1 V SS AA2 PN4 AA3 PN4 AA4 V SS AA5 V SS AA6 V SS AA7 V SS AA8 V SS AA9 V SS AA10 V SS NOTE: 1. These pin positions are reserved for forward clocks to be used in future implementations.

ADVANCED MEMORY BUFFER FOR FULLY BUFFERED DIMM COMMERCIAL TEMPERATURE RANGE Ball No. Signal AA11 V SS AA12 V SS AA13 V SS AA14 V SS AA15 V SS AA16 V SS AA17 V SS AA18 V SS AA19 V SS AA20 V SS AA21 V SS AA22 V SS AA23 V SS AA24 V SS AA25 V SS AA26 V SS AA27 PS9 AA28 PS9 AA29 V SS AB2 V SS AB3 RESET AB4 PN5 AB5 PN13 AB6 RFU (1) AB7 PN12 AB8 PN6 AB9 PN7 AB10 PN8 AB11 PN9 AB12 V SSAPLL AB13 V CCAPLL AB14 PN10 AB15 PN11 AB16 V SS AB17 PN11 AB18 V SS AB19 SCK AB20 TESTLO_AB20 AB21 PS0 AB22 PS1 AB23 PS2 AB24 PS3 AB25 PS4 AB26 RFU (1) AB27 V DDSPD AB28 V SS AC3 V SS AC4 PN5 Ball No. Signal AC5 PN13 AC6 RFU (1) AC7 PN12 AC8 PN6 AC9 PN7 AC10 PN8 AC11 PN9 AC12 FBDRES AC13 PLLTSTO AC14 PN10 AC15 PN11 AC16 RFU AC17 SN11 AC18 V SS AC19 SCK AC20 TESTLO_AC20 AC21 PS0 AC22 PS1 AC23 PS2 AC24 PS3 AC25 PS4 AC26 RFU (1) AC27 V SS ADVANCED MEMORY BUFFER SIGNALS BY BALL NUMBER (CONT.) NOTE: 1. These pin positions are reserved for forward clocks to be used in future implementations.

COMMERCIAL TEMPERATURE RANGE IDTAMB0480 ADVANCED MEMORY BUFFER FOR FULLY BUFFERED DIMM PIN DESCRIPTION Signal Type Description Channel Interface PN[13:0] O Northbound Output Data: High speed serial signal. Read path from AMB toward host on primary side of the DIMM connector. PN[13:0] O Northbound Output Data Complement SN[13:0] I Northbound Input Data: High speed serial signal. Read path from the previous AMB toward this AMB on secondary side of the DIMM connector. SN[13:0] I Northbound Input Data Complement PS[9:0] I Southbound Input Data: High speed serial signal. Write path from host toward AMB on primary side of the DIMM connector. PS[9:0] I Southbound Input Data Complement SS[9:0] O Southbound Output Da ta: High speed serial signal. Write path from this AMB toward next AMB on secondary side of the DIMM connector. These output buffers are disabled for the last AMB on the channel. SS[9:0] O Southbound Output Data Complement FBDRES A External 100Ω precision resistor connected to VCC. On-die termination calibrated against this resistor. DRAM Interface CB[7:0] I/O Check bits DQ[63:0] I/O Data DQS[17:0] I/O Data Strobe: DDR2 data and check-bit strobe. DQS[17:0] I/O Data Strobe Complement: DDR2 data and check-bit strobe complements. A0A-A15A, O Address: Used for providing multiplexed row and column address to SDRAM. A0B-A15B BA0A-BA2A, O Bank Active: Used to select the bank within a rank. BA0B-BA2B RASA, RASB O Row Address Strobe: Used with CS, CAS, and WE to specify the SDRAM command. CASA, CASB O Column Address Strobe: Used with CS, RAS, and WE to specify the SDRAM command. WEA, WEB O Write Enable: Used with CS, CAS, and RAS to specify the SDRAM command. CS0A-CS1A, O Chip Select: Used with CAS, RAS, and WE to specify the SDRAM command. These signals are used for selecting one of two SDRAM ranks. CS0 is used to select the first rank and CS1 is used to select the second rank. CKE0A-CKE1A, O Clock Enable: DIMM command register enable. CKE0B-CKE1B ODT0A, ODT0B O DIMM On-Die-Termination: Dynamic ODT enables for each DIMM on the channel. CLK[3:0] O Clock: Clocks to DRAMs. CLK0 and CLK1 are always used. CLK2 and CLK3 are used when the AMB is configured for dual rank DIMMs. CLK[3:0] O Clock Complement: Clocks to DRAMs. DDR Compensation DDRC_C14 A DDR Compensation Common: Common return (ground) pin for DDRC_B18 and DDRC_C18 DDRC_B18 A DDR Compensation Ball Resistor (825 Ω) connected to Compensation Common above DDRC_C18 A DDR Compensation Ball Resistor (121Ω) connected to Compensation Common above DDRC_B12 A DDR Compensation Ball Resistor (82 Ω) connected to VSS DDRC_C12 A DDR Compensation Ball Resistor (82Ω) connected to VDD CS0B-CS1B

ADVANCED MEMORY BUFFER FOR FULLY BUFFERED DIMM COMMERCIAL TEMPERATURE RANGE Signal Type Description Clocking SCK I AMB Clock: This is one of the two differential reference clock inputs to the Phase Locked Loop in the AMB core. Phase Locke d Loops in the AMB will shift this to all frequencies required by the core, DDR channels, and FBD Channel. SCK I AMB Clock Complement: This is the other differential reference clock input to the Phase Locked Loop in the AMB core. Phase Locked Loops in the AMB will shift this to all frequencies required by the core, DDR channels, and FBD Channel. PLLTSTO O PLL Clock Observability Output: This pin can be used to observe VCO, reference clock, core clock, etc. For system debug and design characterization. VCCA PLL A V CC: PLL Analog Voltage for the core PLL VSSA PLL A V SS: PLL Analog Voltage for the core PLL System Management SCL I/O SMBus Clock SDA I/O SMBus Address/Data SA[2:0] DIMM Select ID Reset RESET Power Good Reset Miscellaneous Test TEST (4 pins) N C Pin for debug and test. Must be floated on DIMM. TESTLO (5 pins) A Pin for debug and test. Must be tied to Ground on DIMM TESTLO_AB20 A Pin for debug and test. Connected to two resistors. One resistor is connected to VCCFBD, the other resistor is connected to VSS. TESTLO_AC20 A Pin for debug and test. Connected to two resistors. One resistor is connected to VCCFBD, the other resistor is connected to VSS. Power Supplies VCC (24 pins) A 1.5V nominal supply for core I/O VCCFBD (8 pins) A 1.5V nominal supply for FBD high speed I/O VDD (24 pins) A 1.8V nominal supply for DDR I/O VSS (156 pins) A Ground VDDSPD A 3.3V nominal supply for SMB receivers and ESD diodes Other Pins BFUNC I Buffer Function Bit: When BFUNC = 0, AMB is used as a regular buffer on FBDIMM. When BFUNC = 1, AMB is used as either a repeater or a buffer for LAI function. On FB-DIMM, BFUNC is tied to Ground RFU (18 pins) N C Reserved for Future Use. Must be floated on DIMM. RFU pins denoted by “a” are reserved for forwarded clocks in f uture AMB implementations. Other No Connect Pins NC (129 pins) N C No Connect pins PIN DESCRIPTION (CONT.)

COMMERCIAL TEMPERATURE RANGE IDTAMB0480 ADVANCED MEMORY BUFFER FOR FULLY BUFFERED DIMM Symbol Description Min Max Unit VDD Supply voltage DRAM Interface -0.5 +2.3 V VIN (DDR2). Voltage on any DDR2 interface 0.5 +2.3 V VOUT (DDR2) pin relative to Vss(2) IINK Input Clamp Current +30 mA (VIN < 0 or VIN > VDD) IOUTK Output Clamp Current +30 mA (VOUT < 0 or VOUT > VDD) IOUT Continous Output Current +30 mA (VOUT = 0 to VDD) N/A Continuous current through +100 mA each VDD or GND VCC Supply voltage for Core -0.3 +1.75 V and High Speed Interface TJ Junction Temperature +125 ° C TSTG Storage Temperature Range –55 +100 ° C ABSOLUTE MAXIMUM RATINGS(1) NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. This value is limited to 2.3V maximum. ADVANCED MEMORY BUFFER NORMAL MODE DC ELECTRICAL PARAMETERS Parameter Min Typ Max Unit VCC link / core(1,2,3,4) 1.425 1.5 1.59 V VDD 1.7 1.8 1.9 V VDDSPD 3.0 3.3 3.6 V NOTES: 1. AMB 1.5V voltage regulation as measured at the package Balls. 2. DC defined as 0 KHz to 30 KHz. 3. DC + AC specified as 1.5V +6%, -5% 30KHz to 1 MHz. 4. There is also a +7%, -5% tolerance allowed for current load steps associated with initialization/error-recovery state transitions, such as into and out of EI, IBIST, and MEMBIST. For these transitions, a temporary voltage overshoot is expected and acceptable as long as it is within +7% (step transition for 20μs and maximum duty cycle of 10 -6 %). Transitions between Active and Idle states are not included in this +7%, -5% tolerance. ELECTRICAL, POWER, AND THERMAL

ADVANCED MEMORY BUFFER FOR FULLY BUFFERED DIMM COMMERCIAL TEMPERATURE RANGE DDR BIAS PLL AND CHANNEL BIAS AMB0480 DDRC_B18 DDRC_C14 DDRC_C18 VDD VSS RC12 RB12 DDRC_C12 DDRC_B12 RB18 RC18 AMB0480 VCC VSS C1 C2 VSSAPLL VCCFBD RFBDRES FBDRES VCCAPLL PLLTSTO RPLLTST R L NOTES: 1. Refer to JEDEC PC2-4200/5300/6400 DDR2 FULLY BUFFERED DIMM DESIGN SPECIFICATIONS, rev 2.0. 2. The resistor R must be 0 Ω and the inductor L needs to be replaced with a 0 Ω resistor. The resistor R FBDRES = 100 Ω and Resistor R PLLTST = 51 Ω. 3. It is not recommended to use a serpentine copper trace in place of the resistor R. This resistor value needs to be AMB manufa cturer defined and not set to a single fixed value. Some raw cards have implemented the resistor with a serpentine copper trace on the DIMM PCB, while others use a discrete resist or. The limitation of using the copper trace has been discussed in JEDEC, highlighting that the resistor implemented as a serpentine copper trace is not a generic solution. The raw card artwork now allows the option of bypassing any serpentine trace with a 0 Ω resistor to V CC.

COMMERCIAL TEMPERATURE RANGE IDTAMB0480 ADVANCED MEMORY BUFFER FOR FULLY BUFFERED DIMM MISCELLANEOUS BIAS BIAS COMPONENTS - RECOMMENDED VALUES AMB0480 AMB0480 VDD VSS HVM TESTLO_AC20 RSA0 R4R3 VSS VSS TESTLO_AB20 SA0 SA0 SPD Gold Finger TESTLO_F8 TESTLO_A13 TESTLO_B13 TESTLO_B17 TESTLO_G16 BFUNC TEST_F9 TEST_A17 TEST_F21 TEST_F22 NC NC NC NC NOTES: 1. Refer to JEDEC PC2-4200/5300/6400 DDR2 FULLY BUFFERED DIMM DESIGN SPECIFICATIONS, rev 2.0. 2. Component values for the AMB0480 are summarized in the BIAS COMPONENT table. Schematic Diagram Reference Value Description RC12 82Ω The impedance of the pull up (PRU) and pull down (PRD) on the AMB DDR Outputs is relatedto RB12 & RC12 as follows: RC12 = RB12 = 5.3125 * Desired Output Impedance DDR Bias RB 12 82Ω A resistor value of 82Ω results in an impedance at a JEDEC nominal value of 15Ω. The user can adjust these value to optimize the DDR output impedance for a DIMM raw card configuration. RB18 825Ω RC18 121Ω R0 Ω Resistor R must be 0Ω L0 Ω Inductor L needs to be replaced with a 0Ω resistor PLL and Channel C 1 10μF C2 10μF RPLLTSTO 51 Ω RFBDRES 100Ω R1 Not loaded R2 Not loaded Miscellaneous R 3 0Ω R4 0Ω RSA0 825 Ω

ADVANCED MEMORY BUFFER FOR FULLY BUFFERED DIMM COMMERCIAL TEMPERATURE RANGE

ORDERING INFORMATION

CORPORATE HEADQUARTERS for SALES: for Tech Support: 6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 logichelp@idt.com San Jose, CA 95138 fax: 408-284-2775 www.idt.com IDTAMB Temp. Range XXXX Device Type XX Package Advanced Memory Buffer for Fully Buffered DIMM Modules RJ BJG RH HJG 0480 Ball Grid Array - RoHS Compliant BGA - Green Ball Grid Array with heat spreader - RoHS Compliant BGA with heat spreader- Green Blank Commercial (0°C to +70°C) (1) (1) Device RevisionXX XXX Revision Blank Tray Tape and Reel Shipping Carrier X NOTE: 1. Contact factory for availability. Other Ordering Information AMB0480xxRJ8 AMB in bare die packaged in tape/reel AMB0480xxRJ AMB in bare die packaged in tray AMB0480xxRH8 AMB with heatspreader packaged in tape/reel AMB0480xxRH AMB with heatspreader packaged in tray Device Revision Status A5 AMB revision A1.5 Active