AM9551

AM8251 ETC | Alldatasheet

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Technical content

Am8251 • Am9551 Programmable Communications Interface DISTINCTIVE CHARACTERISTICS

• Improved performance with Am9551
• Separate control and transmit register input buffers
• 8080A/9080A compatible
• Synchronous or asynchronous serial data transfer
• Parity, overrun and framing errors detected
• Half or full duplex signalling
• Character length of 5, 6, 7 or 8 bits
• Internal or external synchronization
• Odd parity, even parity or no parity bit
• Modem interface controlled by processor
• Programmable Sync pattern
• Fully TTL compatible logic levels
• +5 only power supply
• Commercial and military temperature range operation
• Ion-implanted N-channel silicon gate MOS technology
• 100% M I L-STD-883 reliabi lity assurance testing BLOCK DIAGRAM DBO- DB7 ClK C/O RESET cs AD WR GENERAL DESCRIPTION The Am8251/9551 is a programmable serial data communi­ cation interface that provides a Universal Synchronous/Asyn­ chronous Receiver/Transmitter (USART) function_ It is nor­ mally used as a peripheral device for an associated processor, and may be programmed by the processor to operate in a variety of standard serial communication formats. The device accepts parallel data from the CPU, formats and serializes the information based on its current operating mode, and then transmits the data as a serial bit stream. Simultane­ ously, serial data can be received, converted into parallel form, de-formated, and then presented to the CPU. The USART can operate in an independent full duplex mode. Data, Control, operation and format options are all selected by commands from an associated processor. This provides an unusual degree of flexibility and allows the Am8251/9551 to service a wide range of communication disciplines and appli­ cations. DATA BUS 2 DATA BUS 3 RECEIVER DATA (GND) VSS DATA BUS 4 DATA BUSS DATA BUS 6 DATA BUS 7 TRANSMITTER CLOCK WRITE CHIP SELECT CaNTRall DATA READ RECEIVER READY CONNECTION DIAGRAM Top View
• 1 2B Am9551 10 19 11 18 12 17 13 16 14 15 Pin 1 is marked for orientation. DATA BUS 1 DATA BUS 0 VCC (+5.0V) "RECETilER ClDCK DATA TERMINAL READY REQUEST TO SEND DATA SET iiEAl5Y RESET CLOCK TRANSMITTER DATA TRANSMITTER EMPTY CLEAR TO SEND SYNC DETECT TRANSMITTER READY MOS·214 MOS·215

ORDERING INFORMATION

Ambient Temperature 9551 Specifications Package Type Specification 8251 Specifications Standard Upgraded Hermetic DIP* AM8251 DC/D8251 AM9551DC AM9551-4DC O°C <s; T A <S; + 70°C AM8251 CC/C8251 AM9551CC AM9551-4CC Molded DIP AM8251 PC/P8251 AM9551PC AM9551-4PC Hermetic DIP -55°C <S; TA <S; +125°C AM8251 DM/M8251 AM9551DM *Hermetic = Ceramic = DC = CC = D-28-1. 7-36

INTERFACE SIGNAL DESCRIPTION Data Bus The Am9551 uses an 8 bit bi-directional data bus to exchange information with an associated processor. Internally, data is routed between the data bus buffers and the transmitter sec­ tion or receiver section as selected by the Read (RD) or Write (WR) control inputs. Chip Select (CS) The active low Chip Select input allows the Am9551 to be in­ dividually selected from other devices within its address range. When Chip Select is high, reading or writing is inhibited, and the data bus output is in it's high impedance state. Reset The Am9551 will assume an idle state when a high level is applied to the Reset input. When the Reset is returned low, the Am9551 will remain in the idle state until it receives a new mode control instruction. Read (RD) The active low Read input enables data to be transferred from the Am9551 to the processor. Write (WR) The active low Write input enables data to be transferred from the processor to the Am9551. Control/Data (C/O) During a Read operation, if this input is at a high level the status byte will be read, and if it is at a low level the receive data will be read by the processor. When a Write operation is being performed, this input will indicate to the Am9551 that the bus information being written is a command if ci5 is high and data if cio is low. C/O RD WR CS 0 0 1 0 Am9551 DATA ~ DATA BUS 0 1 0 0 DATA BUS~ Am9551 DATA 1 0 1 0 Am9551 STATUS~ DATA BUS 1 1 0 0 DATA BUS~Am9551 COMMAND X X X 1 DATA BUS ~ 3-STATE Clock (ClK) This input is used for internal timing within the Am9551. It does not control the transmit or receive rate. However, it should be at least 30 times the receive or transmit rate in the synchronous mode and 4.5 times the receive or transmit rate in the asynchronous mode. The ClK frequency is also re­ stricted by both an upper and a lower bound. This input is often connected to a clock from the associated processor. Receiver Data (RxD) Serial data is received from the communication line on this input. Receiver Clock (RxC) The serial data on input RxD is clocked into the Am9551 by the RxC clock signal. In the synchronous mode, RxC is deter­ mined by the baud rate and supplied by the modem. In the asynchronous mode, RxC is 1, 16, or 64 times the baud rate as selected in the mode control instruction. Data is sampled by the Am9551 on the rising edge of RxC. Receiver Ready (RxRDY) The RxRDY output signal indicates to the processor that data has been shifted into the receiver buffer from the receiver sec­ tion and may be read. The signal is active high and will be re- 7-37 Am8251 • Am9551 set when the buffer is read by the processor. RxRDY can be activated only if the receiver enable (RxE) has been set in the command register, even though the receiver may be running. If the processor does not read the receiver buffer before the next character is shifted from the receiver section then an overrun error will be indicated in the status buffer. Sync Detect (SYNDET) This signal is used only in the synchronous mode. It can be either an output or input depending on whether the program is set for internal or external synchronization. As an output, a high level indicates when the sync character has been de­ tected in the received data stream after the Internal Synchron­ ization mode has been programmed. If the Am9551 is pro­ grammed to utilize two sync characters, then SYNDET will go to a high level when the last bit of the second sync character is received. SYNDET is reset when the status buffer is read or when a Reset signal is activated. SYNDET will perform as an input when the External Synchronization mode is programmed. External logic can supply a positive-going signal to indicate to the Am9551 that synchronization has been attained. This will cause it to initialize the assembly of characters on the next falling edge of RxC. To successfully achieve synchronization the SYNDET signal should be maintained in a high condition for at least one full period of RxC. Transmit Data (TxD) Serial data is transmitted to the communication line on this output. Transmitter Clock (TxC) The serial data on TxD is clocked out with the TxC signal. The relationship between clock rate and baud rate is similar to that for RxC. Data is shifted out of the Am9551 on the falling edge of TxC. Transmitter Ready (TxRDY) The TxRDY output signal goes high when data in the Transmit Data Buffer has been shifted into the transmitter section al­ lowing the Transmit Data Buffer to accept the next byte from the processor. TxRDY will be reset when information is writ­ ten into the Transmit Data Buffer. loading command register also resets TxRDY. TxRDY will be available on this output pin only when the Am9551 is enable to transmit (CTS = 0, TxEN = 1). However, the TxRDY bit in the status Buffer will always be set when the Transmit Data Buffer is empty regard­ less of the state of TxEN and CTS. Transmitter Empty (TxE) The TxE output signal goes high when the Transmitter section has transmitted its data and is empty. The signal will remain high until a new data byte is shifted from the Transmit Data Buffer to the Transmitter section. In the synchronous mode if the processor does not load a new byte into the buffer in time, TxE will, independent of the status of the TxEN bit in the command register, momentarily go to a high level as SYNC characters are loaded into the Transmitter Section. Data Terminal Ready (DTR) This signal is a general purpose output which reflects the state of bit 1 in the Command instruction. It is commonly connected to an associated modem to indicate that the Am9551 is ready. Data Set Ready (DSR) This is a general purpose input signal and forms part of the sta­ tus byte that may be read by the processor. DSR is generally used as a response to DTR, by the Modem, to indicate that it is ready. The signal acts only as a flag and does not control any internal logic.

• Outputs control codes
• Inputs status
• Outputs data to be transmitted
• Inputs data which have been received Control codes determine the mode in which the Am9551 will operate and are used to set or reset control signals output by the Am9551. The Status register contents will be read by the program moni­ toring this device's operation in order to determine error con­ ditions, when and how to read data, write data or output con­ trol codes. Program logic may be based on reading status bit levels, or control signals may be used to request interrupts. INITIALIZING THE Am9551 The Am9551 may be initialized following a system reset or prior to starting a new serial I/O sequence. The USART must be reset following power up and subsequently may be reset at any time following completion of one activity and preceeding a new set of operations. Following a reset, the Am9551 enters an idle state in which it can neither transmit nor receive data. The Am9551 is initialized with two, three or four control words from the processor. Figure 1 shows the sequence of control words needed to initialize the Am9551, for synchron­ ous or for asynchronous operation. Note that in asynchronous operation a mode control is output to the device followed by a command. For synchronous operation, the mode control is followed by one or two SYNC characters, and then a com­ mand. 00",1 Of'"'! ASYNCHRONOUS OPERATION MODE CONTROL I ""'''''' SEQUENCE COMMAND DATA 0/'"' I ",",I SYNCHRONOUS OPERATION MODE CONTROL SYNC#1 SYNC#2 (OPTIONAL) COMMAND DATA INITIALIZING SEQUENCE '-105-216

Figure 1. Control Word Sequence for Initialization. per destination based on the sequence in which it is received. 8251/9551 data transmission will not be disabled. the mode of operation as synchronous. Figure 2. Synchronous Mode Control Code.

00 Invalid

10 IlS stop bits

Figure 3. Asynchronous Mode Control Code.

Am9551, or when SYNC characters are recognized. Figure 6. The Am9551 Status Register. TxE signals the processor that the Transmit Register is empty. with an incorrect number of binary "1" bits. a new byte before being transferred to the processor. to indicate that the communication Data Set is operational. All status bits are set by the functions described for them. Register. QE, FE, PE are reset only by command. exposure to excessive voltages. Parameters Description Test Conditions Min_ Typ.

SWITCHING CHARACTERISTICS OVER OPERATING RANGE (Note 2) Am8251 Parameters Description Min Max tAR CS, C/O Stable to READ Low Set-up TITle 50 tAW CS, C/O Stable to WRITE Low Set-up Time 20 tCR DSR, CTS to READ Low Set-up Time 16 tCY Clock Period .420 1.35 tDF READ High to Data Bus Off Delay 25 200 tDTx TxC Low to TxD Delay 1.0 tow Data to WRITE High Set-up Time 200 tES External SYNDET to RxC Low Set-up Time 16 tHRx Sampling Pulse to Rx Data Hold Time 2.0 tiS Data Bit (Center) to Internal SYNDET Delay 25 t¢W Clock Pulse Width 220 0.7tCY tR, tF Clock Rise & Fall Time 0 50 tRA READ High to CS, C/O Hold Time 5.0 tRD READ Low to Data Bus On Delay 350 1x Baud Rate 15 tRPD Receiver Clock High Time 16x & 64x Baud Rate 3.0 1x Baud Rate 12 tRPW Receiver Clock Low Time 16x & 64x 1.0 Baud Rate tRR READ Pulse Width 430 tRV Time Between WRITE Pulses During Initialization 6.0 (Note 3) tRx Data Bit (Center) to RxRDY Delay 20 tSRx Rx Data to Sampling Pulse Set-up Time 2.0 1x Baud Rate 15 tTPD Transmitter Clock High Time 16x & 64x Baud Rate 3.0 1x Baud Rate 12 tTPW Transmitter Clock Low Time 16x & 64x 1.0 Baud Rate tTx Data Bit (Center) to TxRDY Delay 16 tTxE Data Bit (Center) to Tx EMPTY Delay 16 tWA WR ITE High to CS, C/O Hold Time 20 twc WRITE High to TxE, DTR, RTS Delay 16 two WRITE High to Data Hold Time 40 tWVY WRITE Pulse Width 400 1x Baud Rate DC 56 fRx Receiver Clock Frequency 16x & 64x DC 520 Baud Rate 1x Baud Rate DC 56 fTx Transmitter Clock Frequency 16x & 64x Baud Rate DC 520 NOTES: Am9551DM Am9551DC Min. Max .380 1.35 25 200 1.0 150 2.0 175 0.7tCY 0 50 5.0 250 3.0 1.0 380 6.0 2.0 3.0 1.0 380 DC 56 DC 520 DC 56 DC 520 1. Typical values are 'for T A = 25°C, nominal supply voltage and nominal processing parameters. Am8251 • Am9551 Am9551-4DC Min. Max. Units 50 ns 20 ns 16 tCY .380 1.35 J.Ls 25 200 ns 1.0 J.Ls 100 ns 16 tCY 2.0 J.LS 25 tCY 175 0.7tCY ns 0 50 ns 5.0 ns 180 ns 3.0 tCY 1.0 tCY 250 ns 6.0 tCY 20 tCY 2.0 J.LS tCY 3.0 1.0 tCY 16 tCY 16 tCY 20 ns 16 tCY 40 ns 250 ns DC 56 kHz DC 520 DC 56 kHz DC 520 2. Test conditions include: transition times < 20nS, output loading of 1TTL gate plus 100pF, input and output timing reference levels of O.BV and 2.0V. 3. This time period between write pulses is specified for initialization purposes only; when MODE, SYNC 1, SYNC 2, COMMAND and first DATA BYTE are written into the Am9551. Subsequent writing of both COMMAND and DATA are only allowed when TxRDY = 1. 4. Reset Pulse Width = 6tCY min. 5. Switching Characteristic parameters are listed in alphabetical order. 6. The maximum Input Low Current (lOL) is 1.6mA at VOL = .4V max over the military temperature range (-55 to +125°C) and VCC = 5V ±10%. 7-41

Am8251 • Am9551 SWITCHING WAVEFORMS READ OPERATION I f---t-tRA LtARLtRR 11 tDF .tCR I I I tRD TRANSMITTER CLOCK AND DATA tTPW ,I r-" __ tTP_C _-,,\\' I TxC ~ I 16TxCPERtODS I TXC~ r-\\ r- ~ ~tDTX --*== TxD ---- TxRDY TIMING (ASYNC MODE) TxEMPTY \\ 1\\ If'tTX TxR Dy WRITE WRITE TxD INTERNAL SYNC DETECT (SYNC MODE ONLY) SYNDET WRITE OPERATION f--tAW~tWW I I tWA \\ -j t---tDW -I----tWD_1 I----j--tWC RxC 116 x BAUD) RxC 11 x BAUD) RECEIVER CLOCK AND DATA --1l-tRPW --1l-tRPD INTERNAL I M05·221 !--tSRX---j-tH RX----j RxD -----* *.----- M05-222 RxRDY TIMING (ASYNC MODE) ----, START I ~ RxD BIT DATA BITS RxR Dy --r\\ M05-223 EXTERNAL SYNC DETECT (SYNC MODE ONLY) RxC RESET BY STATUS READ RxD 1--1 "0-----1 ST. DATA BYTE----- M05-224 7-42