AM75PDL191CHH

AM75PDL191CHH_0402 SPANSION | Alldatasheet

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The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig- inally developed the specification, these products will be offered to customers of both AMD and Fujitsu. Continuity of Specifications There is no change to this datasheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary. Continuity of Ordering Part Numbers AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order these products, please use only the Ordering Part Numbers listed in this document. For More Information Please contact your local AMD or Fujitsu sales office for additional information about Spansion memory solutions. Am75PDL191CHH/ Am75PDL193CHH Data Sheet Publication Number 31096 Revision A Amendment +1 Issue Date February 5, 2004

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This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. Publication# 31096 Rev: A Amendment 1 Issue Date: February 5, 2004 Refer to AMD’s Website (www.amd.com) for the latest information. Am75PDL191CHH/Am75PDL193CHH 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory with Enhanced Versatile I/O Control and Dual Chip Enable Input plus, for Additional Code or Data Storage, 64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only Simultaneous Read/Write Flash Memory and 64 Mbit (4 M x 16-Bit) CMOS Pseudo Static RAM DISTINCTIVE CHARACTERISTICS For Code Storage: Am29PDL127H/Am29PDL129H Features ARCHITECTURAL ADVANTAGES

128 Mbit Page Mode device

Page size of 8 words: Fast page read access from random locations within the page Dual Chip Enable inputs (PDL129 only) Two CE inputs control selection of each half of the memory space Single power supply operation Full Voltage range: 2.7 to 3.3 volt read, erase, and program operations for battery-powered applications Simultaneous Read/Write Operation Data can be continuously read from one bank while executing erase/program functions in another bank Zero latency switching from write to read operations FlexBank Architecture 4 separate banks, with up to two simultaneous operations per device PDL127: Bank A: 16 Mbit (4 Kw x 8 and 32 Kw x 31) Bank B: 48 Mbit (32 Kw x 96) Bank C: 48 Mbit (32 Kw x 96) Bank D: 16 Mbit (4 Kw x 8 and 32 Kw x 31) PDL129: Bank 1A: 48 Mbit (32 Kw x 96) Bank 1B: 16 Mbit (4 Kw x 8 and 32 Kw x 31) Bank 2A: 16 Mbit (4 Kw x 8 and 32 Kw x 31) Bank 2B: 48 Mbit (32 Kw x 96) SecSi TM (Secured Silicon) Sector region Up to 128 words accessible through a command sequence Up to 64 factory-locked words Up to 64 customer-lockable words Both top and bottom boot blocks in one device Manufactured on 0.13 µm process technology 20-year data retention at 125°C Minimum 1 million erase cycle guarantee per sector PERFORMANCE CHARACTERISTICS High Performance Page access times as fast as 30 ns Random access times as fast as 70 ns Power consumption (typical values at 10 MHz) 45 mA active read current 25 mA program/erase current 1 µA typical standby mode current SOFTWARE FEATURES Software command-set compatible with JEDEC 42.4 standard Backward compatible with Am29F and Am29LV families CFI (Common Flash Interface) complaint Provides device-specific information to the system, allowing host software to easily reconfigure for different Flash devices Erase Suspend / Erase Resume Suspends an erase operation to allow read or program operations in other sectors of same bank Unlock Bypass Program command Reduces overall programming time when issuing multiple program command sequences

Am75PDL191CHH/Am75PDL193CHH February 5, 2004 A D V A N C E I N F O R M A T I O N HARDWARE FEATURES Ready/Busy# pin (RY/BY#) Provides a hardware method of detecting program or erase cycle completion Hardware reset pin (RESET#) Hardware method to reset the device to reading array data WP#/ACC (Write Protect/Acceleration) input At VIL, hardware level protection for the first and last two 4K word sectors. At VIH, allows removal of sector protection At VHH, provides accelerated programming in a factory setting Persistent Sector Protection A command sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector Sectors can be locked and unlocked in-system at VCC level Password Sector Protection A sophisticated sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector using a user-defined 64-bit password FOR CODE OR DATA STORAGE: AM29DL640H Simultaneous Read/Write operations — Data can be continuously read from one bank while executing erase/program functions in another bank. — Zero latency between read and write operations Flexible Bank TM architecture — Read may occur in any of the three banks not being written or erased. — Four banks may be grouped by customer to achieve desired bank divisions. Boot Sectors — Top and bottom boot sectors in the same device — Any combination of sectors can be erased Manufactured on 0.13 µm process technology SecSi™ (Secured Silicon) Sector: Extra 256 Byte sector — Factory locked and identifiable: 16 bytes available for secure, random factory Electronic Serial Number; verifiable as factory locked through autoselect function. ExpressFlash option allows entire sector to be available for factory-secured data — Customer lockable: One-time programmable only. Once locked, data cannot be changed Zero Power Operation — Sophisticated power management circuits reduce power consumed during inactive periods to nearly zero. Compatible with JEDEC standards — Pinout and software compatible with single-power-supply flash standard PERFORMANCE CHARACTERISTICS High performance — Access time as fast as 70 ns — Program time: 4 µs/word typical utilizing Accelerate function Ultra low power consumption (typical values) — 2 mA active read current at 1 MHz — 10 mA active read current at 5 MHz — 200 nA in standby or automatic sleep mode Minimum 1 million erase cycles guaranteed per sector 20 year data retention at 125°C — Reliable operation for the life of the system SOFTWARE FEATURES Data Management Software (DMS) — AMD-supplied software manages data programming, enabling EEPROM emulation — Eases historical sector erase flash limitations Supports Common Flash Memory Interface (CFI) Erase Suspend/Erase Resume — Suspends erase operations to allow reading from other sectors in same bank Data# Polling and Toggle Bits — Provides a software method of detecting the status of program or erase cycles Unlock Bypass Program command — Reduces overall programming time when issuing multiple program command sequences HARDWARE FEATURES Ready/Busy# output (RY/BY#) — Hardware method for detecting program or erase cycle completion Hardware reset pin (RESET#) — Hardware method of resetting the internal state machine to the read mode WP#/ACC input pin — Write protect (WP#) function protects sectors 0, 1, 140, and 141, regardless of sector protect status — Acceleration (ACC) function accelerates program timing Sector protection — Hardware method of locking a sector, either in-system or using programming equipment, to prevent any program or erase operation within that sector — Temporary Sector Unprotect allows changing data in protected sectors in-system

February 5, 2004 Am75PDL191CHH/Am75PDL193CHH A D V A N C E I N F O R M A T I O N PSRAM FEATURES Organized as 4,194,304 words by 16 bits Single power supply voltage of 2.7 to 3.3 V Direct TTL compatibility for all inputs and outputs Deep power-down mode: Memory cell data invalid Page operation mode: 8-word Page read operation Logic compatible with SRAM R/W (WE) pin Standby current Standby 100 µA Deep power-down standby 5 µA

Am75PDL191CHH/Am75PDL193CHH February 5, 2004 A D V A N C E I N F O R M A T I O N GENERAL DESCRIPTION (PDL129) The Am29PDL129H is a 128 Mbit, 3.0 volt-only Page Mode and Simultaneous Read/Write Flash memory device orga- nized as 8 Mwords. The word-wide data (x16) appears on DQ15-DQ0. This device can be programmed in-system or in standard EPROM programmers. A 12.0 V VPP is not required for write or erase operations. The device offers fast page access time of 25 and 30 ns, with corresponding random access times of 65 and 85 ns, respectively, allowing high speed microprocessors to oper- ate without wait states. To eliminate bus contention the de- vice has separate chip enable (CE#f1, CE#f2), write enable (WE#) and output enable (OE#) controls. Dual Chip Enables allow access to two 64 Mbit partitions of the 128 Mbit mem- ory space. Simultaneous Read/Write Operation with Zero Latency The Simultaneous Read/Write architecture provides simul- taneous operation by dividing the memory space into 4 banks, which can be considered to be four separate memory arrays as far as certain operations are concerned. The de- vice can improve overall system performance by allowing a host system to program or erase in one bank, then immedi- ately and simultaneously read from another bank with zero latency (with two simultaneous operations operating at any one time). This releases the system from waiting for the completion of a program or erase operation, greatly improv- ing system performance. The device can be organized in both top and bottom sector configurations. The banks are organized as follows: Page Mode Features The page size is 8 words. After initial page access is accom- plished, the page mode operation provides fast read access speed of random locations within that page. Standard Flash Memory Features The device requires a single 3.0 volt power supply (2.7 V to 3.3 V) for both read and write functions. Internally gener- ated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC 42.4 single-power-supply Flash standard. Com- mands are written to the command register using standard microprocessor write timing. Register contents serve as in- puts to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch ad- dresses and data needed for the programming and erase operations. Reading data out of the device is similar to read- ing from other Flash or EPROM devices. Device programming occurs by executing the program com- mand sequence. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to pro- gram data instead of four. Device erasure occurs by execut- ing the erase command sequence. The host system can detect whether a program or erase op- eration is complete by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or ac- cept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data con- tents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC de- tector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combina- tion of sectors of memory. This can be achieved in-system or via programming equipment. The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. If a read is needed from the SecSi Sector area (One Time Pro- gram area) after an erase suspend, then the user must use the proper command sequence to enter and exit this region. The device offers two power-saving features. When ad- dresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power con- sumption is greatly reduced in both these modes. AMD’s Flash technology combined years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electri- cally erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection. Chip Enable Configuration CE#f1 Control CE#f2 Control Bank 1A

48 Mbit (32 Kw x 96)

16 Mbit (4 Kw x 8 and 32 Kw x 31)

February 5, 2004 Am75PDL191CHH/Am75PDL193CHH A D V A N C E I N F O R M A T I O N GENERAL DESCRIPTION (PDL127) The Am29PDL127H is a 128 Mbit, 3.0 volt-only Page Mode and Simultaneous Read/Write Flash memory device orga- nized as 8 Mwords. The word-wide data (x16) appears on DQ15-DQ0. This device can be programmed in-system or in standard EPROM programmers. A 12.0 V VPP is not required for write or erase operations. The device offers fast page access time of 25 and 30 ns, with corresponding random access times of 65 and 85 ns, respectively, allowing high speed microprocessors to oper- ate without wait states. To eliminate bus contention the de- vice has separate chip enable (CE#f1), write enable (WE#) and output enable (OE#) controls. Simultaneous Read/Write Operation with Zero Latency The Simultaneous Read/Write architecture provides simul- taneous operation by dividing the memory space into 4 banks, which can be considered to be four separate memory arrays as far as certain operations are concerned. The de- vice can improve overall system performance by allowing a host system to program or erase in one bank, then immedi- ately and simultaneously read from another bank with zero latency (with two simultaneous operations operating at any one time). This releases the system from waiting for the completion of a program or erase operation, greatly improv- ing system performance. The device can be organized in both top and bottom sector configurations. The banks are organized as follows: Page Mode Features The page size is 8 words. After initial page access is accom- plished, the page mode operation provides fast read access speed of random locations within that page. Standard Flash Memory Features The device requires a single 3.0 volt power supply (2.7 V to 3.3 V) for both read and write functions. Internally gener- ated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC 42.4 single-power-supply Flash standard. Com- mands are written to the command register using standard microprocessor write timing. Register contents serve as in- puts to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch ad- dresses and data needed for the programming and erase operations. Reading data out of the device is similar to read- ing from other Flash or EPROM devices. Device programming occurs by executing the program com- mand sequence. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to pro- gram data instead of four. Device erasure occurs by execut- ing the erase command sequence. The host system can detect whether a program or erase op- eration is complete by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or ac- cept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data con- tents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC de- tector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combina- tion of sectors of memory. This can be achieved in-system or via programming equipment. The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. If a read is needed from the SecSi Sector area (One Time Pro- gram area) after an erase suspend, then the user must use the proper command sequence to enter and exit this region. The device offers two power-saving features. When ad- dresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power con- sumption is greatly reduced in both these modes. AMD’s Flash technology combined years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electri- cally erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection. Bank Sectors A B C D

Am75PDL191CHH/Am75PDL193CHH February 5, 2004 A D V A N C E I N F O R M A T I O N GENERAL DESCRIPTION (DL640) The Am29DL640H is a 64 megabit, 3.0 volt-only flash memory device, organized as 4,194,304 words of 16 bits each or 8,388,608 bytes of 8 bits each. Word mode data appears on DQ15–DQ0; byte mode data appears on DQ7–DQ0. The device is designed to be programmed in-system with the standard 3.0 volt VCC supply, and can also be programmed in standard EPROM programmers. The device is available with an access time of 70, 90, or 120 ns and is offered in 48-pin TSOP, 63-ball Fine-Pitch BGA, and 64-ball Fortified BGA packages. Standard control pins—chip enable (CE#), write en- able (WE#), and output enable (OE#)—control normal read and write operations, and avoid bus contention issues. The device requires only a single 3.0 volt power sup- ply for both read and write functions. Internally gener- ated and regulated voltages are provided for the program and erase operations. Simultaneous Read/Write Operations with Zero Latency The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into four banks, two 8 Mb banks with small and large sectors, and two 24 Mb banks of large sectors. Sector addresses are fixed, system software can be used to form user-defined bank groups. During an Erase/Program operation, any of the three non-busy banks may be read from. Note that only two banks can operate simultaneously. The device can im- prove overall system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from the other bank, with zero latency. This releases the system from waiting for the completion of program or erase operations. The Am29DL640H can be organized as both a top and bottom boot sector configuration. Am29DL640H Features The SecSi™ (Secured Silicon) Sector is an extra 256 byte sector capable of being permanently locked by AMD or customers. The SecSi Customer Indica- tor Bit (DQ6) is permanently set to a 1 if the part has been customer locked, permanently set to 0 if the part has been factory locked, and is 0 if customer lock- able. This way, customer lockable parts can never be used to replace a factory locked part. Factory locked parts provide several options. The SecSi Sector may store a secure, random 16 byte ESN (Electronic Serial Number), customer code (pro- grammed through AMD’s ExpressFlash service), or both. Customer Lockable parts may utilize the SecSi Sector as bonus space, reading and writing like any other flash sector, or may permanently lock their own code there. DMS (Data Management Software) allows systems to easily take advantage of the advanced architecture of the simultaneous read/write product line by allowing removal of EEPROM devices. DMS will also allow the system software to be simplified, as it will perform all functions necessary to modify data in file structures, as opposed to single-byte modifications. To write or update a particular piece of data (a phone number or configuration data, for example), the user only needs to state which piece of data is to be updated, and where the updated data is located in the system. This is an advantage compared to systems where user-written software must keep track of the old data location, status, logical to physical translation of the data onto the Flash memory device (or memory de- vices), and more. Using DMS, user-written software does not need to interface with the Flash memory di- rectly. Instead, the user's software accesses the Flash memory by calling one of only six functions. AMD pro- vides this software to simplify system design and soft- ware integration efforts. The device offers complete compatibility with the JEDEC single-power-supply Flash command set standard. Commands are written to the command register using standard microprocessor write timings. Reading data out of the device is similar to reading from other Flash or EPROM devices. The host system can detect whether a program or erase operation is complete by using the device sta- tus bits: RY/BY# pin, DQ7 (Data# Polling) and DQ6/DQ2 (toggle bits). After a program or erase cycle has been completed, the device automatically returns to the read mode. The sector erase architecture allows memory sec- tors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write opera- tions during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of mem- ory. This can be achieved in-system or via program- ming equipment. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly re- duced in both modes. Bank Megabits Sector Sizes Bank 1 8 Mb Eight 8 Kbyte/4 Kword, Fifteen 64 Kbyte/32 Kword Bank 2 24 Mb Forty-eight 64 Kbyte/32 Kword Bank 3 24 Mb Forty-eight 64 Kbyte/32 Kword Bank 4 8 Mb Eight 8 Kbyte/4 Kword, Fifteen 64 Kbyte/32 Kword

February 5, 2004 Am75PDL191CHH/Am75PDL193CHH A D V A N C E I N F O R M A T I O N Pseudo SRAM Memory The pSRAM device is a 64 Mbit pseudo static random access memory (PSRAM) organized as 4,194,304 words by 16 bits. The device operates a single power supply. The device also features SRAM-like W/R tim- ing whereby the device is controlled by CE1#, OE#, and WE# on anynchronous. The device also supports deep power-down mode, realizing low-power standby.

February 5, 2004 Am75PDL191CHH/Am75PDL193CHH A D V A N C E I N F O R M A T I O N PRODUCT SELECTOR GUIDE Part Number Am29PDL129H Speed Option VCC, VIO = 2.7–3.3 V Max Access Time, ns (tACC) Max CE# Access, ns (tCE) Max Page Access, ns (tPACC) Max OE# Access, ns (tOE) Part Number Am29DL640H Speed Option Standard Voltage Range: VCC = 2.7–3.3 V Max Access Time (ns), tACC CE# Access (ns), tCE OE# Access (ns), tOE Part Number pSRAM Speed Option Standard Voltage Range: VCC = 2.7–3.3 V pSRAM Max Access Time, ns (tACC) Max CE# Access, ns (tCE) Max OE# Access, ns (tOE) Page Access, ns (tAA)

Am75PDL191CHH/Am75PDL193CHH February 5, 2004 A D V A N C E I N F O R M A T I O N MCP BLOCK DIAGRAM VSS VCC CE#f3 WE# WP#/ACC OE# RESET# Am29DL640G Am29PDL127H or Am29PDL129H VIO = VCC DQ0 to DQ15 DQ0 to DQ15 A0 to A21 A0 to A21 (A22) CE#f2 CE#f1 DQ0 to DQ15 CE2ps UB# CE#1ps LB# 64 Mb pSRAM VCC = VCCQ A0 to A21 DQ0 to DQ15 VSS VCC VSS VCC VSSA VSSQ VCCps A0 to A21 (A22 PDL127 Only)

February 5, 2004 Am75PDL191CHH/Am75PDL193CHH A D V A N C E I N F O R M A T I O N CONNECTION DIAGRAM–PDL127 Special Package Handling Instructions Special handling is required for Flash Memory products in molded packages (BGA). The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time. A10 B10 F10 G10 L10 M10 NC NC NC NC NC NC NC NC NC CE#f1 CE#1ps VSS OE# DQ0 DQ8 LB# UB# A18 A17 DQ1 DQ9 DQ10 DQ2 CE#f3 WP#/ACC RESET# RY/BY# DQ3 VCCf DQ11 NC WE# CE2ps A20 DQ4 VCCps NC A19 A10 DQ6 DQ13 DQ12 DQ5 A11 A12 A13 A14 NC DQ15 DQ7 DQ14 A15 A21 A22 A16 NC VSS NC NC NC NC NC NC Pseudo SRAM Only PDL127H Only Flash Shared Only DL640G Only 73-Ball FBGA Top View

Am75PDL191CHH/Am75PDL193CHH February 5, 2004 A D V A N C E I N F O R M A T I O N CONNECTION DIAGRAM–PDL129 Special Package Handling Instructions Special handling is required for Flash Memory products in molded packages (BGA). The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time. A10 B10 F10 G10 L10 M10 NC NC NC NC NC NC NC NC NC CE#f1 CE#1ps VSS OE# DQ0 DQ8 LB# UB# A18 A17 DQ1 DQ9 DQ10 DQ2 CE#f3 WP#/ACC RESET# RY/BY# DQ3 VCCf DQ11 NC WE# CE2ps A20 DQ4 VCCps NC A19 A10 DQ6 DQ13 DQ12 DQ5 A11 A12 A13 A14 NC DQ15 DQ7 DQ14 A15 A21 CE#f2 A16 NC VSS NC NC NC NC NC NC Pseudo SRAM Only Flash Shared Only PDL129 Only DL640G Only 73-Ball FBGA Top View

February 5, 2004 Am75PDL191CHH/Am75PDL193CHH A D V A N C E I N F O R M A T I O N PIN DESCRIPTION A21–A0 = 22 Address Inputs (Common) A22 = Address Input (PDL127 only) (Flash) DQ15–DQ0 = 16 Data Inputs/Outputs (Common) CE#f1 = Chip Enable 1 (Flash) (PDL 127 only) CE#f1, CE#f2 = Chip Enable Inputs. CE#f1 controls the 64 Mb in Banks 1A and 1B. CE#f2 controls the 64 Mb in Banks 2A and 2B. CE#1ps = Chip Enable 1 (pSRAM) (PDL129 only) CE2ps = Chip Enable 2 (pSRAM) OE# = Output Enable (Common) WE# = Write Enable (Common) RY/BY# = Ready/Busy Output and open drain. When RY/BY# = VIH, the device is ready to accept read operations and commands. When RY/BY# = VOL, the device is either executing an em- bedded algorithm or the device is executing a hardware reset opera- tion. UB#s = Upper Byte Control (pSRAM) LB#s = Lower Byte Control (pSRAM) RESET# = Hardware Reset Pin, Active Low WP#/ACC = Write Protect/Acceleration Input. When WP/ACC#= VIL, the highest and lowest two 4K-word sectors are write protected regardless of other sector protection configurations. When WP/ACC#= VIH, these sector are unprotected unless the DYB or PPB is programmed. When WP/ACC#= 12V, program and erase operations are accelerated. VCCf = Flash 3.0 volt-only single power sup- ply (see Product Selector Guide for speed options and voltage supply tolerances) VCCs = pSRAM Power Supply VSS = Device Ground (Common) NC = Pin Not Connected Internally LOGIC SYMBOL DQ15–DQ0 A21–A0 CE#f1 OE# WE# RESET# UB#s RY/BY# WP#/ACC LB#s CE#1ps CE2ps CE#f2 (PDL129 Only) A22 (PDL127 Only)

Am75PDL191CHH/Am75PDL193CHH February 5, 2004 A D V A N C E I N F O R M A T I O N

ORDERING INFORMATION

The order number (Valid Combination) is formed by the following: Valid Combinations Valid Combinations list configurations planned to be supported in vol- ume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly re- leased combinations. Am75PDL19 C H H N TEMPERATURE RANGE N Light Industrial (–25°C to +85°C) SPEED OPTION See “Product Selector Guide” on page 5. PROCESS TECHNOLOGY OF AM29DL640 H 0.13 µm PROCESS TECHNOLOGY OF AM29PDL127/129 H 0.13 µm PSEUDO SRAM DEVICE DENSITY C

64 Mbits

1 CE Flash

2 CE Flash

AMD DEVICE NUMBER/DESCRIPTION Am75PDL191CHH/Am75PDL193CHH Am29PDL127H/129H–128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory, One Chip Enable Input on Am29PDL127H, Dual Chip Enable Inputs on Am29PDL129H Am29DL640H–64 Megabit (4M x 16-Bit) CMOS Flash Memory

64 Mb pSRAM

Valid Combinations for BGA Packages Order Number Package Marking VIO Range Am75PDL191CHH70I M750000008 2.7–3.3 V Am75PDL193CHH70I M750000009 2.7–3.3 V

February 5, 2004 Am75PDL191CHH/Am75PDL193CHH A D V A N C E I N F O R M A T I O N Am29PDL127H/AM29PDL129H Device Bus Operations This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory loca- tion. The register is a latch used to store the com- mands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Tables 1-2 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail.

Am75PDL191CHH/Am75PDL193CHH February 5, 2004 A D V A N C E I N F O R M A T I O N Table 1. Device Bus Operations Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SADD = Flash Sector Address, AIN = Address In, DIN = Data In, DOUT = Data Out Notes: Other operations except for those indicated in this column are inhibited. Do not apply CE#f1 or 2 = VIL, CE#1ps = VIL and CE2ps = VIH at the same time. Don’t care or open LB#s or UB#s. If WP#/ACC = VIL, the boot sectors will be protected. If WP#/ACC = VIH the boot sectors protection will be removed. If WP#/ACC = VACC (9V), the program time will be reduced by 40%. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector Block Protection and Unprotection” section. If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”. If WP#/ACC = VHH, all sectors will be unprotected. Data will be retained in pSRAM. Data will be lost in pSRAM. Both CE#f1 inputs may be held low for this operation. Operation (Notes 1, 2) CE#f1 Active CE#f2 (PDL129 only) CE#1ps CE2ps OE# WE# Addr. LB#s (Note UB#s (Note RESET# WP#/ ACC (Note 4) DQ7– DQ0 DQ15– DQ8 Read from Active Flash (Note 7) L (H) H (L) H H L H AIN X X H L/H DOUT DOUT (Note 8) H L Write to Active Flash (Note 7) L (H) H (L) H H H L AIN X X H (Note 4) DIN DIN (Note 8) H L Standby VCC ± 0.3 V H H X X X X X VCC ± 0.3 V H High-Z High-Z Deep Power-down Standby VCC ± 0.3 V H L X X X X X VCC ± 0.3 V H High-Z High-Z Output Disable (Note 9) L (H) H (L) L H H H X X X H L/H High-Z High-Z H H X X X Flash Hardware Reset (Note 7) X H H X X X X X L L/H High-Z High-Z (Note 8) H L Sector Protect (Notes 6, 10) (Note 7) L (H) H (L) H H H L SADD, A6 = L, A1 = H, A0 = L X X VID L/H DIN X (Note 9) H L Sector Unprotect (Notes 5, 9) (Note 7) L (H) H (L) H H H L SADD, A6 = H, A1 = H, A0 = L X X VID (Note 6) DIN X (Note 8) H L Temporary Sector Unprotect (Note 7) X H H X X X X X VID (Note 6) DIN High-Z (Note 8) H L Read from pSRAM H H L H L H AIN L L H X DOUT DOUT H L High-Z DOUT L H DOUT High-Z Write to pSRAM H H L H X L AIN L L H X DIN DIN H L High-Z DIN L H DIN High-Z

February 5, 2004 Am75PDL191CHH/Am75PDL193CHH A D V A N C E I N F O R M A T I O N Requirements for Reading Array Data To read array data from the outputs, the system must drive the OE# and appropriate CE#f1/CE#f2 (PDL129 only) pins to VIL. CE#f1 and CE#f2 are the power con- trol and for PDL129 select the lower (CE#f1) or upper (CE#f2) halves of the device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No com- mand is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. Each bank remains enabled for read access until the command register contents are altered. Refer to the AC Characteristics table for timing specifi- cations and to Figure 13 for the timing diagram. ICC1 in the DC Characteristics table represents the active cur- rent specification for reading array data. Random Read (Non-Page Read) Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (tCE) is the delay from the stable ad- dresses and stable CE#f1 to valid data at the output inputs. The output enable access time is the delay from the falling edge of the OE# to valid data at the output inputs (assuming the addresses have been sta- ble for at least tACC–tOE time). Page Mode Read The device is capable of fast page mode read and is compatible with the page mode Mask ROM read oper- ation. This mode provides faster read access speed for random locations within a page. Address bits A22–A3 (A21–A3 for PDL129) select an 8-word page, and address bits A2–A0 select a specific word within that page. This is an asynchronous operation with the microprocessor supplying the specific word location. The random or initial page access is tACC or tCE and subsequent page read accesses (as long as the loca- tions specified by the microprocessor fall within that page) are tPACC. When CE#f1 and CE#f2 (PDL129 only) are deasserted (CE#f1=CE#f2=VIH), the reasser- tion of CE#f1 or CE#f2 (PDL129 only) for subsequent access has access time of tACC or tCE. Here again, CE#f1/CE#f2 (PDL129 only) selects the device and OE# is the output control and should be used to gate data to the output inputs if the device is selected. Fast page mode accesses are obtained by keeping A22–A3 (A21–A3 for PDL129) constant and changing A2 to A0 to select the specific word within that page. Table 2. Page Select Simultaneous Operation In addition to the conventional features (read, pro- gram, erase-suspend read, and erase-suspend pro- gram), the device is capable of reading data from one bank of memory while a program or erase operation is in progress in another bank of memory (simultaneous operation), The bank can be selected by bank ad- dresses (A22–A20) (A21–A20 for PDL129) with zero latency. The simultaneous operation can execute multi-func- tion mode in the same bank. Table 3. Bank Select (PDL129H) Table 4. Bank Select (PDL127H) Word Word 0 Word 1 Word 2 Word 3 Word 4 Word 5 Word 6 Word 7 Bank CE#f1 CE#f2 A21–A20 Bank 1A 00, 01, 10 Bank 1B Bank 2A Bank 2B 01, 10, 11 Bank A22–A20 Bank A 000 Bank B 001, 010, 011 Bank C 100, 101, 110 Bank D 111

Am75PDL191CHH/Am75PDL193CHH February 5, 2004 A D V A N C E I N F O R M A T I O N Writing Commands/Command Sequences To write a command or command sequence (which in- cludes programming data to the device and erasing sectors of memory), the system must drive WE# and CE#f1 or CE#f2 (PDL 129 only) to VIL, and OE# to VIH. The device features an Unlock Bypass mode to facili- tate faster programming. Once a bank enters the Un- lock Bypass mode, only two write cycles are required to program a word, instead of four. The “Word Pro- gram Command Sequence” section has details on programming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sec- tors, or the entire device. Table 4 indicates the address space that each sector occupies. A “bank address” is the address bits required to uniquely select a bank. Similarly, a “sector address” refers to the address bits required to uniquely select a sector. The “Command Definitions” section has details on erasing a sector or the entire chip, or suspending/resuming the erase op- eration. ICC2 in the DC Characteristics table represents the ac- tive current specification for the write mode. The AC Characteristics section contains timing specification tables and timing diagrams for write operations. Accelerated Program Operation The device offers accelerated program operations through the ACC function. This function is primarily in- tended to allow faster manufacturing throughput at the factory. If the system asserts VHH on this pin, the device auto- matically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing VHH from the WP#/ACC pin returns the device to nor- mal operation. Note that VHH must not be asserted on WP#/ACC for operations other than accelerated pro- gramming, or device damage may result. In addition, the WP#/ACC pin should be raised to VCC when not in use. That is, the WP#/ACC pin should not be left float- ing or unconnected; inconsistent behavior of the de- vice may result. Autoselect Functions If the system writes the autoselect command se- quence, the device enters the autoselect mode. The system can then read autoselect codes from the inter- nal register (which is separate from the memory array) on DQ15–DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect Command Se- quence sections for more information. Standby Mode When the system is not reading or writing to the de- vice, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE#f1, CE#f2 (PDL129 only) and RESET# pins are all held at VIO ± 0.3 V. (Note that this is a more restricted voltage range than VIH.) If CE#f1, CE#f2 (PDL129 only), and RESET# are held at VIH, but not within VCC ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device requires standard access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. ICC3 in the DC Characteristics table represents the CMOS standby current specification. Automatic Sleep Mode The automatic sleep mode minimizes Flash device en- ergy consumption. The device automatically enables this mode when addresses remain stable for tACC + 150 ns. The automatic sleep mode is independent of the CE#f1/CE#f2 (PDL129 only), WE#, and OE# con- trol signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always avail- able to the system. Note that during automatic sleep mode, OE# must be at VIH before the device reduces current to the stated sleep mode specification. ICC5 in the DC Characteristics table represents the automatic sleep mode current specification.

February 5, 2004 Am75PDL191CHH/Am75PDL193CHH A D V A N C E I N F O R M A T I O N RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of re- setting the device to reading array data. When the RE- SET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state ma- chine to reading array data. The operation that was in- terrupted should be reinitiated once the device is ready to accept another command sequence, to en- sure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS±0.3 V, the standby current will be greater. The RESET# pin may be tied to the system reset cir- cuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firm- ware from the Flash memory. If RESET# is asserted during a program or erase op- eration, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The sys- tem can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is “1”), the reset operation is completed within a time of tREADY (not during Embedded Algo- rithms). The system can read data tRH after the RE- SET# pin returns to VIH. Refer to the pSRAM AC Characteristics tables for RE- SET# parameters and to Figure 15 for the timing dia- gram. Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The output pins (except for RY/BY#) are placed in the highest Impedance state Table 5. SecSi TM Sector Addresses Sector Size Address Range Am29PDL127H/ Am29PDL129H 128 words 000000h–00007Fh Factory-Locked Area 64 words 000000h-00003Fh Customer-Lockable Area 64 words 000040h-00007Fh

Am75PDL191CHH/Am75PDL193CHH February 5, 2004 A D V A N C E I N F O R M A T I O N Table 6. Am29PDL127H Sector Architecture Bank Sector Sector Address (A22-A12) Sector Size (Kwords) Address Range (x16) Bank A SA0 00000000000 000000h–000FFFh SA1 00000000001 001000h–001FFFh SA2 00000000010 002000h–002FFFh SA3 00000000011 003000h–003FFFh SA4 00000000100 004000h–004FFFh SA5 00000000101 005000h–005FFFh SA6 00000000110 006000h–006FFFh SA7 00000000111 007000h–007FFFh SA8 00000001XXX 008000h–00FFFFh SA9 00000010XXX 010000h–017FFFh SA10 00000011XXX 018000h–01FFFFh SA11 00000100XXX 020000h–027FFFh SA12 00000101XXX 028000h–02FFFFh SA13 00000110XXX 030000h–037FFFh SA14 00000111XXX 038000h–03FFFFh SA15 00001000XXX 040000h–047FFFh SA16 00001001XXX 048000h–04FFFFh SA17 00001010XXX 050000h–057FFFh SA18 00001011XXX 058000h–05FFFFh SA19 00001100XXX 060000h–067FFFh SA20 00001101XXX 068000h–06FFFFh SA21 00001110XXX 070000h–077FFFh SA22 00001111XXX 078000h–07FFFFh SA23 00010000XXX 080000h–087FFFh SA24 00010001XXX 088000h–08FFFFh SA25 00010010XXX 090000h–097FFFh SA26 00010011XXX 098000h–09FFFFh SA27 00010100XXX 0A0000h–0A7FFFh SA28 00010101XXX 0A8000h–0AFFFFh SA29 00010110XXX 0B0000h–0B7FFFh SA30 00010111XXX 0B8000h–0BFFFFh SA31 00011000XXX 0C0000h–0C7FFFh SA32 00011001XXX 0C8000h–0CFFFFh SA33 00011010XXX 0D0000h–0D7FFFh SA34 00011011XXX 0D8000h–0DFFFFh SA35 00011100XXX 0E0000h–0E7FFFh SA36 00011101XXX 0E8000h–0EFFFFh SA37 00011110XXX 0F0000h–0F7FFFh SA38 00011111XXX 0F8000h–0FFFFFh

February 5, 2004 Am75PDL191CHH/Am75PDL193CHH A D V A N C E I N F O R M A T I O N Bank Sector Sector Address (A22-A12) Sector Size (Kwords) Address Range (x16) Bank B SA39 00100000XXX 100000h–107FFFh SA40 00100001XXX 108000h–10FFFFh SA41 00100010XXX 110000h–117FFFh SA42 00100011XXX 118000h–11FFFFh SA43 00100100XXX 120000h–127FFFh SA44 00100101XXX 128000h–12FFFFh SA45 00100110XXX 130000h–137FFFh SA46 00100111XXX 138000h–13FFFFh SA47 00101000XXX 140000h–147FFFh SA48 00101001XXX 148000h–14FFFFh SA49 00101010XXX 150000h–157FFFh SA50 00101011XXX 158000h–15FFFFh SA51 00101100XXX 160000h–167FFFh SA52 00101101XXX 168000h–16FFFFh SA53 00101110XXX 170000h–177FFFh SA54 00101111XXX 178000h–17FFFFh SA55 00110000XXX 180000h–187FFFh SA56 00110001XXX 188000h–18FFFFh SA57 00110010XXX 190000h–197FFFh SA58 00110011XXX 198000h–19FFFFh SA59 00110100XXX 1A0000h–1A7FFFh SA60 00110101XXX 1A8000h–1AFFFFh SA61 00110110XXX 1B0000h–1B7FFFh SA62 00110111XXX 1B8000h–1BFFFFh SA63 00111000XXX 1C0000h–1C7FFFh SA64 00111001XXX 1C8000h–1CFFFFh SA65 00111010XXX 1D0000h–1D7FFFh SA66 00111011XXX 1D8000h–1DFFFFh SA67 00111100XXX 1E0000h–1E7FFFh SA68 00111101XXX 1E8000h–1EFFFFh SA69 00111110XXX 1F0000h–1F7FFFh SA70 00111111XXX 1F8000h–1FFFFFh SA71 01000000XXX 200000h–207FFFh SA72 01000001XXX 208000h–20FFFFh SA73 01000010XXX 210000h–217FFFh SA74 01000011XXX 218000h–21FFFFh SA75 01000100XXX 220000h–227FFFh SA76 01000101XXX 228000h–22FFFFh SA77 01000110XXX 230000h–237FFFh SA78 01000111XXX 238000h–23FFFFh Table 6. Am29PDL127H Sector Architecture (Continued)

Am75PDL191CHH/Am75PDL193CHH February 5, 2004 A D V A N C E I N F O R M A T I O N Bank Sector Sector Address (A22-A12) Sector Size (Kwords) Address Range (x16) Bank B SA79 01001000XXX 240000h–247FFFh SA80 01001001XXX 248000h–24FFFFh SA81 01001010XXX 250000h–257FFFh SA82 01001011XXX 258000h–25FFFFh SA83 01001100XXX 260000h–267FFFh SA84 01001101XXX 268000h–26FFFFh SA85 01001110XXX 270000h–277FFFh SA86 01001111XXX 278000h–27FFFFh SA87 01010000XXX 280000h–287FFFh SA88 01010001XXX 288000h–28FFFFh SA89 01010010XXX 290000h–297FFFh SA90 01010011XXX 298000h–29FFFFh SA91 01010100XXX 2A0000h–2A7FFFh SA92 01010101XXX 2A8000h–2AFFFFh SA93 01010110XXX 2B0000h–2B7FFFh SA94 01010111XXX 2B8000h–2BFFFFh SA95 01011000XXX 2C0000h–2C7FFFh SA96 01011001XXX 2C8000h–2CFFFFh SA97 01011010XXX 2D0000h–2D7FFFh SA98 01011011XXX 2D8000h–2DFFFFh SA99 01011100XXX 2E0000h–2E7FFFh SA100 01011101XXX 2E8000h–2EFFFFh SA101 01011110XXX 2F0000h–2F7FFFh SA102 01011111XXX 2F8000h–2FFFFFh SA103 01100000XXX 300000h–307FFFh SA104 01100001XXX 308000h–30FFFFh SA105 01100010XXX 310000h–317FFFh SA106 01100011XXX 318000h–31FFFFh SA107 01100100XXX 320000h–327FFFh SA108 01100101XXX 328000h–32FFFFh SA109 01100110XXX 330000h–337FFFh SA110 01100111XXX 338000h–33FFFFh SA111 01101000XXX 340000h–347FFFh SA112 01101001XXX 348000h–34FFFFh SA113 01101010XXX 350000h–357FFFh SA114 01101011XXX 358000h–35FFFFh SA115 01101100XXX 360000h–367FFFh SA116 01101101XXX 368000h–36FFFFh SA117 01101110XXX 370000h–377FFFh SA118 01101111XXX 378000h–37FFFFh Table 6. Am29PDL127H Sector Architecture (Continued)

February 5, 2004 Am75PDL191CHH/Am75PDL193CHH A D V A N C E I N F O R M A T I O N Bank Sector Sector Address (A22-A12) Sector Size (Kwords) Address Range (x16) Bank B SA119 01110000XXX 380000h–387FFFh SA120 01110001XXX 388000h–38FFFFh SA121 01110010XXX 390000h–397FFFh SA122 01110011XXX 398000h–39FFFFh SA123 01110100XXX 3A0000h–3A7FFFh SA124 01110101XXX 3A8000h–3AFFFFh SA125 01110110XXX 3B0000h–3B7FFFh SA126 01110111XXX 3B8000h–3BFFFFh SA127 01111000XXX 3C0000h–3C7FFFh SA128 01111001XXX 3C8000h–3CFFFFh SA129 01111010XXX 3D0000h–3D7FFFh SA130 01111011XXX 3D8000h–3DFFFFh SA131 01111100XXX 3E0000h–3E7FFFh SA132 01111101XXX 3E8000h–3EFFFFh SA133 01111110XXX 3F0000h–3F7FFFh SA134 01111111XXX 3F8000h–3FFFFFh Bank C SA135 10000000XXX 400000h–407FFFh SA136 10000001XXX 408000h–40FFFFh SA137 10000010XXX 410000h–417FFFh SA138 10000011XXX 418000h–41FFFFh SA139 10000100XXX 420000h–427FFFh SA140 10000101XXX 428000h–42FFFFh SA141 10000110XXX 430000h–437FFFh SA142 10000111XXX 438000h–43FFFFh SA143 10001000XXX 440000h–447FFFh SA144 10001001XXX 448000h–44FFFFh SA145 10001010XXX 450000h–457FFFh SA146 10001011XXX 458000h–45FFFFh SA147 10001100XXX 460000h–467FFFh SA148 10001101XXX 468000h–46FFFFh SA149 10001110XXX 470000h–477FFFh SA150 10001111XXX 478000h–47FFFFh SA151 10010000XXX 480000h–487FFFh SA152 10010001XXX 488000h–48FFFFh SA153 10010010XXX 490000h–497FFFh SA154 10010011XXX 498000h–49FFFFh SA155 10010100XXX 4A0000h–4A7FFFh SA156 10010101XXX 4A8000h–4AFFFFh SA157 10010110XXX 4B0000h–4B7FFFh SA158 10010111XXX 4B8000h–4BFFFFh Table 6. Am29PDL127H Sector Architecture (Continued)

Am75PDL191CHH/Am75PDL193CHH February 5, 2004 A D V A N C E I N F O R M A T I O N Bank Sector Sector Address (A22-A12) Sector Size (Kwords) Address Range (x16) Bank C SA159 10011000XXX 4C0000h–4C7FFFh SA160 10011001XXX 4C8000h–4CFFFFh SA161 10011010XXX 4D0000h–4D7FFFh SA162 10011011XXX 4D8000h–4DFFFFh SA163 10011100XXX 4E0000h–4E7FFFh SA164 10011101XXX 4E8000h–4EFFFFh SA165 10011110XXX 4F0000h–4F7FFFh SA166 10011111XXX 4F8000h–4FFFFFh SA167 10100000XXX 500000h–507FFFh SA168 10100001XXX 508000h–50FFFFh SA169 10100010XXX 510000h–517FFFh SA170 10100011XXX 518000h–51FFFFh SA171 10100100XXX 520000h–527FFFh SA172 10100101XXX 528000h–52FFFFh SA173 10100110XXX 530000h–537FFFh SA174 10100111XXX 538000h–53FFFFh SA175 10101000XXX 540000h–547FFFh SA176 10101001XXX 548000h–54FFFFh SA177 10101010XXX 550000h–557FFFh SA178 10101011XXX 558000h–15FFFFh SA179 10101100XXX 560000h–567FFFh SA180 10101101XXX 568000h–56FFFFh SA181 10101110XXX 570000h–577FFFh SA182 10101111XXX 578000h–57FFFFh SA183 10110000XXX 580000h–587FFFh SA184 10110001XXX 588000h–58FFFFh SA185 10110010XXX 590000h–597FFFh SA186 10110011XXX 598000h–59FFFFh SA187 10110100XXX 5A0000h–5A7FFFh SA188 10110101XXX 5A8000h–5AFFFFh SA189 10110110XXX 5B0000h–5B7FFFh SA190 10110111XXX 5B8000h–5BFFFFh SA191 10111000XXX 5C0000h–5C7FFFh SA192 10111001XXX 5C8000h–5CFFFFh SA193 10111010XXX 5D0000h–5D7FFFh SA194 10111011XXX 5D8000h–5DFFFFh SA195 10111100XXX 5E0000h–5E7FFFh SA196 10111101XXX 5E8000h–5EFFFFh SA197 10111110XXX 5F0000h–5F7FFFh SA198 10111111XXX 5F8000h–5FFFFFh Table 6. Am29PDL127H Sector Architecture (Continued)

February 5, 2004 Am75PDL191CHH/Am75PDL193CHH A D V A N C E I N F O R M A T I O N Bank Sector Sector Address (A22-A12) Sector Size (Kwords) Address Range (x16) Bank C SA199 11000000XXX 600000h–607FFFh SA200 11000001XXX 608000h–60FFFFh SA201 11000010XXX 610000h–617FFFh SA202 11000011XXX 618000h–61FFFFh SA203 11000100XXX 620000h–627FFFh SA204 11000101XXX 628000h–62FFFFh SA205 11000110XXX 630000h–637FFFh SA206 11000111XXX 638000h–63FFFFh SA207 11001000XXX 640000h–647FFFh SA208 11001001XXX 648000h–64FFFFh SA209 11001010XXX 650000h–657FFFh SA210 11001011XXX 658000h–65FFFFh SA211 11001100XXX 660000h–667FFFh SA212 11001101XXX 668000h–66FFFFh SA213 11001110XXX 670000h–677FFFh SA214 11001111XXX 678000h–67FFFFh SA215 11010000XXX 680000h–687FFFh SA216 11010001XXX 688000h–68FFFFh SA217 11010010XXX 690000h–697FFFh SA218 11010011XXX 698000h–69FFFFh SA219 11010100XXX 6A0000h–6A7FFFh SA220 11010101XXX 6A8000h–6AFFFFh SA221 11010110XXX 6B0000h–6B7FFFh SA222 11010111XXX 6B8000h–6BFFFFh SA223 11011000XXX 6C0000h–6C7FFFh SA224 11011001XXX 6C8000h–6CFFFFh SA225 11011010XXX 6D0000h–6D7FFFh SA226 11011011XXX 6D8000h–6DFFFFh SA227 11011100XXX 6E0000h–6E7FFFh SA228 11011101XXX 6E8000h–6EFFFFh SA229 11011110XXX 6F0000h–6F7FFFh SA230 11011111XXX 6F8000h–6FFFFFh Table 6. Am29PDL127H Sector Architecture (Continued)

Am75PDL191CHH/Am75PDL193CHH February 5, 2004 A D V A N C E I N F O R M A T I O N Bank Sector Sector Address (A22-A12) Sector Size (Kwords) Address Range (x16) Bank D SA231 11100000XXX 700000h–707FFFh SA232 11100001XXX 708000h–70FFFFh SA233 11100010XXX 710000h–717FFFh SA234 11100011XXX 718000h–71FFFFh SA235 11100100XXX 720000h–727FFFh SA236 11100101XXX 728000h–72FFFFh SA237 11100110XXX 730000h–737FFFh SA238 11100111XXX 738000h–73FFFFh SA239 11101000XXX 740000h–747FFFh SA240 11101001XXX 748000h–74FFFFh SA241 11101010XXX 750000h–757FFFh SA242 11101011XXX 758000h–75FFFFh SA243 11101100XXX 760000h–767FFFh SA244 11101101XXX 768000h–76FFFFh SA245 11101110XXX 770000h–777FFFh SA246 11101111XXX 778000h–77FFFFh SA247 11110000XXX 780000h–787FFFh SA248 11110001XXX 788000h–78FFFFh SA249 11110010XXX 790000h–797FFFh SA250 11110011XXX 798000h–79FFFFh SA251 11110100XXX 7A0000h–7A7FFFh SA252 11110101XXX 7A8000h–7AFFFFh SA253 11110110XXX 7B0000h–7B7FFFh SA254 11110111XXX 7B8000h–7BFFFFh SA255 11111000XXX 7C0000h–7C7FFFh SA256 11111001XXX 7C8000h–7CFFFFh SA257 11111010XXX 7D0000h–7D7FFFh SA258 11111011XXX 7D8000h–7DFFFFh SA259 11111100XXX 7E0000h–7E7FFFh SA260 11111101XXX 7E8000h–7EFFFFh SA261 11111110XXX 7F0000h–7F7FFFh SA262 11111111000 7F8000h–7F8FFFh SA263 11111111001 7F9000h–7F9FFFh SA264 11111111010 7FA000h–7FAFFFh SA265 11111111011 7FB000h–7FBFFFh SA266 11111111100 7FC000h–7FCFFFh SA267 11111111101 7FD000h–7FDFFFh SA268 11111111110 7FE000h–7FEFFFh SA269 11111111111 7FF000h–7FFFFFh Table 6. Am29PDL127H Sector Architecture (Continued)

February 5, 2004 Am75PDL191CHH/Am75PDL193CHH A D V A N C E I N F O R M A T I O N Table 7. Am29PDL129H Sector Architecture Bank Sector CE#f1 CE#f2 Sector Address (A21-A12) Sector Size (Kwords) Address Range (x16) Bank 1A SA1-0 0000000XXX 000000h–007FFFh SA1-1 0000001XXX 008000h–00FFFFh SA1-2 0000010XXX 010000h–017FFFh SA1-3 0000011XXX 018000h–01FFFFh SA1-4 0000100XXX 020000h–027FFFh SA1-5 0000101XXX 028000h–02FFFFh SA1-6 0000110XXX 030000h–037FFFh SA1-7 0000111XXX 038000h–03FFFFh SA1-8 0001000XXX 040000h–047FFFh SA1-9 0001001XXX 048000h–04FFFFh SA1-10 0001010XXX 050000h–057FFFh SA1-11 0001011XXX 058000h–05FFFFh SA1-12 0001100XXX 060000h–067FFFh SA1-13 0001101XXX 068000h–06FFFFh SA1-14 0001110XXX 070000h–077FFFh SA1-15 0001111XXX 078000h–07FFFFh SA1-16 0010000XXX 080000h–087FFFh SA1-17 0010001XXX 088000h–08FFFFh SA1-18 0010010XXX 090000h–097FFFh SA1-19 0010011XXX 098000h–09FFFFh SA1-20 0010100XXX 0A0000h–0A7FFFh SA1-21 0010101XXX 0A8000h–0AFFFFh SA1-22 0010110XXX 0B0000h–0B7FFFh SA1-23 0010111XXX 0B8000h–0BFFFFh SA1-24 0011000XXX 0C0000h–0C7FFFh SA1-25 0011001XXX 0C8000h–0CFFFFh SA1-26 0011010XXX 0D0000h–0D7FFFh SA1-27 0011011XXX 0D8000h–0DFFFFh SA1-28 0011100XXX 0E0000h–0E7FFFh SA1-29 0011101XXX 0E8000h–0EFFFFh SA1-30 0011110XXX 0F0000h–0F7FFFh SA1-31 0011111XXX 0F8000h–0FFFFFh SA1-32 0100000XXX 100000h–107FFFh SA1-33 0100001XXX 108000h–10FFFFh SA1-34 0100010XXX 110000h–117FFFh SA1-35 0100011XXX 118000h–11FFFFh SA1-36 0100100XXX 120000h–127FFFh SA1-37 0100101XXX 128000h–12FFFFh

Am75PDL191CHH/Am75PDL193CHH February 5, 2004 A D V A N C E I N F O R M A T I O N Bank Sector CE#f1 CE#f2 Sector Address (A21-A12) Sector Size (Kwords) Address Range (x16) Bank 1A SA1-38 0100110XXX 130000h–137FFFh SA1-39 0100111XXX 138000h–13FFFFh SA1-40 0101000XXX 140000h–147FFFh SA1-41 0101001XXX 148000h–14FFFFh SA1-42 0101010XXX 150000h–157FFFh SA1-43 0101011XXX 158000h–15FFFFh SA1-44 0101100XXX 160000h–167FFFh SA1-45 0101101XXX 168000h–16FFFFh SA1-46 0101110XXX 170000h–177FFFh SA1-47 0101111XXX 178000h–17FFFFh SA1-48 0110000XXX 180000h–187FFFh SA1-49 0110001XXX 188000h–18FFFFh SA1-50 0110010XXX 190000h–197FFFh SA1-51 0110011XXX 198000h–19FFFFh SA1-52 0110100XXX 1A0000h–1A7FFFh SA1-53 0110101XXX 1A8000h–1AFFFFh SA1-54 0110110XXX 1B0000h–1B7FFFh SA1-55 0110111XXX 1B8000h–1BFFFFh SA1-56 0111000XXX 1C0000h–1C7FFFh SA1-57 0111001XXX 1C8000h–1CFFFFh SA1-58 0111010XXX 1D0000h–1D7FFFh SA1-59 0111011XXX 1D8000h–1DFFFFh SA1-60 0111100XXX 1E0000h–1E7FFFh SA1-61 0111101XXX 1E8000h–1EFFFFh SA1-62 0111110XXX 1F0000h–1F7FFFh SA1-63 0111111XXX 1F8000h–1FFFFFh SA1-64 1000000XXX 200000h–207FFFh SA1-65 1000001XXX 208000h–20FFFFh SA1-66 1000010XXX 210000h–217FFFh SA1-67 1000011XXX 218000h–21FFFFh SA1-68 1000100XXX 220000h–227FFFh SA1-69 1000101XXX 228000h–22FFFFh SA1-70 1000110XXX 230000h–237FFFh SA1-71 1000111XXX 238000h–23FFFFh SA1-72 1001000XXX 240000h–247FFFh SA1-73 1001001XXX 248000h–24FFFFh SA1-74 1001010XXX 250000h–257FFFh SA1-75 1001011XXX 258000h–25FFFFh SA1-76 1001100XXX 260000h–267FFFh SA1-77 1001101XXX 268000h–26FFFFh Table 7. Am29PDL129H Sector Architecture (Continued)

February 5, 2004 Am75PDL191CHH/Am75PDL193CHH A D V A N C E I N F O R M A T I O N Bank Sector CE#f1 CE#f2 Sector Address (A21-A12) Sector Size (Kwords) Address Range (x16) Bank 1A SA1-78 1001110XXX 270000h–277FFFh SA1-79 1001111XXX 278000h–27FFFFh SA1-80 1010000XXX 280000h–287FFFh SA1-81 1010001XXX 288000h–28FFFFh SA1-82 1010010XXX 290000h–297FFFh SA1-83 1010011XXX 298000h–29FFFFh SA1-84 1010100XXX 2A0000h–2A7FFFh SA1-85 1010101XXX 2A8000h–2AFFFFh SA1-86 1010110XXX 2B0000h–2B7FFFh SA1-87 1010111XXX 2B8000h–2BFFFFh SA1-88 1011000XXX 2C0000h–2C7FFFh SA1-89 1011001XXX 2C8000h–2CFFFFh SA1-90 1011010XXX 2D0000h–2D7FFFh SA1-91 1011011XXX 2D8000h–2DFFFFh SA1-92 1011100XXX 2E0000h–2E7FFFh SA1-93 1011101XXX 2E8000h–2EFFFFh SA1-94 1011110XXX 2F0000h–2F7FFFh SA1-95 1011111XXX 2F8000h–2FFFFFh Table 7. Am29PDL129H Sector Architecture (Continued)

Am75PDL191CHH/Am75PDL193CHH February 5, 2004 A D V A N C E I N F O R M A T I O N Bank Sector CE#f1 CE#f2 Sector Address (A21-A12) Sector Size (Kwords) Address Range (x16) Bank 1B SA1-96 1100000XXX 300000h–307FFFh SA1-97 1100001XXX 308000h–30FFFFh SA1-98 1100010XXX 310000h–317FFFh SA1-99 1100011XXX 318000h–31FFFFh SA1-100 1100100XXX 320000h–327FFFh SA1-101 1100101XXX 328000h–32FFFFh SA1-102 1100110XXX 330000h–337FFFh SA1-103 1100111XXX 338000h–33FFFFh SA1-104 1101000XXX 340000h–347FFFh SA1-105 1101001XXX 348000h–34FFFFh SA1-106 1101010XXX 350000h–357FFFh SA1-107 1101011XXX 358000h–35FFFFh SA1-108 1101100XXX 360000h–367FFFh SA1-109 1101101XXX 368000h–36FFFFh SA1-110 1101110XXX 370000h–377FFFh SA1-111 1101111XXX 378000h–37FFFFh SA1-112 1110000XXX 380000h–387FFFh SA1-113 1110001XXX 388000h–38FFFFh SA1-114 1110010XXX 390000h–397FFFh SA1-115 1110011XXX 398000h–39FFFFh SA1-116 1110100XXX 3A0000h–3A7FFFh SA1-117 1110101XXX 3A8000h–3AFFFFh SA1-118 1110110XXX 3B0000h–3B7FFFh SA1-119 1110111XXX 3B8000h–3BFFFFh SA1-120 1111000XXX 3C0000h–3C7FFFh SA1-121 1111001XXX 3C8000h–3CFFFFh SA1-122 1111010XXX 3D0000h–3D7FFFh SA1-123 1111011XXX 3D8000h–3DFFFFh SA1-124 1111100XXX 3E0000h–3E7FFFh SA1-125 1111101XXX 3E8000h–3EFFFFh SA1-126 1111110XXX 3F0000h–3F7FFFh SA1-127 1111111000 3F8000h–3F8FFFh SA1-128 1111111001 3F9000h–3F9FFFh SA1-129 1111111010 3FA000h–3FAFFFh SA1-130 1111111011 3FB000h–3FBFFFh SA1-131 1111111100 3FC000h–3FCFFFh SA1-132 1111111101 3FD000h–3FDFFFh SA1-133 1111111110 3FE000h–3FEFFFh SA1-134 1111111111 3FF000h–3FFFFFh Table 7. Am29PDL129H Sector Architecture (Continued)

February 5, 2004 Am75PDL191CHH/Am75PDL193CHH A D V A N C E I N F O R M A T I O N Bank Sector CE#f1 CE#f2 Sector Address (A21-A12) Sector Size (Kwords) Address Range (x16) Bank 2A SA2-0 0000000000 000000h–000FFFh SA2-1 0000000001 001000h–001FFFh SA2-2 0000000010 002000h–002FFFh SA2-3 0000000011 003000h–003FFFh SA2-4 0000000100 004000h–004FFFh SA2-5 0000000101 005000h–005FFFh SA2-6 0000000110 006000h–006FFFh SA2-7 0000000111 007000h–007FFFh SA2-8 0000001XXX 008000h–00FFFFh SA2-9 0000010XXX 010000h–017FFFh SA2-10 0000011XXX 018000h–01FFFFh SA2-11 0000100XXX 020000h–027FFFh SA2-12 0000101XXX 028000h–02FFFFh SA2-13 0000110XXX 030000h–037FFFh SA2-14 0000111XXX 038000h–03FFFFh SA2-15 0001000XXX 040000h–047FFFh SA2-16 0001001XXX 048000h–04FFFFh SA2-17 0001010XXX 050000h–057FFFh SA2-18 0001011XXX 058000h–05FFFFh SA2-19 0001100XXX 060000h–067FFFh SA2-20 0001101XXX 068000h–06FFFFh SA2-21 0001110XXX 070000h–077FFFh SA2-22 0001111XXX 078000h–07FFFFh SA2-23 0010000XXX 080000h–087FFFh SA2-24 0010001XXX 088000h–08FFFFh SA2-25 0010010XXX 090000h–097FFFh SA2-26 0010011XXX 098000h–09FFFFh SA2-27 0010100XXX 0A0000h–0A7FFFh SA2-28 0010101XXX 0A8000h–0AFFFFh SA2-29 0010110XXX 0B0000h–0B7FFFh SA2-30 0010111XXX 0B8000h–0BFFFFh SA2-31 0011000XXX 0C0000h–0C7FFFh SA2-32 0011001XXX 0C8000h–0CFFFFh SA2-33 0011010XXX 0D0000h–0D7FFFh SA2-34 0011011XXX 0D8000h–0DFFFFh SA2-35 0011100XXX 0E0000h–0E7FFFh SA2-36 0011101XXX 0E8000h–0EFFFFh SA2-37 0011110XXX 0F0000h–0F7FFFh SA2-38 0011111XXX 0F8000h–0FFFFFh Table 7. Am29PDL129H Sector Architecture (Continued)

Am75PDL191CHH/Am75PDL193CHH February 5, 2004 A D V A N C E I N F O R M A T I O N Bank Sector CE#f1 CE#f2 Sector Address (A21-A12) Sector Size (Kwords) Address Range (x16) Bank 2B SA2-39 0100000XXX 100000h–107FFFh SA2-40 0100001XXX 108000h–10FFFFh SA2-41 0100010XXX 110000h–117FFFh SA2-42 0100011XXX 118000h–11FFFFh SA2-43 0100100XXX 120000h–127FFFh SA2-44 0100101XXX 128000h–12FFFFh SA2-45 0100110XXX 130000h–137FFFh SA2-46 0100111XXX 138000h–13FFFFh SA2-47 0101000XXX 140000h–147FFFh SA2-48 0101001XXX 148000h–14FFFFh SA2-49 0101010XXX 150000h–157FFFh SA2-50 0101011XXX 158000h–15FFFFh SA2-51 0101100XXX 160000h–167FFFh SA2-52 0101101XXX 168000h–16FFFFh SA2-53 0101110XXX 170000h–177FFFh SA2-54 0101111XXX 178000h–17FFFFh SA2-55 0110000XXX 180000h–187FFFh SA2-56 0110001XXX 188000h–18FFFFh SA2-57 0110010XXX 190000h–197FFFh SA2-58 0110011XXX 198000h–19FFFFh SA2-59 0110100XXX 1A0000h–1A7FFFh SA2-60 0110101XXX 1A8000h–1AFFFFh SA2-61 0110110XXX 1B0000h–1B7FFFh SA2-62 0110111XXX 1B8000h–1BFFFFh SA2-63 0111000XXX 1C0000h–1C7FFFh SA2-64 0111001XXX 1C8000h–1CFFFFh SA2-65 0111010XXX 1D0000h–1D7FFFh SA2-66 0111011XXX 1D8000h–1DFFFFh SA2-67 0111100XXX 1E0000h–1E7FFFh SA2-68 0111101XXX 1E8000h–1EFFFFh SA2-69 0111110XXX 1F0000h–1F7FFFh SA2-70 0111111XXX 1F8000h–1FFFFFh SA2-71 1000000XXX 200000h–207FFFh SA2-72 1000001XXX 208000h–20FFFFh SA2-73 1000010XXX 210000h–217FFFh SA2-74 1000011XXX 218000h–21FFFFh SA2-75 1000100XXX 220000h–227FFFh SA2-76 1000101XXX 228000h–22FFFFh SA2-77 1000110XXX 230000h–237FFFh SA2-78 1000111XXX 238000h–23FFFFh Table 7. Am29PDL129H Sector Architecture (Continued)

February 5, 2004 Am75PDL191CHH/Am75PDL193CHH A D V A N C E I N F O R M A T I O N Bank Sector CE#f1 CE#f2 Sector Address (A21-A12) Sector Size (Kwords) Address Range (x16) Bank 2B SA2-79 1001000XXX 240000h–247FFFh SA2-80 1001001XXX 248000h–24FFFFh SA2-81 1001010XXX 250000h–257FFFh SA2-82 1001011XXX 258000h–25FFFFh SA2-83 1001100XXX 260000h–267FFFh SA2-84 1001101XXX 268000h–26FFFFh SA2-85 1001110XXX 270000h–277FFFh SA2-86 1001111XXX 278000h–27FFFFh SA2-87 1010000XXX 280000h–287FFFh SA2-88 1010001XXX 288000h–28FFFFh SA2-89 1010010XXX 290000h–297FFFh SA2-90 1010011XXX 298000h–29FFFFh SA2-91 1010100XXX 2A0000h–2A7FFFh SA2-92 1010101XXX 2A8000h–2AFFFFh SA2-93 1010110XXX 2B0000h–2B7FFFh SA2-94 1010111XXX 2B8000h–2BFFFFh SA2-95 1011000XXX 2C0000h–2C7FFFh SA2-96 1011001XXX 2C8000h–2CFFFFh SA2-97 1011010XXX 2D0000h–2D7FFFh SA2-98 1011011XXX 2D8000h–2DFFFFh SA2-99 1011100XXX 2E0000h–2E7FFFh SA2-100 1011101XXX 2E8000h–2EFFFFh SA2-101 1011110XXX 2F0000h–2F7FFFh SA2-102 1011111XXX 2F8000h–2FFFFFh SA2-103 1100000XXX 300000h–307FFFh SA2-104 1100001XXX 308000h–30FFFFh SA2-105 1100010XXX 310000h–317FFFh SA2-106 1100011XXX 318000h–31FFFFh SA2-107 1100100XXX 320000h–327FFFh SA2-108 1100101XXX 328000h–32FFFFh SA2-109 1100110XXX 330000h–337FFFh SA2-110 1100111XXX 338000h–33FFFFh SA2-111 1101000XXX 340000h–347FFFh SA2-112 1101001XXX 348000h–34FFFFh SA2-113 1101010XXX 350000h–357FFFh SA2-114 1101011XXX 358000h–35FFFFh SA2-115 1101100XXX 360000h–367FFFh SA2-116 1101101XXX 368000h–36FFFFh SA2-117 1101110XXX 370000h–377FFFh SA2-118 1101111XXX 378000h–37FFFFh Table 7. Am29PDL129H Sector Architecture (Continued)

Am75PDL191CHH/Am75PDL193CHH February 5, 2004 A D V A N C E I N F O R M A T I O N Bank Sector CE#f1 CE#f2 Sector Address (A21-A12) Sector Size (Kwords) Address Range (x16) Bank 2B SA2-119 1110000XXX 380000h–387FFFh SA2-120 1110001XXX 388000h–38FFFFh SA2-121 1110010XXX 390000h–397FFFh SA2-122 1110011XXX 398000h–39FFFFh SA2-123 1110100XXX 3A0000h–3A7FFFh SA2-124 1110101XXX 3A8000h–3AFFFFh SA2-125 1110110XXX 3B0000h–3B7FFFh SA2-126 1110111XXX 3B8000h–3BFFFFh SA2-127 1111000XXX 3C0000h–3C7FFFh SA2-128 1111001XXX 3C8000h–3CFFFFh SA2-129 1111010XXX 3D0000h–3D7FFFh SA2-130 1111011XXX 3D8000h–3DFFFFh SA2-131 1111100XXX 3E0000h–3E7FFFh SA2-132 1111101XXX 3E8000h–3EFFFFh SA2-133 1111110XXX 3F0000h–3F7FFFh SA2-134 1111111XXX 3F8000h–3FFFFFh Table 7. Am29PDL129H Sector Architecture (Continued)

February 5, 2004 Am75PDL191CHH/Am75PDL193CHH A D V A N C E I N F O R M A T I O N Table 8. Am29PDL127H Boot Sector/Sector Block Addresses for Protection/Unprotection Sector A22-A12 Sector/ Sector Block Size SA0 00000000000

4 Kwords

32 Kwords

128 (4x32) Kwords SA15-SA18 000010XXXXX 128 (4x32) Kwords SA19-SA22 000011XXXXX 128 (4x32) Kwords SA23-SA26 000100XXXXX 128 (4x32) Kwords SA27-SA30 000101XXXXX 128 (4x32) Kwords SA31-SA34 000110XXXXX 128 (4x32) Kwords SA35-SA38 000111XXXXX 128 (4x32) Kwords SA39-SA42 001000XXXXX 128 (4x32) Kwords SA43-SA46 001001XXXXX 128 (4x32) Kwords SA47-SA50 001010XXXXX 128 (4x32) Kwords SA51-SA54 001011XXXXX 128 (4x32) Kwords SA55-SA58 001100XXXXX 128 (4x32) Kwords SA59-SA62 001101XXXXX 128 (4x32) Kwords SA63-SA66 001110XXXXX 128 (4x32) Kwords SA67-SA70 001111XXXXX 128 (4x32) Kwords SA71-SA74 010000XXXXX 128 (4x32) Kwords SA75-SA78 010001XXXXX 128 (4x32) Kwords SA79-SA82 010010XXXXX 128 (4x32) Kwords SA83-SA86 010011XXXXX 128 (4x32) Kwords SA87-SA90 010100XXXXX 128 (4x32) Kwords SA91-SA94 010101XXXXX 128 (4x32) Kwords SA95-SA98 010110XXXXX 128 (4x32) Kwords SA99-SA102 010111XXXXX 128 (4x32) Kwords SA103-SA106 011000XXXXX 128 (4x32) Kwords SA107-SA110 011001XXXXX 128 (4x32) Kwords SA111-SA114 011010XXXXX 128 (4x32) Kwords SA115-SA118 011011XXXXX 128 (4x32) Kwords SA119-SA122 011100XXXXX 128 (4x32) Kwords SA123-SA126 011101XXXXX 128 (4x32) Kwords SA127-SA130 011110XXXXX 128 (4x32) Kwords Sector A22-A12 Sector/ Sector Block Size SA131-SA134 011111XXXXX 128 (4x32) Kwords SA135-SA138 100000XXXXX 128 (4x32) Kwords SA139-SA142 100001XXXXX 128 (4x32) Kwords SA143-SA146 100010XXXXX 128 (4x32) Kwords SA147-SA150 100011XXXXX 128 (4x32) Kwords SA151-SA154 100100XXXXX 128 (4x32) Kwords SA155-SA158 100101XXXXX 128 (4x32) Kwords SA159-SA162 100110XXXXX 128 (4x32) Kwords SA163-SA166 100111XXXXX 128 (4x32) Kwords SA167-SA170 101000XXXXX 128 (4x32) Kwords SA171-SA174 101001XXXXX 128 (4x32) Kwords SA175-SA178 101010XXXXX 128 (4x32) Kwords SA179-SA182 101011XXXXX 128 (4x32) Kwords SA183-SA186 101100XXXXX 128 (4x32) Kwords SA187-SA190 101101XXXXX 128 (4x32) Kwords SA191-SA194 101110XXXXX 128 (4x32) Kwords SA195-SA198 101111XXXXX 128 (4x32) Kwords SA199-SA202 110000XXXXX 128 (4x32) Kwords SA203-SA206 110001XXXXX 128 (4x32) Kwords SA207-SA210 110010XXXXX 128 (4x32) Kwords SA211-SA214 110011XXXXX 128 (4x32) Kwords SA215-SA218 110100XXXXX 128 (4x32) Kwords SA219-SA222 110101XXXXX 128 (4x32) Kwords SA223-SA226 110110XXXXX 128 (4x32) Kwords SA227-SA230 110111XXXXX 128 (4x32) Kwords SA231-SA234 111000XXXXX 128 (4x32) Kwords SA235-SA238 111001XXXXX 128 (4x32) Kwords SA239-SA242 111010XXXXX 128 (4x32) Kwords SA243-SA246 111011XXXXX 128 (4x32) Kwords SA247-SA250 111100XXXXX 128 (4x32) Kwords SA251-SA254 111101XXXXX 128 (4x32) Kwords SA255-SA258 111110XXXXX 128 (4x32) Kwords SA259 11111100XXX

Am75PDL191CHH/Am75PDL193CHH February 5, 2004 A D V A N C E I N F O R M A T I O N Table 9. Am29PDL129H Boot Sector/Sector Block Addresses for Protection/Unprotection CE#f1 Control Table 10. Am29PDL129H Boot Sector/Sector Block Addresses for Protection/Unprotection CE#f2 Control Sector Group A21-12 Sector/Sector Block Size SA1-0–SA1-3 00000XXXXX 128 (4x32) Kwords SA1-4–SA1-7 00001XXXXX 128 (4x32) Kwords SA1-8–SA1-11 00010XXXXX 128 (4x32) Kwords SA1-12–SA1-15 00011XXXXX 128 (4x32) Kwords SA1-16–SA1-19 00100XXXXX 128 (4x32) Kwords SA1-20–SA1-23 00101XXXXX 128 (4x32) Kwords SA1-24–SA1-27 00110XXXXX 128 (4x32) Kwords SA1-28–SA1-31 00111XXXXX 128 (4x32) Kwords SA1-32–SA1-35 01000XXXXX 128 (4x32) Kwords SA1-36–SA1-39 01001XXXXX 128 (4x32) Kwords SA1-40–SA1-43 01010XXXXX 128 (4x32) Kwords SA1-44–SA1-47 01011XXXXX 128 (4x32) Kwords SA1-48–SA1-51 01100XXXXX 128 (4x32) Kwords SA1-52–SA1-55 01101XXXXX 128 (4x32) Kwords SA1-56–SA1-59 01110XXXXX 128 (4x32) Kwords SA1-60–SA1-63 01111XXXXX 128 (4x32) Kwords SA1-64–SA1-67 10000XXXXX 128 (4x32) Kwords SA1-68–SA1-71 10001XXXXX 128 (4x32) Kwords SA1-72–SA1-75 10010XXXXX 128 (4x32) Kwords SA1-76–SA1-79 10011XXXXX 128 (4x32) Kwords SA1-80–SA1-83 10100XXXXX 128 (4x32) Kwords SA1-84–SA1-87 10101XXXXX 128 (4x32) Kwords SA1-88–SA1-91 10110XXXXX 128 (4x32) Kwords SA1-92–SA1-95 10111XXXXX 128 (4x32) Kwords SA1-96–SA1-99 11000XXXXX 128 (4x32) Kwords SA1-100–SA1-103 11001XXXXX 128 (4x32) Kwords SA1-104–SA1-107 11010XXXXX 128 (4x32) Kwords SA1-108–SA1-111 11011XXXXX 128 (4x32) Kwords SA1-112–SA1-115 11100XXXXX 128 (4x32) Kwords SA1-116–SA1-119 11101XXXXX 128 (4x32) Kwords SA1-120–SA1-123 11110XXXXX 128 (4x32) Kwords SA1-124 1111100XXX 128 (4x32) Kwords SA2-15 - SA2-18 00010XXXXX 128 (4x32) Kwords SA2-19 - SA2-22 00011XXXXX 128 (4x32) Kwords SA2-23 - SA2-26 00100XXXXX 128 (4x32) Kwords SA2-27 - SA2-30 00101XXXXX 128 (4x32) Kwords SA2-31 - SA2-34 00110XXXXX 128 (4x32) Kwords SA2-35 - SA2-38 00111XXXXX 128 (4x32) Kwords SA2-39 - SA2-42 01000XXXXX 128 (4x32) Kwords SA2-43 - SA2-46 01001XXXXX 128 (4x32) Kwords SA2-47 - SA2-50 01010XXXXX 128 (4x32) Kwords SA2-51 - SA2-54 01011XXXXX 128 (4x32) Kwords SA2-55 - SA2-58 01100XXXXX 128 (4x32) Kwords SA2-59 - SA2-62 01101XXXXX 128 (4x32) Kwords SA2-63 - SA2-66 01110XXXXX 128 (4x32) Kwords SA2-67 - SA2-70 01111XXXXX 128 (4x32) Kwords SA2-71 - SA2-74 10000XXXXX 128 (4x32) Kwords SA2-75 - SA2-78 10001XXXXX 128 (4x32) Kwords SA2-79 - SA2-82 10010XXXXX 128 (4x32) Kwords SA2-83 - SA2-86 10011XXXXX 128 (4x32) Kwords SA2-87 - SA2-90 10100XXXXX 128 (4x32) Kwords SA2-91 - SA2-94 10101XXXXX 128 (4x32) Kwords SA2-95 - SA2-98 10110XXXXX 128 (4x32) Kwords SA2-99 - SA2-102 10111XXXXX 128 (4x32) Kwords SA2-103 - SA2-106 11000XXXXX 128 (4x32) Kwords SA2-107 - SA2-110 11001XXXXX 128 (4x32) Kwords SA2-111 - SA2-114 11010XXXXX 128 (4x32) Kwords SA2-115 - SA2-118 11011XXXXX 128 (4x32) Kwords SA2-119 - SA2-122 11100XXXXX 128 (4x32) Kwords SA2-123 - SA2-126 11101XXXXX 128 (4x32) Kwords SA2-127 - SA2-130 11110XXXXX 128 (4x32) Kwords SA2-131 - SA2-134 11111XXXXX 128 (4x32) Kwords

February 5, 2004 Am75PDL191CHH/Am75PDL193CHH A D V A N C E I N F O R M A T I O N SECTOR PROTECTION The Am50PDL191CH/Am50PDL193CH features sev- eral levels of sector protection, which can disable both the program and erase operations in certain sectors or sector groups: Persistent Sector Protection A command sector protection method that replaces the old 12 V controlled protection method. Password Sector Protection A highly sophisticated protection method that requires a password before changes to certain sectors or sec- tor groups are permitted. WP# Hardware Protection A write protect pin that can prevent program or erase operations in sectors 0, 1, 268, and 269 in PDL 127 or in SA1-133, SA1-134, SA2-0, SA2-1 in PDL 129. The WP# Hardware Protection feature is always available, regardless of which of the other two methods are cho- sen. Selecting a Sector Protection Mode The device defaults to the Persistent Sector Protection mode. However, to prevents a program or virus from later setting the Password Mode Locking Bit, which would cause an unexpected shift from the default Per- sistent Sector Protection Mode into the Password Pro- tection Mode, it is recommended that either of two one-time programmable non-volatile bits that perma- nently define which sector protection method be set before the device is first programmed. The Persis- tent Sector Protection Mode Locking Bit perma- nently sets the device to the Persistent Sector Protection mode. The Password Mode Locking Bit permanently sets the device to the Password Sector Protection mode. It is not possible to switch between the two protection modes once a locking bit has been set. The device is shipped with all sectors unprotected. AMD offers the option of programming and protecting sectors at the factory prior to shipping the device through AMD’s ExpressFlash™ Service. Contact an AMD representative for details. It is possible to determine whether a sector is pro- tected or unprotected. See Autoselect Command Se- quence for details. Persistent Sector Protection The Persistent Sector Protection method replaces the

12 V controlled protection method in previous AMD

flash devices. This new method provides three differ- ent sector protection states: ■Persistently Locked—The sector is protected and cannot be changed. ■Dynamically Locked—The sector is protected and can be changed by a simple command. ■Unlocked—The sector is unprotected and can be changed by a simple command. To achieve these states, three types of “bits” are used: Persistent Protection Bit (PPB) A single Persistent (non-volatile) Protection Bit is as- signed to a maximum four sectors (see the sector ad- dress tables for specific sector protection groupings). All 4 Kword boot-block sectors have individual sector Persistent Protection Bits (PPBs) for greater flexibility. Each PPB is individually modifiable through the PPB Write Command. The device erases all PPBs in parallel. If any PPB re- quires erasure, the device must be instructed to pre- program all of the sector PPBs prior to PPB erasure. Otherwise, a previously erased sector PPBs can po- tentially be over-erased. The flash device does not have a built-in means of preventing sector PPBs over-erasure. Persistent Protection Bit Lock (PPB Lock) The Persistent Protection Bit Lock (PPB Lock) is a glo- bal volatile bit. When set to “1”, the PPBs cannot be changed. When cleared (“0”), the PPBs are change- able. There is only one PPB Lock bit per device. The PPB Lock is cleared after power-up or hardware reset. There is no command sequence to unlock the PPB Lock. Dynamic Protection Bit (DYB) A volatile protection bit is assigned for each sector. After power-up or hardware reset, the contents of all DYBs is “0”. Each DYB is individually modifiable through the DYB Write Command. When the parts are first shipped, the PPBs are cleared, the DYBs are cleared, and PPB Lock is de- faulted to power up in the cleared state – meaning the PPBs are changeable. When the device is first powered on the DYBs power up cleared (sectors not protected). The Protection State for each sector is determined by the logical OR of the PPB and the DYB related to that sector. For the sectors that have the PPBs cleared, the DYBs control whether or not the sector is protected or unprotected. By issuing the DYB Write command sequences, the DYBs will be set or cleared, thus placing each sector in the protected or unprotected state. These are the so-called Dynamic Locked or Unlocked states. They are called dynamic states because it is very easy to switch back and forth between the protected and un- protected conditions. This allows software to easily protect sectors against inadvertent changes yet does

Am75PDL191CHH/Am75PDL193CHH February 5, 2004 A D V A N C E I N F O R M A T I O N not prevent the easy removal of protection when changes are needed. The DYBs maybe set or cleared as often as needed. The PPBs allow for a more static, and difficult to change, level of protection. The PPBs retain their state across power cycles because they are non-volatile. In- dividual PPBs are set with a command but must all be cleared as a group through a complex sequence of program and erasing commands. The PPBs are also limited to 100 erase cycles. The PPB Lock bit adds an additional level of protec- tion. Once all PPBs are programmed to the desired settings, the PPB Lock may be set to “1”. Setting the PPB Lock disables all program and erase commands to the non-volatile PPBs. In effect, the PPB Lock Bit locks the PPBs into their current state. The only way to clear the PPB Lock is to go through a power cycle. System boot code can determine if any changes to the PPB are needed; for example, to allow new system code to be downloaded. If no changes are needed then the boot code can set the PPB Lock to disable any further changes to the PPBs during system opera- tion. The WP#/ACC write protect pin adds a final level of hardware protection to sectors 0, 1, 268, and 269 in PDL 127 or in SA1-133, SA1-134, SA2-0, SA2-1 in PDL 129. When this pin is low it is not possible to change the contents of these sectors. These sectors generally hold system boot code. The WP#/ACC pin can prevent any changes to the boot code that could override the choices made while setting up sector pro- tection during system initialization. It is possible to have sectors that have been persis- tently locked, and sectors that are left in the dynamic state. The sectors in the dynamic state are all unpro- tected. If there is a need to protect some of them, a simple DYB Write command sequence is all that is necessary. The DYB write command for the dynamic sectors switch the DYBs to signify protected and un- protected, respectively. If there is a need to change the status of the persistently locked sectors, a few more steps are required. First, the PPB Lock bit must be dis- abled by either putting the device through a power-cy- cle, or hardware reset. The PPBs can then be changed to reflect the desired settings. Setting the PPB lock bit once again will lock the PPBs, and the de- vice operates normally again. The best protection is achieved by executing the PPB lock bit set command early in the boot code, and pro- tect the boot code by holding WP#/ACC = VIL. Table 11. Sector Protection Schemes Table 11 contains all possible combinations of the DYB, PPB, and PPB lock relating to the status of the sector. In summary, if the PPB is set, and the PPB lock is set, the sector is protected and the protection can not be removed until the next power cycle clears the PPB lock. If the PPB is cleared, the sector can be dynami- cally locked or unlocked. The DYB then controls whether or not the sector is protected or unprotected. If the user attempts to program or erase a protected sector, the device ignores the command and returns to read mode. A program command to a protected sector enables status polling for approximately 1 µs before the device returns to read mode without having modi- fied the contents of the protected sector. An erase command to a protected sector enables status polling for approximately 50 µs after which the device returns to read mode without having erased the protected sec- tor. The programming of the DYB, PPB, and PPB lock for a given sector can be verified by writing a DYB/PPB/PPB lock verify command to the device. Persistent Sector Protection Mode Locking Bit Like the password mode locking bit, a Persistent Sec- tor Protection mode locking bit exists to guarantee that the device remain in software sector protection. Once set, the Persistent Sector Protection locking bit pre- vents programming of the password protection mode locking bit. This guarantees that a hacker could not place the device in password protection mode. Password Protection Mode The Password Sector Protection Mode method allows an even higher level of security than the Persistent Sector Protection Mode. There are two main differ- DYB PPB PPB Lock Sector State Unprotected—PPB and DYB are changeable Unprotected—PPB not changeable, DYB is changeable Protected—PPB and DYB are changeable Protected—PPB not changeable, DYB is changeable

February 5, 2004 Am75PDL191CHH/Am75PDL193CHH A D V A N C E I N F O R M A T I O N ences between the Persistent Sector Protection and the Password Sector Protection Mode: ■When the device is first powered on, or comes out of a reset cycle, the PPB Lock bit set to the locked state, rather than cleared to the unlocked state. ■The only means to clear the PPB Lock bit is by writ- ing a unique 64-bit Password to the device. The Password Sector Protection method is otherwise identical to the Persistent Sector Protection method. A 64-bit password is the only additional tool utilized in this method. Once the Password Mode Locking Bit is set, the pass- word is permanently set with no means to read, pro- gram, or erase it. The password is used to clear the PPB Lock bit. The Password Unlock command must be written to the flash, along with a password. The flash device internally compares the given password with the pre-programmed password. If they match, the PPB Lock bit is cleared, and the PPBs can be altered. If they do not match, the flash device does nothing. There is a built-in 2 µs delay for each “password check.” This delay is intended to thwart any efforts to run a program that tries all possible combinations in order to crack the password. Password and Password Mode Locking Bit In order to select the Password sector protection scheme, the customer must first program the pass- word. The password may be correlated to the unique Electronic Serial Number (ESN) of the particular flash device. Each ESN is different for every flash device; therefore each password should be different for every flash device. While programming in the password re- gion, the customer may perform Password Verify oper- ations. Once the desired password is programmed in, the customer must then set the Password Mode Locking Bit. This operation achieves two objectives: 1. Permanently sets the device to operate using the Password Protection Mode. It is not possible to re- verse this function. 2. Disables all further commands to the password re- gion. All program, and read operations are ignored. Both of these objectives are important, and if not care- fully considered, may lead to unrecoverable errors. The user must be sure that the Password Protection method is desired when setting the Password Mode Locking Bit. More importantly, the user must be sure that the password is correct when the Password Mode Locking Bit is set. Due to the fact that read operations are disabled, there is no means to verify what the password is afterwards. If the password is lost after setting the Password Mode Locking Bit, there will be no way to clear the PPB Lock bit. The Password Mode Locking Bit, once set, prevents reading the 64-bit password on the DQ bus and further password programming. The Password Mode Locking Bit is not erasable. Once Password Mode Locking Bit is programmed, the Persistent Sector Protection Lock- ing Bit is disabled from programming, guaranteeing that no changes to the protection scheme are allowed. 64-bit Password The 64-bit Password is located in its own memory space and is accessible through the use of the Pass- word Program and Verify commands (see “Password Verify Command”). The password function works in conjunction with the Password Mode Locking Bit, which when set, prevents the Password Verify com- mand from reading the contents of the password on the pins of the device. Write Protect (WP#) The Write Protect feature provides a hardware method of protecting sectors 0, 1, 268, and 269 in PDL 127 or in SA1-133, SA1-134, SA2-0, SA2-1 in PDL 129 with- out using VID. This function is provided by the WP# pin and overrides the previously discussed High Voltage Sector Protection method. If the system asserts VIL on the WP#/ACC pin, the de- vice disables program and erase functions in the two outermost 4 Kword sectors on both ends of the flash array independent of whether it was previously pro- tected or unprotected. If the system asserts VIH on the WP#/ACC pin, the de- vice reverts to whether sectors 0, 1, 268, and 269 in PDL 127 or in SA1-133, SA1-134, SA2-0, SA2-1 in PDL 129 were last set to be protected or unprotected. That is, sector protection or unprotection for these sec- tors depends on whether they were last protected or unprotected using the method described in High Volt- age Sector Protection. Note that the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Persistent Protection Bit Lock The Persistent Protection Bit (PPB) Lock is a volatile bit that reflects the state of the Password Mode Lock- ing Bit after power-up reset. If the Password Mode Lock Bit is also set after a hardware reset (RESET# asserted) or a power-up reset, the ONLY means for clearing the PPB Lock Bit in Password Protection Mode is to issue the Password Unlock command. Suc- cessful execution of the Password Unlock command clears the PPB Lock Bit, allowing for sector PPBs modifications. Asserting RESET#, taking the device through a power-on reset, or issuing the PPB Lock Bit Set command sets the PPB Lock Bit to a “1” when the Password Mode Lock Bit is not set.

Am75PDL191CHH/Am75PDL193CHH February 5, 2004 A D V A N C E I N F O R M A T I O N If the Password Mode Locking Bit is not set, including Persistent Protection Mode, the PPB Lock Bit is cleared after power-up or hardware reset. The PPB Lock Bit is set by issuing the PPB Lock Bit Set com- mand. Once set the only means for clearing the PPB Lock Bit is by issuing a hardware or power-up reset. The Password Unlock command is ignored in Persis- tent Protection Mode. High Voltage Sector Protection Sector protection and unprotection may also be imple- mented using programming equipment. The proce- dure requires high voltage (VID) to be placed on the RESET# pin. Refer to Figure 1 for details on this pro- cedure. Note that for sector unprotect, all unprotected sectors must first be protected prior to the first sector write cycle.

February 5, 2004 Am75PDL191CHH/Am75PDL193CHH A D V A N C E I N F O R M A T I O N Figure 1. In-System Sector Protection/ Sector Unprotection Algorithms Sector Protect: Write 60h to sector address with A7-A0 = 00000010 Set up sector address Wait 100 µs Verify Sector Protect: Write 40h to sector address with A7-A0 = 00000010 Read from sector address with A7-A0 = 00000010 START PLSCNT = 1 RESET# = VID Wait 4 µs First Write Cycle = 60h? Data = 01h? Remove VID from RESET# Write reset command Sector Protect complete Yes Yes No PLSCNT = 25? Yes Device failed Increment PLSCNT Temporary Sector Unprotect Mode No Sector Unprotect: Write 60h to sector address with A7-A0 = 01000010 Set up first sector address Wait 1.2 ms Verify Sector Unprotect: Write 40h to sector address with A7-A0 = 00000010 Read from sector address with A7-A0 = 00000010 START PLSCNT = 1 RESET# = VID Wait 4 µs Data = 00h? Last sector verified? Remove VID from RESET# Write reset command Sector Unprotect complete Yes No PLSCNT = 1000? Yes Device failed Increment PLSCNT Temporary Sector Unprotect Mode No All sectors protected? Yes Protect all sectors: The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address Set up next sector address No Yes No Yes No No Yes No Sector Protect Algorithm Sector Unprotect Algorithm First Write Cycle = 60h? Protect another sector? Reset PLSCNT = 1 Remove VID from RESET# Write reset command Sector Protect complete Remove VID from RESET# Write reset command Sector Unprotect complete

February 5, 2004 Am75PDL191CHH/Am75PDL193CHH A D V A N C E I N F O R M A T I O N Figure 3. SecSi Protection Algorithm START SecSiTM Sector Entry Write AAh to address 555h Write 55h to address 2AAh Write 88h to address 555h SecSi Sector Protection Entry Write AAh to address 555h Write 55h to address 2AAh Write 60h to address 555h PLSCNT = 1 Protect SecSi Sector: write 68h to sector address with A7–A0 = 00011010 Time out 256 µs Read from sector address (SA0 + 1Ah) Data = 01h? Yes Yes SecSi Sector Protection Completed SecSi Sector Exit Write 555h/AAh Write 2AAh/55h Write SA0+555h/90h Write XXXh/00h Verify SecSi Sector: write 48h to sector address with A7–A0 = 00011010 Increment PLSCNT PLSCNT = 25? Device Failed SecSi Sector Entry SecSi Sector Protection SecSi Sector Exit No No

Am75PDL191CHH/Am75PDL193CHH February 5, 2004 A D V A N C E I N F O R M A T I O N Once the SecSi Sector is locked and verified, the sys- tem must write the Exit SecSi Sector Region com- mand sequence to return to reading and writing the remainder of the array. The SecSi Sector lock must be used with caution since, once locked, there is no procedure available for unlocking the SecSi Sector area and none of the bits in the SecSi Sector memory space can be modified in any way. SecSi Sector Protection Bits The SecSi Sector Protection Bits prevent program- ming of the SecSi Sector memory area. Once set, the SecSi Sector memory area contents are non-modifi- able. Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes. In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise. Low VCC Write Inhibit When VCC is less than VLKO, the device does not ac- cept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to the read mode. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO. Write Pulse “Glitch” Protection Noise pulses of less than 3 ns (typical) on OE#, CE#f1, CE#f2 or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE#f1 =CE#f2 = VIH or WE# = VIH. To initiate a write cycle, CE#f1/CE#f2 and WE# must be a logical zero while OE# is a logical one. Power-Up Write Inhibit If WE# = CE#f1 = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automati- cally reset to the read mode on power-up. COMMON FLASH MEMORY INTERFACE (CFI) The Common Flash Interface (CFI) specification out- lines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-inde- pendent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the sys- tem writes the CFI Query command, 98h, to address 55h, any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 12–15. To terminate reading CFI data, the system must write the reset command. The CFI Query mode is not accessible when the device is exe- cuting an Embedded Program or embedded Erase al- gorithm. The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Tables 12–15. The system must write the reset command to return the device to reading array data. For further information, please refer to the CFI Specifi- cation and CFI Publication 100, available via the World Wide Web at http://www.amd.com/flash/cfi. Alterna- tively, contact an AMD representative for copies of these documents.

February 5, 2004 Am75PDL191CHH/Am75PDL193CHH A D V A N C E I N F O R M A T I O N Table 12. CFI Query Identification String Table 13. System Interface String Addresses Data

Description

Query Unique ASCII string “QRY” 13h 14h 0002h 0000h Primary OEM Command Set 15h 16h 0040h 0000h Address for Primary Extended Table 17h 18h 0000h 0000h Alternate OEM Command Set (00h = none exists) 19h 1Ah 0000h 0000h Address for Alternate OEM Extended Table (00h = none exists) Addresses Data VCC Min. (write/erase) D7–D4: volt, D3–D0: 100 millivolt 1Ch 0036h VCC Max. (write/erase) D7–D4: volt, D3–D0: 100 millivolt 1Dh 0000h VPP Min. voltage (00h = no VPP pin present) 1Eh 0000h VPP Max. voltage (00h = no VPP pin present) 1Fh 0004h Typical timeout per single byte/word write 2 N µs 20h 0000h Typical timeout for Min. size buffer write 2 N µs (00h = not supported) 21h 0009h Typical timeout per individual block erase 2 N ms 22h 0000h Typical timeout for full chip erase 2 N ms (00h = not supported) 23h 0005h Max. timeout for byte/word write 2 N times typical 24h 0000h Max. timeout for buffer write 2 N times typical 25h 0004h Max. timeout per individual block erase 2 N times typical 26h 0000h Max. timeout for full chip erase 2 N times typical (00h = not supported)

Am75PDL191CHH/Am75PDL193CHH February 5, 2004 A D V A N C E I N F O R M A T I O N Table 14. Device Geometry Definition Addresses Data Device Size = 2 N byte 28h 29h 0001h 0000h Flash Device Interface description (refer to CFI publication 100) 2Ah 2Bh 0000h 0000h Max. number of byte in multi-byte write = 2 N (00h = not supported) 2Ch 0003h Number of Erase Block Regions within device 2Dh 2Eh 2Fh 30h 0007h 0000h 0020h 0000h Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100) 31h 32h 33h 34h 00FDh 0000h 0000h 0001h Erase Block Region 2 Information (refer to the CFI specification or CFI publication 100) 35h 36h 37h 38h 0007h 0000h 0020h 0000h Erase Block Region 3 Information (refer to the CFI specification or CFI publication 100) 39h 3Ah 3Bh 3Ch 0000h 0000h 0000h 0000h Erase Block Region 4 Information (refer to the CFI specification or CFI publication 100)

February 5, 2004 Am75PDL191CHH/Am75PDL193CHH A D V A N C E I N F O R M A T I O N Table 15. Primary Vendor-Specific Extended Query Addresses Data Query-unique ASCII string “PRI” 43h 0031h Major version number, ASCII (reflects modifications to the silicon) 44h 0033h Minor version number, ASCII (reflects modifications to the CFI table) 45h 000Ch Address Sensitive Unlock (Bits 1-0) 0 = Required, 1 = Not Required Silicon Revision Number (Bits 7-2) 46h 0002h Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write 47h 0001h Sector Protect 0 = Not Supported, X = Number of sectors in per group 48h 0001h Sector Temporary Unprotect 00 = Not Supported, 01 = Supported 49h 0007h Sector Protect/Unprotect scheme 01 =29F040 mode, 02 = 29F016 mode, 03 = 29F400, 04 = 29LV800 mode 4Ah 00E7h Simultaneous Operation 00 = Not Supported, X = Number of Sectors excluding Bank 1 4Bh 0000h Burst Mode Type 00 = Not Supported, 01 = Supported 4Ch 0002h Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page 4Dh 0085h ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV 4Eh 0095h ACC (Acceleration) Supply Maximum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV 4Fh 0001h Top/Bottom Boot Sector Flag 00h = Uniform device, 02h = Bottom Boot Device, 03h = Top Boot Device, 04h = Both Top and Bottom 50h 0001h Program Suspend 0 = Not supported, 1 = Supported 57h 0004h Bank Organization 00 = Data at 4Ah is zero, X = Number of Banks 58h 0027h Bank 1 Region Information X = Number of Sectors in Bank 1 59h 0060h Bank 2 Region Information X = Number of Sectors in Bank 2 5Ah 0060h Bank 3 Region Information X = Number of Sectors in Bank 3 5Bh 0027h Bank 4 Region Information X = Number of Sectors in Bank 4

Am75PDL191CHH/Am75PDL193CHH February 5, 2004 A D V A N C E I N F O R M A T I O N COMMAND DEFINITIONS Writing specific address and data commands or se- quences into the command register initiates device op- erations. Table 16 defines the valid register command sequences. Writing incorrect address and data val- ues or writing them in the improper sequence may place the device in an unknown state. A reset com- mand is then required to return the device to reading array data. All addresses are latched on the falling edge of WE# or CE#f1/CE#f2 (PDL129H only), whichever happens later. All data is latched on the rising edge of WE# or CE#f1/CE#f2 (PDL129H only), whichever happens first. Refer to the AC Characteristics section for timing diagrams. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. Each bank is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the corresponding bank enters the erase-sus- pend-read mode, after which the system can read data from any non-erase-suspended sector within the same bank. The system can read array data using the standard read timing, except that if it reads at an ad- dress within erase-suspended sectors, the device out- puts status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same excep- tion. See the Erase Suspend/Erase Resume Com- mands section for more information. The system must issue the reset command to return a bank to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase opera- tion, or if the bank is in the autoselect mode. See the next section, Reset Command, for more information. See also Requirements for Reading Array Data in the MCP Device Bus Operations section for more informa- tion. The Read-Only Operations – Am29PDL127H and Read-Only Operations – Am29PDL127H tables pro- vide the read parameters, and Figure 13 shows the timing diagram. Reset Command Writing the reset command resets the banks to the read or erase-suspend-read mode. Address bits are don’t cares for this command. The reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. This resets the bank to which the sys- tem was writing to the read mode. Once erasure be- gins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the bank to which the system was writing to the read mode. If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset command returns that bank to the erase-sus- pend-read mode. Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the se- quence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If a bank entered the autoselect mode while in the Erase Sus- pend mode, writing the reset command returns that bank to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the banks to the read mode (or erase-suspend-read mode if that bank was in Erase Suspend). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. The autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the device is actively pro- gramming or erasing in the other bank. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the bank address and the au- toselect command. The bank then enters the autose- lect mode. The system may read any number of autoselect codes without reinitiating the command se- quence. Table 16 shows the address and data requirements. To determine sector protection information, the system must write to the appropriate bank address (BA) and sector address (SA). Table 4 shows the address range and bank number associated with each sector. The system must write the reset command to return to the read mode (or erase-suspend-read mode if the bank was previously in Erase Suspend).

February 5, 2004 Am75PDL191CHH/Am75PDL193CHH A D V A N C E I N F O R M A T I O N Enter SecSi™ Sector/Exit SecSi Sector Command Sequence The SecSi Sector region provides a secured data area containing a random, eight word electronic serial num- ber (ESN). The system can access the SecSi Sector region by issuing the three-cycle Enter SecSi Sector command sequence. The device continues to access the SecSi Sector region until the system issues the four-cycle Exit SecSi Sector command sequence. The Exit SecSi Sector command sequence returns the de- vice to normal operation. The SecSi Sector is not ac- cessible when the device is executing an Embedded Program or embedded Erase algorithm. Table 16 shows the address and data requirements for both command sequences. See also “SecSi™ (Secured Sili- con) Sector Flash Memory Region” for further informa- tion. Note that the ACC function and unlock bypass modes are not available when the SecSi Sector is en- abled. Word Program Command Sequence Programming is a four-bus-cycle operation. The pro- gram command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program al- gorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Table 16 shows the address and data requirements for the program command se- quence. When the Embedded Program algorithm is complete, that bank then returns to the read mode and ad- dresses are no longer latched. The system can deter- mine the status of the program operation by using DQ7, DQ6, or RY/BY#. Refer to the Write Operation Status section for information on these status bits. Any commands written to the device during the Em- bedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program operation. Note that the SecSi sector, autoselect, and CFI functions are unavailable when the SecSi Sector is enabled. The program command sequence should be reinitiated once that bank has returned to the read mode, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from “0” back to a “1.” Attempting to do so may cause that bank to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was success- ful. However, a succeeding read will show that the data is still “0.” Only erase operations can convert a “0” to a “1.” Unlock Bypass Command Sequence The unlock bypass feature allows the system to pro- gram data to a bank faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two un- lock cycles. This is followed by a third write cycle con- taining the unlock bypass command, 20h. That bank then enters the unlock bypass mode. A two-cycle un- lock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program com- mand, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total program- ming time. Table 16 shows the requirements for the command sequence. During the unlock bypass mode, only the Unlock By- pass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset com- mand sequence. The device offers accelerated program operations through the WP#/ACC pin. When the system asserts VHH on the WP#/ACC pin, the device automatically en- ters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program command sequence. The device uses the higher voltage on the WP#/ACC pin to accelerate the operation. Note that the WP#/ACC pin must not be at VHH any operation other than accelerated programming, or device dam- age may result. In addition, the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Figure 4 illustrates the algorithm for the program oper- ation. Refer to the Erase and Program Operations table in the AC Characteristics section for parameters, and Figures 16 and 17 for timing diagrams.

Am75PDL191CHH/Am75PDL193CHH February 5, 2004 A D V A N C E I N F O R M A T I O N of the password when programming. There are no pro- visions for entering the 2-cycle unlock cycle, the pass- word program command, and all the password data. There is no special addressing order required for pro- gramming the password. Also, when the password is undergoing programming, Simultaneous Operation is disabled. Read operations to any memory location will return the programming status. Once programming is complete, the user must issue a Read/Reset com- mand to return the device to normal operation. Once the Password is written and verified, the Password Mode Locking Bit must be set in order to prevent verifi- cation. The Password Program Command is only ca- pable of programming “0”s. Programming a “1” after a cell is programmed as a “0” results in a time-out by the Embedded Program Algorithm™ with the cell remain- ing as a “0”. The password is all ones when shipped from the factory. All 64-bit password combinations are valid as a password. Password Verify Command The Password Verify Command is used to verify the Password. The Password is verifiable only when the Password Mode Locking Bit is not programmed. If the Password Mode Locking Bit is programmed and the user attempts to verify the Password, the device will al- ways drive all F’s onto the DQ data bus. The Password Verify command is permitted if the SecSi sector is enabled. Also, the device will not oper- ate in Simultaneous Operation when the Password Verify command is executed. Only the password is re- turned regardless of the bank address. The lower two address bits (A1-A0) are valid during the Password Verify. Writing the Read/Reset command returns the device back to normal operation. Password Protection Mode Locking Bit Program Command The Password Protection Mode Locking Bit Program Command programs the Password Protection Mode Locking Bit, which prevents further verifies or updates to the Password. Once programmed, the Password Protection Mode Locking Bit cannot be erased! If the Password Protection Mode Locking Bit is verified as program without margin, the Password Protection Mode Locking Bit Program command can be executed to improve the program margin. Once the Password Protection Mode Locking Bit is programmed, the Per- sistent Sector Protection Locking Bit program circuitry is disabled, thereby forcing the device to remain in the Password Protection mode. Exiting the Mode Locking Bit Program command is accomplished by writing the Read/Reset command. Persistent Sector Protection Mode Locking Bit Program Command The Persistent Sector Protection Mode Locking Bit Program Command programs the Persistent Sector Protection Mode Locking Bit, which prevents the Pass- word Mode Locking Bit from ever being programmed. If the Persistent Sector Protection Mode Locking Bit is verified as programmed without margin, the Persistent Sector Protection Mode Locking Bit Program Com- mand should be reissued to improve program margin. By disabling the program circuitry of the Password Mode Locking Bit, the device is forced to remain in the Persistent Sector Protection mode of operation, once this bit is set. Exiting the Persistent Protection Mode Locking Bit Program command is accomplished by writing the Read/Reset command. SecSi Sector Protection Bit Program Command The SecSi Sector Protection Bit Program Command programs the SecSi Sector Protection Bit, which pre- vents the SecSi sector memory from being cleared. If the SecSi Sector Protection Bit is verified as pro- grammed without margin, the SecSi Sector Protection Bit Program Command should be reissued to improve program margin. Exiting the VCC-level SecSi Sector Protection Bit Program Command is accomplished by writing the Read/Reset command. PPB Lock Bit Set Command The PPB Lock Bit Set command is used to set the PPB Lock bit if it is cleared either at reset or if the Password Unlock command was successfully exe- cuted. There is no PPB Lock Bit Clear command. Once the PPB Lock Bit is set, it cannot be cleared un- less the device is taken through a power-on clear or the Password Unlock command is executed. Upon set- ting the PPB Lock Bit, the PPBs are latched into the DYBs. If the Password Mode Locking Bit is set, the PPB Lock Bit status is reflected as set, even after a power-on reset cycle. Exiting the PPB Lock Bit Set command is accomplished by writing the Read/Reset command (only in the Persistent Protection Mode). DYB Write Command The DYB Write command is used to set or clear a DYB for a given sector. The high order address bits A22-A12 for PDL127 and (A21–A12) for PDL129H are issued at the same time as the code 01h or 00h on DQ7-DQ0. All other DQ data bus pins are ignored dur- ing the data write cycle. The DYBs are modifiable at any time, regardless of the state of the PPB or PPB Lock Bit. The DYBs are cleared at power-up or hard- ware reset. Exiting the DYB Write command is accom- plished by writing the Read/Reset command.

February 5, 2004 Am75PDL191CHH/Am75PDL193CHH A D V A N C E I N F O R M A T I O N Password Unlock Command The Password Unlock command is used to clear the PPB Lock Bit so that the PPBs can be unlocked for modification, thereby allowing the PPBs to become ac- cessible for modification. The exact password must be entered in order for the unlocking function to occur. This command cannot be issued any faster than 2 µs at a time to prevent a hacker from running through all 64-bit combinations in an attempt to correctly match a password. If the command is issued before the 2 µs execution window for each portion of the unlock, the command will be ignored. Once the Password Unlock command is entered, the RY/BY# indicates that the device is busy. Approxi- mately 1 µs is required for each portion of the unlock. Once the first portion of the password unlock com- pletes (RY/BY# is not low or DQ6 does not toggle when read), the next part of the password is written. The system must thus monitor RY/BY# or the status bits to confirm when to write the next portion of the password. Seven cycles are required to successfully clear the PPB Lock Bit. PPB Program Command The PPB Program command is used to program, or set, a given PPB. Each PPB is individually pro- grammed (but is bulk erased with the other PPBs). The specific sector address (A21–A12) are written at the same time as the program command 60h with A6 = 0. If the PPB Lock Bit is set and the corresponding PPB is set for the sector, the PPB Program command will not execute and the command will time-out without programming the PPB. After programming a PPB, two additional cycles are needed to determine whether the PPB has been pro- grammed with margin. If the PPB has been pro- grammed without margin, the program command should be reissued to improve the program margin. Also note that the total number of PPB program/erase cycles is limited to 100 cycles. Cycling the PPBs be- yond 100 cycles is not guaranteed. The PPB Program command does not follow the Em- bedded Program algorithm. All PPB Erase Command The All PPB Erase command is used to erase all PPBs in bulk. There is no means for individually eras- ing a specific PPB. Unlike the PPB program, no spe- cific sector address is required. However, when the PPB erase command is written all Sector PPBs are erased in parallel. If the PPB Lock Bit is set the ALL PPB Erase command will not execute and the com- mand will time-out without erasing the PPBs. After erasing the PPBs, two additional cycles are needed to determine whether the PPB has been erased with margin. If the PPBs has been erased without margin, the erase command should be reissued to improve the program margin. It is the responsibility of the user to preprogram all PPBs prior to issuing the All PPB Erase command. If the user attempts to erase a cleared PPB, over-era- sure may occur making it difficult to program the PPB at a later time. Also note that the total number of PPB program/erase cycles is limited to 100 cycles. Cycling the PPBs beyond 100 cycles is not guaranteed. DYB Write Command The DYB Write command is used for setting the DYB, which is a volatile bit that is cleared at reset. There is one DYB per sector. If the PPB is set, the sector is pro- tected regardless of the value of the DYB. If the PPB is cleared, setting the DYB to a 1 protects the sector from programs or erases. Since this is a volatile bit, remov- ing power or resetting the device will clear the DYBs. The bank address is latched when the command is written. PPB Lock Bit Set Command The PPB Lock Bit set command is used for setting the DYB, which is a volatile bit that is cleared at reset. There is one DYB per sector. If the PPB is set, the sec- tor is protected regardless of the value of the DYB. If the PPB is cleared, setting the DYB to a 1 protects the sector from programs or erases. Since this is a volatile bit, removing power or resetting the device will clear the DYBs. The bank address is latched when the com- mand is written. PPB Status Command The programming of the PPB for a given sector can be verified by writing a PPB status verify command to the device. PPB Lock Bit Status Command The programming of the PPB Lock Bit for a given sec- tor can be verified by writing a PPB Lock Bit status ver- ify command to the device. Sector Protection Status Command The programming of either the PPB or DYB for a given sector or sector group can be verified by writing a Sec- tor Protection Status command to the device. Note that there is no single command to independently verify the programming of a DYB for a given sector group.

Am75PDL191CHH/Am75PDL193CHH February 5, 2004 A D V A N C E I N F O R M A T I O N Command Definitions Tables Legend: BA = Address of bank switching to autoselect mode, bypass mode, or erase operation. Determined by A22:A20, (A21:A20 for PDL129) see Tables 4 and 5 for more detail. PA = Program Address (A22:A0) (A21:A0 for PDL129). Addresses latch on falling edge of WE# or CE#f1/CE#f2 (PDL129 only) pulse, whichever happens later. PD = Program Data (DQ15:DQ0) written to location PA. Data latches on rising edge of WE# or CE#f1/CE#f2 (PDL129 only) pulse, whichever happens first. RA = Read Address (A22:A0) (A21:A0 for PDL129). RD = Read Data (DQ15:DQ0) from location RA. SA = Sector Address (A22:A12) (A21:A12 for PDL129) for verifying (in autoselect mode) or erasing. WD = Write Data. See “Configuration Register” definition for specific write data. Data latched on rising edge of WE#. X = Don’t care Notes: See Table 1 for description of bus operations. All values are in hexadecimal. Shaded cells in table denote read cycles. All other cycles are write operations. During unlock and command cycles, when lower address bits are 555 or 2AAh as shown in table, address bits higher than A11 (except where BA is required) and data bits higher than DQ7 are don’t cares. No unlock or command cycles required when bank is reading array data. The Reset command is required to return to reading array (or to erase-suspend-read mode if previously in Erase Suspend) when bank is in autoselect mode, or if DQ5 goes high (while bank is providing status information). Fourth cycle of autoselect command sequence is a read cycle. System must provide bank address to obtain manufacturer ID or device ID information. See Autoselect Command Sequence section for more information. The data is C0h for factory or customer locked and 80h for factory locked. The data is 00h for an unprotected sector group and 01h for a protected sector group. 10. Device ID must be read across cycles 4, 5, and 6. 20 for Am29PDL127H and 21 for Am29PDL129H. 11. System may read and program in non-erasing sectors, or enter autoselect mode, when in Program/Erase Suspend mode. Program/Erase Suspend command is valid only during a sector erase operation, and requires bank address. 12. Program/Erase Resume command is valid only during Erase Suspend mode, and requires bank address. 13. Command is valid when device is ready to read array data or when device is in autoselect mode. 14. WP#/ACC must be at VID during the entire operation of command. 15. Unlock Bypass Entry command is required prior to any Unlock Bypass operation. Unlock Bypass Reset command is required to return to the reading array. Table 16. Memory Array Command Definitions Command (Notes) Cycles Bus Cycles (Notes 1–4) Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Read (5) RA RD Reset (6) XXX Autoselect (Note 7) Manufacturer ID 555 AA 2AA 555 (BA)X00 Device ID (10) 555 AA 2AA 555 (BA)X01 (BA)X0E (Note 10) (BA)X0F SecSi Sector Factory Protect (8) 555 AA 2AA 555 X03 (see note 8) Sector Group Protect Verify (9) 555 AAA 2AA 555 (SA)X02 XX00/ XX01 Program 555 AA 2AA 555 PA PD Chip Erase 555 AA 2AA 555 555 AA 2AA 555 Sector Erase 555 AA 2AA 555 555 AA 2AA SA Program/Erase Suspend (11) BA Program/Erase Resume (12) BA CFI Query (13) Accelerated Program (15) XX PA PD Unlock Bypass Entry (15) 555 AA 2AA 555 Unlock Bypass Program (15) XX PA PD Unlock Bypass Erase (15) XX XX Unlock Bypass CFI (13, 15) XX Unlock Bypass Reset (15) XXX XXX

February 5, 2004 Am75PDL191CHH/Am75PDL193CHH A D V A N C E I N F O R M A T I O N Legend: DYB = Dynamic Protection Bit OW = Address (A7:A0) is (00011010) PD[3:0] = Password Data (1 of 4 portions) PPB = Persistent Protection Bit PWA = Password Address. A1:A0 selects portion of password. PWD = Password Data being verified. PL = Password Protection Mode Lock Address (A7:A0) is (00001010) RD(0) = Read Data DQ0 for protection indicator bit. RD(1) = Read Data DQ1 for PPB Lock status. SA = Sector Address where security command applies. Address bits A21:A12 uniquely select any sector. SL = Persistent Protection Mode Lock Address (A7:A0) is (00010010) WP = PPB Address (A7:A0) is (00000010) (NoteTable.16 31096a1.fm) X = Don’t care PPMLB = Password Protection Mode Locking Bit SPMLB = Persistent Protection Mode Locking Bit See Table 1 for description of bus operations. All values are in hexadecimal. Shaded cells in table denote read cycles. All other cycles are write operations. During unlock and command cycles, when lower address bits are 555 or 2AAh as shown in table, address bits higher than A11 (except where BA is required) and data bits higher than DQ7 are don’t cares. The reset command returns device to reading array. Cycle 4 programs the addressed locking bit. Cycles 5 and 6 validate bit has been fully programmed when DQ0 = 1. If DQ0 = 0 in cycle 6, program command must be issued and verified again. Data is latched on the rising edge of WE#. Entire command sequence must be entered for each portion of password. Command sequence returns FFh if PPMLB is set. 10. The password is written over four consecutive cycles, at addresses 0-3. 11. A 2 µs timeout is required between any two portions of password. 12. A 100 µs timeout is required between cycles 4 and 5. 13. A 1.2 ms timeout is required between cycles 4 and 5. 14. Cycle 4 erases all PPBs. Cycles 5 and 6 validate bits have been fully erased when DQ0 = 0. If DQ0 = 1 in cycle 6, erase command must be issued and verified again. Before issuing erase command, all PPBs should be programmed to prevent PPB overerasure. 15. DQ1 = 1 if PPB locked, 0 if unlocked. 16. For PDL128G and PDL640G, the WP address is 0111010. The EP address (PPB Erase Address) is 1111010. 17. Following the final cycle of the command sequence, the user must write the first three cycles of the Autoselect command and then write a Reset command. 18. If checking the DYB status of sectors in multiple banks, the user must follow Note 17 before crossing a bank boundary. Table 17. Sector Protection Command Definitions Command (Notes) Cycles Bus Cycles (Notes 1-4) Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Reset XXX SecSi Sector Entry 3 555 AA 2AA 555 SecSi Sector Exit 555 AA 2AA 555 XX SecSi Protection Bit Program (5, 6) 555 AA 2AA 555 OW OW OW RD(0) SecSi Protection Bit Status 555 AA 2AA 555 OW OW RD(0) Password Program (5, 7, 8) 555 AA 2AA 555 XX[0-3] PD[0-3] Password Verify (6, 8, 9) 555 AA 2AA 555 PWA[0-3] PWD[0-3] Password Unlock (7, 10, 11) 555 AA 2AA 555 PWA[0] PWD[0] PWA[1] PWD[1] PWA[2] PWD[2] PWA[3] PWD[3] PPB Program (5, 6, 12, 17) 555 AA 2AA 555 (SA)WP (SA)WP (SA)WP RD(0) PPB Status 555 AA 2AA 555 (SA)WP (SA)WP RD (0) All PPB Erase (5, 6, 13, 14) 555 AA 2AA 555 WP (SA) (SA)WP RD(0) PPB Lock Bit Set (17) 555 AA 2AA 555 PPB Lock Bit Status (15) 555 AA 2AA 555 SA RD(1) DYB Write (7) 555 AA 2AA 555 SA DYB Erase (7) 555 AA 2AA 555 SA DYB Status (6, 18) 555 AA 2AA 555 SA RD(0) PPMLB Program (5, 6, 12) 555 AA 2AA 555 PL PL PL RD(0) PPMLB Status (5) 555 AA 2AA 555 PL PL RD(0) SPMLB Program (5, 6, 12) 555 AA 2AA 555 SL SL SL RD(0) SPMLB Status (5) 555 AA 2AA 555 SL SL RD(0)

February 5, 2004 Am75PDL191CHH/Am75PDL193CHH A D V A N C E I N F O R M A T I O N Table 18. Write Operation Status Notes: 1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to the section on DQ5 for more information. 2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm is in progress. The device outputs array data if the system addresses a non-busy bank. Status DQ7 (Note 2) DQ6 DQ5 (Note 1) DQ3 DQ2 (Note 2) RY/BY# Standard Mode Embedded Program Algorithm DQ7# Toggle N/A No toggle Embedded Erase Algorithm Toggle Toggle Erase Suspend Mode Erase-Suspend- Read Erase Suspended Sector No toggle N/A Toggle Non-Erase Suspended Sector Data Data Data Data Data Erase-Suspend-Program DQ7# Toggle N/A N/A

February 5, 2004 Am75PDL191CHH/Am75PDL193CHH A D V A N C E I N F O R M A T I O N

Am75PDL191CHH/Am75PDL193CHH February 5, 2004 A D V A N C E I N F O R M A T I O N DC CHARACTERISTICS CMOS Compatible Notes: Valid CE#f1/CE#f2 conditions (PDL129 only): (CE#f1= VIL, CE#f2= VIH) or (CE#f1= VIH, CE#f2= VIL) The ICC current listed is typically less than 5 mA/MHz, with OE# at VIH. Maximum ICC specifications are tested with VCC = VCCmax. ICC active while Embedded Erase or Embedded Program is in progress. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 150 ns. Typical sleep mode current is 1 µA. Not 100% tested. Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit ILI Input Load Current VIN = VSS to VCC, VCC = VCC max ±1.0 µA ILIT A9, OE#, RESET# Input Load Current VCC = VCC max; VID= 12.5 V µA ILR Reset Leakage Current VCC = VCC max; VID= 12.5 V µA ILO Output Leakage Current VOUT = VSS to VCC, OE# = VIH VCC = VCC max ±1.0 µA ICC1 VCC Active Read Current (Notes Table.1 31096a1.fm, 2, 3) OE# = VIH, VCC = VCC max (Note 1)

5 MHz

10 MHz

VCC Active Write Current (Notes Table.1 31096a1.fm, 3, 4) OE# = VIH, WE# = VIL mA ICC3 VCC Standby Current (Note 3) CE#f1, CE#f2 (PDL129 only), RESET#, WP/ACC# = VIO ± 0.3 V µA ICC4 VCC Reset Current (Note 3) RESET# = VSS ± 0.3 V, CE# = VSS µA ICC5 Automatic Sleep Mode (Notes 3, 5) VIH = VIO ± 0.3 V; VIL = VSS ± 0.3 V, CE# = VSS µA ICC6 VCC Active Read-While-Program Current (Notes 1, 2, 3) OE# = VIH Word mA ICC7 VCC Active Read-While-Erase Current (Notes 1, 2, 3) OE# = VIH Word mA ICC8 VCC Active Program-While-Erase- Suspended Current (Notes 1, 3, 6) OE# = VIH mA VIL Input Low Voltage VIO = 2.7–3.6 V –0.5 0.8 V VIH Input High Voltage VIO = 2.7–3.6 V 2.0 VCC+0.3 V VHH Voltage for ACC Program Acceleration VCC = 3.0 V ± 10% 8.5 9.5 V VID Voltage for Autoselect and Temporary Sector Unprotect VCC = 3.0 V ± 10% 11.5 12.5 V VOL Output Low Voltage IOL = 2.0 mA, VCC = VCC min 0.4 V VOH Output High Voltage IOH = –2.0 mA, VCC = VCC min 2.4 V VLKO Low VCC Lock-Out Voltage (Note 6) 2.3 2.5 V

February 5, 2004 Am75PDL191CHH/Am75PDL193CHH A D V A N C E I N F O R M A T I O N TEST CONDITIONS Table 19. Test Specifications KEY TO SWITCHING WAVEFORMS 2.7 kΩ CL 6.2 kΩ 3.3 V Device Under Test Note: Diodes are IN3064 or equivalent Figure 10. Test Setup Test Condition Unit Output Load

1 TTL gate

Output Load Capacitance, CL (including jig capacitance) pF Input Rise and Fall Times ns Input Pulse Levels 0.0–3.0 V Input timing measurement reference levels 1.5 V Output timing measurement reference levels 1.5 V KS000010-PAL WAVEFORM INPUTS OUTPUTS Steady Changing from H to L Changing from L to H Don’t Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is High Impedance State (High Z) 3.0 V 0.0 V 1.5 V 1.5 V Output Measurement Level Input Figure 11. Input Waveforms and Measurement Levels

Am75PDL191CHH/Am75PDL193CHH February 5, 2004 A D V A N C E I N F O R M A T I O N pSRAM AC CHARACTERISTICS CE#1ps Timing Figure 12. Timing Diagram for Alternating Between Pseudo SRAM and Flash Parameter CE#1ps Recover Time Min ns CE#1ps tCCR tCCR CE2ps

February 5, 2004 Am75PDL191CHH/Am75PDL193CHH A D V A N C E I N F O R M A T I O N AC CHARACTERISTICS Read-Only Operations – Am29PDL127H Notes: Not 100% tested. See Figure 10 and Table 19 for test specifications Measurements performed by placing a 50 ohm termination on the data pin with a bias of VCC/2. The time from OE# high to the data bus driven to VCC/2 is taken as tDF. Read-Only Operations – Am29PDL129H Notes: Not 100% tested. See Figure 10 and Table 19 for test specifications Valid CE#f1/CE#f2 conditions: (CE#f1= VIL, CE#f2= VIH) or (CE#f1= VIH, CE#f2=VIL). Valid CE#f1/CE#f2 transitions: (CE#f1= CE#f2= VIH) to (CE#f1= VIL, CE#f2=VIH) or (CE#f1= VIH, CE#f2=VIL). Measurements performed by placing a 50 ohm termination on the data pin with a bias of VCC/2. The time from OE# high to the data bus driven to VCC/2 is taken as tDF. Valid CE#f1/CE#f2 transitions: (CE#f1= VIL, CE#f2= VIH) or (CE#f1= VIH, CE#f2=VIL) to (CE#f1= CE#f2= VIH). Parameter Std. Unit tAVAV tRC Read Cycle Time (Note 1) Min ns tAVQV tACC Address to Output Delay CE#f1, OE# = VIL Max ns tELQV tCE Chip Enable to Output Delay OE# = VIL Max ns tPACC Page Access Time Max ns tGLQV tOE Output Enable to Output Delay Max ns tEHQZ tDF Chip Enable to Output High Z (Note 1, 3) Max ns tGHQZ tDF Output Enable to Output High Z (Notes 1, 3) Max ns tAXQX tOH Output Hold Time From Addresses, CE#f1 or OE#, Whichever Occurs First (Notes 3) Min ns tOEH Output Enable Hold Time (Note 1) Read Min ns Toggle and Data# Polling Min ns Parameter Std. Unit tAVAV tRC Read Cycle Time (Note 1) Min ns tAVQV tACC Address to Output Delay (Note 3) CE#f1, OE# = VIL Max ns tELQV tCE Chip Enable to Output Delay (Note 4) OE# = VIL Max ns tPACC Page Access Time Max ns tGLQV tOE Output Enable to Output Delay Max ns tEHQZ tDF Chip Enable to Output High Z (Notes 1, 5, 6) Max ns tGHQZ tDF Output Enable to Output High Z (Notes 1, 5) Max ns tAXQX tOH Output Hold Time From Addresses, CE#f1/CE#f2 or OE#, Whichever Occurs First (Notes 5, 6) Min ns tOEH Output Enable Hold Time (Note 1) Read Min ns Toggle and Data# Polling Min ns

February 5, 2004 Am75PDL191CHH/Am75PDL193CHH A D V A N C E I N F O R M A T I O N AC CHARACTERISTICS Hardware Reset (RESET#) Note: Not 100% tested. Parameter RESET# Pin Low (During Embedded Algorithms) to Read Mode (See Note) Max µs tReady RESET# Pin Low (NOT During Embedded Algorithms) to Read Mode (See Note) Max 500 ns tRP RESET# Pulse Width Min 500 ns tRH Reset High Time Before Read (See Note) Min ns tRPD RESET# Low to Standby Mode Min µs tRB RY/BY# Recovery Time Min ns RESET# RY/BY# RY/BY#1 tRP tReady Reset Timings NOT during Embedded Algorithms tReady CE#f1, CE#f2 (PDL129 only), OE# tRH CE#f1, CE#f2 (PDL129 only), OE# Reset Timings during Embedded Algorithms RESET# tRP tRB Figure 15. Reset Timings

Am75PDL191CHH/Am75PDL193CHH February 5, 2004 A D V A N C E I N F O R M A T I O N AC CHARACTERISTICS Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Flash Erase And Programming Performance” section for more information. Parameter All Speeds JEDEC Std Write Cycle Time (Note 1) Min ns tAVWL tAS Address Setup Time Min ns tASO Address Setup Time to OE# low during toggle bit polling Min ns tWLAX tAH Address Hold Time Min ns tAHT Address Hold Time From CE#1f or OE# high during toggle bit polling Min ns tDVWH tDS Data Setup Time Min ns tWHDX tDH Data Hold Time Min ns tOEPH Output Enable High during toggle bit polling Min ns tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) Min ns tWLEL tWS WE# Setup Time (CE#f1 to WE#) Min ns tELWL tCS CE#f1 Setup Time Min ns tEHWH tWH WE# Hold Time (CE#f1 to WE#) Min ns tWHEH tCH CE#f1 Hold Time Min ns tWLWH tWP Write Pulse Width Min ns tWHDL tWPH Write Pulse Width High Min ns tSR/W Latency Between Read and Write Operations Min ns tWHWH1 tWHWH1 Programming Operation (Note 2) Word Typ µs tWHWH1 tWHWH1 Accelerated Programming Operation, Word or Byte (Note 2) Typ µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.5 sec tVCS VCC Setup Time (Note 1) Min µs tRB Write Recovery Time from RY/BY# Min ns tBUSY Program/Erase Valid to RY/BY# Delay Max ns

Am75PDL191CHH/Am75PDL193CHH February 5, 2004 A D V A N C E I N F O R M A T I O N AC CHARACTERISTICS OE# CE#f1 (PDL129 only) Addresses VCCf WE# Data 2AAh SADD tGHWL tAH tWP tWC tAS tWPH 555h for chip erase 10 for Chip Erase 30h tDS tVCS tCS tDH 55h tCH In Progress Complete tWHWH2 VA VA Erase Command Sequence (last two cycles) Read Status Data RY/BY# tRB tBUSY Notes: 1. SADD = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Flash Write Operation Status”. For PDL129 during CE#f1 transitions the other CE#f1 pin = VIH. Figure 18. Chip/Sector Erase Operation Timings

February 5, 2004 Am75PDL191CHH/Am75PDL193CHH A D V A N C E I N F O R M A T I O N AC CHARACTERISTICS Temporary Sector Unprotect Note: Not 100% tested. Parameter All Speed Options JEDEC Std VID Rise and Fall Time (See Note) Min 500 ns tVHH VHH Rise and Fall Time (See Note) Min 250 ns tRSP RESET# Setup Time for Temporary Sector Unprotect Min µs tRRB RESET# Hold Time from RY/BY# High for Temporary Sector Unprotect Min µs RESET# tVIDR VID VSS, VIL, or VIH VID VSS, VIL, or VIH CE#f1 or CE#f2 (PDL129 only) WE# RY/BY# tVIDR tRSP Program or Erase Command Sequence tRRB Figure 23. Temporary Sector Unprotect Timing Diagram

Am75PDL191CHH/Am75PDL193CHH February 5, 2004 A D V A N C E I N F O R M A T I O N AC CHARACTERISTICS Sector/Sector Block Protect: 150 µs, Sector/Sector Block Unprotect: 15 ms 1 µs RESET# SADD, A6, A1, A0 Data CE#f1 or CE#f1(PDL129 only) WE# OE# 60h 60h 40h Valid* Valid* Valid* Status Sector/Sector Block Protect or Unprotect Verify VID VIH For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0, SADD = Sector Address. For PDL129 during CE#f1 transitions the other CE#f1 pin = VIH. Figure 24. Sector/Sector Block Protect and Unprotect Timing Diagram

February 5, 2004 Am75PDL191CHH/Am75PDL193CHH A D V A N C E I N F O R M A T I O N AC CHARACTERISTICS Alternate CE# Controlled Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Flash Erase And Programming Performance” section for more information. Parameter All Speeds JEDEC Std Write Cycle Time (Note 1) Min ns tAVWL tAS Address Setup Time Min ns tELAX tAH Address Hold Time Min ns tDVEH tDS Data Setup Time Min ns tEHDX tDH Data Hold Time Min ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to WE# Low) Min ns tWLEL tWS WE# Setup Time Min ns tEHWH tWH WE# Hold Time Min ns tELEH tCP CE#f Pulse Width Min ns tEHEL tCPH CE#f Pulse Width High Min ns tWHWH1 tWHWH1 Programming Operation (Note 2) Word Typ µs tWHWH1 tWHWH1 Accelerated Programming Operation, Word or Byte (Note 2) Typ µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.4 sec

Am75PDL191CHH/Am75PDL193CHH February 5, 2004 A D V A N C E I N F O R M A T I O N AC CHARACTERISTICS tGHEL tWS OE# CE#f1 or CE#f2 (PDL129 only) WE# RESET# tDS Data tAH Addresses tDH tCP DQ7# DOUT tWC tAS tCPH PA Data# Polling A0 for program 55 for erase tRH tWHWH1 or 2 RY/BY# tWH PD for program 30 for sector erase 10 for chip erase 555 for program 2AA for erase PA for program SADD for sector erase 555 for chip erase tBUSY Notes: 1. Figure indicates last two bus cycles of a program or erase operation. PA = program address, SADD = sector address, PD = program data. DQ7# is the complement of the data written to the device. DOUT is the data written to the device. Figure 25. Flash Alternate CE# Controlled Write (Erase/Program) Operation Timings

February 5, 2004 Am75PDL191CHH/Am75PDL193CHH A D V A N C E I N F O R M A T I O N ERASE AND PROGRAMMING PERFORMANCE Notes: 1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. All values are subject to change. 2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles. All values are subject to change. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Tables Table 16 for further information on command definitions. 6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles. LATCHUP CHARACTERISTICS Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time. PACKAGE PIN CAPACITANCE Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25°C, f = 1.0 MHz. FLASH DATA RETENTION Parameter Typ (Note 1) Max (Note 2) Unit Comments Sector Erase Time 0.4 sec Excludes 00h programming prior to erasure (Note 4) Chip Erase Time 108 sec Word Program Time 210 µs Excludes system level overhead (Note 5) Accelerated Word Program Time 120 µs Chip Program Time (Note 3) 200 sec Input voltage with respect to VSS on all pins except I/O pins (including A9, OE#, and RESET#) –1.0 V 12.5 V Input voltage with respect to VSS on all I/O pins –1.0 V VCC + 1.0 V VCC Current –100 mA +100 mA Parameter Symbol Parameter Description Test Setup Typ Max Unit CIN Input Capacitance VIN = 0 pF COUT Output Capacitance VOUT = 0 pF CIN2 Control Pin Capacitance VIN = 0 pF CIN3 WP#/ACC Pin Capacitance VIN = 0 pF Parameter Description Test Conditions Min Unit Minimum Pattern Data Retention Time 150°C Years 125°C Years

Am75PDL191CHH/Am75PDL193CHH February 5, 2004 A D V A N C E I N F O R M A T I O N DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory loca- tion. The register is a latch used to store the com- mands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the in- puts and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail. Table 1. Am29DL640H Device Bus Operations Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = Sector Address, AIN = Address In, DIN = Data In, DOUT = Data Out Notes: 1. Addresses are A21:A0 in word mode. 2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector Block Protection and Unprotection” section. 3. If WP#/ACC = VIL, sectors 0, 1, 140, and 141 remain protected. If WP#/ACC = VIH, protection on sectors 0, 1, 140, and 141 depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”. If WP#/ACC = VHH, all sectors will be unprotected. Word/Byte Configuration The BYTE# pin controls whether the device data I/O pins operate in the byte or word configuration. If the BYTE# pin is set at logic ‘1’, the device is in word con- figuration, DQ15–DQ0 are active and controlled by CE# and OE#. If the BYTE# pin is set at logic ‘0’, the device is in byte configuration, and only data I/O pins DQ7–DQ0 are active and controlled by CE# and OE#. The data I/O pins DQ14–DQ8 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function. Requirements for Reading Array Data To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output con- trol and gates array data to the output pins. WE# should remain at VIH. The BYTE# pin determines whether the device outputs array data in words or bytes. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No com- mand is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. Each bank remains enabled for read access until the command register contents are altered. Operation CE# OE# WE# RESET# WP#/ACC Addresses (Note 2) DQ15–DQ8 DQ7– DQ0 Read L L H H L/H AIN DOUT DOUT Write L H L H (Note 3) AIN DIN DIN Standby VCC ± 0.3 V X X VCC ± 0.3 V L/H X High-Z High-Z Output Disable L H H H L/H X High-Z High-Z Reset X X X L L/H X High-Z High-Z Sector Protect (Note 2) L H L VID L/H SA, A6 = L, A1 = H, A0 = L X DIN Sector Unprotect (Note 2) L H L VID (Note 3) SA, A6 = H, A1 = H, A0 = L X DIN Temporary Sector Unprotect X X X VID (Note 3) AIN DIN DIN

February 5, 2004 Am75PDL191CHH/Am75PDL193CHH A D V A N C E I N F O R M A T I O N Refer to the AC AC Characteristics table for timing specifications and to Figure 13 for the timing diagram. ICC1 in the DC Characteristics table represents the ac- tive current specification for reading array data. Writing Commands/Command Sequences To write a command or command sequence (which in- cludes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH. For program operations, the BYTE# pin determines whether the device accepts program data in bytes or words. Refer to “Requirements for Reading Array Data” for more information. The device features an Unlock Bypass mode to facili- tate faster programming. Once a bank enters the Un- lock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The “Word Program Command Sequence” section has details on programming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sec- tors, or the entire device. Table 2 indicates the address space that each sector occupies. Similarly, a “sector address” is the address bits required to uniquely select a sector. The “Command Definitions” section has de- tails on erasing a sector or the entire chip, or suspend- ing/resuming the erase operation. The device address space is divided into four banks. A “bank address” is the address bits required to uniquely select a bank. ICC2 in the DC Characteristics table represents the ac- tive current specification for the write mode. The AC Characteristics section contains timing specification tables and timing diagrams for write operations. Accelerated Program Operation The device offers accelerated program operations through the ACC function. This is one of two functions provided by the WP#/ACC pin. This function is prima- rily intended to allow faster manufacturing throughput at the factory. If the system asserts VHH on this pin, the device auto- matically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing VHH from the WP#/ACC pin returns the device to nor- mal operation. Note that VHH must not be asserted on WP#/ACC for operations other than accelerated pro- gramming, or device damage may result. In addition, the WP#/ACC pin must not be left floating or uncon- nected; inconsistent behavior of the device may result. See “Write Protect (WP#)” on page 87 for related infor- mation. Autoselect Functions If the system writes the autoselect command se- quence, the device enters the autoselect mode. The system can then read autoselect codes from the inter- nal register (which is separate from the memory array) on DQ15–DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode and Autose- lect Command Sequence sections for more informa- tion. Simultaneous Read/Write Operations with Zero Latency This device is capable of reading data from one bank of memory while programming or erasing in the other bank of memory. An erase operation may also be sus- pended to read from or program to another location within the same bank (except the sector being erased). Figure 19 shows how read and write cycles may be initiated for simultaneous operation with zero latency. ICC6 and ICC7 in the DC Characteristics table represent the current specifications for read-while-pro- gram and read-while-erase, respectively. Standby Mode When the system is not reading or writing to the de- vice, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VCC ± 0.3 V. (Note that this is a more restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within VCC ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device re- quires standard access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. ICC3 in the DC Characteristics table represents the standby current specification. Automatic Sleep Mode The automatic sleep mode minimizes Flash device en- ergy consumption. The device automatically enables this mode when addresses remain stable for tACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard ad- dress access timings provide new data when ad-

Am75PDL191CHH/Am75PDL193CHH February 5, 2004 A D V A N C E I N F O R M A T I O N dresses are changed. While in sleep mode, output data is latched and always available to the system. ICC5 in the DC Characteristics table represents the automatic sleep mode current specification. RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of re- setting the device to reading array data. When the RE- SET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state ma- chine to reading array data. The operation that was in- terrupted should be reinitiated once the device is ready to accept another command sequence, to en- sure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS±0.3 V, the standby current will be greater. The RESET# pin may be tied to the system reset cir- cuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firm- ware from the Flash memory. If RESET# is asserted during a program or erase op- eration, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The sys- tem can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is “1”), the reset operation is completed within a time of tREADY (not during Embedded Algo- rithms). The system can read data tRH after the RE- SET# pin returns to VIH. Refer to the pSRAM AC Characteristics tables for RE- SET# parameters and to Figure 15 for the timing dia- gram. Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state. Table 2. Am29DL640H Sector Architecture Bank Sector Sector Address A21–A12 Sector Size (Kwords) (x16) Address Range Bank 1 SA0 0000000000 00000h–00FFFh SA1 0000000001 01000h–01FFFh SA2 0000000010 02000h–02FFFh SA3 0000000011 03000h–03FFFh SA4 0000000100 04000h–04FFFh SA5 0000000101 05000h–05FFFh SA6 0000000110 06000h–06FFFh SA7 0000000111 07000h–07FFFh SA8 0000001xxx 08000h–0FFFFh SA9 0000010xxx 10000h–17FFFh SA10 0000011xxx 18000h–1FFFFh SA11 0000100xxx 20000h–27FFFh SA12 0000101xxx 28000h–2FFFFh SA13 0000110xxx 30000h–37FFFh SA14 0000111xxx 38000h–3FFFFh SA15 0001000xxx 40000h–47FFFh SA16 0001001xxx 48000h–4FFFFh SA17 0001010xxx 50000h–57FFFh SA18 0001011xxx 58000h–5FFFFh SA19 0001100xxx 60000h–67FFFh SA20 0001101xxx 68000h–6FFFFh SA21 0001101xxx 70000h–77FFFh SA22 0001111xxx 78000h–7FFFFh

February 5, 2004 Am75PDL191CHH/Am75PDL193CHH A D V A N C E I N F O R M A T I O N Bank 2 SA23 0010000xxx 80000h–87FFFh SA24 0010001xxx 88000h–8FFFFh SA25 0010010xxx 90000h–97FFFh SA26 0010011xxx 98000h–9FFFFh SA27 0010100xxx A0000h–A7FFFh SA28 0010101xxx A8000h–AFFFFh SA29 0010110xxx B0000h–B7FFFh SA30 0010111xxx B8000h–BFFFFh SA31 0011000xxx C0000h–C7FFFh SA32 0011001xxx C8000h–CFFFFh SA33 0011010xxx D0000h–D7FFFh SA34 0011011xxx D8000h–DFFFFh SA35 0011000xxx E0000h–E7FFFh SA36 0011101xxx E8000h–EFFFFh SA37 0011110xxx F0000h–F7FFFh SA38 0011111xxx F8000h–FFFFFh SA39 0100000xxx F9000h–107FFFh SA40 0100001xxx 108000h–10FFFFh SA41 0100010xxx 110000h–117FFFh SA42 0101011xxx 118000h–11FFFFh SA43 0100100xxx 120000h–127FFFh SA44 0100101xxx 128000h–12FFFFh SA45 0100110xxx 130000h–137FFFh SA46 0100111xxx 138000h–13FFFFh SA47 0101000xxx 140000h–147FFFh SA48 0101001xxx 148000h–14FFFFh SA49 0101010xxx 150000h–157FFFh SA50 0101011xxx 158000h–15FFFFh SA51 0101100xxx 160000h–167FFFh SA52 0101101xxx 168000h–16FFFFh SA53 0101110xxx 170000h–177FFFh SA54 0101111xxx 178000h–17FFFFh SA55 0110000xxx 180000h–187FFFh SA56 0110001xxx 188000h–18FFFFh SA57 0110010xxx 190000h–197FFFh SA58 0110011xxx 198000h–19FFFFh SA59 0100100xxx 1A0000h–1A7FFFh SA60 0110101xxx 1A8000h–1AFFFFh SA61 0110110xxx 1B0000h–1B7FFFh SA62 0110111xxx 1B8000h–1BFFFFh SA63 0111000xxx 1C0000h–1C7FFFh SA64 0111001xxx 1C8000h–1CFFFFh SA65 0111010xxx 1D0000h–1D7FFFh SA66 0111011xxx 1D8000h–1DFFFFh SA67 0111100xxx 1E0000h–1E7FFFh SA68 0111101xxx 1E8000h–1EFFFFh SA69 0111110xxx 1F0000h–1F7FFFh SA70 0111111xxx 1F8000h–1FFFFFh Table 2. Am29DL640H Sector Architecture (Continued) Bank Sector Sector Address A21–A12 Sector Size (Kwords) (x16) Address Range

Am75PDL191CHH/Am75PDL193CHH February 5, 2004 A D V A N C E I N F O R M A T I O N Bank 3 SA71 1000000xxx 200000h–207FFFh SA72 1000001xxx 208000h–20FFFFh SA73 1000010xxx 210000h–217FFFh SA74 1000011xxx 218000h–21FFFFh SA75 1000100xxx 220000h–227FFFh SA76 1000101xxx 228000h–22FFFFh SA77 1000110xxx 230000h–237FFFh SA78 1000111xxx 238000h–23FFFFh SA79 1001000xxx 240000h–247FFFh SA80 1001001xxx 248000h–24FFFFh SA81 1001010xxx 250000h–257FFFh SA82 1001011xxx 258000h–25FFFFh SA83 1001100xxx 260000h–267FFFh SA84 1001101xxx 268000h–26FFFFh SA85 1001110xxx 270000h–277FFFh SA86 1001111xxx 278000h–27FFFFh SA87 1010000xxx 280000h–28FFFFh SA88 1010001xxx 288000h–28FFFFh SA89 1010010xxx 290000h–297FFFh SA90 1010011xxx 298000h–29FFFFh SA91 1010100xxx 2A0000h–2A7FFFh SA92 1010101xxx 2A8000h–2AFFFFh SA93 1010110xxx 2B0000h–2B7FFFh SA94 1010111xxx 2B8000h–2BFFFFh SA95 1011000xxx 2C0000h–2C7FFFh SA96 1011001xxx 2C8000h–2CFFFFh SA97 1011010xxx 2D0000h–2D7FFFh SA98 1011011xxx 2D8000h–2DFFFFh SA99 1011100xxx 2E0000h–2E7FFFh SA100 1011101xxx 2E8000h–2EFFFFh SA101 1011110xxx 2F0000h–2FFFFFh SA102 1011111xxx 2F8000h–2FFFFFh SA103 1100000xxx 300000h–307FFFh SA104 1100001xxx 308000h–30FFFFh SA105 1100010xxx 310000h–317FFFh SA106 1100011xxx 318000h–31FFFFh SA107 1100100xxx 320000h–327FFFh SA108 1100101xxx 328000h–32FFFFh SA109 1100110xxx 330000h–337FFFh SA110 1100111xxx 338000h–33FFFFh SA111 1101000xxx 340000h–347FFFh SA112 1101001xxx 348000h–34FFFFh SA113 1101010xxx 350000h–357FFFh SA114 1101011xxx 358000h–35FFFFh SA115 1101100xxx 360000h–367FFFh SA116 1101101xxx 368000h–36FFFFh SA117 1101110xxx 370000h–377FFFh SA118 1101111xxx 378000h–37FFFFh Table 2. Am29DL640H Sector Architecture (Continued) Bank Sector Sector Address A21–A12 Sector Size (Kwords) (x16) Address Range

February 5, 2004 Am75PDL191CHH/Am75PDL193CHH A D V A N C E I N F O R M A T I O N Table 3. Bank Address Table 4. SecSi TM Sector Addresses Autoselect Mode The autoselect mode provides manufacturer and de- vice identification, and sector protection verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming equip- ment to automatically match a device to be pro- grammed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register. When using programming equipment, the autoselect mode requires VID on address pin A9. Address pins must be as shown in Table 5. In addition, when verify- ing sector protection, the sector address must appear on the appropriate highest order address bits (see Table 2). Table 5 shows the remaining address bits that are don’t care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ7–DQ0. However, the autoselect codes can also be accessed in-system through the command register, for instances when the Am29DL640 is erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is illustrated in Table 11. Note that if a Bank Address (BA) on address bits A21, A20, and A19 is asserted during the third write cycle of the autoselect command, the host system can read autoselect data from that bank and then immediately read array data from the other bank, without exiting the autoselect mode. To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table 11. This method Bank 4 SA119 1110000xxx 380000h–387FFFh SA120 1110001xxx 388000h–38FFFFh SA121 1110010xxx 390000h–397FFFh SA122 1110011xxx 398000h–39FFFFh SA123 1110100xxx 3A0000h–3A7FFFh SA124 1110101xxx 3A8000h–3AFFFFh SA125 1110110xxx 3B0000h–3B7FFFh SA126 1110111xxx 3B8000h–3BFFFFh SA127 1111000xxx 3C0000h–3C7FFFh SA128 1111001xxx 3C8000h–3CFFFFh SA129 1111010xxx 3D0000h–3D7FFFh SA130 1111011xxx 3D8000h–3DFFFFh SA131 1111100xxx 3E0000h–3E7FFFh SA132 1111101xxx 3E8000h–3EFFFFh SA133 1111110xxx 3F0000h–3F7FFFh SA134 1111111000 3F8000h–3F8FFFh SA135 1111111001 3F9000h–3F9FFFh SA136 1111111010 3FA000h–3FAFFFh SA137 1111111011 3FB000h–3FBFFFh SA138 1111111100 3FC000h–3FCFFFh SA139 1111111101 3FD000h–3FDFFFh SA140 1111111110 3FE000h–3FEFFFh SA141 1111111111 3FF000h–3FFFFFh Bank A21–A19 000 001, 010, 011 100, 101, 110 111 Device Sector Size (x16) Address Range Am29DL640H 256 bytes 00000h–0007Fh Table 2. Am29DL640H Sector Architecture (Continued) Bank Sector Sector Address A21–A12 Sector Size (Kwords) (x16) Address Range

Am75PDL191CHH/Am75PDL193CHH February 5, 2004 A D V A N C E I N F O R M A T I O N does not require VID. Refer to the Autoselect Com- mand Sequence section for more information.

February 5, 2004 Am75PDL191CHH/Am75PDL193CHH A D V A N C E I N F O R M A T I O N Sector/Sector Block Protection and Unprotection (Note: For the following discussion, the term “sector” applies to both sectors and sector blocks. A sector block consists of two or more adjacent sectors that are protected or unprotected at the same time (see Table 10). The hardware sector protection feature disables both program and erase operations in any sector. The hard- ware sector unprotection feature re-enables both pro- gram and erase operations in previously protected sectors. Sector protection/unprotection can be imple- mented via two methods. Table 5. Am29DL640H Boot Sector/Sector Block Addresses for Protection/Unprotection Sector protection/sector unprotection requires VID on the RESET# pin only, and can be implemented either in-system or via programming equipment. Figure 1 shows the algorithms and Figure 24 shows the timing diagram. For sector unprotect, all unprotected sectors must first be protected prior to the first sector unpro- tect write cycle. Note that the sector unprotect algo- rithm unprotects all sectors in parallel. All previously protected sectors must be individually re-protected. To change data in protected sectors efficiently, the tem- porary sector unprotect function is available. See “Temporary Sector Unprotect”. The device is shipped with all sectors unprotected. AMD offers the option of programming and protecting sectors at its factory prior to shipping the device through AMD’s ExpressFlash™ Service. Contact an AMD representative for details. It is possible to determine whether a sector is pro- tected or unprotected. See the Autoselect Mode sec- tion for details. Write Protect (WP#) The Write Protect function provides a hardware method of protecting without using VID. This function is one of two provided by the WP#/ACC pin. If the system asserts VIL on the WP#/ACC pin, the de- vice disables program and erase functions in sectors 0, 1, 140, and 141, independently of whether those sectors were protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”. Sector A21–A12 Sector/ Sector Block Size SA0 0000000000

8 Kbytes

SA8–SA10 0000001XXX, 0000010XXX, 0000011XXX, 192 (3x64) Kbytes SA11–SA14 00001XXXXX 256 (4x64) Kbytes SA15–SA18 00010XXXXX 256 (4x64) Kbytes SA19–SA22 00011XXXXX 256 (4x64) Kbytes SA23–SA26 00100XXXXX 256 (4x64) Kbytes SA27-SA30 00101XXXXX 256 (4x64) Kbytes SA31-SA34 00110XXXXX 256 (4x64) Kbytes SA35-SA38 00111XXXXX 256 (4x64) Kbytes SA39-SA42 01000XXXXX 256 (4x64) Kbytes SA43-SA46 01001XXXXX 256 (4x64) Kbytes SA47-SA50 01010XXXXX 256 (4x64) Kbytes SA51-SA54 01011XXXXX 256 (4x64) Kbytes SA55–SA58 01100XXXXX 256 (4x64) Kbytes SA59–SA62 01101XXXXX 256 (4x64) Kbytes SA63–SA66 01110XXXXX 256 (4x64) Kbytes SA67–SA70 01111XXXXX 256 (4x64) Kbytes SA71–SA74 10000XXXXX 256 (4x64) Kbytes SA75–SA78 10001XXXXX 256 (4x64) Kbytes SA79–SA82 10010XXXXX 256 (4x64) Kbytes SA83–SA86 10011XXXXX 256 (4x64) Kbytes SA87–SA90 10100XXXXX 256 (4x64) Kbytes SA91–SA94 10101XXXXX 256 (4x64) Kbytes SA95–SA98 10110XXXXX 256 (4x64) Kbytes SA99–SA102 10111XXXXX 256 (4x64) Kbytes SA103–SA106 11000XXXXX 256 (4x64) Kbytes SA107–SA110 11001XXXXX 256 (4x64) Kbytes SA111–SA114 11010XXXXX 256 (4x64) Kbytes SA115–SA118 11011XXXXX 256 (4x64) Kbytes SA119–SA122 11100XXXXX 256 (4x64) Kbytes SA123–SA126 11101XXXXX 256 (4x64) Kbytes SA127–SA130 11110XXXXX 256 (4x64) Kbytes SA131–SA133 1111100XXX, 1111101XXX, 1111110XXX 192 (3x64) Kbytes SA134 1111111000 A21–A12 Sector/ Sector Block Size

February 5, 2004 Am75PDL191CHH/Am75PDL193CHH A D V A N C E I N F O R M A T I O N Figure 2. In-System Sector Protect/Unprotect Algorithms Sector Protect: Write 60h to sector address with A7-A0 = 00000010 Set up sector address Wait 100 µs Verify Sector Protect: Write 40h to sector address with A7-A0 = 00000010 Read from sector address with A7-A0 = 00000010 START PLSCNT = 1 RESET# = VID Wait 4 µs First Write Cycle = 60h? Data = 01h? Remove VID from RESET# Write reset command Sector Protect complete Yes Yes No PLSCNT = 25? Yes Device failed Increment PLSCNT Temporary Sector Unprotect Mode No Sector Unprotect: Write 60h to sector address with A7-A0 = 01000010 Set up first sector address Wait 1.2 ms Verify Sector Unprotect: Write 40h to sector address with A7-A0 = 00000010 Read from sector address with A7-A0 = 00000010 START PLSCNT = 1 RESET# = VID Wait 4 µs Data = 00h? Last sector verified? Remove VID from RESET# Write reset command Sector Unprotect complete Yes No PLSCNT = 1000? Yes Device failed Increment PLSCNT Temporary Sector Unprotect Mode No All sectors protected? Yes Protect all sectors: The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address Set up next sector address No Yes No Yes No No Yes No Sector Protect Algorithm Sector Unprotect Algorithm First Write Cycle = 60h? Protect another sector? Reset PLSCNT = 1 Remove VID from RESET# Write reset command Sector Protect complete Remove VID from RESET# Write reset command Sector Unprotect complete

Am75PDL191CHH/Am75PDL193CHH February 5, 2004 A D V A N C E I N F O R M A T I O N SecSi™ (Secured Silicon) Sector Flash Memory Region The SecSi (Secured Silicon) Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The SecSi Sector is 256 bytes in length, and uses a SecSi Sector Indicator Bit (DQ7) to indicate whether or not the SecSi Sector is locked when shipped from the factory. This bit is permanently set at the factory and cannot be changed, which prevents cloning of a factory locked part. This ensures the secu- rity of the ESN once the product is shipped to the field. AMD offers the device with the SecSi Sector either factory locked or customer lockable. The fac- tory-locked version is always protected when shipped from the factory, and has the SecSi (Secured Silicon) Sector Indicator Bit permanently set to a “1.” The cus- tomer-lockable version is shipped with the SecSi Sec- tor unprotected, allowing customers to utilize the that sector in any manner they choose. The customer-lock- able version has the SecSi (Secured Silicon) Sector Indicator Bit permanently set to a “0.” Thus, the SecSi Sector Indicator Bit prevents customer-lockable de- vices from being used to replace devices that are fac- tory locked. The system accesses the SecSi Sector Secure through a command sequence (see “Enter SecSi™ Sector/Exit SecSi Sector Command Sequence”). After the system has written the Enter SecSi Sector com- mand sequence, it may read the SecSi Sector by using the addresses normally occupied by the boot sectors. This mode of operation continues until the system issues the Exit SecSi Sector command se- quence, or until power is removed from the device. On power-up, or following a hardware reset, the device re- verts to sending commands to the first 256 bytes of Sector 0. Note that the ACC function and unlock by- pass modes are not available when the SecSi Sector is enabled. Factory Locked: SecSi Sector Programmed and Protected At the Factory In a factory locked device, the SecSi Sector is pro- tected when the device is shipped from the factory. The SecSi Sector cannot be modified in any way. The device is preprogrammed with both a random number and a secure ESN. The 8-word random number is at addresses 000000h–000007h in word mode (or 000000h–00000Fh in byte mode). The secure ESN is programmed in the next 8 words at addresses 000008h–00000Fh (or 000010h–00001Fh in byte mode). The device is available preprogrammed with one of the following: ■A random, secure ESN only ■Customer code through the ExpressFlash service ■Both a random, secure ESN and customer code through the ExpressFlash service. Customers may opt to have their code programmed by AMD through the AMD ExpressFlash service. AMD programs the customer’s code, with or without the ran- dom ESN. The devices are then shipped from AMD’s factory with the SecSi Sector permanently locked. Contact an AMD representative for details on using AMD’s ExpressFlash service. Customer Lockable: SecSi Sector NOT Programmed or Protected at the Factory If the security feature is not required, the SecSi Sector can be treated as an additional Flash memory space. The SecSi Sector can be read any number of times, but can be programmed and locked only once. Note that the accelerated programming (ACC) and unlock bypass functions are not available when programming the SecSi Sector. The SecSi Sector area can be protected using one of the following procedures: ■Write the three-cycle Enter SecSi Sector Region command sequence, and then follow the in-system sector protect algorithm as shown in Figure 1, ex- cept that RESET# may be at either VIH or VID. This allows in-system protection of the SecSi Sector Re- gion without raising any device pin to a high voltage. Note that this method is only applicable to the SecSi Sector. ■To verify the protect/unprotect status of the SecSi Sector, follow the algorithm shown in Figure 3. Once the SecSi Sector is locked and verified, the sys- tem must write the Exit SecSi Sector Region com- mand sequence to return to reading and writing the remainder of the array. The SecSi Sector lock must be used with caution since, once locked, there is no procedure available for unlocking the SecSi Sector area and none of the bits in the SecSi Sector memory space can be modified in any way.

February 5, 2004 Am75PDL191CHH/Am75PDL193CHH A D V A N C E I N F O R M A T I O N Figure 3. SecSi Sector Protect Verify Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Table 11 for com- mand definitions). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise. Low VCC Write Inhibit When VCC is less than VLKO, the device does not ac- cept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to the read mode. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO. Write Pulse “Glitch” Protection Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. Power-Up Write Inhibit If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automati- cally reset to the read mode on power-up. COMMON FLASH MEMORY INTERFACE (CFI) The Common Flash Interface (CFI) specification out- lines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-inde- pendent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the sys- tem writes the CFI Query command, 98h, to address 55h in word mode (or address AAh in byte mode), any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 12–15. To terminate reading CFI data, the system must write the reset command.The CFI Query mode is not accessible when the device is exe- cuting an Embedded Program or embedded Erase al- gorithm. The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Tables 12–15. The system must write the reset command to return the device to reading array data. For further information, please refer to the CFI Specifi- cation and CFI Publication 100, available via the World Wide Web at http://www.amd.com/flash/cfi. Alterna- tively, contact an AMD representative for copies of these documents. Write 60h to any address Write 40h to SecSi Sector address with A6 = 0, A1 = 1, A0 = 0 START RESET# = VIH or VID Wait 1 µs Read from SecSi Sector address with A6 = 0, A1 = 1, A0 = 0 If data = 00h, SecSi Sector is unprotected. If data = 01h, SecSi Sector is protected. Remove VIH or VID from RESET# Write reset command SecSi Sector Protect Verify complete

Am75PDL191CHH/Am75PDL193CHH February 5, 2004 A D V A N C E I N F O R M A T I O N Table 7. CFI Query Identification String Table 8. System Interface String Addresses (Word Mode) Addresses (Byte Mode) Data Query Unique ASCII string “QRY” 13h 14h 26h 28h 0002h 0000h Primary OEM Command Set 15h 16h 2Ah 2Ch 0040h 0000h Address for Primary Extended Table 17h 18h 2Eh 30h 0000h 0000h Alternate OEM Command Set (00h = none exists) 19h 1Ah 32h 34h 0000h 0000h Address for Alternate OEM Extended Table (00h = none exists) Addresses (Word Mode) Addresses (Byte Mode) Data VCC Min. (write/erase) D7–D4: volt, D3–D0: 100 millivolt 1Ch 38h 0036h VCC Max. (write/erase) D7–D4: volt, D3–D0: 100 millivolt 1Dh 3Ah 0000h VPP Min. voltage (00h = no VPP pin present) 1Eh 3Ch 0000h VPP Max. voltage (00h = no VPP pin present) 1Fh 3Eh 0004h Typical timeout per single byte/word write 2 N µs 20h 40h 0000h Typical timeout for Min. size buffer write 2 N µs (00h = not supported) 21h 42h 000Ah Typical timeout per individual block erase 2 N ms 22h 44h 0000h Typical timeout for full chip erase 2 N ms (00h = not supported) 23h 46h 0005h Max. timeout for byte/word write 2 N times typical 24h 48h 0000h Max. timeout for buffer write 2 N times typical 25h 4Ah 0004h Max. timeout per individual block erase 2 N times typical 26h 4Ch 0000h Max. timeout for full chip erase 2 N times typical (00h = not supported)

February 5, 2004 Am75PDL191CHH/Am75PDL193CHH A D V A N C E I N F O R M A T I O N Table 9. Device Geometry Definition Addresses (Word Mode) Addresses (Byte Mode) Data Device Size = 2 N byte 28h 29h 50h 52h 0002h 0000h Flash Device Interface description (refer to CFI publication 100) 2Ah 2Bh 54h 56h 0000h 0000h Max. number of byte in multi-byte write = 2 N (00h = not supported) 2Ch 58h 0003h Number of Erase Block Regions within device 2Dh 2Eh 2Fh 30h 5Ah 5Ch 5Eh 60h 0007h 0000h 0020h 0000h Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100) 31h 32h 33h 34h 62h 64h 66h 68h 007Dh 0000h 0000h 0001h Erase Block Region 2 Information (refer to the CFI specification or CFI publication 100) 35h 36h 37h 38h 6Ah 6Ch 6Eh 70h 0007h 0000h 0020h 0000h Erase Block Region 3 Information (refer to the CFI specification or CFI publication 100) 39h 3Ah 3Bh 3Ch 72h 74h 76h 78h 0000h 0000h 0000h 0000h Erase Block Region 4 Information (refer to the CFI specification or CFI publication 100)

Am75PDL191CHH/Am75PDL193CHH February 5, 2004 A D V A N C E I N F O R M A T I O N Table 10. Primary Vendor-Specific Extended Query Addresses (Word Mode) Addresses (Byte Mode) Data Query-unique ASCII string “PRI” 43h 86h 0031h Major version number, ASCII (reflects modifications to the silicon) 44h 88h 0033h Minor version number, ASCII (reflects modifications to the CFI table) 45h 8Ah 0004h Address Sensitive Unlock (Bits 1-0) 0 = Required, 1 = Not Required Silicon Revision Number (Bits 7-2) 46h 8Ch 0002h Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write 47h 8Eh 0001h Sector Protect 0 = Not Supported, X = Number of sectors in per group 48h 90h 0001h Sector Temporary Unprotect 00 = Not Supported, 01 = Supported 49h 92h 0004h Sector Protect/Unprotect scheme 01 =29F040 mode, 02 = 29F016 mode, 03 = 29F400, 04 = 29LV800 mode 4Ah 94h 0077h Simultaneous Operation 00 = Not Supported, X = Number of Sectors (excluding Bank 1) 4Bh 96h 0000h Burst Mode Type 00 = Not Supported, 01 = Supported 4Ch 98h 0000h Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page 4Dh 9Ah 0085h ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV 4Eh 9Ch 0095h ACC (Acceleration) Supply Maximum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV 4Fh 9Eh 0004h Top/Bottom Boot Sector Flag 00h = Uniform device, 01h = 8 x 8 Kbyte Sectors, Top And Bottom Boot with Write Protect, 02h = Bottom Boot Device, 03h = Top Boot Device, 04h = Both Top and Bottom 50h A0h 0001h Program Suspend 0 = Not supported, 1 = Supported, but not tested 57h AEh 0004h Bank Organization 00 = Data at 4Ah is zero, X = Number of Banks 58h B0h 0017h Bank 1 Region Information X = Number of Sectors in Bank 1 59h B2h 0030h Bank 2 Region Information X = Number of Sectors in Bank 2 5Ah B4h 0030h Bank 3 Region Information X = Number of Sectors in Bank 3 5Bh B6h 0017h Bank 4 Region Information X = Number of Sectors in Bank 4

February 5, 2004 Am75PDL191CHH/Am75PDL193CHH A D V A N C E I N F O R M A T I O N COMMAND DEFINITIONS Writing specific address and data commands or se- quences into the command register initiates device op- erations. Table 11 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence may place the device to an unknown state. A reset command is required to return the device to read array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the pSRAM AC Characteristics section for timing diagrams. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. Each bank is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the corresponding bank enters the erase-sus- pend-read mode, after which the system can read data from any non-erase-suspended sector within the same bank. The system can read array data using the standard read timing, except that if it reads at an ad- dress within erase-suspended sectors, the device out- puts status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same excep- tion. See the Erase Suspend/Erase Resume Com- mands section for more information. The system must issue the reset command to return a bank to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase opera- tion, or if the bank is in the autoselect mode. See the next section, Reset Command, for more information. See also Requirements for Reading Array Data in the section for more information. The AC Characteristics table provides the read parameters, and Figure 13 shows the timing diagram. Reset Command Writing the reset command resets the banks to the read or erase-suspend-read mode. Address bits are don’t cares for this command. The reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. This resets the bank to which the sys- tem was writing to the read mode. Once erasure be- gins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the bank to which the system was writing to the read mode. If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset command returns that bank to the erase-sus- pend-read mode. Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the se- quence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If a bank entered the autoselect mode while in the Erase Sus- pend mode, writing the reset command returns that bank to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the banks to the read mode (or erase-suspend-read mode if that bank was in Erase Suspend). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. The autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the device is actively pro- gramming or erasing in the other bank. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the bank address and the au- toselect command. The bank then enters the autose- lect mode. The system may read any number of autoselect codes without reinitiating the command se- quence. Table 11 shows the address and data requirements. To determine sector protection information, the system must write to the appropriate bank address (BA) and sector address (SA). Table 2 shows the address range and bank number associated with each sector. The system must write the reset command to return to the read mode (or erase-suspend-read mode if the bank was previously in Erase Suspend). Enter SecSi™ Sector/Exit SecSi Sector Command Sequence The SecSi Sector region provides a secured data area containing a random, sixteen-byte electronic serial number (ESN). The system can access the SecSi Sector region by issuing the three-cycle Enter SecSi Sector command sequence. The device continues to access the SecSi Sector region until the system is-

Am75PDL191CHH/Am75PDL193CHH February 5, 2004 A D V A N C E I N F O R M A T I O N sues the four-cycle Exit SecSi Sector command se- quence. The Exit SecSi Sector command sequence returns the device to normal operation. The SecSi Sector is not accessible when the device is executing an Embedded Program or embedded Erase algorithm. Table 11 shows the address and data requirements for both command sequences. See also “SecSi™ (Se- cured Silicon) Sector Flash Memory Region” for further information. Note that the ACC function and unlock by- pass modes are not available when the SecSi Sector is enabled. Word Program Command Sequence Programming is a four-bus-cycle operation. The pro- gram command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program al- gorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Table 11 shows the address and data requirements for the byte program command sequence. When the Embedded Program algorithm is complete, that bank then returns to the read mode and ad- dresses are no longer latched. The system can deter- mine the status of the program operation by using DQ7, DQ6, or RY/BY#. Refer to the Write Operation Status section for information on these status bits. Any commands written to the device during the Em- bedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program operation. SecSi sector, autoselect, and CFI are not allowed. The program command sequence should be reinitiated once that bank has returned to the read mode, to ensure data integrity. Note that the SecSi Sector, autoselect, and CFI functions are unavailable when a program operation is in progress. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from “0” back to a “1.” Attempting to do so may cause that bank to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was success- ful. However, a succeeding read will show that the data is still “0.” Only erase operations can convert a “0” to a “1.” Unlock Bypass Command Sequence The unlock bypass feature allows the system to pro- gram bytes or words to a bank faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. That bank then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass pro- gram command, A0h; the second cycle contains the program address and data. Additional data is pro- grammed in the same manner. This mode dispenses with the initial two unlock cycles required in the stan- dard program command sequence, resulting in faster total programming time. Table 11 shows the require- ments for the command sequence. During the unlock bypass mode, only the Unlock By- pass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset com- mand sequence. See Table 12. The device offers accelerated program operations through the WP#/ACC pin. When the system asserts VHH on the WP#/ACC pin, the device automatically en- ters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program command sequence. The device uses the higher voltage on the WP#/ACC pin to accelerate the operation. Note that the WP#/ACC pin must not be at VHH any operation other than accelerated programming, or device dam- age may result. In addition, the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Figure 4 illustrates the algorithm for the program oper- ation. Refer to the Erase and Program Operations table in the AC Characteristics section for parameters, and Figure 16 for timing diagrams.

February 5, 2004 Am75PDL191CHH/Am75PDL193CHH A D V A N C E I N F O R M A T I O N Table 11. Am29DL640H Command Definitions Legend: X = Don’t care RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later. PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first. SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A21–A12 uniquely select any sector. Refer to Table 2 for information on sector addresses. BA = Address of the bank that is being switched to autoselect mode, is in bypass mode, or is being erased. A21–A19 uniquely select a bank. Notes: See Table 1 for description of bus operations. All values are in hexadecimal. Except for the read cycle and the fourth, fifth, and sixth cycle of the autoselect command sequence, all bus cycles are write cycles. Data bits DQ15–DQ8 are don’t care in command sequences, except for RD and PD. Unless otherwise noted, address bits A21–A11 are don’t cares for unlock and command cycles, unless SA or PA is required. No unlock or command cycles required when bank is reading array data. The Reset command is required to return to the read mode (or to the erase-suspend-read mode if previously in Erase Suspend) when a bank is in the autoselect mode, or if DQ5 goes high (while the bank is providing status information). The fourth cycle of the autoselect command sequence is a read cycle. The system must provide the bank address to obtain the manufacturer ID, device ID, or SecSi Sector factory protect information. Data bits DQ15–DQ8 are don’t care. While reading the autoselect addresses, the bank address must be the same until a reset command is given. See the Autoselect Command Sequence section for more information. The device ID must be read across the fourth, fifth, and sixth cycles. 10. The data is 80h for factory locked, 40h for customer locked, and 00h for not factory/customer locked. 11. The data is 00h for an unprotected sector/sector block and 01h for a protected sector/sector block. 12. The Unlock Bypass command is required prior to the Unlock Bypass Program command. 13. The Unlock Bypass Reset command is required to return to the read mode when the bank is in the unlock bypass mode. 14. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation, and requires the bank address. 15. The Erase Resume command is valid only during the Erase Suspend mode, and requires the bank address. 16. Command is valid when device is ready to read array data or when device is in autoselect mode. Command Sequence (Note 1) Cycles Bus Cycles (Notes 2–5) First Second Third Fourth Fifth Sixth Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Read (Note 5) RA RD Reset (Note 6) XXX Autoselect (Note 7) Manufacturer ID Word 555 AA 2AA (BA)555 (BA)X00 Byte AAA 555 (BA)AAA Device ID (Note 9) Word 555 AA 2AA (BA)555 (BA)X01 (BA)X0E (BA)X0F Byte AAA 555 (BA)AAA (BA)X02 (BA)X1C (BA)X1E SecSi Sector Factory Protect (Note 10) Word 555 AA 2AA (BA)555 (BA)X03 Byte AAA 555 (BA)AAA (BA)X06 Sector/Sector Block Protect Verify (Note 11) Word 555 AA 2AA (BA)555 (SA)X02 Byte AAA 555 (BA)AAA (SA)X04 Enter SecSi Sector Region Word 555 AA 2AA 555 Byte AAA 555 AAA Exit SecSi Sector Region Word 555 AA 2AA 555 XXX Byte AAA 555 AAA Program Word 555 AA 2AA 555 PA PD Byte AAA 555 AAA Unlock Bypass Word 555 AA 2AA 555 Byte AAA 555 AAA Unlock Bypass Program (Note 15) XXX PA PD Unlock Bypass Reset (Note 15) XXX XXX Chip Erase Word 555 AA 2AA 555 555 AA 2AA 555 Byte AAA 555 AAA AAA 555 AAA Sector Erase Word 555 AA 2AA 555 555 AA 2AA SA Byte AAA 555 AAA AAA 555 Erase Suspend (Note 11) BA Erase Resume (Note 12) BA CFI Query (Note 13) Word Byte AA

February 5, 2004 Am75PDL191CHH/Am75PDL193CHH 103 A D V A N C E I N F O R M A T I O N Table 12. Write Operation Status Notes: 1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to the section on DQ5 for more information. 2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm is in progress. The device outputs array data if the system addresses a non-busy bank. Status DQ7 (Note 2) DQ6 DQ5 (Note 1) DQ3 DQ2 (Note 2) RY/BY# Standard Mode Embedded Program Algorithm DQ7# Toggle N/A No toggle Embedded Erase Algorithm Toggle Toggle Erase Suspend Mode Erase-Suspend- Read Erase Suspended Sector No toggle N/A Toggle Non-Erase Suspended Sector Data Data Data Data Data Erase-Suspend-Program DQ7# Toggle N/A N/A

February 5, 2004 Am75PDL191CHH/Am75PDL193CHH 105 A D V A N C E I N F O R M A T I O N DC CHARACTERISTICS CMOS Compatible Notes: 1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. 2. Maximum ICC specifications are tested with VCC = VCCmax. 3. ICC active while Embedded Erase or Embedded Program is in progress. 4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is 200 nA. 5. Not 100% tested. Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit ILI Input Load Current VIN = VSS to VCC, VCC = VCC max ±1.0 µA ILIT A9 Input Load Current VCC = VCC max; A9 = 12.5 V µA ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC max ±1.0 µA ILR Reset Leakage Current VCC = VCC max; RESET= 12.5 V µA ICC1 VCC Active Read Current (Notes 1, 2) CE# = VIL, OE# = VIH, Byte Mode

1 MHz

CE# = VIL, OE# = VIH, Word Mode VCC Active Write Current (Notes 2, 3) CE# = VIL, OE# = VIH, WE# = VIL mA ICC3 VCC Standby Current (Note 2) CE#, RESET# = VCC ± 0.3 V 0.2 µA ICC4 VCC Reset Current (Note 2) RESET# = VSS ± 0.3 V 0.2 µA ICC5 Automatic Sleep Mode (Notes 2, 4) VIH = VCC ± 0.3 V; VIL = VSS ± 0.3 V 0.2 µA ICC6 VCC Active Read-While-Program Current (Notes 1, 2) CE# = VIL, OE# = VIH Word mA ICC7 VCC Active Read-While-Erase Current (Notes 1, 2) CE# = VIL, OE# = VIH Word mA ICC8 VCC Active Program-While-Erase-Suspended Current (Notes 2, 5) CE# = VIL, OE# = VIH mA VIL Input Low Voltage –0.5 0.8 V VIH Input High Voltage 0.7 x VCC VCC + 0.3 V VHH Voltage for WP#/ACC Sector Protect/Unprotect and Program Acceleration VCC = 3.0 V ± 10% 8.5 9.5 V VID Voltage for Autoselect and Temporary Sector Unprotect VCC = 3.0 V ± 10% 11.5 12.5 V VOL Output Low Voltage IOL = 2.0 mA, VCC = VCC min 0.45 V VOH1 Output High Voltage IOH = –2.0 mA, VCC = VCC min

0.85 VCC

V VOH2 IOH = –100 µA, VCC = VCC min VCC–0.4 VLKO Low VCC Lock-Out Voltage (Note 5) 2.0 2.5 V

February 5, 2004 Am75PDL191CHH/Am75PDL193CHH 107 A D V A N C E I N F O R M A T I O N TEST CONDITIONS Table 13. Test Specifications KEY TO SWITCHING WAVEFORMS 2.7 kΩ CL 6.2 kΩ 3.1 V Device Under Test Note: Diodes are IN3064 or equivalent Figure 12. Test Setup Test Condition All Speed Options Unit Output Load Output Load Capacitance, CL (including jig capacitance) pF Input Rise and Fall Times ns Input Pulse Levels 0.0–3.0 V Input timing measurement reference levels 1.5 V Output timing measurement reference levels 1.5 V WAVEFORM INPUTS OUTPUTS Steady Changing from H to L Changing from L to H Don’t Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is High Impedance State (High Z) 3.0 V 0.0 V 1.5 V 1.5 V Output Measurement Level Input Figure 13. Input Waveforms and Measurement Levels

Am75PDL191CHH/Am75PDL193CHH February 5, 2004 A D V A N C E I N F O R M A T I O N AC CHARACTERISTICS Read-Only Operations Notes: 1. Not 100% tested. 2. See Figure 10 and Table 19 for test specifications 3. Measurements performed by placing a 50 ohm termination on the data pin with a bias of VCC/2. The time from OE# high to the data bus driven to VCC/2 is taken as tDF Parameter Std. Unit tAVAV tRC Read Cycle Time (Note 1) Min ns tAVQV tACC Address to Output Delay CE#, OE# = VIL Max ns tELQV tCE Chip Enable to Output Delay OE# = VIL Max ns tGLQV tOE Output Enable to Output Delay Max ns tEHQZ tDF Chip Enable to Output High Z (Notes 1, 3) Max ns tGHQZ tDF Output Enable to Output High Z (Notes 1, 3) Max ns tAXQX tOH Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First Min ns tOEH Output Enable Hold Time (Note 1) Read Min ns Toggle and Data# Polling Min ns tOH tCE Outputs WE# Addresses CE# OE# HIGH Z Output Valid HIGH Z Addresses Stable tRC tACC tOEH tRH tOE tRH 0 V RY/BY# RESET# tDF Figure 14. Read Operation Timings

February 5, 2004 Am75PDL191CHH/Am75PDL193CHH 109 A D V A N C E I N F O R M A T I O N AC CHARACTERISTICS Hardware Reset (RESET#) Note: Not 100% tested. Parameter RESET# Pin Low (During Embedded Algorithms) to Read Mode (See Note) Max µs tReady RESET# Pin Low (NOT During Embedded Algorithms) to Read Mode (See Note) Max 500 ns tRP RESET# Pulse Width Min 500 ns tRH Reset High Time Before Read (See Note) Min ns tRPD RESET# Low to Standby Mode Min µs tRB RY/BY# Recovery Time Min ns RESET# RY/BY# RY/BY# tRP tReady Reset Timings NOT during Embedded Algorithms tReady CE#, OE# tRH CE#, OE# Reset Timings during Embedded Algorithms RESET# tRP tRB Figure 15. Reset Timings

Am75PDL191CHH/Am75PDL193CHH February 5, 2004 A D V A N C E I N F O R M A T I O N AC CHARACTERISTICS Erase and Program Operations Notes: 1. Not 100% tested. Parameter All Speed Options JEDEC Std Write Cycle Time (Note 1) Min ns tAVWL tAS Address Setup Time Min ns tASO Address Setup Time to OE# low during toggle bit polling Min ns tWLAX tAH Address Hold Time Min ns tAHT Address Hold Time From CE# or OE# high during toggle bit polling Min ns tDVWH tDS Data Setup Time Min ns tWHDX tDH Data Hold Time Min ns tOEPH Output Enable High during toggle bit polling Min ns tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) Min ns tELWL tCS CE# Setup Time Min ns tWHEH tCH CE# Hold Time Min ns tWLWH tWP Write Pulse Width Min ns tWHDL tWPH Write Pulse Width High Min ns tSR/W Latency Between Read and Write Operations Min ns tWHWH1 tWHWH1 Programming Operation (Note 2) Word Typ µs tWHWH1 tWHWH1 Accelerated Programming Operation, Word or Byte (Note 2) Typ µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.4 sec tVCS VCC Setup Time (Note 1) Min µs tRB Write Recovery Time from RY/BY# Min ns tBUSY Program/Erase Valid to RY/BY# Delay Max ns

Am75PDL191CHH/Am75PDL193CHH February 5, 2004 A D V A N C E I N F O R M A T I O N AC CHARACTERISTICS OE# CE# Addresses VCC WE# Data 2AAh SA tAH tWP tWC tAS tWPH 555h for chip erase 10 for Chip Erase 30h tDS tVCS tCS tDH 55h tCH In Progress Complete tWHWH2 VA VA Erase Command Sequence (last two cycles) Read Status Data RY/BY# tRB tBUSY Notes: 1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”. These waveforms are for the word mode. Figure 18. Chip/Sector Erase Operation Timings

February 5, 2004 Am75PDL191CHH/Am75PDL193CHH 115 A D V A N C E I N F O R M A T I O N AC CHARACTERISTICS Temporary Sector Unprotect Note: Not 100% tested. Parameter All Speed Options JEDEC Std VID Rise and Fall Time (See Note) Min 500 ns tVHH VHH Rise and Fall Time (See Note) Min 250 ns tRSP RESET# Setup Time for Temporary Sector Unprotect Min µs tRRB RESET# Hold Time from RY/BY# High for Temporary Sector Unprotect Min µs RESET# tVIDR VID VSS, VIL, or VIH VID VSS, VIL, or VIH CE# WE# RY/BY# tVIDR tRSP Program or Erase Command Sequence tRRB Figure 23. Temporary Sector Unprotect Timing Diagram

Am75PDL191CHH/Am75PDL193CHH February 5, 2004 A D V A N C E I N F O R M A T I O N AC CHARACTERISTICS Sector Group Protect: 150 µs Sector Group Unprotect: 15 ms 1 µs RESET# SA, A6, A1, A0 Data CE# WE# OE# 60h 60h 40h Valid* Valid* Valid* Status Sector Group Protect/Unprotect Verify VID VIH * For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0. Figure 24. Sector/Sector Block Protect and Unprotect Timing Diagram

February 5, 2004 Am75PDL191CHH/Am75PDL193CHH 117 A D V A N C E I N F O R M A T I O N AC CHARACTERISTICS Alternate CE# Controlled Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Erase and Programming” section for more information. Parameter All Speed Options JEDEC Std. Write Cycle Time (Note 1) Min ns tAVWL tAS Address Setup Time Min ns tELAX tAH Address Hold Time Min ns tDVEH tDS Data Setup Time Min ns tEHDX tDH Data Hold Time Min ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to WE# Low) Min ns tWLEL tWS WE# Setup Time Min ns tEHWH tWH WE# Hold Time Min ns tELEH tCP CE# Pulse Width Min ns tEHEL tCPH CE# Pulse Width High Min ns tWHWH1 tWHWH1 Programming Operation (Note 2) Word Typ µs tWHWH1 tWHWH1 Accelerated Programming Operation, Word or Byte (Note 2) Typ µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.4 sec

Am75PDL191CHH/Am75PDL193CHH February 5, 2004 A D V A N C E I N F O R M A T I O N AC CHARACTERISTICS tGHEL tWS OE# CE# WE# RESET# tDS Data tAH Addresses tDH tCP DQ7# DOUT tWC tAS tCPH PA Data# Polling A0 for program 55 for erase tRH tWHWH1 or 2 RY/BY# tWH PD for program 30 for sector erase 10 for chip erase 555 for program 2AA for erase PA for program SA for sector erase 555 for chip erase tBUSY Notes: 1. Figure indicates last two bus cycles of a program or erase operation. PA = program address, SA = sector address, PD = program data. DQ7# is the complement of the data written to the device. DOUT is the data written to the device. 4. Waveforms are for the word mode. Figure 25. Alternate CE# Controlled Write (Erase/Program) Operation Timings

February 5, 2004 Am75PDL191CHH/Am75PDL193CHH 119 A D V A N C E I N F O R M A T I O N ERASE AND PROGRAMMING PERFORMANCE Notes: 1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 11 for further information on command definitions. 6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles. LATCHUP CHARACTERISTICS Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time. DATA RETENTION Parameter Typ (Note 1) Max (Note 2) Unit Comments Sector Erase Time 0.4 sec Excludes 00h programming prior to erasure (Note 4) Chip Erase Time sec Byte Program Time 150 µs Excludes system level overhead (Note 5) Accelerated Byte/Word Program Time 120 µs Word Program Time 210 µs Chip Program Time (Note 3) Word Mode sec Input voltage with respect to VSS on all pins except I/O pins (including A9, OE#, and RESET#) –1.0 V 12.5 V Input voltage with respect to VSS on all I/O pins –1.0 V VCC + 1.0 V VCC Current –100 mA +100 mA Parameter Description Test Conditions Min Unit Minimum Pattern Data Retention Time 150°C Years 125°C Years

February 5, 2004 Am75PDL191CHH/Am75PDL193CHH 121 A D V A N C E I N F O R M A T I O N PSRAM AC CHARACTERISTICS Functional Description Note: L = Low-level Input (VIL), H = High-level Input (VIH), X = VIH or VIL, High-Z = High-impedance. Absolute Maximum Ratings Note: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. DC Recommended Operating Conditions (Ta = -25 oC to 85 oC) Note: All voltages are reference to GND. *: VIH (Max) VDD+1.0 V with 10 ns pulse width, VIL (Min) -1.0 V with 10 ns pulse width. Mode CE1# CE2 OE# WE# LB# UB# Add I/01 to I/08 I/01 to I/08 Power Read (Word) L H L H L L X DOUT DOUT IDDO Read (Lower Byte) L H L H L H X DOUT High-Z IDDO Read (Upper Byte) L H L H H L X High-Z DOUT IDDO Write (Word) L H X L L L X DIN DIN IDDO Write (Lower Byte) L H X L L H X DIN Invalid IDDO Write (Upper Byte) L H X L H L X Invalid DIN IDDO Outputs Disabled L H H H X X X High-Z High-Z IDDO Standby H H X X X X X High-Z High-Z IDDO Deep Power-down Standby H L X X X X X High-Z High-Z IDDO Symbol Ratings Value Unit VDD Power Supply Voltage -1.0 to 3.6 V VIN Input Voltage -1.0 to 3.6 V VOUT Output Voltage -1.0 to 3.6 V Topr. Operating Temperature -25 to 85 oC Tstrg. Storage Temperature -55 to 150 W PD Power Dissipation 0.6 oC IOUT Short Circuit Output Current oC Symbol Ratings Min Typ Max Unit VDD Power Supply Voltage 2.6 2.75 3.3 V VIH Input High Voltage 2.0 VDD + 0.3* IOUT Input Low Voltage -0.3* 0.4

Am75PDL191CHH/Am75PDL193CHH February 5, 2004 A D V A N C E I N F O R M A T I O N DC Characteristics (Ta = -25 oC to 85 oC, VDD = 2.6 to 3.3 V) Notes: IDDO depends on the cycle time. IDDO depends on output loading. Specified values are defined with the output open condition. Capacitance (Ta = -25 oC, f = 1 MHz) Note: This parameter is sampled periodically and is not 100% tested. AC measurements are assumed tR, tF = 5 ns. Parameters tOD, tODO, tBD and tODW define the time at which the output goes the open condition and are not output voltage reference levels. Data cannot be retained at deep power-down standby mode. If OE# is high during the write cycle, the outputs will remain at high impedance. During the output state of I/O signals, input signals of reverse polarity must not be applied. If CE1# or LB#/UB# goes LOW coincident with or after WE# goes LOW, the outputs will remain at high impedance. If CE1 or LB#/UB# goes HIGH coincident with or before WE# goes HIGH, the outputs will remain at high impedance. Symbol Parameter Test Condition Min Typ Max Unit IIL Input Leakage Current VIN = 0 V to VDD -1.0 +1.0 µA ILO Output Leakage Current Output disable, VOUT = 0 V to VDD -1.0 +1.0 µA VOH Output High Voltage IOH = -0.5 mA 2.4 V VOL Output Low Voltage IOL = -1.0 mA 0.4 V IDDO1 Operating Current CE1# = VIL CE2 = VIH, IOUT = 0 mA tRC = min mA IDDO2 Page Access Operating Current CE1# = VIL, CE2 = VIH, Page add. cycling, IOUT = 0 mA tPC = min mA IDDS Standby Current (MOS) CE1# = VDD - 0.2V, CE2 = VDD - 0.2V 100 µA IDDSD Deep Power-down Standby Current CE2 = 0.2V µA Symbol Parameter Test Condition Max Unit CIN Input Capitance VIN = GND pF COUT Output Capitance VOUT = GND pF

February 5, 2004 Am75PDL191CHH/Am75PDL193CHH 123 A D V A N C E I N F O R M A T I O N AC Characteristics and Operating Conditions Notes: Stresses greater than listed under “Absolute Maximum Ratings” may cause permanent damage to the device. All voltages are reference to GND. IDDO depends on the cycle time. IDDO depends on output loading. Specified values are defined with the output open condition. AC measurements are assumed tR, tF = 5 ns. Parameters tOD, tODO, tBD and tODW define the time at which the output goes the open condition and are not output voltage reference levels. Data cannot be retained at deep power-down standby mode. Symbol Parameter Min Max Unit tRC Read Cycle Time 1000 ns tACC Address Access Time ns tCO Chip Enable (CE1#) Access Time ns tOE Output Enable Access Time ns tBA Data Byte Control Access Time ns tCOE Chip Enable Low to Output Active ns tOEE Output Enable Low to Output Active ns tBE Data Byte Control Low to Output Active ns tOD Chip Enable High to Output High-Z ns tODO Output Enable High to Output High-Z ns tBD Data Byte Control High to Output High-Z ns tOH Output Data Hold Time ns tPM Page Mode Time 10000 ns tPC Page Mode Cycle Time ns tAA Page Mode Address Access Time ns tAOH Page Mode Output Data Hold Time ns tWC Write Cycle Time 10000 ns tWP Write Pulse Width ns tCW Chip Enable to End of Write ns tBW Data Byte Control to End of Write ns tAW Address Valid to End of Write ns tAS Address Set-up Time ns tWR Write Recovery Time ns tCEH Chip Enable High Pulse Width ns tWEH Write Enable High Pulse Width ns tODW WE# Low to Output High-Z ns tOEW WE# High to Output Active ns tDS Data Set-up Time ns tDH Data Hold Time ns tCS CE2 Set-up Time ns tCH CE2 Hold Time 300 ns tCPD CE2 Pulse Width ms tCHC CE2 Hold from CE1# ns tCHP CE2 Hold from Power on µs

Am75PDL191CHH/Am75PDL193CHH February 5, 2004 A D V A N C E I N F O R M A T I O N AC Test Conditions Parameter Condition Output Load 30 pF + 1 TTL Gate Input Pulse Level VDD - 0.2 V, 0.2 V Timing Measurements VDD x 0.5 Reference Level VDD x 0.5 tR, tF 5 ns

February 5, 2004 Am75PDL191CHH/Am75PDL193CHH 125 A D V A N C E I N F O R M A T I O N Timing Diagrams Read Cycle Page Read Cycle (8 words access)

Am75PDL191CHH/Am75PDL193CHH February 5, 2004 A D V A N C E I N F O R M A T I O N Write Cycle 1 Write Cycle 2

February 5, 2004 Am75PDL191CHH/Am75PDL193CHH 127 A D V A N C E I N F O R M A T I O N

Am75PDL191CHH/Am75PDL193CHH February 5, 2004 A D V A N C E I N F O R M A T I O N PHYSICAL DIMENSIONS FMB073—73-Ball Fine-Pitch Grid Array 9 x 12 mm NOTES: DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010. e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "MD" IS THE BALL MATRIX IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX IN THE "E" DIRECTION. n IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = E/2 "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. NOT USED. 10. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. PACKAGE FMB 073 JEDEC N/A 13.00 mm X 9.00 mm PACKAGE NOTE SYMBOL MIN. NOM. MAX. A --- --- 1.40 PROFILE 0.20 --- --- BALL HEIGHT 1.02 --- 1.17 BODY THICKNESS D

13.00 BSC

E

9.00 BSC

8.80 BSC

7.20 BSC

n BALL COUNT Ob 0.29 --- 0.39 BALL DIAMETER eE

0.80 BSC

0.40 BSC

A2,A3,A4,A5,A6,A7,A8,A9 DEPOPULATED SOLDER BALLS B2,B3,B4,B5,B6,B7,B8,B9 C2,C9,C10,D1,D10,E1,E10 F5,F6,G5,G6,H1,H10,J1,J10 K1,K2,K9,K10,L2,L3,L4,L7,L8,L9 M2,M3,M4,M5,M6,M7,M8,M9 w053003f-163814c INDEX MARK 73X C 0.15 (2X) (2X) C 0.15 B A b 0.20 C C 0.15 M C M C A B 0.08 D E PIN A1 C TOP VIEW SIDE VIEW CORNER A 0.08 A D C E F G H J K L M B eD CORNER SE eE SD BOTTOM VIEW PIN A1

February 5, 2004 Am75PDL191CHH/Am75PDL193CHH 129 A D V A N C E I N F O R M A T I O N REVISION SUMMARY Revision A (December 5, 2003) Initial release. Revision A+1 (February 5, 2004) ESD Immunity Added an ESD Immunity qualification statement re- garding component devices manufactured by third par- ties.

Am75PDL191CHH/Am75PDL193CHH February 5, 2004 A D V A N C E I N F O R M A T I O N Trademarks Copyright © 2003 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

February 5, 2004 Am75PDL191CHH/Am75PDL193CHH 131 A D V A N C E I N F O R M A T I O N