AM75DL9608HG

AM75DL9608HG SPANSION | Alldatasheet

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The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig- inally developed the specification, these products will be offered to customers of both AMD and Fujitsu. Continuity of Specifications There is no change to this datasheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary. Continuity of Ordering Part Numbers AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order these products, please use only the Ordering Part Numbers listed in this document. For More Information Please contact your local AMD or Fujitsu sales office for additional information about Spansion memory solutions. Am75DL9608HG Data Sheet Publication Number 30772 Revision A Amendment +1 Issue Date November 17, 2003

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This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. 11/18/03 Publication# 30772 Rev:A Amendment/+1 Issue Date: November 17, 2003 Refer to AMD’s Website (www.amd.com) for the latest information. Am75DL9608HG Stacked Multi-Chip Package (MCP) Flash Memory and Pseudo SRAM

64 Megabit (4 M x 16-Bit) and 32 Megabit (2 M x 16-Bit)

CMOS 3.0 Volt-only, Simultaneous Operation Flash Memories, and

8 Mbit (512 K x 16-Bit) Pseudo Static RAM

DISTINCTIVE CHARACTERISTICS MCP Features ■ Power supply voltage of 2.7 to 3.3 volt ■ High performance — Flash access time as fast as 70 ns — Pseudo SRAM access time as fast as 55 ns ■ Package — 73-Ball FBGA ■ Operating Temperature — –40°C to +85°C Flash Memory Features (Am29DL640H/Am29DL320G) — Features apply to Am29DL640H and Am29DL320G independently. ARCHITECTURAL ADVANTAGES ■ Simultaneous Read/Write operations — Data can be continuously read from one bank while executing erase/program functions in another bank. — Zero latency between read and write operations ■ Flexible Bank™ architecture — Read may occur in any of the three banks not being written or erased. — Four banks may be grouped by customer to achieve desired bank divisions. ■ Manufactured on 0.17 µm process technology (Am29DL320G), 0.13 µm process technology (Am29DL640H) ■ SecSi™ (Secured Silicon) Sector — Extra 256 byte sector on Am29DL640H — Extra 256 byte sector on Am29DL320G Factory locked and identifiable: 16 bytes available for secure, random factory Electronic Serial Number; verifiable as factory locked through autoselect function. ExpressFlash option allows entire sector to be available for factory-secured data Customer lockable: Sector is one-time programmable. Once sector is locked, data cannot be changed. ■ Zero Power Operation — Sophisticated power management circuits reduce power consumed during inactive periods to nearly zero. ■ Boot sectors — Top and bottom boot sectors in Am29DL640H — Top or bottom boot options in Am29DL320G ■ Compatible with JEDEC standards — Pinout and software compatible with single-power-supply flash standard PERFORMANCE CHARACTERISTICS ■ High performance — Access time as fast as 70 ns — Program time: 4 µs/word typical utilizing Accelerate function ■ Ultra low power consumption (typical values) — 2 mA active read current at 1 MHz — 10 mA active read current at 5 MHz — 200 nA in standby or automatic sleep mode ■ Minimum 1 million erase cycles guaranteed per sector ■ 20 year data retention at 125°C — Reliable operation for the life of the system SOFTWARE FEATURES ■ Supports Common Flash Memory Interface (CFI) ■ Program/Erase Suspend/Erase Resume — Suspends program/erase operations to allow programming/erasing in same bank ■ Data# Polling and Toggle Bits — Provides a software method of detecting the status of program or erase cycles HARDWARE FEATURES ■ Any combination of sectors can be erased ■ Ready/Busy# output (RY/BY#) — Hardware method for detecting program or erase cycle completion ■ Hardware reset pin (RESET#) — Hardware method of resetting the internal state machine to the read mode ■ WP#/ACC input pin — Write protect (WP#) protects sectors 0, 1, 140, and 141 in Am29DL640H, and two outermost boot sectors in Am29DL320G — Acceleration (ACC) function accelerates program timing ■ Sector protection — Hardware method of locking a sector, either in-system or using programming equipment, to prevent any program or erase operation within that sector — Temporary Sector Unprotect allows changing data in protected sectors in-system Pseudo SRAM Features ■ Power dissipation — Operating: 30 mA maximum — Standby: 60 µA maximum ■ CE1s# and CE2s Chip Select ■ Power down features using CE1s# and CE2s ■ Data retention supply voltage: 2.7 to 3.3 volt ■ Byte data control: LB#s (DQ7–DQ0), UB#s (DQ15–DQ8)

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The Am75DL9608HG consists of two flash memory devices (one 64-Mbit Am29DL640H and one 32-Mbit Am29DL320G), and one 8 Mbit pseudo SRAM device. Am29DL640H and Am29DL320G Features Am29DL640H is a 64 megabit, 3.0 volt-only flash memory device, organized as 4,194,304 words. The Am29DL320G is a 32 megabit, 3.0 volt-only flash memory device, organized as 2,097,152 words. Word mode data appears on DQ15–DQ0. The device is de- signed to be programmed in-system with the standard 3.0 volt V CC supply, and can also be programmed in standard EPROM programmers. The device is available with an access time of 70 or 85 ns and is offered in a 73-ball FBGA package. Standard control pins—chip enable (CE#fx), write enable (WE#), and output enable (OE#)—control normal read and write operations, and avoid bus contention issues. The device requires only a single 3.0 volt power sup- ply for both read and write functions. Internally gener- ated and regulated voltages are provided for the program and erase operations. Simultaneous Read/Write Operations with Zero Latency The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into four banks . Sector addresses are fixed, system software can be used to form user-defined bank groups. During an Erase/Program operation, any of the three non-busy banks may be read from. Note that only two banks can operate simultaneously. The device can im- prove overall system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from the other bank, with zero latency. This releases the system from waiting for the completion of program or erase operations. The Am29DL640H can be organized as both a top and bottom boot sector configuration. The Am29DL320G can be organized as either a top or bottom boot sector configuration. Top boot configura- tion is shown in the following table. Bottom boot configuration is shown in the following ta- ble. Available on Am29DL640H and Am29DL320G, the SecSi™ (Secured Silicon) Sector is an extra 256 byte sector capable of being permanently locked by AMD or customers. The Secure Sector SecSi Indica- tor Bit (DQ7) is permanently set to a 1 if the part is factory locked, and set to a 0 if customer lockable . This way, customer lockable parts can never be used to replace a factory locked part. Factory locked parts provide several options. The Se- cure SectorSecSi Sector may store a secure, random 16 byte ESN (Electronic Serial Number), customer code (programmed through AMD’s ExpressFlash ser- vice), or both. Customer Lockable parts may utilize the Secure SectorSecSi Sector as a one-time programma- ble area. The AMD DMS (Data Management Software) man- ages data programming, enables EEPROM emulation, and eases historical sector erase flash limitations. For more information on DMS or to obtain the software, contact AMD or an authorized representative. The device offers complete compatibility with the JEDEC single-power-supply Flash command set standard . Commands are written to the command register using standard microprocessor write timings. Reading data out of the device is similar to reading from other Flash or EPROM devices. The host system can detect whether a program or erase operation is complete by using the device sta- tus bits: RY/BY# pin, DQ7 (Data# Polling) and DQ6/DQ2 (toggle bits). After a program or erase cycle has been completed, the device automatically returns to the read mode. The sector erase architecture allows memory sec- tors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low V CC detector that automatically inhibits write opera- tions during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of mem- ory. This can be achieved in-system or via program- ming equipment. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode . The system can also place the device into the standby mode . Power consumption is greatly re- duced in both modes. Bank Megabits Sector Sizes Bank 1 8 Mb Eight 4 Kword, Fifteen 32 Kword Bank 2 24 Mb Forty-eight 32 Kword Bank 3 24 Mb Forty-eight 32 Kword Bank 4 8 Mb Eight 4 Kword, Fifteen 32 Kword Bank Megabits Sector Sizes Bank 1 4 Mb Eight 4 Kword, Seven 32 Kword Bank 2 12 Mb Twenty-four 32 Kword Bank 3 12 Mb Twenty-four 32 Kword Bank 4 4 Mb Eight 32 Kword Bank Megabits Sector Sizes Bank 1 4 Mb Eight 32 Kword Bank 2 12 Mb Twenty-four 32 Kword Bank 3 12 Mb Twenty-four 32 Kword Bank 4 4 Mb Eight 4 Kword, Seven 32 Kword

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Table 4. Am29DL640H SecSi Table 6. Am29DL320G Top Boot SecSi Table 8. Am29DL320G Bottom Boot SecSi Table 9. Am29DL640H Boot Sector/Sector Block Table 10. Am29DL320G Top Boot Sector/Sector Table 11. Am29DL320G Bottom Boot Sector/Sector Block Addresses Table 17. Am29DL640H Primary Vendor-Specific Table 21. Am29DL320G Primary Vendor-Specific Table 22. Am29DL640H and Am29DL320G Command Definitions 39 Figure 10. ICC1 Current vs. Time (Showing Active and Figure 11. Typical I Figure 15. Timing Diagram for Alternating Figure 22. Data# Polling Timings (During Embedded Algorithms). 56 Figure 26. Sector/Sector Block Protect and Figure 27. Flash Alternate CE#f Controlled Write (Erase/Program)

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Standard Voltage Range: VCC = 2.7–3.3 V Flash Memory (Am29DL640H, Am29DL320G) Pseudo SRAM 75 70 75 70 Max Access Time (ns) 70 70 55 70 CE# Access (ns) 70 70 55 70 OE# Access (ns) 30 30 30 35 VSSVCCs RESET# WE# OE# CE1#s LB#s UB#s WP#/ACC CE#f1 CE2s

8 MBit

32 MBit

RY/BY# VSSVCCf

64 MBit

CE#f2 DQ15 to DQ0 VSSVCCf RY/BY#

November 17, 2003 Am75DL9608HG 7 ADVANCE INFORMATION FLASH MEMORY BLOCK DIAGRAM * Addresses for Am29DL640H are A21–A0. Address for Am29DL320G are A20–A0. VCC VSS Bank 1 Address Bank 2 Address A21*–A0 RESET# WE# CE# WP#/ACC STATE CONTROL COMMAND REGISTER RY/BY# Bank 1 X-Decoder OE# DQ15–DQ0 Status Control A21*–A0 A21*–A0 A21*–A0A21*–A0 DQ15–DQ0 DQ15–DQ0 DQ15–DQ0 DQ15–DQ0 Mux Mux Mux Bank 2 X-Decoder Y-gate Bank 3 X-Decoder Bank 4 X-Decoder Y-gate Bank 3 Address Bank 4 Address

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Special Package Handling Instructions Special handling is required for Flash Memory products in molded packages (BGA). The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150 °C for prolonged periods of time. A10 B10 F10 G10 L10 M10 NC NC NC NC NC NC NCNC NC CE#f1 CE1#s V SS OE# DQ0 DQ8 LB# UB# A18 A17 DQ1 DQ9 DQ10 DQ2 NC WP#/ACC RESET# RY/BY# DQ3 V CCf DQ11 NC WE# CE2s A20 DQ4 VCCs NC A19 A10 DQ6 DQ13 DQ12 DQ5 A11 A12 A13 A14 NC DQ15 DQ7 DQ14 A15 A21 CE#f2 A16 NC V SS NC NC NC NC NC NC Pseudo SRAM only Shared Flash only 73-Ball FBGA Top View

November 17, 2003 Am75DL9608HG 9 ADVANCE INFORMATION PIN DESCRIPTION A18–A0 = 19 Address Inputs (Common) A21–A19, A-1 = 4 Address Inputs (Flash) DQ15–DQ0 = 16 Data Inputs/Outputs (Common) CE#f1 = Flash Chip Enable 1 (Am29DL640H) CE#f2 = Flash Chip Enable 2 (Am29DL320G) CE#1s = Pseudo SRAM Chip Enable 1 CE2s = Pseudo SRAM Chip Enable 2 OE# = Output Enable (Common) WE# = Write Enable (Common) RY/BY# = Ready/Busy Output UB#s = Upper Byte Control (Pseudo SRAM) LB#s = Lower Byte Control (Pseudo SRAM) RESET# = Hardware Reset Pin, Active Low WP#/ACC = Hardware Write Protect/ Acceleration Pin (Flash) VCCf = Flash 3.0 volt-only single power sup- ply (see Product Selector Guide for speed options and voltage supply tolerances) V CCs = Pseudo SRAM Power Supply VSS = Device Ground (Common) NC = Pin Not Connected Internally LOGIC SYMBOL DQ15–DQ0 A18–A0 CE#f1 OE# WE# RESET# UB#s RY/BY# WP#/ACC A21–A19 LB#s CE1#s CE2s CE#f2

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ORDERING INFORMATION

The order number (Valid Combination) is formed by the following: Valid Combinations Valid Combinations list configurations planned to be supported in vol- ume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly re- leased combinations. MCP DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory loca- tion. The register is a latch used to store the com- mands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Tables 1-2 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail. Am75DL960 8 HG T 75 I T TAPE AND REEL T = 7 inches S = 13 inches TEMPERATURE RANGE I = Industrial (–40 °C to +85°C) SPEED OPTION 75 = 70 ns Flash + 55 ns pSRAM 70 = 70 ns Flash + 70 ns pSRAM (See page 5) BOOT SECTOR ARCHITECTURE T = Top Boot of Am29DL320G Flash B = Bottom Boot of Am29DL320G Flash PROCESS TECHNOLOGY H = 0.13 µm (Am29DL640H) G = 0.17 µm (Am29DL320G) PSEUDO SRAM DEVICE DENSITY 8= 8 M b i t s AMD DEVICE NUMBER/DESCRIPTION Am75DL9608HG Stacked Multi-Chip Package (MCP) Flash Memory and Pseudo SRAM Am29DL640H 64 Megabit (8/4 M x 16-Bit) and Am29DL320G 32 Megabit (4/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 8 Mbit (512 K x 16-Bit) Pseudo Static RAM Valid Combinations Order Number Package Marking Am75DL9608HGT70I Am75DL9608HGB70I T, S M750000000 M750000001 Am75DL9608HGT75I Am75DL9608HGB75I T, S M750000002 M750000003

Table 1. Device Bus Operations—Flash Word Mode

1. Other operations except for those indicated in this column are inhibited.
2. Do not apply CE#fx = V IL, CE1#s = VIL and CE2s = VIH at the same time.
3. Don’t care or open LB#s or UB#s.
4. If WP#/ACC = V IL, the boot sectors will be protected. If WP#/ACC = VIH the boot sectors protection will be removed.

If WP#/ACC = VACC (9V), the program time will be reduced by 40%.

1. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector

Block Protection and Unprotection” section.

1. If WP#/ACC = V IL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection

Unprotection”. If WP#/ACC = VHH, all sectors will be unprotected.

1. Only one flash device should be accessed at a time. For Am29DL640H flash access, CE#f1 = VIL, CE#f2 = VIH. For Am29DL320G

flash access, CE#f1 = VIH, CE#f2 = ViL.

1. CE#1s= V IL, CE2s= VIH, CE#f1=VIH and CE#f2=VIH when accessing pseudo SRAM.

0.3 V H High-Z High-Z

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FLASH DEVICE BUS OPERATIONS Requirements for Reading Array Data To read array data from the outputs, the system must drive the CE#f and OE# pins to V IL. CE#f is the power control and selects the device. OE# is the output con- trol and gates array data to the output pins. WE# should remain at V IH. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No com- mand is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. Each bank remains enabled for read access until the command register contents are altered. Refer to the AC Read-Only Operations table for timing specifications and to Figure 14 for the timing diagram. I CC1 in the DC Characteristics table represents the ac- tive current specification for reading array data. Writing Commands/Command Sequences To write a command or command sequence (which in- cludes programming data to the device and erasing sectors of memory), the system must drive WE# and CE#f to V IL, and OE# to VIH. The device features an Unlock Bypass mode to facili- tate faster programming. Once a bank enters the Un- lock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The “Byte/Word Program Command Sequence” section has details on programming data to the device using both standard and Unlock Bypass command se- quences. An erase operation can erase one sector, multiple sec- tors, or the entire device. Table 2 indicates the address space that each sector occupies. Similarly, a “sector address” is the address bits required to uniquely select a sector. The “Flash Command Definitions” section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. The device address space is divided into four banks. A “bank address” is the address bits required to uniquely select a bank. I CC2 in the DC Characteristics table represents the ac- tive current specification for the write mode. The Flash AC Characteristics section contains timing specifica- tion tables and timing diagrams for write operations. Accelerated Program Operation The device offers accelerated program operations through the ACC function. This is one of two functions provided by the WP#/ACC pin. This function is prima- rily intended to allow faster manufacturing throughput at the factory. If the system asserts V HH on this pin, the device auto- matically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing V HH from the WP#/ACC pin returns the device to nor- mal operation. Note that VHH must not be asserted on WP#/ACC for operations other than accelerated pro- gramming, or device damage may result. In addition, the WP#/ACC pin must not be left floating or uncon- nected; inconsistent behavior of the device may result . See “Write Protect (WP#)” on page 23 for related infor- mation. Autoselect Functions If the system writes the autoselect command se- quence, the device enters the autoselect mode. The system can then read autoselect codes from the inter- nal register (which is separate from the memory array) on DQ15–DQ0. Standard read cycle timings apply in this mode. Refer to the Sector/Sector Block Protection and Unprotection and Autoselect Command Se- quence sections for more information. Simultaneous Read/Write Operations with Zero Latency This device is capable of reading data from one bank of memory while programming or erasing in the other bank of memory. An erase operation may also be sus- pended to read from or program to another location within the same bank (except the sector being erased). Figure 19 shows how read and write cycles may be initiated for simultaneous operation with zero latency. I CC6f and I CC7f in the table represent the cur- rent specifications for read-while-program and read-while-erase, respectively. Standby Mode When the system is not reading or writing to the de- vice, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE#f and RESET# pins are both held at V CC ± 0.3 V. (Note that this is a more restricted voltage range than V IH .) If CE#f and RESET# are held at V IH , but not within V CC ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The de-

November 17, 2003 Am75DL9608HG 13 ADVANCE INFORMATION vice requires standard access time (t CE) for read ac- cess when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. I CC3f in the table represents the standby current speci- fication. Automatic Sleep Mode The automatic sleep mode minimizes Flash device en- ergy consumption. The device automatically enables this mode when addresses remain stable for t ACC + 30 ns. The automatic sleep mode is independent of the CE#f, WE#, and OE# control signals. Standard ad- dress access timings provide new data when ad- dresses are changed. While in sleep mode, output data is latched and always available to the system. I CC5f in the table represents the automatic sleep mode current specification. RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of re- setting the device to reading array data. When the RE- SET# pin is driven low for at least a period of t RP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state ma- chine to reading array data. The operation that was in- terrupted should be reinitiated once the device is ready to accept another command sequence, to en- sure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at V SS±0.3 V , the device draws CMOS standby current (I CC4 f). If RESET# is held at V IL but not within V SS±0.3 V, the standby cur- rent will be greater. The RESET# pin may be tied to the system reset cir- cuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firm- ware from the Flash memory. If RESET# is asserted during a program or erase op- eration, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a time of t READY (during Embedded Algorithms). The sys- tem can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is “1”), the reset operation is completed within a time of t READY (not during Embedded Algo- rithms). The system can read data t RH after the RE- SET# pin returns to VIH. Refer to the Flash AC Characteristics tables for RE- SET# parameters and to Figure 15 for the timing dia- gram. Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state.

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Table 2. Am29DL640H Sector Architecture

Table 2. Am29DL640H Sector Architecture (Continued)

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Table 3. Am29DL640H Bank Address Table 4. Am29DL640H SecSi ™ Sector Addresses

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Table 5. Am29DL320G Top Boot Sector Addresses

Note: The address range is A20:A0. Table 5. Am29DL320G Top Boot Sector Addresses (Continued)

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Table 7. Am29DL320G Bottom Boot Sector Addresses

Table 8. Am29DL320G Bottom Boot SecSi TM Sector Addresses Table 7. Am29DL320G Bottom Boot Sector Addresses (Continued)

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Table 11. Am29DL320G Bottom Boot

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“Temporary Sector Unprotect”. The device is shipped with all sectors unprotected. AMD representative for details. Protection and Unprotection section for details. one of two provided by the WP#/ACC pin. Am29DL320G is enabled (CE#f2). Block Protection and Unprotection”. Table 12. WP#/ACC Modes Figure 23 shows the timing diagrams, for this feature. “Accelerated Program Operation” on page 11.

Figure 1. Temporar y Sector Unprotect Operation

1. All protected sectors unprotected (If WP#/ACC = V IL,
2. All previously protected sectors are protected once

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Figure 2. In-System Sector Protect/Unprotect Algorithms

rity of the ESN once the product is shipped to the field. quence, or until power is removed from the device. are not available when the SecSi Sector is enabled. tected when the device is shipped from the factory. Table 13. SecSi Sector Programming through the ExpressFlash service. factory with the SecSi Sector permanently locked. can be treated as an additional Flash memory space. gion without raising any device pin to a high voltage. Sector, follow the algorithm shown in Figure 3.

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Figure 3. SecSi Sector Protect Verify and power-down transitions, or from system noise. or WE# do not initiate a write cycle. cally reset to the read mode on power-up. interfaces for long-term compatibility. device to reading array data.

Table 14. Am29DL640H CFI Qu ery Identification String Table 15. Am29DL640H System Interface String

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Table 16. Am29DL640H Device Geometry Definition

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Table 18. Am29DL320G CFI Query Identification String Table 19. Am29DL320G System Interface String

Table 20. Am29DL320G Device Geometry Definition

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November 17, 2003 Am75DL9608HG 35 ADVANCE INFORMATION FLASH COMMAND DEFINITIONS Writing specific address and data commands or se- quences into the command register initiates device op- erations. Table 22 defines the valid register command sequences. Writing incorrect address and data val- ues or writing them in the improper sequence may place the device in an unknown state. A reset com- mand is then required to return the device to reading array data. All addresses are latched on the falling edge of WE# or CE#f, whichever happens later. All data is latched on the rising edge of WE# or CE#f, whichever hap- pens first. Refer to the Flash AC Characteristics sec- tion for timing diagrams. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. Each bank is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the corresponding bank enters the erase-sus- pend-read mode, after which the system can read data from any non-erase-suspended sector within the same bank. The system can read array data using the standard read timing, except that if it reads at an ad- dress within erase-suspended sectors, the device out- puts status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same excep- tion. See the Erase Suspend/Erase Resume Com- mands section for more information. The system must issue the reset command to return a bank to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase opera- tion, or if the bank is in the autoselect mode. See the next section, Reset Command, for more information. See also Requirements for Reading Array Data in the section for more information. The Read-Only Opera- tions table provides the read parameters, and Figure 14 shows the timing diagram. Reset Command Writing the reset command resets the banks to the read or erase-suspend-read mode. Address bits are don’t cares for this command. The reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. This resets the bank to which the sys- tem was writing to the read mode. Once erasure be- gins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the bank to which the system was writing to the read mode. If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset command returns that bank to the erase-sus- pend-read mode. Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the se- quence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If a bank entered the autoselect mode while in the Erase Sus- pend mode, writing the reset command returns that bank to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the banks to the read mode (or erase-suspend-read mode if that bank was in Erase Suspend). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. The autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the device is actively pro- gramming or erasing in the other bank. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the bank address and the au- toselect command. The bank then enters the autose- lect mode. The system may read any number of autoselect codes without reinitiating the command se- quence. Table 22 shows the address and data requirements. To determine sector protection information, the system must write to the appropriate bank address (BA) and sector address (SADD). Table 2 shows the address range and bank number associated with each sector. The system must write the reset command to return to the read mode (or erase-suspend-read mode if the bank was previously in Erase Suspend). Enter SecSi™ Sector/Exit SecSi Sector Command Sequence The SecSi Sector region provides a secured data area containing a random, sixteen-byte electronic serial number (ESN). The system can access the SecSi Sector region by issuing the three-cycle Enter SecSi

36 Am75DL9608HG November 17, 2003

Sector command sequence. The device continues to access the SecSi Sector region until the system is- sues the four-cycle Exit SecSi Sector command se- quence. The Exit SecSi Sector command sequence returns the device to normal operation. The SecSi Sector is not accessible when the device is executing an Embedded Program or embedded Erase algorithm. Table 22 shows the address and data requirements for both command sequences. Note that the ACC function and unlock bypass modes are not available when the SecSi sector is enabled. See also “SecSi™ (Secured Silicon) Sector SectorFlash Memory Region” for further information. Program Command Sequence Programming is a four-bus-cycle operation. The pro- gram command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program al- gorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Table 22 shows the address and data requirements for the byte program command sequence. Note that the SecSi Sector, autoselect, and CFI functions are unavailable when a program opera- tion is in progress. When the Embedded Program algorithm is complete, that bank then returns to the read mode and ad- dresses are no longer latched. The system can deter- mine the status of the program operation by using DQ7, DQ6, or RY/BY#. Refer to the Flash Write Oper- ation Status section for information on these status bits. Any commands written to the device during the Em- bedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once that bank has returned to the read mode, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from “0” back to a “1.” Attempting to do so may cause that bank to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was success- ful. However, a succeeding read will show that the data is still “0.” Only erase operations can convert a “0” to a “1.” Unlock Bypass Command Sequence The unlock bypass feature allows the system to pro- gram bytes or words to a bank faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. That bank then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass pro- gram command, A0h; the second cycle contains the program address and data. Additional data is pro- grammed in the same manner. This mode dispenses with the initial two unlock cycles required in the stan- dard program command sequence, resulting in faster total programming time. Table 22 shows the require- ments for the command sequence. During the unlock bypass mode, only the Unlock By- pass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset com- mand sequence (See Table 12). The device offers accelerated program operations through the WP#/ACC pin. When the system asserts V HH on the WP#/ACC pin, the device automatically en- ters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program command sequence. The device uses the higher voltage on the WP#/ACC pin to accelerate the operation. Note that the WP#/ACC pin must not be at V HH any operation other than accelerated programming, or device dam- age may result. In addition, the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Figure 3 illustrates the algorithm for the program oper- ation. Refer to the Erase and Program Operations table in the AC Characteristics section for parameters, and Figure 16 for timing diagrams.

38 Am75DL9608HG November 17, 2003

mation on these status bits. reading array data, to ensure data integrity. and Figure 18 section for timing diagrams. Figure 5. Erase Operation period during the sector erase command sequence. writing the Erase suspend command. if a sector is actively erasing or is erase-suspended. information on these status bits. just as in the standard Byte Program operation. pend mode, and is ready for another valid operation. pended bank is required when writing this command. Further writes of the Resume command are ignored. the chip has resumed erasing.

1. See Table 22 for erase command sequence.
2. See the section on DQ3 for information on the sector

Table 22. Am29DL640H and Am29DL320G Command Definitions RA = Address of the memory location to be read. RD = Data read from location RA during read operation. edge of WE# or CE#f pulse, whichever happens first. Table 2 for information on sector addresses. bank. Refer to Table 3 for information on sector addresses.

1. See Tables 1 to 2 for description of bus operations.
2. All values are in hexadecimal.
3. Except for the read cycle and the fourth cycle of the autoselect

command sequence, all bus cycles are write cycles.

1. Data bits DQ15–DQ8 are don’t care in command sequences,
2. Unless otherwise noted, address bits A21–A12 are don’t cares for

unlock and command cycles, unless SADD or PA is required.

1. No unlock or command cycles required when bank is reading
2. The Reset command is required to return to the read mode (or to

the bank is providing status information).

1. The fourth cycle of the autoselect command sequence is a read

Autoselect Command Sequence section for more information.

1. The device ID must be read across the fourth, fifth, and sixth
2. For Am29DL640H, the data is 80h for factory locked, 40h for

are 81H and 01h respectively.

1. The data is 00h for an unprotected sector/sector block and 01h for

a protected sector/sector block.

1. The Unlock Bypass command is required prior to the Unlock
2. The Unlock Bypass Reset command is required to return to the

read mode when the bank is in the unlock bypass mode.

1. The system may read and program in non-erasing sectors, or

enter the autoselect mode, when in the Erase Suspend mode. operation, and requires the bank address.

1. The Erase Resume command is valid only during the Erase

Suspend mode, and requires the bank address.

1. Command is valid when device is ready to read array data or when

device is in autoselect mode.

40 Am75DL9608HG November 17, 2003

WE# pulse in the command sequence. Suspend mode, Data# Polling produces a “1” on DQ7. sector, the status may not be valid. byte mode) will appear on successive read cycles. Table 23 shows the outputs for Data# Polling on DQ7. Data# Polling timing diagram. Figure 6. Data# Polling Algorithm

1. VA = Valid address for programming. During a sector

valid address is any non-protected sector address.

1. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

42 Am75DL9608HG November 17, 2003

DQ2: Toggle Bit II The “Toggle Bit II” on DQ2, when used with DQ6, indi- cates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for era- sure. (The system may use either OE# or CE#f to con- trol the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-sus- pended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for era- sure. Thus, both status bits are required for sector and mode information. Refer to Table 23 to compare out- puts for DQ2 and DQ6. Figure 6 shows the toggle bit algorithm in flowchart form, and the section “DQ2: Toggle Bit II” explains the algorithm. See also the DQ6: Toggle Bit I subsection. Figure 21 shows the toggle bit timing diagram. Figure 22 shows the differences between DQ2 and DQ6 in graphical form. Reading Toggle Bits DQ6/DQ2 Refer to Figure 6 for the following discussion. When- ever the system initially begins reading toggle bit sta- tus, it must read DQ15–DQ0 (or DQ7–DQ0 for byte mode) at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ15–DQ0 (or DQ7–DQ0 for byte mode) on the fol- lowing read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the sys- tem also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is tog- gling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the de- vice did not completed the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially de- termines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cy- cles, determining the status as described in the previ- ous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to de- termine the status of the operation (top of Figure 6). DQ5: Exceeded Timing Limits DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a “1,” indicating that the program or erase cycle was not successfully completed. The device may output a “1” on DQ5 if the system tries to program a “1” to a location that was previously pro- grammed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition, the device halts the operation, and when the timing limit has been exceeded, DQ5 produces a “1.” Under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspend-read mode if a bank was previ- ously in the erase-suspend-program mode). DQ3: Sector Erase Timer After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase com- mand. When the time-out period is complete, DQ3 switches from a “0” to a “1.” If the time between addi- tional sector erase commands from the system can be assumed to be less than 50 µs, the system need not monitor DQ3. See also the Sector Erase Command Sequence section. After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is “1,” the Embedded Erase algorithm has begun; all fur- ther commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is “0,” the device will accept additional sector erase commands. To ensure the command has been accepted, the sys- tem software should check the status of DQ3 prior to and following each subsequent sector erase com- mand. If DQ3 is high on the second status check, the last command might not have been accepted. Table 23 shows the status of DQ3 relative to the other status bits.

Table 23. Write Operation Status

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

Refer to the section on DQ5 for more information.

1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further
2. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm

is in progress. The device outputs array data if the system addresses a non-busy bank.

44 Am75DL9608HG November 17, 2003

1. Minimum DC voltage on input or I/O pins is –0.5 V.

overshoot V SS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is V CC +0.5 V .

1. Minimum DC input voltage on pins RESET#, and

+12.0 V for periods up to 20 ns.

1. No more than one output may be shorted to ground at a

operational sections of this data sheet is not implied. conditions for extended periods may affect device reliability. Figure 8. Maximum Negative Figure 9. Maximum Positive functionality of the device is guaranteed.

November 17, 2003 Am75DL9608HG 45 ADVANCE INFORMATION Notes: 1. The I CC current listed is typically less than 2 mA/MHz, with OE# at VIH. 2. Maximum I CC specifications are tested with VCC = VCCmax. 3. I CC active while Embedded Erase or Embedded Program is in progress. 4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is 200 nA. 5. Not 100% tested. 6. 2 Flash stack together → double the current limit from 5 →10 µA FLASH DC CHARACTERISTICS CMOS Compatible Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit ILI Input Load Current VIN = VSS to VCC, VCC = VCC max ±1.0 µA ILIT RESET# Input Load Current V CC = VCC max; RESET# = 12.5 V 35 µA ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC max ±1.0 µA ILR Reset Leakage Current V CC = VCC max; RESET# = 12.5 V 35 µA ILIA ACC Input Leakage Current V CC = VCC max, WP#/ACC = VACC max 35 µA ICC1f Flash VCC Active Read Current (Notes 1, 2) CE#f = VIL, OE# = VIH, Word Mode

5 MHz 10 16

1 MHz 2 4

ICC2f Flash VCC Active Write Current (Notes 2, 3) CE#f = V IL, OE# = VIH, WE# = VIL 15 30 mA ICC3f Flash VCC Standby Current (Note 2) VCCf = VCC max, CE#f, RESET#, WP#/ACC = VCCf ± 0.3 V 0.2 10 µA ICC4f Flash VCC Reset Current (Note 2) VCCf = VCC max, RESET# = VSS ± 0.3 V, WP#/ACC = VCCf ± 0.3 V 0.2 10 µA ICC5f Flash VCC Current Automatic Sleep Mode (Notes 2, 4) VCCf = VCC max, VIH = VCC ± 0.3 V; VIL = VSS ± 0.3 V 0.2 10 µA ICC6f Flash VCC Active Read-While-Program Current (Notes 1, 2) CE#f = VIL, OE# = VIH 21 45 mA ICC7f Flash VCC Active Read-While-Erase Current (Notes 1, 2) CE#f = VIL, OE# = VIH 21 45 mA ICC8f Flash VCC Active Program-While-Erase-Suspended Current (Notes 2, 5) CE#f = VIL, OE#f = VIH 17 35 mA VIL Input Low Voltage –0.2 0.8 V VIH Input High Voltage 2.4 VCC + 0.2 V VHH Voltage for WP#/ACC Program Acceleration and Sector Protection/Unprotection 8.5 9.5 V VID Voltage for Sector Protection, Autoselect and Temporary Sector Unprotect 11.5 12.5 V VOL Output Low Voltage I OL = 2.0 mA, VCCf = VCCs = VCC min 0.45 V VOH1 Output High Voltage IOH = –2.0 mA, VCCf = VCCs = VCC min 0.85 x VCC V VOH2 IOH = –100 µA, VCC = VCC min VCC–0.4 VLKO Flash Low VCC Lock-Out Voltage (Note 5) 2.0 2.5 V

46 Am75DL9608HG November 17, 2003

Figure 10. I CC1 Current vs. Time (Showing Active and Automatic Sleep Currents) Figure 11. Typical I CC1 vs. Frequency

1. T A= –40° to 85°C, otherwise specified.
2. Overshoot: V CC+1.0V if pulse width ≤ 20 ns.
3. Undershoot: –1.0V if pulse width ≤ 20 ns.
4. Overshoot and undershoot are sampled, not 100% tested.
5. Stable power supply required 200 µs before device operation.

Figure 12. Standby Current ISB CMOS

1. At 70 °, for reference only

48 Am75DL9608HG November 17, 2003

Table 24. Test Specifications Figure 13. Test Setup Figure 14. Input Waveforms and Measurement Levels

November 17, 2003 Am75DL9608HG 49 ADVANCE INFORMATION FLASH AC CHARACTERISTICS Pseudo SRAM CE#s Timing

Description

Test Setup All Speeds Unit JEDEC Std —t CCR CE#s Recover Time — Min 0 ns CE#f tCCR tCCR CE1#s CE2s tCCR tCCR

50 Am75DL9608HG November 17, 2003

1. See Figure 11 and Table 24 for test specifications
2. Measurements performed by placing a 50 Ω termination on the data pin with a bias of V CC/2. The time from OE# high to the

0 VRY/BY#

Figure 16. Read Operation Timings

Figure 17. Reset Timings

52 Am75DL9608HG November 17, 2003

Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Flash Erase And Programming Performance” section for more information. Parameter All Speed OptionsJEDEC Std Description Unit tAVAV tWC Write Cycle Time (Note 1) Min 70 ns tAVWL tAS Address Setup Time Min 0 ns tASO Address Setup Time to OE# low during toggle bit polling Min 15 ns tWLAX tAH Address Hold Time Am29DL640H Min ns Am29DL320G 45 tAHT Address Hold Time From CE#f or OE# high during toggle bit polling Min 0 ns tDVWH tDS Data Setup Time Am29DL640H Min ns Am29DL320G 35 tWHDX tDH Data Hold Time Min 0 ns tOEPH Output Enable High during toggle bit polling Min 20 ns tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tWLEL tWS WE# Setup Time (CE#f to WE#) Min 0 ns tELWL tCS CE#f Setup Time Min 0 ns tEHWH tWH WE# Hold Time (CE#f to WE#) Min 0 ns tWHEH tCH CE#f Hold Time Min 0 ns tWLWH tWP Write Pulse Width Min 30 ns tWHDL tWPH Write Pulse Width High Min 30 ns tSR/W Latency Between Read and Write Operations Min 0 ns tWHWH1 tWHWH1 Programming Operation (Note 2) Typ 7 µs tWHWH1 tWHWH1 Accelerated Programming Operation, Word or Byte (Note 2) Typ 4 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.4 sec tVCS VCC Setup Time (Note 1) Min 50 µs tRB Write Recovery Time from RY/BY# Min 0 ns tBUSY Program/Erase Valid to RY/BY# Delay Max 90 ns

54 Am75DL9608HG November 17, 2003

1. SADD = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Flash Write Operation Status”.
2. These waveforms are for the word mode.

Figure 20. Chip/Sector Erase Operation Timings

56 Am75DL9608HG November 17, 2003

cycle, and array data read cycle. Figure 23. Toggle Bit Timings (During Embedded Algorithms) Figure 24. DQ2 vs. DQ6

Figure 25. Temporary Sector Unprotect Timing Diagram

58 Am75DL9608HG November 17, 2003

• For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0, SADD = Sector Address.

November 17, 2003 Am75DL9608HG 59 ADVANCE INFORMATION FLASH AC CHARACTERISTICS Alternate CE#f Controlled Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Flash Erase And Programming Performance” section for more information. Parameter All Speed OptionsJEDEC Std Description Unit tAVAV tWC Write Cycle Time (Note 1) Min 70 ns tAVWL tAS Address Setup Time Min 0 ns tELAX tAH Address Hold Time Min 40 ns tDVEH tDS Data Setup Time Min 40 ns tEHDX tDH Data Hold Time Min 0 ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tWLEL tWS WE# Setup Time Min 0 ns tEHWH tWH WE# Hold Time Min 0 ns tELEH tCP CE#f Pulse Width Min 40 ns tEHEL tCPH CE#f Pulse Width High Min 30 ns tWHWH1 tWHWH1 Programming Operation (Note 2) Typ 7 µs tWHWH1 tWHWH1 Accelerated Programming Operation, Word or Byte (Note 2) Typ 4 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.4 sec

60 Am75DL9608HG November 17, 2003

1. Figure indicates last two bus cycles of a program or erase operation.
2. PA = program address, SADD = sector address, PD = program data.
3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device.
4. Waveforms are for the word mode.

Figure 27. Flash Alternate CE#f Controlled Write (Erase/Program) Operation Timings

When powering up the SRAM, maintain V CCs for 100 µs minimum with CE#1s at VIH.

1. CE1#s = OE# = V IL, CE2s = WE# = VIH, UB#s and/or LB#s = VIL
2. Do not access device with cycle timing shorter than tRC for continuous periods < 10 µs.

Figure 28. Pseudo SRAM Read Cycle—Address Controlled

62 Am75DL9608HG November 17, 2003

1. t HZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output
2. At any given temperature and voltage condition, tHZ (Max.) is less than tLZ (Min.) both for a given device and from device to device
3. Do not access device with cycle timing shorter than tRC for continuous periods < 10 µs.

Figure 29. Pseudo SRAM Read Cycle

1. t CW is measured from CE1#s going low to the end of write.
2. t WR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high.
3. t AS is measured from the address valid to the beginning of write.
4. A write occurs during the overlap (tWP) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when

Figure 30. Pseudo SRAM Write Cycle—WE# Control

64 Am75DL9608HG November 17, 2003

1. t CW is measured from CE1#s going low to the end of write.
2. t WR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high.
3. t AS is measured from the address valid to the beginning of write.
4. A write occurs during the overlap (tWP) of low CE1#s and low WE#. A write begins when CE1#s goes low and WE# goes low when

Figure 31. Pseudo SRAM Write Cycle—CE1#s Control

1. UB#s and LB#s controlled.
2. t CW is measured from CE1#s going low to the end of write.
3. t WR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high.
4. t AS is measured from the address valid to the beginning of write.
5. A write occurs during the overlap (tWP) of low CE#1s and low WE#. A write begins when CE1#s goes low and WE# goes low when

Figure 32. Pseudo SRAM Write Cycle—

66 Am75DL9608HG November 17, 2003

FLASH ERASE AND PROGRAMMING PERFORMANCE Notes: 1. Typical program and erase times assume the following conditions: 25 °C, 3.0 V VCC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 22 for further information on command definitions. 6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles. LATCHUP CHARACTERISTICS Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time. BGA PACKAGE CAPACITANCE Notes: 1. Sampled, not 100% tested. 2. T est conditions TA = 25°C, f = 1.0 MHz. FLASH DATA RETENTION Parameter Typ (Note 1) Max (Note 2) Unit Comments Sector Erase Time 0.4 5 sec Excludes 00h programming prior to erasure (Note 4)Chip Erase Time Am29DL640H 56 sec Am29DL320G 28 Accelerated Word Program Time 4 120 µs Excludes system level overhead (Note 5) Word Program Time 7 210 µs Chip Program Time (Note 3) Am29DL640H 28 84 sec Am29DL320G 14 42 Description Min Max Input voltage with respect to VSS on all pins except I/O pins (including A9, OE#, and RESET#) –1.0 V 12.5 V Input voltage with respect to VSS on all I/O pins –1.0 V V CC + 1.0 V VCC Current –100 mA +100 mA Parameter Symbol Parameter Description Test Setup Typ Max Unit CIN Input Capacitance V IN = 0 11 14 pF COUT Output Capacitance V OUT = 0 12 16 pF CIN2 Control Pin Capacitance V IN = 0 14 16 pF CIN3 WP#/ACC Pin Capacitance V IN = 0 17 20 pF Parameter Description Test Conditions Min Unit Minimum Pattern Data Retention Time 150°C1 0 Y e a r s 125°C2 0 Y e a r s

November 17, 2003 Am75DL9608HG 67 ADVANCE INFORMATION PHYSICAL DIMENSIONS FTA073—73-Ball Fine-Pitch Grid Array 8 x 11.6 mm 3159\\38.14b N/A 11.60 mm x 8.00 mm PACKAGE FTA 073 NOM. --- --- --- 1.40 --- 1.11 MAX. 8.00 BSC. 11.60 BSC. --- MIN. 1.00 0.25 8.80 BSC. 7.20 BSC. 0.35 0.40

0.40 BSC

A2,A3,A4,A5,A6,A7,A8,A9 B2,B3,B4,B7,B8,B9,C2,C9,C10 D1,D10,E1,E10,F5,F6,G5,G6 H1,H10,J1,J10,K1,K2,K9,K10 L2,L3,L4,L7,L8,L9 M2,M3,M4,M5,M6,M7,M8,M9 0.30

0.80 BSC

D JEDEC PACKAGE SYMBOL A MD E n NOTE DEPOPULATED SOLDER BALL MATRIX SIZE E DIRECTION MATRIX FOOTPRINT BALL PITCH

0.80 BSC BALL PITCH

NOTES: 1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. 3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010. 4. e REPRESENTS THE SOLDER BALL GRID PITCH. 5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME.

6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL

DIAMETER IN A PLANE PARALLEL TO DATUM C.

7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A

AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 9. N/A

10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK

MARK, METALLIZED MARK INDENTION OR OTHER MEANS. bO INDEX MARK 73X C0.15 (2X) (2X) C0.15 B A b 0.20 C C 0.15 C CABM 0.08 M D E PIN A1 C TOP VIEW SIDE VIEW CORNER A 0.08 BOTTOM VIEW LM eD CORNER 7SE ABDCEFHG JK eE SD PIN A17

68 Am75DL9608HG November 17, 2003

Revision A (October 6, 2003) Initial release. Revision A+1 (November 17, 2003) CMOS Compatible Changed the test condition for the VOL to IOL = 2.0 mA. Trademarks Copyright © 2003 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification pur poses only and may be trademarks of their respective companies .