AM42BDS6408H

AM42BDS6408H SPANSION | Alldatasheet

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The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig- inally developed the specification, these products will be offered to customers of both AMD and Fujitsu. Continuity of Specifications There is no change to this datasheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary. Continuity of Ordering Part Numbers AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order these products, please use only the Ordering Part Numbers listed in this document. For More Information Please contact your local AMD or Fujitsu sales office for additional information about Spansion memory solutions. Am42BDS6408H Data Sheet Publication Number 30491 Revision A Amendment +3 Issue Date October 23, 2003

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This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. AMD re- serves the right to change or discontinue work on this proposed product without notice. Publication# 30491 Rev: A Amendment: +3 Issue Date: October 23, 2003 Refer to AMD’s Website (www.amd.com) for the latest information. Am42BDS6408H Am29BDS640H 64 Megabit (4 M x 16-Bit) Stacked MultiChip Package (MCP) Flash Memory and SRAM CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory, and 8 Mbit (512 K x 16-Bit) SRAM FLASH DISTINCTIVE CHARACTERISTICS ARCHITECTURAL ADVANTAGES ■ Single 1.8 volt read, program and erase (1.65 to 1.95 volt) ■ Manufactured on 0.13 µm process technology ■ VersatileIO™ (V IO) Feature — Device generates data output voltages and tolerates data input voltages as determined by the voltage on the V IO pin — 1.8V compatible I/O signals — Contact factory for availability of 1.5V compatible I/O signals ■ Simultaneous Read/Write operation — Data can be continuously read from one bank while executing erase/program functions in other bank — Zero latency between read and write operations — Four bank architecture: 8Mb/24Mb/24Mb/8Mb ■ Programable Burst Interface — 2 Modes of Burst Read Operation — Linear Burst: 8, 16, and 32 words with wrap-around — Continuous Sequential Burst ■ SecSiTM (Secured Silicon) Sector region — Up to 128 words accessible through a command sequence — Up to 64 factory-locked words — Up to 64 customer-lockable words ■ Sector Architecture — Sixteen 4 Kword sectors and one hundred twenty-six

32 Kword sectors

— Banks A and D each contain eight 4 Kword sectors and fifteen 32 Kword sectors; Banks B and C each contain forty-eight 32 Kword sectors — Sixteen 4 Kword boot sectors: eight at the top of the address range and eight at the bottom of the address range ■ Minimum 1 million erase cycle guarantee per sector ■ 20-year data retention at 125°C — Reliable operation for the life of the system ■ 89-ball FBGA package PERFORMANCE CHARCTERISTICS ■ Read access times at 66/54 MHz (CL=30 pF) — Burst access times of 11/13.5 ns at industrial temperature range — Synchronous latency of 56/69 ns — Asynchronous random access times of 45/50/55 ns ■ Power dissipation (typical values, C L = 30 pF) — Burst Mode Read: 10 mA — Simultaneous Operation: 25 mA — Program/Erase: 15 mA — Standby mode: 0.2 µA HARDWARE FEATURES ■ Handshaking feature — Provides host system with minimum possible latency by monitoring RDY — Reduced Wait-state handshaking option further reduces initial access cycles required for burst accesses beginning on even addresses ■ Hardware reset input (RESET#) — Hardware method to reset the device for reading array data ■ WP# input — Write protect (WP#) function allows protection of the four highest and four lowest 4 kWord boot sectors, regardless of sector protect status ■ Persistent Sector Protection — A command sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector — Sectors can be locked and unlocked in-system at V CC level ■ Password Sector Protection — A sophisticated sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector using a user-defined 64-bit password ■ ACC input: Acceleration function reduces programming time; all sectors locked when ACC = V IL

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■ CMOS compatible inputs, CMOS compatible outputs ■ Low VCC write inhibit SOFTWARE FEATURES ■ Supports Common Flash Memory Interface (CFI) ■ Software command set compatible with JEDEC 42.4 standards — Backwards compatible with Am29F and Am29LV families ■ Data# Polling and toggle bits — Provides a software method of detecting program and erase operation completion ■ Erase Suspend/Resume — Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation ■ Unlock Bypass Program command — Reduces overall programming time when issuing multiple program command sequences ■ Burst Suspend/Resume — Suspends a burst operation to allow system use of the address and data bus, than resumes the burst at the previous state SRAM FEATURES ■ Power dissipation — Operating: 10 mA typical — Standby: 2 µA ■ CE1s# and CE2 Chip Select ■ Power down features using CE1s# and CE2s ■ Data retention supply voltage: 1.0 to 2.2 volt ■ Byte data control: LB# (DQ7-DQ0), UB#s (DQ15-DQ8)

October 23, 2003 Am42BDS6408H 3 ADVANCE INFORMATION GENERAL DESCRIPTION The Am29BDS640H is a 64 Mbit, 1.8 Volt-only, simultaneous Read/Write, Burst Mode Flash memory device, organized as 4,194,304 words of 16 bits each. This device uses a single VCC of 1.65 to 1.95 V to read, program, and erase the mem- ory array. A 12.0-volt V HH on ACC may be used for faster program performance if desired. At 66 MHz, the device provides a burst access of 11 ns at 30 pF with a latency of 56 ns at 30 pF .At 54 MHz, the device provides a burst access of 13.5 ns at 30 pF with a latency of 69ns at 30 pF . The device operates within the industrial tem- perature range of -40°C to +85°C. The device is offered in the 64-ball FBGA package. The Simultaneous Read/Write architecture provides simul- taneous operation by dividing the memory space into four banks. The device can improve overall system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from another bank, with zero latency. This releases the system from wait- ing for the completion of program or erase operations. The device is divided as shown in the following table: The VersatileIO™ (V IO) control allows the host system to set the voltage levels that the device generates at its data out- puts and the voltages tolerated at its data inputs to the same voltage level that is asserted on the V IO pin. The device uses Chip Enable (CE#), Write Enable (WE#), Address Valid (AVD#) and Output Enable (OE#) to control asynchronous read and write operations. For burst opera- tions, the device additionally requires Ready (RDY), and Clock (CLK). This implementation allows easy interface with minimal glue logic to a wide range of microprocessors/micro- controllers for high performance read operations. The burst read mode feature gives system designers flexibil- ity in the interface to the device. The user can preset the burst length and wrap through the same memory space, or read the flash array in continuous mode. The clock polarity feature provides system designers a choice of active clock edges, eit her rising or falling. The ac- tive clock edge initiates burst accesses and determines when data will be output. The device is entirely command set compatible with the JEDEC 42.4 single-power-supply Flash standard . Com- mands are written to the command register using standard microprocessor write timing. Register contents serve as in- puts to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch ad- dresses and data needed for the programming and erase operations. Reading data out of the device is similar to read- ing from other Flash or EPROM devices. The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. If a read is needed from the SecSi Sector area (One Time Pro- gram area) after an erase suspend, then the user must use the proper command sequence to enter and exit this region. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read boot-up firm- ware from the Flash memory device. The host system can detect whether a program or erase op- eration is complete by using the device status bit DQ7 (Data# Polling) and DQ6/DQ2 (t oggle bits). After a program or erase cycle has been completed, the device automatically returns to reading array data. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data con- tents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low V CC de- tector that automatically inhibits write operations during power transitions. The device also offers two types of data protection at the sector level. When at V IL, WP# locks the four highest and four lowest boot sectors. The device offers two power-saving features. When ad- dresses have been stable for a specified amount of time, the device enters the automatic sleep mode . The system can also place the device into the standby mode . Power con- sumption is greatly reduced in both modes. AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electri- cally erases all bits within a sector simultaneously via Fowler-Nordheim tunnelling. The data is programmed using hot electron injection. Bank Quantity Size A

84 K w o r d s

D 15 32 Kwords

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Table 3. Am42BDS6408H Boot Sector/Sector Block Addresses for Protec- Figure 2. In-System Sector Protection/

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Note: Speed Options ending in “8” and “6” indicate the “reduced wait-state handshaking” option, which speeds initial synchronous accesses for even addresses. Speed Options ending in “9” and “7” indicate the “standard handshaking” option. See the AC Characteristics section of this datasheet for full specifications. Part Number Am42BDS6408H Burst Frequency 66 MHz 54 MHz Speed Option V CC, VIO = 1.65 – 1.95 V E8, E9 E3, E4 D8, D9 D3, D4 FLASH Max Initial Synchronous Access Time, ns (TIACC) Reduced Wait-state Handshaking; Even Address 56 56 69 69 Max Initial Synchronous Access Time, ns (TIACC) Reduced Wait-state Handshaking; Odd Address; or Standard Handshaking 71 71 87.5 87.5 Max Burst Access Time, ns (TBACC) 11 13.5 Max Asynchronous Access Time, ns (TACC) 50 50 55 55 Max CE# Access Time, ns (TCE) Max OE# Access Time, ns (TOE) 11 13.5 SRAM Max Access time, ns (tACC) 7 05 57 0 5 5 Max CE# Access time, ns (tCE) 7 05 57 0 5 5 Max OE# Access, ns (tOE) 3 52 53 5 2 5

October 23, 2003 Am42BDS6408H 7 ADVANCE INFORMATION FLASH MEMORY BLOCK DIAGRAM Input/Output Buffers X-Decoder Y-Decoder Chip Enable Output Enable Logic Erase Voltage Generator PGM Voltage Generator TimerVCC Detector State Control Command Register VCC VSS VSSIO VIO WE# RESET# WP# ACC CE# OE# DQ15–DQ0 Data Latch Y-Gating Cell Matrix Address Latch A21–A0 RDY Buffer RDY Burst State Control Burst Address Counter AVD# CLK

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BLOCK DIAGRAM OF SIMULTANEOUS OPERATION CIRCUIT VSS VCC VIO Bank B Address RESET# ACC WE# CE# AVD# RDY DQ15–DQ0 WP# STATE CONTROL COMMAND REGISTER Bank B X-Decoder Y-Decoder Latches and Control Logic Bank A X-Decoder Y-Decoder Latches and Control Logic DQ15–DQ0 DQ15–DQ0 DQ15–DQ0 DQ15–DQ0 DQ15–DQ0 Bank C Y-Decoder X-Decoder Latches and Control Logic Bank D Y-Decoder X-Decoder Latches and Control Logic OE# Status Control A21–A0 A21–A0 A21–A0 A21–A0 A21–A0 Bank C Address Bank D Address Bank A Address

October 23, 2003 Am42BDS6408H 9 ADVANCE INFORMATION CONNECTION DIAGRAM Special Handling Instructions for FBGA Package Special handling is required for Flash Memory products in FBGA packages. Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compro- mised if the package body is exposed to temperatures above 150°C for prolonged periods of time. G2 G3 G4 G5 G6 G7 G8 F1 F2 F3 F4 F5 F6 F7 F8 E1 E2 E3 E4 E5 E6 E7 E8 D2 D3 D4 D5 D6 D7 D8 C2 C3 C4 C5 C6 C7 C8 B1 B2 B3 B4 B5 B6 B7 B8 A8 A11WE#ACCLB#A7WP#NC A1 A2 A3 A4 A5 A6 A7 A8 NC NCNCNCCLKVSSADV#NC A19 A12CE2sRESET#UB#A6A3 A9 A13A20RDYA18A5A2 A10 A14NCNCA17A4A1NC DQ6 NCNCNCDQ1VSSA0NC DQ13 DQ15DQ4DQ3DQ9OE#CE#f H2 H3 H4 H5 H6 H7 H8 DQ12 DQ7VCCsVCCfDQ10DQ0CE1#s F9 F10 E9 E10 NC A9 A10 NC NC A15 A21 NC NC A16 NC NC VSS J2 J3 J4 J5 J6 J7 J8 DQ5 DQ14NCDQ11DQ2DQ8NC K1 K2 K3 K4 K5 K6 K7 K8 NC NCNCVIOfVSSNCNCNC NC K9 K10 NC NC Flash Only SRAM Only 89-ball Fine-Pitch Ball Grid Array (Top View, Balls Facing Down)

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A18–A0 = 19 Address Inputs (Common) A21–A19 = 3 Address Inputs (Flash) DQ15–DQ0 = 16 Data Inputs/Outputs (Common) CE#f = Chip Enable (Flash) CE1#s = Chip Enable 1 (SRAM) CE2s = Chip Enable 2 (SRAM) OE# = Output Enable (Common) WE# = Write Enable (Common) UB#s = Upper Byte Control (SRAM) LB#s = Lower Byte Control (SRAM) RESET# = Hardware Reset Pin, Active Low VCCf = Flash 1.8 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) V IOf = Input & Output Buffer Power Supply must be tied to VCC. VCCs = SRAM Power Supply VSSIOf = Output Buffer Ground VSS = Device Ground (Common) NC = Pin Not Connected Internally RDY = Ready output; indicates the status of the Burst read. Low = data not valid at expected time. High = data valid. CLK = CLK is not required in asynchronous mode. In burst mode, after the initial word is output, subsequent active edges of CLK increment the internal address counter. AVD# = Address Valid input. Indicates to de- vice that the valid address is present on the address inputs (A21–A0). Low = for asynchronous mode, indi- cates valid address; for burst mode, causes starting address to be latched. High = device ignores address in- puts WP# = Hardware write protect input. At V IL, disables program and erase func- tions in the two outermost sectors. Should be at V IH for all other condi- tions. ACC = At V ID, accelerates programming; automatically places device in un- lock bypass mode. At V IL, locks all sectors. Should be at VIH for all other conditions. LOGIC SYMBOL DQ15–DQ0 A18–A0 CE#f OE# WE# RESET# UB#s RDY WP# A21–A19 LB#s ACC CE1#s CE2s AVD# CLK

October 23, 2003 Am42BDS6408H 11 ADVANCE INFORMATION

ORDERING INFORMATION

The order number (Valid Combination) is formed by the following: Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to con- firm availability of specific valid combinations and to check on newly released combinations. Note: For the Am29BDS640H, the last digit of the speed grade specifies the V IO range of the device. Speed options ending in “8” and “9” (e.g., D8, D9) indicate a 1.8 Volt V IO range. Am42BDS6408 H D 8 I T Tape and Reel T =7 I n c h e s S =1 3 I n c h e s TEMPERATURE RANGE I = Industrial (–40 °C to +85°C) HANDSHAKING OPTIONS + SRAM speed 8 = Reduced wait-state handshaking Enabled + 70 ns SRAM 9 = Standard handshaking + 70 ns SRAM 3 = Reduced Wait-state handshaking Enabled + 55 ns SRAM 4 = Standard handshaking + 55 ns SRAM SPEED E=6 6 M H z D=5 4 M H z PROCESS TECHNOLOGY H = 0.13 um DEVICE NUMBER/DESCRIPTION Am42BDS6408H

64 Megabit (4 M x 16-Bit) CMOS Flash Memory, Simultaneous Read/Write,

Burst Mode Flash Memory, 1.8 Volt-only Read, Program, and Erase

8 Mb (512 K x 16-bit) SRAM

WP# at V IL level protects top and bottom sectors Valid Combinations Flash Burst Frequency (MHz) SRAM Speed (ns)Order Number Package Marking Am42BDS6408HE8 I M420000070 Am42BDS6408HE9 M420000071 Am42BDS6408HD8 M420000072 Am42BDS6408HD9 M420000073 Am42BDS6408HE3 M420000074 Am42BDS6408HE4 M420000075 Am42BDS6408HD3 M420000076 Am42BDS6408HD4 M420000077

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each of these operations in further detail. Table 1. Device Bus Operations Legend: L = Logic 0, H = Logic 1, X = Don’t Care, S = Stable Logic 0 or 1 but no transitions. Note: Default active edge of CLK is the rising edge. addresses and stable CE# to valid data at the outputs. the falling edge of OE# to valid data at the output. operation and linear burst operation of a preset length.

page 30 for further details. with Boundary Crossing,” on page 76. values by a multiple of 64) will not occur. Table 1, “Device Bus Operations,” on page 12. indicates the length of the latency by pulsing low. Table 2. Burst Address Groups back to the first address in the selected address group. inserted (except during the initial access). The RDY pin indicates when data is valid on the bus. new synchronous access (latching of a new address). data and the current state are retained.

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Handshake Burst Suspend/Resume at address 3Eh (or offset from 3Eh),” on page 58, Figure 21, “Reduced Wait-state Handshake Burst Suspend/Resume at address 3Fh (or offset from 3Fh by a multiple of 64),” on page 58, Figure 22, “Standard Handshake Burst Suspend prior to Initial Access,” on page 59, Figure 23, “Standard Handshake Burst Suspend at or after Inital Access,” on page 59, Figure 24, “Standard Handshake Burst Suspend at address 3Fh (starting address 3Dh or earlier),” on page 60, Figure 25, “Standard Hand- shake Burst Suspend at address 3Eh/3Fh (without a valid Initial Access),” on page 60, and Figure 26, “Stan- dard Handshake Burst Suspend at address 3Eh/3Fh (with 1 Access CLK),” on page 61. Burst plus Burst Suspend should not last longer than t RCC without re-latching an address or crossing an address boundary. To resume the burst access, OE# must be re-asserted. The next active CLK edge will resume the burst sequence where it had been sus- pended. See , Figure 27, “Read Cycle for Continuous Suspend,” on page 61. The RDY pin is only controlled by CE#. RDY will remain active and is not placed into a high-impedance state when OE# is de-asserted. Configuration Register The device uses a configuration register to set the various burst parameters: number of wait states, burst read mode, active clock edge, RDY configuration, and synchronous mode active. Reduced Wait-state Handshaking Option The device can be equipped with a reduced wait-state handshaking feature that allows the host system to simply monitor the RDY signal from the device to deter- mine when the initial word of burst data is ready to be read. The host system should use the programmable wait state configuration to set the number of wait states for optimal burst mode operation. The initial word of burst data is indicated by the rising edge of RDY after OE# goes low. The presence of the reduced wait-state handshaking feature may be verified by writing the autoselect command sequence to the device. See “Autoselect Command Sequence” for details. For optimal burst mode performance on devices without the reduced wait-state handshaking option, the host system must set the appropriate number of wait states in the flash device depending on clock frequency and the presence of a boundary crossing. See “Set Configuration Register Command Sequence” section on page 30 section for more information. The device will automatically delay RDY and data by one additional clock cycle when the starting address is odd. The autoselect function allows the host system to determine whether the flash device is enabled for reduced wait-state handshaking. See the “Autoselect Command Sequence” section for more information. Simultaneous Read/Write Operations with Zero Latency This device is capable of reading data from one bank of memory while programming or erasing in another bank of memory. An erase operation may also be suspended to read from or program to another location within the same bank (except the sector being erased). Figure 46, “Back-to-Back Read/Write Cycle Timings,” on page 79 shows how read and write cycles may be initiated for simultaneous operation with zero latency. Refer to the DC Characteristics table for read-while-program and read-while-erase current specifications. Writing Commands/Command Sequences The device has the capability of performing an asyn- chronous or synchronous write operation. While the device is configured in Asynchronous read it is able to perform Asynchronous write operations only. CLK is ignored in the Asynchronous programming mode. When in the Synchronous read mode configuration, the device is able to perform both Asynchronous and Syn- chronous write operations. CLK and WE# address latch is supported in the Synchronous programming mode. During a synchronous write operation, to write a command or command sequence (which includes pro- gramming data to the device and erasing sectors of memory), the system must drive AVD# and CE# to V IL, and OE# to V IH when providing an address to the device, and drive WE# and CE# to VIL, and OE# to VIH when writing commands or data. During an asynchro- nous write operation, the system must drive CE# and WE# to V IL and OE# to VIH when providing an address, command, and data. Addresses are latched on the last falling edge of WE# or CE#, while data is latched on the 1st rising edge of WE# or CE#. The asynchronous and synchronous programing operation is independent of the Set Device Read Mode bit in the Configuration Register (see Table 15, “Configuration Register,” on page 33). The device features an Unlock Bypass mode to facili- tate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word, instead of four. An erase operation can erase one sector, multiple sec- tors, or the entire device. Table 10, “Sector Address Table,” on page 26 indicates the address space that each sector occupies. The device address space is divided into four banks: Banks B and C contain only 32 Kword sectors, while Banks A and D contain both 4 Kword boot sectors in addition to 32 Kword sectors. A

October 23, 2003 Am42BDS6408H 15 ADVANCE INFORMATION “bank address” is the address bits required to uniquely select a bank. Similarly, a “sector address” is the address bits required to uniquely select a sector. I CC2 in the “DC Characteristics” section on page 49 represents the active current specification for the write mode. The AC Characteristics section contains timing specification tables and timing diagrams for write oper- ations. Accelerated Program Operation The device offers accelerated program operations through the ACC function. ACC is primarily intended to allow faster manufacturing throughput at the factory. If the system asserts V HH on this input, the device auto- matically enters the aforementioned Unlock Bypass mode and uses the higher voltage on the input to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing V HH from the ACC input returns the device to normal operation. Note that sectors must be unlocked prior to raising ACC to V HH. Note that the ACC pin must not be at V HH for operations other than accelerated programming, or device damage may result. In addition, the ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. When at VIL, ACC locks all sectors. ACC should be at VIH for all other conditions.

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Table 3. Am42BDS6408H Boot Sector/Sector the old 12 V controlled protection method. operations in the outermost sectors.

October 23, 2003 Am42BDS6408H 17 ADVANCE INFORMATION erate only using Persistent Sector Protection. If the customer decides to use the password method, they must set the Password Mode Locking Bit . This will permanently set the part to operate only using pass- word sector protection. It is important to remember that setting either the Per- sistent Sector Protection Mode Locking Bit or the Password Mode Locking Bit permanently selects the protection mode. It is not possible to switch between the two methods once a locking bit has been set. It is important that one mode is explicitly selected when the device is first programmed, rather than relying on the default mode alone. This is so that it is not possible for a system program or virus to later set the Password Mode Locking Bit, which would cause an unexpected shift from the default Persistent Sector Protection Mode into the Password Protection Mode. The device is shipped with all sectors unprotected. AMD offers the option of programming and protecting sectors at the factory prior to shipping the device through AMD’s ExpressFlash™ Service. Contact an AMD representative for details. It is possible to determine whether a sector is pro- tected or unprotected. See “Autoselect Command Se- quence” section on page 33 for details. Persistent Sector Protection The Persistent Sector Protection method replaces the old 12 V controlled protection method while at the same time enhancing flexibility by providing three dif- ferent sector protection states: ■ Persistently Locked —A sector is protected and cannot be changed. ■ Dynamically Locked—The sector is protected and can be changed by a simple command ■ Unlocked—The sector is unprotected and can be changed by a simple command In order to achieve these states, three types of “bits” are going to be used: Persistent Protection Bit (PPB) A single Persistent (non-volatile) Protection Bit is as- signed to a maximum four sectors ( “Am42BDS6408H Boot Sector/Sector Block Addresses for Protec- tion/Unprotection” section on page 16 ). All 4 Kbyte boot-block sectors have individual sector Persistent Protection Bits (PPBs) for greater flexibility. Each PPB is individually modifiable through the PPB Program Command. Note: If a PPB requires erasure, all of the sector PPBs must first be preprogrammed prior to PPB erasing. All PPBs erase in parallel, unlike programming where in- dividual PPBs are programmable. It is the responsibil- ity of the user to perform the preprogramming operation. Otherwise, an already erased sector PPBs has the potential of being over-erased. There is no hardware mechanism to prevent sector PPBs over-erasure. Persistent Protection Bit Lock (PPB Lock) A global volatile bit. When set to “1”, the PPBs cannot be changed. When cleared (“0”), the PPBs are changeable. There is only one PPB Lock bit per de- vice. The PPB Lock is cleared after power-up or hard- ware reset. There is no command sequence to unlock the PPB Lock. Dynamic Protection Bit (DYB) A volatile protection bit is assigned for each sector. After power-up or hardware reset, the contents of all DYBs is “0”. Each DYB is individually modifiable through the DYB Write Command. When the parts are first shipped, the PPBs are cleared. The DYBs and PPB Lock are defaulted to power up in the cleared state – meaning the PPBs are changeable. When the device is first powered on the DYBs power up cleared (sectors not protected). The Protection State for each sector is determined by the logical OR of the PPB and the DYB related to that sector. For the sectors that have the PPBs cleared, the DYBs control whether or not the sector is protected or unprotected. By issuing the DYB Write command sequences, the DYBs will be set or cleared, thus placing each sector in the protected or unprotected state. These are the so-called Dynamic Locked or Unlocked states. They are called dynamic states because it is very easy to switch back and forth between the protected and un- protected conditions. This allows software to easily protect sectors against inadvertent changes yet does not prevent the easy removal of protection when changes are needed. The DYBs maybe set or cleared as often as needed. The PPBs allow for a more static, and difficult to change, level of protection. The PPBs retain their state across power cycles because they are Non-Volatile. Individual PPBs are set with a command but must all be cleared as a group through a complex sequence of program and erasing commands. The PPBs are also limited to 100 erase cycles. The PBB Lock bit adds an addi tional level of protec- tion. Once all PPBs are programmed to the desired settings, the PPB Lock may be set to “1”. Setting the PPB Lock disables all program and erase commands to the Non-Volatile PPBs. In effect, the PPB Lock Bit locks the PPBs into their current state. The only way to clear the PPB Lock is to go through a power cycle. System boot code can determine if any changes to the

18 Am42BDS6408H October 23, 2003

changes to the PPBs during system operation. tion during system initialization. vice operates normally again. Table 4. Sector Protection Schemes PPB, and PPB lock relating to the status of the sector. whether or not the sector is protected or unprotected. DYB/PPB/PPB lock verify command to the device. place the device in password protection mode. ing a unique 64-bit Password to the device. identical to the Persistent Sector Protection method.

000 Unprotected—PPB and DYB are

001 Unprotected—PPB not

October 23, 2003 Am42BDS6408H 19 ADVANCE INFORMATION grammed password. If they match, the PPB Lock bit is cleared, and the PPBs can be altered. If they do not match, the flash device does nothing. There is a built-in 2 µs delay for each “password check.” This delay is intended to thwart any efforts to run a program that tries all possible combinations in order to crack the password. Password and Password Mode Locking Bit In order to select the Password sector protection scheme, the customer must first program the pass- word. AMD recommends that the password be somehow correlated to the unique Electronic Serial Number (ESN) of the particular flash device. Each ESN is different for every flash device; therefore each pass- word should be different for every flash device. While programming in the password region, the customer may perform Password Verify operations. Once the desired password is programmed in, the customer must then set the Password Mode Locking Bit. This operation achieves two objectives: 1. It permanently sets the device to operate using the Password Protection Mode. It is not possible to re- verse this function. 2. It also disables all further commands to the pass- word region. All program, and read operations are ignored. Both of these objectives are important, and if not care- fully considered, may lead to unrecoverable errors. The user must be sure that the Password Protection method is desired when setting the Password Mode Locking Bit. More importantly, the user must be sure that the password is correct when the Password Mode Locking Bit is set. Due to the fact that read operations are disabled, there is no means to verify what the password is afterwards. If the password is lost after setting the Password Mode Locking Bit, there will be no way to clear the PPB Lock bit. The Password Mode Locking Bit, once set, prevents reading the 64-bit password on the DQ bus and further password programming. The Password Mode Locking Bit is not erasable. Once Password Mode Locking Bit is programmed, the Persistent Sector Protection Lock- ing Bit is disabled from programming, guaranteeing that no changes to the protection scheme are allowed. 64-bit Password The 64-bit Password is located in its own memory space and is accessible through the use of the Pass- word Program and Verify commands (see “Password Program Command” section on page 37 and “Pass- word Verify Command” section on page 37 ). The password function works in conjunction with the Pass- word Mode Locking Bit, which when set, prevents the Password Verify command from reading the contents of the password on the pins of the device. Persistent Protection Bit Lock The Persistent Protection Bit (PPB) Lock is a volatile bit that reflects the state of the Password Mode Lock- ing Bit after power-up reset. If the Password Mode Lock Bit is also set, after a hardware reset (RESET# asserted) or a power-up reset the ONL Y means for clearing the PPB Lock Bit in Password Protection Mode is to issue the Password Unlock command. Suc- cessful execution of the Password Unlock command clears the PPB Lock Bit, allowing for sector PPBs modifications. Asserting RESET#, taking the device through a power-on reset, or issuing the PPB Lock Bit Set command sets the PPB Lock Bit to a “1”. If the Password Mode Locking Bit is not set, including Persistent Protection Mode, the PPB Lock Bit is cleared after power-up or hardware reset. The PPB Lock Bit is set by issuing the PPB Lock Bit Set com- mand. Once set the only means for clearing the PPB Lock Bit is by issuing a hardware or power-up reset. The Password Unlock command is ignored in Persis- tent Protection Mode. High Voltage Sector Protection Sector protection and unprotection may also be imple- mented using programming equipment. The procedure requires high voltage (V ID ) to be placed on the RESET# pin. Refer to Figure 2, “In-System Sector Pro- tection/ Sector Unprotection Algorithms,” on page 21 for details on this procedure. Note that for sector unpro- tect, all unprotected sectors must be first protected prior to the first sector write cycle. Once the Password Mode Locking bit or Persistent Protection Locking bit are set, the high voltage sector protect/unprotect capa- bility is disabled. Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, inde- pendent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# inputs are both held at V CC ± 0.2 V. The device requires standard access time (tCE) for read access, before it is ready to read data. If the device is deselected during erasure or program- ming, the device draws active current until the opera- tion is completed. I CC3 in the “DC Characteristics” section on page 49 represents the standby current specification.

20 Am42BDS6408H October 23, 2003

tion is required to provide new data. sequence, to ensure data integrity. RH after RESET# returns to VIH. ings,” on page 64 for the timing diagram. Figure 1. Temporary Sector Unprotect Operation

1. All protected sectors unprotected (If WP# = V IL,

outermost boot sectors will remain protected).

1. All previously protected sectors are protected once

22 Am42BDS6408H October 23, 2003

tory-locked and customer-locked status of the part. ing commands to the normal address space. Table 5. SecSi gion without raising any device pin to a high voltage. High Voltage Sector Protection section. erase operations in any sector or sector group. ■ When ACC is at VIL, all sectors are locked. tions, or from system noise.

ermost” 4 Kword boot sectors. WE# do not initiate a write cycle. automatically reset to the read mode on power-up. ward-compatible for the specified flash device families. for long-term compatibility. CFI data, the system must write the reset command. device to the autoselect mode. http://www.amd.com/flash/cfi. Table 6. CFI Query Identification String

24 Am42BDS6408H October 23, 2003

Table 7. System Interface String Table 8. Device Geometry Definition

Table 9. Primary Vendor-Specific Extended Query

26 Am42BDS6408H October 23, 2003

Table 10. Sector Address Table

October 23, 2003 Am42BDS6408H 27 ADVANCE INFORMATION Bank C SA39 32 Kwords 100000h-107FFFh SA40 32 Kwords 108000h-10FFFFh SA41 32 Kwords 110000h-117FFFh SA42 32 Kwords 118000h-11FFFFh SA43 32 Kwords 120000h-127FFFh SA44 32 Kwords 128000h-12FFFFh SA45 32 Kwords 130000h-137FFFh SA46 32 Kwords 138000h-13FFFFh SA47 32 Kwords 140000h-147FFFh SA48 32 Kwords 148000h-14FFFFh SA49 32 Kwords 150000h-157FFFh SA50 32 Kwords 158000h-15FFFFh SA51 32 Kwords 160000h-167FFFh SA52 32 Kwords 168000h-16FFFFh SA53 32 Kwords 170000h-177FFFh SA54 32 Kwords 178000h-17FFFFh SA55 32 Kwords 180000h-187FFFh SA56 32 Kwords 188000h-18FFFFh SA57 32 Kwords 190000h-197FFFh SA58 32 Kwords 198000h-19FFFFh SA59 32 Kwords 1A0000h-1A7FFFh SA60 32 Kwords 1A8000h-1AFFFFh SA61 32 Kwords 1B0000h-1B7FFFh SA62 32 Kwords 1B8000h-1BFFFFh SA63 32 Kwords 1C0000h-1C7FFFh SA64 32 Kwords 1C8000h-1CFFFFh SA65 32 Kwords 1D0000h-1D7FFFh SA66 32 Kwords 1D8000h-1DFFFFh SA67 32 Kwords 1E0000h-1E7FFFh SA68 32 Kwords 1E8000h-1EFFFFh SA69 32 Kwords 1F0000h-1F7FFFh SA70 32 Kwords 1F8000h-1FFFFFh Bank Sector Sector Size Address Range

28 Am42BDS6408H October 23, 2003

SA71 32 Kwords 200000h-207FFFh SA72 32 Kwords 208000h-20FFFFh SA73 32 Kwords 210000h-217FFFh SA74 32 Kwords 218000h-21FFFFh SA75 32 Kwords 220000h-227FFFh SA76 32 Kwords 228000h-22FFFFh SA77 32 Kwords 230000h-237FFFh SA78 32 Kwords 238000h-23FFFFh SA79 32 Kwords 240000h-247FFFh SA80 32 Kwords 248000h-24FFFFh SA81 32 Kwords 250000h-257FFFh SA82 32 Kwords 258000h-25FFFFh SA83 32 Kwords 260000h-267FFFh SA84 32 Kwords 268000h-26FFFFh SA85 32 Kwords 270000h-277FFFh SA86 32 Kwords 278000h-27FFFFh SA87 32 Kwords 280000h-287FFFh SA88 32 Kwords 288000h-28FFFFh SA89 32 Kwords 290000h-297FFFh SA90 32 Kwords 298000h-29FFFFh SA91 32 Kwords 2A0000h-2A7FFFh SA92 32 Kwords 2A8000h-2AFFFFh SA93 32 Kwords 2B0000h-2B7FFFh SA94 32 Kwords 2B8000h-2BFFFFh SA95 32 Kwords 2C0000h-2C7FFFh SA96 32 Kwords 2C8000h-2CFFFFh SA97 32 Kwords 2D0000h-2D7FFFh SA98 32 Kwords 2D8000h-2DFFFFh SA99 32 Kwords 2E0000h-2E7FFFh SA100 32 Kwords 2E8000h-2EFFFFh SA101 32 Kwords 2F0000h-2F7FFFh SA102 32 Kwords 2F8000h-2FFFFFh Bank Sector Sector Size Address Range

October 23, 2003 Am42BDS6408H 29 ADVANCE INFORMATION Bank B SA103 32 Kwords 300000h-307FFFh SA104 32 Kwords 308000h-30FFFFh SA105 32 Kwords 310000h-317FFFh SA106 32 Kwords 318000h-31FFFFh SA107 32 Kwords 320000h-327FFFh SA108 32 Kwords 328000h-32FFFFh SA109 32 Kwords 330000h-337FFFh SA110 32 Kwords 338000h-33FFFFh SA111 32 Kwords 340000h-347FFFh SA112 32 Kwords 348000h-34FFFFh SA113 32 Kwords 350000h-357FFFh SA114 32 Kwords 358000h-35FFFFh SA115 32 Kwords 360000h-367FFFh SA116 32 Kwords 368000h-36FFFFh SA117 32 Kwords 370000h-377FFFh SA118 32 Kwords 378000h-37FFFFh Bank A SA119 32 Kwords 380000h-387FFFh SA120 32 Kwords 388000h-38FFFFh SA121 32 Kwords 390000h-397FFFh SA122 32 Kwords 398000h-39FFFFh SA123 32 Kwords 3A0000h-3A7FFFh SA124 32 Kwords 3A8000h-3AFFFFh SA125 32 Kwords 3B0000h-3B7FFFh SA126 32 Kwords 3B8000h-3BFFFFh SA127 32 Kwords 3C0000h-3C7FFFh SA128 32 Kwords 3C8000h-3CFFFFh SA129 32 Kwords 3D0000h-3D7FFFh SA130 32 Kwords 3D8000h-3DFFFFh SA131 32 Kwords 3E0000h-3E7FFFh SA132 32 Kwords 3E8000h-3EFFFFh SA133 32 Kwords 3F0000h-3F7FFFh SA134 4 Kwords 3F8000h-3F8FFFh SA135 4 Kwords 3F9000h-3F9FFFh SA136 4 Kwords 3FA000h-3FAFFFh SA137 4 Kwords 3FB000h-3FBFFFh SA138 4 Kwords 3FC000h-3FCFFFh SA139 4 Kwords 3FD000h-3FDFFFh SA140 4 Kwords 3FE000h-3FEFFFh SA141 4 Kwords 3FF000h-3FFFFFh Bank Sector Sector Size Address Range

30 Am42BDS6408H October 23, 2003

Program or Embedded Erase algorithm. Command” section on page 33 for more information. with Latched Addresses,” on page 63 show the timings. must be set before the device will enter burst mode. Figure 3. Synchronous/Asynchronous State asynchronous mode, “0” for synchronous mode. after AVD# is driven active before data will be available. related to the clock frequency.

Table 11. Programmable Wait State Settings

1. Upon power-up or hardware reset, the default setting is
2. RDY will default to being active with data when the Wait

State Setting is set to a total initial access cycle of 2. (wait states) for various conditions. Table 12. Wait States for Reduced wait-state

1. If the latched address is 3Eh or 3Fh (or an address offset

cycles to the values listed.

1. In the 8-, 16-, and 32-word burst modes, the address

addresses offset from 3Fh by a multiple of 64).

1. T ypical initial access cycles may vary depending on

flash device depending on the clock frequency.

110 R e s e r v e d

111 R e s e r v e d

32 Am42BDS6408H October 23, 2003

Table 13. Wait States for Standard Handshaking which are multiples of 3Fh). Sequence” section on page 33 for more information. device and then advances to the next 8 word boundary. Table 14. Read Mode Settings ting; “1” for rising active, “0” for falling active. OH whenever there is valid data on the outputs. chronous mode, RDY is an open-drain output.

Table 15. Configuration Register Note:Device will be in the default state upon power-up or hardware reset. don’t cares for this command. until the operation is complete. before programming begins (prior to the third cycle). until the operation is complete. sequence cycles in an autoselect command sequence. and determine whether or not a sector is protected. mands to other banks will return data from the array.

34 Am42BDS6408H October 23, 2003

SA represents the sector address. The device ID is read in three cycles. The system must write the reset command to return to the read mode (or erase-suspend-read mode if the bank was previously in Erase Suspend). Enter SecSi™ Sector/Exit SecSi Sector Command Sequence The SecSi Sector region provides a secured data area containing a random, eight word electronic serial num- ber (ESN). The system can access the SecSi Sector region by issuing the three-cycle Enter SecSi Sector command sequence. The device continues to access the SecSi Sector region until the system issues the four-cycle Exit SecSi Sector command sequence. The Exit SecSi Sector command sequence returns the de- vice to normal operation. The SecSi Sector is not ac- cessible when the device is executing an Embedded Program or embedded Erase algorithm. Table 16, “Command Definitions,” on page 40 shows the address and data requirements for both command sequences. Program Command Sequence Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Table 16, “Command Defini- tions,” on page 40 shows the address and data require- ments for the program command sequence. When the Embedded Program algorithm is complete, that bank then returns to the read mode and addresses are no longer latched. The system can determine the status of the program operation by monitoring DQ7 or DQ6/DQ2. Refer to the “Write Operation Status” section on page 43 for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once that bank has returned to the read mode, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from “0” back to a “1.” Attempting to do so may cause that bank to set DQ5 = 1, or cause the DQ7 and DQ6 status bit to indicate the operation was successful. However, a succeeding read will show that the data is still “0.” Only erase operations can convert a “0” to a “1.” Unlock Bypass Command Sequence The unlock bypass feature allows the system to prima- rily program to a bank faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is pro- grammed in the same manner. This mode dispenses with the initial two unlock cycles required in the stan- dard program command sequence, resulting in faster total programming time. The host system may also ini- tiate the chip erase and sector erase sequences in the unlock bypass mode. The erase command sequences are four cycles in length instead of six cycles. Table 16, “Command Definitions,” on page 40 shows the require- ments for the unlock bypass command sequences. During the unlock bypass mode, only the Read, Unlock Bypass Program, Unlock Bypass Sector Erase, Unlock Bypass Chip Erase, and Unlock Bypass Reset com- mands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the bank address and the data 90h. The second cycle need only contain the data 00h. The bank then returns to the read mode. Description Address Read Data Manufacturer ID (BA) + 00h 0001h Device ID, Word 1 (BA) + 01h 227Eh Device ID, Word 2 (BA) + 0Eh 221Eh Device ID, Word 3 (BA) + 0Fh 2201h Sector Protection Verification (SA) + 02h 0001 (locked), 0000 (unlocked) Indicator Bits (BA) + 03h DQ15 - DQ8 = 0 DQ7: Factory Lock Bit 1 = Locked, 0 = Not Locked DQ6: Customer Lock Bit 1 = Locked, 0 = Not Locked DQ5: Handshake Bit 1 = Reduced Wait-state Handshake, 0 = Standard Handshake

36 Am42BDS6408H October 23, 2003

The interrupts can be re-enabled after the last Sector Erase command is written. Any command other than Sector Erase or Erase Suspend during the time-out period resets that bank to the read mode. The system must rewrite the command sequence and any addi- tional addresses and commands. The system can monitor DQ3 to determine if the sector erase timer has timed out (See “DQ3: Sector Erase Timer” section on page 46.) The time-out begins from the rising edge of the final WE# pulse in the command sequence. When the Embedded Erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. Note that while the Embedded Erase operation is in progress, the system can read data from the non-erasing bank. The system can determine the status of the erase operation by reading DQ7 or DQ6/DQ2 in the erasing bank. Refer to the “Write Operation Status” section on page 43 for information on these status bits. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. However, note that a hardware reset immediately terminates t he erase operation. If that occurs, the sector erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. The host system may also initiate the sector erase command sequence while the device is in the unlock bypass mode. The command sequence is four cycles cycles in length instead of six cycles. Figure 5, “Erase Operation,” on page 37 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations table in the Figure , “AC Characteristics,” on page 65 for parameters and timing diagrams. Erase Suspend/Erase Resume Commands The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. The bank address is required when writing this command. This command is valid only during the sector erase operation, including the minimum 50 µs time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. When the Erase Suspend command is written during the sector erase operation, the device requires a maximum of 20 µs to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immedi- ately terminates the time-out period and suspends the erase operation. After the erase operation has been suspended, the bank enters the erase-suspend-read mode. The system can read data from or program data to any sector not selected for erasure. (The device “erase sus- pends” all sectors selected for erasure.) Reading at any address within erase-suspended sectors produces status information on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. Refer to the Figure , “Write Operation Status,” on page 43 for information on these status bits. After an erase-suspended program operation is com- plete, the bank returns to the erase-suspend-read mode. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. Refer to the “Write Operation Status” section on page 43 for more information. In the erase-suspend-read mode, the system can also issue the autoselect command sequence. Refer to the “Am42BDS6408H Boot Sector/Sector Block Addresses for Protection/Unprotection” section on page 16 and “Autoselect Command Sequence” section on page 33 for details. To resume the sector erase operation, the system must write the Erase Resume command. The bank address of the erase-suspended bank is required when writing this command. Further writes of the Resume command

written after the chip has resumed erasing. Figure 5. Erase Operation ways drive all F’s onto the DQ data bus. ation when the Password Verify command is executed. command returns the device back to normal operation. word Mode Locking Bit from ever being programmed. mand should be reissued to improve program margin. programming, Simultaneous Operation is disabled.

1. See Table 16 for erase command sequence.
2. See the section on DQ3 for information on the sector

38 Am42BDS6408H October 23, 2003

SecSi Sector Protection Bit Program Command The SecSi Sector Protection Bit Program Command programs the SecSi Sector Protection Bit, which pre- vents the SecSi sector memory from being cleared. If the SecSi Sector Protection Bit is verified as pro- grammed without margin, the SecSi Sector Protection Bit Program Command should be reissued to improve program margin. Exiting the V CC-level SecSi Sector Protection Bit Program Command is accomplished by writing the Read/Reset command. PPB Lock Bit Set Command The PPB Lock Bit Set command is used to set the PPB Lock bit if it is cleared either at reset or if the Password Unlock command was successfully exe- cuted. There is no PPB Lock Bit Clear command. Once the PPB Lock Bit is set, it cannot be cleared un- less the device is taken through a power-on clear or the Password Unlock command is executed. Upon set- ting the PPB Lock Bit, the PPBs are latched into the DYBs. If the Password Mode Locking Bit is set, the PPB Lock Bit status is reflected as set, even after a power-on reset cycle. Exiting the PPB Lock Bit Set command is accomplished by writing the Read/Reset command, only while in the Persistent Sector Protec- tion Mode. DYB Write Command The DYB Write command is used to set or clear a DYB for a given sector. The high order address bits (A21–A12) are issued at the same time as the code 01h or 00h on DQ7-DQ0. All other DQ data bus pins are ignored during the data write cycle. The DYBs are modifiable at any time, regardless of the state of the PPB or PPB Lock Bit. The DYBs are cleared at power-up or hardware reset. Exiting the DYB Write command is accomplished by writing the Read/Reset command. Password Unlock Command The Password Unlock command is used to clear the PPB Lock Bit so that the PPBs can be unlocked for modification, thereby allowing the PPBs to become ac- cessible for modification. The exact password must be entered in order for the unlocking function to occur. This command cannot be issued any faster than 2 µs at a time to prevent a hacker from running through the all 64-bit combinations in an attempt to correctly match a password. If the command is issued before the 2 µs execution window for each portion of the unlock, the command will be ignored. The Password Unlock function is accomplished by writing Password Unlock command and data to the de- vice to perform the clearing of the PPB Lock Bit. The password is 64 bits long, so the user must write the Password Unlock command 4 times. A1 and A0 are used for matching. Writing the Password Unlock com- mand is not address order specific. The lower address A1–A0= 00, the next Password Unlock command is to A1–A0= 01, then to A1–A0= 10, and finally to A1–A0= 11. Once the Password Unlock command is entered for all four words, the RDY pin goes LOW indicating that the device is busy. Approximately 1uSec is required for each portion of the unlock. Once the first portion of the password unlock completes (RDY is not driven and DQ6 does not toggle when read), the Password Un- lock command is issued again, only this time with the next part of the password. Four Password Unlock com- mands are required to successfully clear the PPB Lock Bit. As with the first Password Unlock command, the RDY signal goes LOW and reading the device re- sults in the DQ6 pin toggling on successive read oper- ations until complete. It is the responsibility of the microprocessor to keep track of the number of Pass- word Unlock commands, the order, and when to read the PPB Lock bit to confirm successful password un- lock. In order to relock the device into the Password Mode, the PPB Lock Bit Set command can be re-is- sued. PPB Program Command The PPB Program command is used to program, or set, a given PPB. Each PPB is individually pro- grammed (but is bulk erased with the other PPBs). The specific sector address (A21–A12) are written at the same time as the program command 60h with A6 = 0. If the PPB Lock Bit is set and the corresponding PPB is set for the sector, the PPB Program command will not execute and the command will time-out without programming the PPB. After programming a PPB, two additional cycles are needed to determine whether the PPB has been pro- grammed with margin. If the PPB has been pro- grammed without margin, the program command should be reissued to improve the program margin. The PPB Program command does not follow the Em- bedded Program algorithm. All PPB Erase Command The All PPB Erase command is used to erase all PPBs in bulk. There is no means for individually eras- ing a specific PPB. Unlike the PPB program, no spe- cific sector address is required. However, when the PPB erase command is written (60h) and A6 = 1, all Sector PPBs are erased in parallel. If the PPB Lock Bit is set the ALL PPB Erase command will not execute and the command will time-out without erasing the PPBs. After erasing the PPBs, two additional cycles are needed to determine whether the PPB has been erased with margin. If the PPBs has been erased with-

October 23, 2003 Am42BDS6408H 39 ADVANCE INFORMATION out margin, the erase command should be reissued to improve the program margin. It is the responsibility of the user to preprogram all PPBs prior to issuing the All PPB Erase command. If the user attempts to erase a cleared PPB, over-era- sure may occur making it difficult to program the PPB at a later time. Also note that the total number of PPB program/erase cycles is limited to 100 cycles. Cycling the PPBs beyond 100 cycles is not guaranteed. DYB Write Command The DYB Write command is used for setting the DYB, which is a volatile bit that is cleared at hardware reset. There is one DYB per sector. If the PPB is set, the sec- tor is protected regardless of the value of the DYB. If the PPB is cleared, setting the DYB to a 1 protects the sector from programs or erases. Since this is a volatile bit, removing power or resetting the device will clear the DYBs. PPB Status Command The programming of the PPB for a given sector can be verified by writing a PPB status verify command to the device. PPB Lock Bit Status Command The programming of the PPB Lock Bit for a given sec- tor can be verified by writing a PPB Lock Bit status ver- ify command to the device. DYB Status Command The programming of the DYB for a given sector can be verified by writing a DYB Status command to the de- vice.

40 Am42BDS6408H October 23, 2003

Table 16. Command Definitions

October 23, 2003 Am42BDS6408H 41 ADVANCE INFORMATION Legend: X = Don’t care RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. Addresses latch on the rising edge of the AVD# pulse or active edge of CLK which ever comes first. PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first. SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A21–A12 uniquely select any sector. BA = Address of the bank (A21, A20, A19) that is being switched to autoselect mode, is in bypass mode, or is being erased. SLA = Address of the sector to be locked. Set sector address (SA) and either A6 = 1 for unlocked or A6 = 0 for locked. CR = Configuration Register address bits A19–A12. OW = Address (A7–A0) is (00011010). PD3–PD0 = Password Data. PD3–PD0 present four 16 bit combinations that represent the 64-bit Password PWA = Password Address. Address bits A1 and A0 are used to select each 16-bit portion of the 64-bit entity. PWD = Password Data. PL = Address (A7-A0) is (00001010) RD(0) = DQ0 protection indicator bit. If protected, DQ0 = 1, if unprotected, DQ0 = 0. RD(1) = DQ1 protection indicator bit. If protected, DQ1 = 1, if unprotected, DQ1 = 0. SL = Address (A7-A0) is (00010010) WD= Write Data. See “Configuration Register” definition for specific write data WP = Address (A7-A0) is (00000010) Notes: 1. See Table 1 for description of bus operations. 2. All values are in hexadecimal. 3. Except for the following, all bus cycles are write cycle: read cycle, fourth through sixth cycles of the Autoselect commands, fourth cycle of the configuration register verify and password verify commands, and any cycle reading at RD(0) and RD(1). 4. Data bits DQ15–DQ8 are don’t care in command sequences, except for RD, PD, WD, PWD, and PD3-PD0. 5. Unless otherwise noted, address bits A21–A12 are don’t cares. 6. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. The system must write the reset command to return the device to reading array data. 7. No unlock or command cycles required when bank is reading array data. 8. The Reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in Erase Suspend) when a bank is in the autoselect mode, or if DQ5 goes high (while the bank is providing status information) or performing sector lock/unlock. 9. The fourth cycle of the autoselect command sequence is a read cycle. The system must provide the bank address. See the Autoselect Command Sequence section for more information. 10. The data is 0000h for an unlocked sector and 0001h for a locked sector 11. DQ15 - DQ8 = 0, DQ7: Factory Lock Bit (1 = Locked, 0 = Not Locked), DQ6: Customer Lock Bit (1 = Locked, 0 = Not Locked), DQ5: Handshake Bit (1 = Reduced wait-state Handshake, 0 = Standard Handshake), DQ4 - DQ0 = 0 12. The Unlock Bypass command sequence is required prior to this command sequence. 13. The Unlock Bypass Reset command is required to return to reading array data when the bank is in the unlock bypass mode. PPB Command s PPB Program (Notes 18, 19, 21) 6 555 AA 2AA 55 555 60 (SA) + WP 68 (SA) + WP 48 XX RD (0) All PPB Erase (Notes 18, 19, 22, 24) 6 555 AA 2AA 55 555 60 WP 60 WP 40 XX RD (0) PPB Status (Note 25) 4 555 AA 2AA 55 (BA) 555 90 (SA) X02 RD (0) PPB Lock Bit PPB Lock Bit Set 3 555 AA 2AA 55 555 78 PPB Lock Bit Status (Note 19) 4 555 AA 2AA 55 (BA) 555 58 SA RD (1) DYB DYB Write 4 555 AA 2AA 55 555 48 SA X1 DYB Erase 4 555 AA 2AA 55 555 48 SA X0 DYB Status 4 555 AA 2AA 55 (BA) 555 58 SA RD (0) Password Protection Mode Locking Bit Program (Notes 18, 19, 21) 6 555 AA 2AA 55 555 60 PL 68 PL 48 PL RD (0) Persistent Protection Mode Locking Bit Program (Notes 18, 19, 21) 6 555 AA 2AA 55 555 60 SL 68 SL 48 SL RD (0) Password Protection Mode Locking Bit Read (Notes 18, 19, 21) 4 555 AA 2AA 55 555 60 PL RD (0) Persistent Protection Mode Locking Bit Read (Notes 18, 19, 21) 4 555 AA 2AA 55 555 60 SL RD (0) Command Sequence (Note 1) Cycles Bus Cycles (Notes 1–6) First Second Third Fourth Fifth Sixth Seventh Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

42 Am42BDS6408H October 23, 2003

1. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation, and requires the bank address. 15. The Erase Resume command is valid only during the Erase Suspend mode, and requires the bank address. 16. See “Set Configuration Register Command Sequence” for details. 17. Command is valid when device is ready to read array data or when device is in autoselect mode. 18. The Reset command returns the device to reading the array. 19. Regardless of CLK and AVD# interaction or Control Register bit 15 setting, command mode verifies are always asynchronous read operations. 20. ACC must be at V HH during the entire operation of this command 21. The fourth cycle progra ms the addressed locking bit. The fifth and sixth cycles are used to validate whether the bit has been fully programmed. If DQ0 (in the sixth cycle) reads 0, the program command must be issued and verified again. 22. The fourth cycle erases all PPBs. The fifth and sixth cycles are used to validate whether the bits have been fully erased. If DQ0 (in the sixth cycle) reads 1, the erase command must be issued and verified again. 23. The entire four bus-cycle sequence must be entered for each portion of the password. 24. Before issuing the erase command, all PPBs should be programmed in order to prevent over-erasure of PPBs. 25. In the fourth cycle, 01h indicates PPB set; 00h indicates PPB not set.

erase operation is complete or in progress. edge of the final WE# pulse in the command sequence. Suspend mode, Data# Polling produces a “1” on DQ7. sector, the status may not be valid.

1. VA = Valid address for programming. During a sector

address is any non-protected sector address.

1. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5. Figure 6. Data# Polling Algorithm

44 Am42BDS6408H October 23, 2003

RDY: Ready The RDY is a dedicated output that, when the device is configured in the Synchronous mode, indicates (when at logic low) the system should wait 1 clock cycle before expecting the next word of data. The RDY pin is only controlled by CE#. Using the RDY Configuration Command Sequence, RDY can be set so that a logic low indicates the system should wait 2 clock cycles before expecting valid data. The following conditions cause the RDY output to be low: during the initial access (in burst mode), and after the boundary that occurs every 64 words beginning with the 64th address, 3Fh. When the device is configured in Asynchronous Mode, the RDY is an open-drain output pin which indicates whether an Embedded Algorithm is in progress or com- pleted. The RDY status is valid after the rising edge of the final WE# pulse in the command sequence. If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is in high imped- ance (Ready), the device is in the read mode, the standby mode, or in the erase-suspend-read mode. Table 18, “Write Operation Status,” on page 47 shows the outputs for RDY . DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address in the same bank, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100 µs, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are pro- tected. The system can use DQ6 and DQ2 together to deter- mine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling). If a program address falls within a protected sector, DQ6 toggles for approximately 1 ms after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. See the following for additional information: Figure 7, “Toggle Bit Algorithm,” on page 45, “DQ6: Toggle Bit I” on page 44 , Figure 38, “Toggl e Bit Timings (During Embedded Algorithm),” on page 72 (toggle bit timing diagram), and Table 17, “DQ6 and DQ2 Indica- tions,” on page 46. Toggle Bit I on DQ6 requires either OE# or CE# to be de-asserted and reasserted to show the change in state.

Figure 7. Toggle Bit Algorithm page 46 to compare outputs for DQ2 and DQ6. Table 17, “DQ6 and DQ2 Indications,” on page 46.

46 Am42BDS6408H October 23, 2003

Table 17. DQ6 and DQ2 Indications DQ7–DQ0 on the following read cycle. Bit Algorithm,” on page 45). the erase-suspend-program mode). applies after each additional sector erase command. be less than 50 µs, the system need not monitor DQ3. programming, at any address, toggles, does not toggle. selected for erasure, toggles, also toggles. selected for erasure, toggles, does not toggle. selected for erasure, does not toggle, toggles. from any sector not selected for erasure. erase suspend at any address, toggles, is not applicable.

device will accept additional sector erase commands. last command might not have been accepted. Table 18. Write Op eration Status

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

Refer to the section on DQ5 for more information.

1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
2. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm

is in progress. The device outputs array data if the system addresses a non-busy bank.

1. The system may read either asynchronously or synchronously (burst) while in erase suspend.
2. The RDY pin acts a dedicated output to indicate the status of an embedded erase or program operation is in progress. This

is available in the Asynchronous mode only.

48 Am42BDS6408H October 23, 2003

1. Minimum DC voltage on input or I/Os is –0.5 V . During

periods up to 20 ns. See Figure 9.

1. No more than one output may be shorted to ground at a
2. Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device. in the operational sections of this data sheet is not implied. tions for extended periods may affect device reliability. Figure 8. Maximum Negative Figure 9. Maximum Positive tionality of the device is guaranteed.

October 23, 2003 Am42BDS6408H 49 ADVANCE INFORMATION DC CHARACTERISTICS CMOS COMPATIBLE Note: 1. Maximum I CC specifications are tested with VCC = VCCmax. 2. V IO= VCC 3. The I CC current listed is typically less than 2 mA/MHz, with OE# at VIH. 4. I CC active while Embedded Erase or Embedded Program is in progress. 5. Device enters automatic sleep mode when addresses are stable for tACC + 60 ns. Typical sleep mode current is equal to ICC3. 6. Total current during accelerated programming is the sum of V ACC and VCC currents. Parameter Description Test Conditions Note: 1 & 2 Min Typ Max Unit ILI Input Load Current V IN = VSS to VCC, VCC = VCCmax ±1 µA ILO Output Leakage Current V OUT = VSS to VCC, VCC = VCCmax ±1 µA ICCB VCC Active burst Read Current CE# = VIL, OE# = VIH, WE# = VIH, burst length = 8

54 MHz 9 17 mA

CE# = VIL, OE# = VIH, WE# = VIH, burst length = 16 54 MHz 8 15.5 mA CE# = VIL, OE# = VIH, WE# = VIH, burst length = Continuous

54 MHz 7 14 mA

CE# = VIL, OE# = VIH, WE# = VIH, burst length = 8 50 200 µA IIO1 VIO Non-active Output OE# = V IH 0.2 10 µA ICC1 VCC Active Asynchronous Read Current (Note 3) CE# = VIL, OE# = VIH, WE# = VIH

10 MHz TBD TBD mA

5 MHz 12 16 mA

1 MHz 3.5 5 mA ICC2 VCC Active Write Current (Note 4) CE# = V IL, OE# = VIH, ACC = VIH 15 40 mA ICC3 VCC Standby Current (Note 5) CE# = RESET# = V CC ± 0.2 V 1 40 µA ICC4 VCC Reset Current RESET# = V IL, CLK = VIL 14 0 µ A ICC5 VCC Active Current (Read While Write) CE# = VIL, OE# = VIH 25 60 mA ICC6 VCC Sleep Current CE# = V IL, OE# = VIH 14 0 µ A IACC Accelerated Program Current (Note 6) CE# = VIL, OE# = VIH, VACC = 12.0 ± 0.5 V VACC 71 5 m A VCC 51 0 m A VIL Input Low Voltage VIO = 1.8 V –0.4 0.4 V VIO = 1.5 V TBD TBD VIH Input High Voltage VIO = 1.8 V V IO – 0.4 V IO + 0.4 VIO = 1.5 V TBD TBD V VOL Output Low Voltage I OL = 100 µA, VIO = VCC = VCC min 0.1 V VOH Output High Voltage I OH = –100 µA, VIO = VCC = VCC min VIO – 0.1 V VID Voltage for Autoselect and Temporary Sector Unprotect VCC = 1.8 11.5 12.5 V VHH Voltage for Accelerated Program 11.5 12.5 V VLKO Low VCC Lock-out Voltage 1.0 1.4 V

50 Am42BDS6408H October 23, 2003

Notes: 1. Typical values measured at V CC = 2.0 V, TA = 25°C. Not 100% tested. 2. Undershoot is –1.0 V when pulse width ≤ 20 ns. 3. Overshoot is V CC + 1.0 V when pulse width ≤ 20 ns. 4. Overshoot and undershoot are sampled, not 100% tested. SRAM DC AND OPERATING CHARACTERISTICS Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit ILI Input Leakage Current V IN = VSS to VCC –1.0 1.0 µA ILO Output Leakage Current CE1#s = VIH, CE2s = VIL or OE# = VIH or WE# = VIL, VIO= VSS to VCC –1.0 1.0 µA ICC Operating Power Supply Current IIO = 0 mA, CE1#s = VIL, CE2s = WE# = VIH, VIN = VIH or VIL 5m A ICC1s Average Operating Current Cycle time = 1 µs, 100% duty, IIO = 0 mA, CE1#s ≤ 0.2 V, CE2 ≥ VCC – 0.2 V, VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V 15 m A ICC2s Average Operating Current Cycle time = Min., IIO = 0 mA, 100% duty, CE1#s = VIL, CE2s = VIH, VIN = VIL = or VIH 81 5 m A VOL Output Low Voltage I OL = 0.1 mA 0.2 V VOH Output High Voltage I OH = –0.1 mA 1.4 V ISB1 Standby Current (CMOS) CE1#s ≥ VCC – 0.2 V, CE2 ≥ VCC – 0.2 V (CE1#s controlled) or CE2 ≤ 0.2 V (CE2s controlled), CIOs = V SS or VCC, Other input = 0 ~ VCC 22 5 µ A VIL Input Low Voltage –0.2 (Note 2) 0.4 V VIH Input High Voltage 1.4 VCC+0. (Note 3) V

52 Am42BDS6408H October 23, 2003

Figure 12. V CC Power-up Diagram

October 23, 2003 Am42BDS6408H 53 ADVANCE INFORMATION Synchronous/Burst Read (VIO = 1.8 V) Notes: 1. Addresses are latched on the first of either the active edge of CLK or the rising edge of AVD#. 2. Please contact AMD for availability of V IO = 1.5 V devices. Parameter

Description

E6, E7, E8, E9 (66 MHz) D6, D7, D8, D9 (54 MHz) UnitJEDEC Standard tIACC Latency (Even address in Reduced wait-state Handshake mode) Max 56 69 ns tIACC Latency (Standard Handshake or Odd address in Reduced wait-state Handshake mode Max 71 87.5 ns tBACC Burst Access Time Valid Clock to Output Delay Max 11 13.5 ns tACS Address Setup Time to CLK (Note 1) Min 4 5 ns tACH Address Hold Time from CLK (Note 1) Min 6 7 ns tBDH Data Hold Time from Next Clock Cycle Min 3 4 ns tCR Chip Enable to RDY Valid Max 11 13.5 ns tOE Output Enable to Output Valid Max 11 13.5 ns tCEZ Chip Enable to High Z Max 8 10 ns tOEZ Output Enable to High Z Max 8 10 ns tCES CE# Setup Time to CLK Min 4 5 ns tRDYS RDY Setup Time to CLK Min 4 5 ns tRACC Ready Access Time from CLK Max 11 13.5 ns tAAS Address Setup Time to AVD# (Note 1) Min 4 5 ns tAAH Address Hold Time to AVD# (Note 1) Min 6 7 ns tCAS CE# Setup Time to AVD# Min 0 ns tAVC AVD# Low to CLK Min 4 5 ns tAVD AVD# Pulse Min 10 12 ns tACC Access Time Max 50 55 ns tCKA CLK to access resume Max 11 13.5 ns tCKZ CLK to High Z Max 8 10 ns tOES Output Enable Setup Time Min 4 5 ns tRCC Read cycle for continuous suspend Max 1 ms

54 Am42BDS6408H October 23, 2003

1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two
2. If any burst address occurs at a 64-word boundary, two additional clock cycle are inserted, and is indicated by RDY .
3. The device is in synchronous mode.

Figure 13. CLK Synchronous Burst Mode Read (rising active CLK)

1. Figure shows total number of wait states set to four cycles. The total number of wait states can be programmed from two

cycles to seven cycles. Clock is set for active falling edge.

1. If any burst address occurs at a 64-word boundary, two additional clock cycle are inserted, and is indicated by RDY .
2. The device is in synchronous mode.

Figure 14. CLK Synchronous Burst Mode Read (Falling Active Clock) 7 cycles for initial access shown. 4 cycles for initial access shown.

56 Am42BDS6408H October 23, 2003

has been written with A18=0; device will output RDY one cycle before valid data. Figure 17. Linear Burst with RDY Set One Cycle Before Data 6 wait cycles for initial access shown.

58 Am42BDS6408H October 23, 2003

Figure 20. Reduced Wait-state Handshake Burst Suspe nd/Resume at address 3Eh (or offset from 3Eh) Figure 21. Reduced Wait-state Handshake Burst Suspend/Resume at address 3Fh (or offset from 3Fh by

60 Am42BDS6408H October 23, 2003

has been written with A18=0; device will output RDY with valid data. Figure 24. Standard Handshake Burst Suspend at address 3Fh (starting address 3Dh or earlier) has been written with A18=0; device will output RDY with valid data. Figure 25. Standard Handshake Burst Suspend at address 3Eh/3Fh (without a valid Initial Access)

62 Am42BDS6408H October 23, 2003

Asynchronous Mode Read (VIO = 1.8 V) Notes: 1. Asynchronous Access Time is from the last of either stable addresses or the falling edge of AVD#. 2. Not 100% tested. Parameter E3, E4, E8, E9 (66 MHz) D6, D7, D8, D9 (54 MHz) UnitJEDEC Standard tCE Access Time from CE# Low Max 50 TBD ns tACC Asynchronous Access Time (Note 1) Max 50 TBD ns tAVDP AVD# Low Time Min 10 12 ns tAAVDS Address Setup Time to Rising Edge of AVD Min 4 5 ns tAAVDH Address Hold Time from Rising Edge of AVD Min 6 7 ns tOE Output Enable to Output Valid Max 11 13.5 ns tOEH Output Enable Hold Time Read Min 0 ns T oggle and Data# Polling Min 8 10 ns tOEZ Output Enable to High Z (Note 2) Max 8 10 ns tCAS CE# Setup Time to AVD# Min 0 ns

64 Am42BDS6408H October 23, 2003

Hardware Reset (RESET#) Note: Not 100% tested. Parameter RESET# Pin Low (During Embedded Algorithms) to Read Mode (See Note) Max 20 µs tReady RESET# Pin Low (NOT During Embedded Algorithms) to Read Mode (See Note) Max 500 ns tRP RESET# Pulse Width Min 500 ns tRH Reset High Time Before Read (See Note) Min 200 ns tRPD RESET# Low to Standby Mode Min 20 µs RESET# tRP tReady Reset Timings NOT during Embedded Algorithms tReady CE#, OE# tRH CE#, OE# Reset Timings during Embedded Algorithms RESET# tRP Figure 30. Reset Timings

October 23, 2003 Am42BDS6408H 65 ADVANCE INFORMATION AC CHARACTERISTICS Erase/Program Operations (VIO = 1.8 V) Notes: 1. Not 100% tested. 2. Asynchronous mode allows the Asynchronous program operation only. Synchronous mode allows both Asynchronous and Synchronous program operation. 3. In asynchronous program operation timing, addresses are latched on the falling edge of WE# or rising edge of AVD#. In synchronous program operation timing, addresses are latched on the first of either the falling edge of WE# or the active edge of CLK. 4. See the “Erase and Programming Performance” section for more information. 5. Does not include the preprogramming time. Parameter E6, E7, E8, E9 (66 MHz) D6, D7, D8, D9 (54 MHz) UnitJEDEC Standard tAVAV tWC Write Cycle Time (Note 1) Min 50 55 ns tAVWL tAS Address Setup Time (Notes 2, 3) Synchronous Min ns Asynchronous 0 tWLAX tAH Address Hold Time (Notes 2, 3) Synchronous Min ns Asynchronous 20 20 tAVDP AVD# Low Time Min 10 12 ns tDVWH tDS Data Setup Time Min 20 45 ns tWHDX tDH Data Hold Time Min 0 ns tGHWL tGHWL Read Recovery Time Before Write Min 0 ns tCAS CE# Setup Time to AVD# Min 0 ns tWHEH tCH CE# Hold Time Min 0 ns tWLWH tWP Write Pulse Width Min 20 30 ns tWHWL tWPH Write Pulse Width High Min 20 20 ns tSR/W Latency Between Read and Write Operations Min 0 ns tWHWH1 tWHWH1 Programming Operation (Note 4) Typ 9 µs tWHWH1 tWHWH1 Accelerated Programming Operation (Note 4) Typ 4 µs tWHWH2 tWHWH2 Sector Erase Operation (Notes 4, 5) Typ 0.4 sec Chip Erase Operation (Notes 4, 5) 54 tVID VACC Rise and Fall Time Min 500 ns tVIDS VACC Setup Time (During Accelerated Programming) Min 1 µs tVCS VCC Setup Time Min 50 µs tELWL tCS CE# Setup Time to WE# Min 0 ns tAVSW AVD# Setup Time to WE# Min 4 5 ns tAVHW AVD# Hold Time to WE# Min 4 5 ns tACS Address Setup Time to CLK (Notes 2, 3) Min 4 5 ns tACH Address Hold Time to CLK (Notes 2, 3) Min 6 7 ns tAVHC AVD# Hold Time to CLK Min 4 5 ns tCSW Clock Setup Time to WE# Min 5 ns

66 Am42BDS6408H October 23, 2003

1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.
2. “In progress” and “complete” refer to status of program operation.
3. A21–A12 are don’t care during command sequence unlock cycles.
4. CLK can be either V IL or VIH.
5. The Asynchronous programming operation is independent of the Set Device Read Mode bit in the Configuration Register.

Figure 31. Asynchronous Program Operat ion Timings: AVD# Latched Addresses

1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.
2. “In progress” and “complete” refer to status of program operation.
3. A21–A12 are don’t care during command sequence unlock cycles.
4. CLK can be either V IL or VIH.
5. The Asynchronous programming operation is independent of the Set Device Read Mode bit in the Configuration Register.

Figure 32. Asynchronous Program Operation Timings: WE# Latched Addresses

68 Am42BDS6408H October 23, 2003

1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.
2. “In progress” and “complete” refer to status of program operation.
3. A21–A12 are don’t care during command sequence unlock cycles.
4. Addresses are latched on the first of either the rising edge of AVD# or the active edge of CLK.
5. Either CE# or AVD# is required to go from low to high in between programming command sequences.
6. The Synchronous programming operation is dependent of the Set Device Read Mode bit in the Configuration Register. The

Configuration Register must be set to the Synchronous Read Mode. Figure 33. Synchronous Program Operation Timings: WE# Latched Addresses

1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.
2. “In progress” and “complete” refer to status of program operation.
3. A21–A12 are don’t care during command sequence unlock cycles.
4. Addresses are latched on the first of either the rising edge of AVD# or the active edge of CLK.
5. Either CE# or AVD# is required to go from low to high in between programming command sequences.
6. The Synchronous programming operation is dependent of the Set Device Read Mode bit in the Configuration Register. The

Configuration Register must be set to the Synchronous Read Mode. Figure 34. Synchronous Program Operat ion Timings: CLK Latched Addresses

70 Am42BDS6408H October 23, 2003

Figure 35. Chip/Sector Erase Command Sequence

1. SA is the sector address for Sector Erase.
2. Address bits A21–A12 are don’t cares during unlock cycles in the command sequence.

Note: Use setup and hold times from conventional program operation. Figure 36. Accelerated Unlock Bypass Programming Timing

72 Am42BDS6408H October 23, 2003

1. Status reads in figure are shown as asynchronous.
2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete,

and Data# Polling will output true data.

1. While in Asynchronous mode, RDY will be low while the device is in embedded erase or programming mode.

Figure 37. Data# Polling Timings (During Embedded Algorithm)

1. Status reads in figure are shown as asynchronous.
2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete,

the toggle bits will stop toggling.

1. While in Asynchronous mode, RDY will be low while the device is in embedded erase or programming mode.

Figure 38. Toggle Bit Timings (During Embedded Algorithm)

74 Am42BDS6408H October 23, 2003

Figure 41. Temporary Sector Unprotect Timing Diagram

Figure 42. Sector/Sector Block Protect and

76 Am42BDS6408H October 23, 2003

1. RDY active with data (A18 = 0 in the Configuration Register).
2. RDY active one clock cycle before data (A18 = 1 in the Configuration Register).
3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60. Figure shows the device not crossing

a bank in the process of performing an erase or program.

1. If the starting address latched in is either 3Eh or 3Fh (or some 64 multiple of either), there is no additional 2 cycle laten cy at

Figure 43. Latency with Boundary Crossing 00003Fh: 00007Fh, 0000BFh, etc.) Address 000000h is also a boundary crossing.

1. RDY active with data (A18 = 0 in the Configuration Register).
2. RDY active one clock cycle before data (A18 = 1 in the Configuration Register).
3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60. Figure shows the device crossing a

bank in the process of performing an erase or program. Figure 44. Latency with Boundary Crossing 00003Fh: (00007Fh, 0000BFh, etc.) Address 000000h is also a boundary crossing.

78 Am42BDS6408H October 23, 2003

Note: Figure assumes address D0 is not at an address boundary, active clock edge is rising, and wait state is set to “101”. Figure 45. Example of Wait States Insertion

the status of the program or erase operation in the “busy” bank. The system should read status twice to ensure valid information. Figure 46. Back-to-Back Read/Write Cycle Timings

80 Am42BDS6408H October 23, 2003

Figure 47. SRAM Read Cycle—Address Controlled

Figure 48. SRAM Read Cycle

1. t HZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output
2. At any given temperature and voltage condition, tHZ (Max.) is less than tLZ (Min.) both for a given device and from device to device

82 Am42BDS6408H October 23, 2003

1. t CW is measured from CE1#s going low to the end of write.
2. t WR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high.
3. t AS is measured from the address valid to the beginning of write.
4. A write occurs during the overlap (tWP) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when

Figure 49. SRAM Write Cycle—WE# Control

1. t CW is measured from CE1#s going low to the end of write.
2. t WR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high.
3. t AS is measured from the address valid to the beginning of write.
4. A write occurs during the overlap (tWP) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when

Figure 50. SRAM Write Cycle—CE1#s Control

84 Am42BDS6408H October 23, 2003

1. UB#s and LB#s controlled.
2. t CW is measured from CE1#s going low to the end of write.
3. t WR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high.
4. t AS is measured from the address valid to the beginning of write.
5. A write occurs during the overlap (tWP) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when

Figure 51. SRAM Write Cycle—UB#s and LB#s Control

October 23, 2003 Am42BDS6408H 85 ADVANCE INFORMATION ERASE AND PROGRAMMING PERFORMANCE Notes: 1. Typical program and erase times assume the following conditions: 25 °C, 1.8 V VCC, 1 million cycles. Additionally, programming typicals assumes a checkerboard pattern. 2. Under worst case conditions of 90°C, V CC = 1.65 V, 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed. 4. In the pre-programming step of the Embedded Erase algorithm, all words are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 16, “Command Definitions,” on page 40 for further information on command definitions. 6. The device has a minimum erase and program cycle endurance of 1 million cycles. BGA BALL CAPACITANCE Notes: 1. Sampled, not 100% tested. 2. Test conditions T A = 25°C, f = 1.0 MHz. DATA RETENTION Parameter Typ (Note 1) Max (Note 2) Unit Comments Sector Erase Time 32 Kword 0.4 5 s Excludes 00h programming prior to erasure (Note 4)4 Kword 0.2 5 Chip Erase Time 54 s Word Programming Time 9 210 µs Excludes system level overhead (Note 5) Accelerated Word Programming Time 4 120 µs Chip Programming Time (Note 3) 38 114 s Excludes system level overhead (Note 5) Accelerated Chip Programming Time 17 50 s Parameter Symbol Parameter Description Test Setup Typ Max Unit CIN Input Capacitance V IN = 0 4.2 5.0 pF COUT Output Capacitance V OUT = 0 5.4 6.5 pF CIN2 Control Pin Capacitance V IN = 0 3.9 4.7 pF Parameter Test Conditions Min Unit Minimum Pattern Data Retention Time 150°C1 0 Y e a r s 125°C2 0 Y e a r s

86 Am42BDS6408H October 23, 2003

TLB 089—89-ball Fine-Pitch Ball Grid Array (FBGA) 10 x 8 mm Package Note: BSC is an ANSI standard for Basic Space Centering 3294\\ 16-038.22a PACKAGE TLB089 JEDEC N/A 10.00 mm x 8.00 mm PACKAGE SYMBOL MIN NOM MAX NOTE A --- --- 1.20 PROFILE A1 0.20 --- --- BALL HEIGHT A2 0.81 --- 0.97 BODY THICKNESS D 10.00 BSC. BODY SIZE E 8.00 BSC. BODY SIZE D1 7.20 BSC. MATRIX FOOTPRINT E1 7.20 BSC. MATRIX FOOTPRINT MD 10 MATRIX SIZE D DIRECTION ME 10 MATRIX SIZE E DIRECTION n 89 BALL COUNT φb 0.33 --- 0.43 BALL DIAMETER eE 0.80 BSC BALL PITCH eD 0.80 BSC BALL PITCH SD / SE 0.40 BSC SOLDER BALL PLACEMENT B10,C1,C10,D1,D10,G1,G10 DEPOPULATED SOLDER BALLS H1,H10,J1,J10 NOTES: 1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. 3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010. 4. e REPRESENTS THE SOLDER BALL GRID PITCH. 5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME.

6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL

DIAMETER IN A PLANE PARALLEL TO DATUM C.

7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A

AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 9. N/A

10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK

MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. INDEX MARK 89X C0.15 (2X) (2X) C0.15 B A b 0.20 C C 0.15 0.08 M M C C AB D E PIN A1 C TOP VIEW SIDE VIEW CORNER A 0.08 eD CORNER 7SE ABDCEFHG JK eE SD BOTTOM VIEW PIN A17

October 23, 2003 Am42BDS6408H 87 ADVANCE INFORMATION REVISION SUMMARY Revision A (July 14, 2003) Initial release. Revision A+1 (July 15, 2003) Corrected Ordering Information OPNs. Revision A+2 (July 21, 2003) Corrected typos in datasheet regarding package name. Revision A+3 (October 23, 2003) Corrected globally all pSRAM to SRAM. Remove 80 MHz option throughout. Trademarks Copyright © 2003 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies .

©2003 Advanced Micro Devices, Inc. Printed in USA One AMD Place, P .O. Box 3453,Sunnyvale, CA 94088-3453 408-732-2400 TWX 910-339-9280 TELEX 34-6306 800-538-8450 http://www.amd.com Advanced Micro Devices reserves the right to make changes in its product without notice in order to improve design or performance characteristics.The performance characteristics listed in this document are guaranteed by specific tests, guard banding, design and other practices common to the industry. For specific testing details, contact your local AMD sales representative.The company assumes no responsibility for the use of any circuits described herein. © Advanced Micro Devices, Inc. All rights reser ved. AMD, the AMD Arrow logo and combination thereof, are trademarks of Advanced Micro Devices, Inc. Other product names are for informational purposes only and may be trademarks of their respective companies. North America CALIFORNIA, FLORIDA, ILLINOIS, NEW JERSEY, TEXAS, International CHINA, GERMANY, JAPAN, UNITED KINGDOM, Representatives in U.S. and Canada ARIZONA, CALIFORNIA, CANADA, COLORADO, FLORIDA, GEORGIA, ILLINOIS, INDIANA, IOWA, KANSAS, MASSACHUSETTS, MICHIGAN, MINNESOTA, MISSOURI, NEW JERSEY, NEW YORK, NORTH CAROLINA, OHIO, OREGON, UTAH, VIRGINIA, WASHINGTON, WISCONSIN, Representatives in Latin America ARGENTINA, CHILE, COLUMBIA, MEXICO, PUERTO RICO, Sales Offices and Representatives es