AM41DL3208G SPANSION | Alldatasheet

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The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig- inally developed the specification, these products will be offered to cu stomers of both AMD and Fujitsu. Continuity of Specifications There is no change to this datasheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary. Continuity of Ordering Part Numbers AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order these products, please use only the Ordering Part Numbers listed in this document. For More Information Please contact your local AMD or Fujitsu sales office for additional information about Spansion memory solutions. Am41DL3208G Data Sheet Publication Number 25870 Revision A Amendment 0 Issue Date February 13, 2002

This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. Publication# 25870 Rev: A Amendment/0 Issue Date: February 13, 2002 Refer to AMD’s Website (www.amd.com) for the latest information. Am41DL3208G Stacked Multi-Chip Package (MCP) Flash Memory and SRAM 32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 8 Mbit (1 M x 8-Bit/512 K x 16-Bit) Static RAM DISTINCTIVE CHARACTERISTICS MCP Features I Power supply voltage of 2.7 to 3.3 volt I High performance — Access time as fast as 70 ns I Package — 73-Ball FBGA I Operating Temperature — –40°C to +85°C Flash Memory Features ARCHITECTURAL ADVANTAGES I Simultaneous Read/Write operations — Data can be continuously read from one bank while executing erase/program functions in other bank — Zero latency between read and write operations I Flexible BankTM architecture — Read may occur in any of the three banks not being written or erased. — Four banks may be grouped by customer to achieve desired bank divisions. I Secured Silicon (SecSi) Sector: Extra 256 Byte sector — Factory locked and identifiable: 16 bytes available for secure, random factory Electronic Serial Number; verifiable as factory locked through autoselect function. — Customer lockable: Sector is one-time programmable. Once locked, data cannot be changed I Zero Power Operation — Sophisticated power management circuits reduce power consumed during inactive periods to nearly zero I Top or bottom boot block I Manufactured on 0.17 µm process technology I Compatible with JEDEC standards — Pinout and software compatible with single-power-supply flash standard PERFORMANCE CHARACTERISTICS I High performance — Access time as fast as 70 ns — Program time: 4 µs/word typical utilizing Accelerate function I Ultra low power consumption (typical values) — 2 mA active read current at 1 MHz — 10 mA active read current at 5 MHz — 200 nA in standby or automatic sleep mode I Minimum 1 million write cycles guaranteed per sector I 20 Year data retention at 125°C — Reliable operation for the life of the system SOFTWARE FEATURES I Data Management Software (DMS) — AMD-supplied software manages data programming and erasing, enabling EEPROM emulation — Eases sector erase limitations I Supports Common Flash Memory Interface (CFI) I Unlock Bypass Program command — Reduces overall programming time when issuing multiple program command sequences HARDWARE FEATURES I Any combination of sectors can be erased I Ready/Busy# output (RY/BY#) — Hardware method for detecting program or erase cycle completion I Hardware reset pin (RESET#) — Hardware method of resetting the internal state machine to reading array data I WP#/ACC input pin — Write protect (WP#) function allows protection of two outermost boot sectors, regardless of sector protect status — Acceleration (ACC) function accelerates program timing I Sector protection — Hardware method of locking a sector, either in-system or using programming equipment, to prevent any program or erase operation within that sector — Temporary Sector Unprotect allows changing data in protected sectors in-system SRAM Features I Power dissipation — Operating: 30 mA maximum — Standby: 15 µA maximum I CE1s# and CE2s Chip Select I Power down features using CE1s# and CE2s I Data retention supply voltage: 1.5 to 3.3 volt I Byte data control: LB#s (DQ7–DQ0), UB#s (DQ15–DQ8)

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The Am29DL320G consists of 32 megabit, 3.0 volt-only flash memory devices, organized as 2,097,152 words of 16 bits each or 4,194,304 bytes of 8 bits each. Word mode data ap- pears on DQ15 – DQ0; byte mode data appears on DQ7 –DQ0. The device is designed to be programmed in-system with the standard 3.0 volt V CC supply, and can also be programmed in standard EPROM programmers. The devices are available with access times of 70 and 85 ns. The device is offered in a 73-ball FBGA package. Standard control pins — chip enable (CE#f), write enable (WE#), and output enable (OE#) — control normal read and write opera- tions, and avoid bus contention issues. The devices requires only a single 3.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. Simultaneous Read/Write Operations with Zero Latency The Simultaneous Read/Write architecture provides simul- taneous operation by dividing the memory space into four banks, two 4 Mb banks with small and large sectors, and two 12 Mb banks of large sectors. Sector addresses are fixed, system software can be used to form user-defined bank groups. During an Erase/Program operation, any of the three non-busy banks may be read from. Note that only two banks can operate simultaneously. The device allows a host sys- tem to program or erase in one bank, then immediately and simultaneously read from the other bank, with zero latency. This releases the system from waiting for the completion of program or erase operations. The Am29DL320G can be organized as either a top or bot- tom boot sector configuration. Am41DL3208G Features The SecSiTM (Secured Silicon) Sector is an 256 byte extra sector capable of being permanently locked by AMD or cus- tomers. The SecSi Indicator Bit (DQ7) is permanently set to a 1 if the part is factory locked , and set to a 0 if cus- tomer lockable . This way, customer lockable parts can never be used to replace a factory locked part. Note that some previous AMD 32 Mbit Am29DL32x devices had a larger SecSi Sector. Factory locked parts provide several options. The SecSi Sector may store a secure, random 16 byte ESN (Electronic Serial Number), customer code (pro- grammed through AMD ’s ExpressFlash service), or both. DMS (Data Management Software) allows systems to eas- ily take advantage of the advanced architecture of the simultaneous read/write product line by allowing removal of EEPROM devices. DMS will also allow the system software to be simplified, as it will perform all functions necessary to modify data in file structures, as opposed to single-byte modifications. To write or update a particular piece of data (a phone number or configuration data, for example), the user only needs to state which piece of data is to be updated, and where the updated data is located in the system. This is an advantage compared to systems where user-written soft- ware must keep track of the old data location, status, logical to physical translation of the data onto the Flash memory de- vice (or memory devices), and more. Using DMS, user-written software does not need to interface with the Flash memory directly. Instead, the user's software ac- cesses the Flash memory by calling one of only six functions. AMD provides this software to simplify system de- sign and software integration efforts. The device offers complete compatibility with the JEDEC single-power-supply Flash command set standard . Commands are written to the command register using stan- dard microprocessor write timings. Reading data out of the device is similar to reading from other Flash or EPROM devices. The host system can detect whether a program or erase op- eration is complete by using the device status bits: RY/BY# pin, DQ7 (Data# Polling) and DQ6/DQ2 (toggle bits). After a program or erase cycle has been completed, the device au- tomatically returns to reading array data. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data con- tents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low V CC de- tector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combi- nation of the sectors of memory. This can be achieved in-system or via programming equipment. The device offers two power-saving features. When ad- dresses have been stable for a specified amount of time, the device enters the automatic sleep mode . The system can also place the device into the standby mode . Power con- sumption is greatly reduced in both modes. Bank Megabits Sector Sizes Bank 1 4 Mb Eight 8 Kbyte/4 Kword, Seven 64 Kbyte/32 Kword Bank 2 12 Mb Twenty-four 64 Kbyte/32 Kword Bank 3 12 Mb Twenty-four 64 Kbyte/32 Kword Bank 4 4 Mb Eight 64 Kbyte/32 Kword

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Figure 25. Temporary Sector/Sector Block Unprotect Figure 26. Sector/Sector Block Protect and Unprotect Figure 27. Flash Alternate CE#f Controlled Write (Erase/Program) Op-

February 13, 2002 Am41DL3208G 5 PRELIMINARY PRODUCT SELECTOR GUIDE MCP BLOCK DIAGRAM Part Number Am41DL3208G Speed Options Standard Voltage Range: VCC = 2.7–3.3 V Flash Memory SRAM 70 85 70 85 Max Access Time (ns) 70 85 70 85 CE# Access (ns) 70 85 70 85 OE# Access (ns) 30 40 35 45 VSS/VSSQVCCs/VCCQ RESET# WE# CE#f OE# CE1#s VSSVCCf RY/BY# LB#s UB#s CIOf WP#/ACC CE2s SA CIOs

8 M Bit

32 M Bit

A–1 A18 to A0

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FLASH MEMORY BLOCK DIAGRAM VCC VSS Upper Bank AddressA20–A0 RESET# WE# CE# CIOf DQ15–DQ0 WP#/ACC STATE CONTROL COMMAND REGISTER RY/BY# Upper Bank X-Decoder Y-Decoder Latches and Control Logic OE# CIOf DQ15–DQ0 Lower Bank Y-Decoder X-Decoder Latches and Control Logic Lower Bank Address OE# CIOf Status Control A20–A0 A20–A0 A20–A0A20–A0 DQ15–DQ0 DQ15 –DQ0

February 13, 2002 Am41DL3208G 7 PRELIMINARY CONNECTION DIAGRAM Special Handling Instructions for FBGA Package Special handling is required for Flash Memory prod- ucts in FBGA packages. Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compro- mised if the package body is exposed to temperatures above 150°C for prolonged periods of time. A10 B10 F10 G10 L10 M10 NC NC NC NC NC NC NCNC NC CE#f CE1#s V SS OE# DQ0 DQ8 LB# UB# A18 A17 DQ1 DQ9 DQ10 DQ2 NC WP#/ACC RESET# RY/BY# DQ3 V CCf DQ11 NC WE# CE2s A20 DQ4 VCCs CIOs A19 A10 DQ6 DQ13 DQ12 DQ5 A11 A12 A13 A14 SA DQ15/A-1 DQ7 DQ14 A15 NC NC A16 CIOf V SS NC NC NC NC NC NC SRAM only Shared Flash only 73-Ball FBGA Top View

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A18–A0 = 19 Address Inputs (Common) A-1, A20–A19 = 3 Address Inputs (Flash) SA = Highest Order Address Pin (SRAM) Byte mode DQ15–DQ0 = 16 Data Inputs/Outputs (Common) CE#f = Chip Enable (Flash) CE#s = Chip Enable (SRAM) OE# = Output Enable (Common) WE# = Write Enable (Common) RY/BY# = Ready/Busy Output UB#s = Upper Byte Control (SRAM) LB#s = Lower Byte Control (SRAM) CIOf = I/O Configuration (Flash) CIOf = VIH = Word mode (x16), CIOf = VIL = Byte mode (x8) CIOs = I/O Configuration (SRAM) CIOs = VIH = Word mode (x16), CIOs = VIL = Byte mode (x8) RESET# = Hardware Reset Pin, Active Low WP#/ACC = Hardware Write Protect/ Acceleration Pin (Flash) VCCf = Flash 3.0 volt-only single power sup- ply (see Product Selector Guide for speed options and voltage supply tolerances) V CCs = SRAM Power Supply VSS = Device Ground (Common) NC = Pin Not Connected Internally LOGIC SYMBOL 16 or 8 DQ15–DQ0 A18–A0 CE#f OE# WE# RESET# UB#s RY/BY# WP#/ACC SA A-1, A20–A19 LB#s CIOf CIOs CE1#s CE2s

February 13, 2002 Am41DL3208G 9 PRELIMINARY

ORDERING INFORMATION

The order number (Valid Combination) is formed by the following: Valid Combinations Valid Combinations list configurations planned to be supported in vol- ume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly re- leased combinations Am41DL320 8 G T 70 I T TAPE AND REEL T= 7 i n c h e s TEMPERATURE RANGE I = Industrial ( –40°C to +85°C) SPEED OPTION See Product Selector Guide and Valid Combinations BOOT CODE SECTOR ARCHITECTURE T= T o p s e c t o r B = Bottom sector PROCESS TECHNOLOGY G = 0.17 µm SRAM DEVICE DENSITY 8= 8 M b i t s AMD DEVICE NUMBER/DESCRIPTION Am41DL3208G Stacked Multi-Chip Package (MCP) Flash Memory and SRAM Am29DL320G 32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 8 Mbit (1 M x 8-Bit/512 K x 16-Bit) Static RAM Valid Combinations Order Number Package Marking Am41DL3208GT70I Am41DL3208GB70I T M41000003D M41000003E Am41DL3208GT85I Am41DL3208GB85I M41000003F M41000003G

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This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory loca- tion. The register is a latch used to store the commands, along with the address and data informa- tion needed to execute the command. The contents of the register serve as inputs to the internal state ma- chine. The state machine outputs dictate the function of the device. Tables 1 through 3 list the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections de- scribe each of these operations in further detail.

Table 1. Device Bus Operations — Flash Word Mode, CIOf = VIH; SRAM Word Mode, CIOs = VCC

  1. Other operations except for those indicated in this column are inhibited.

IL, CE1#s = VIL and CE2s = VIH at the same time.

  1. Don’t care or open LB#s or UB#s.
  2. If WP#/ACC = V IL , the boot sectors will be protected. If WP#/ACC = VIH the boot sectors protection will be removed.

If WP#/ACC = VACC (9V), the program time will be reduced by 40%.

  1. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector

Block Protection and Unprotection” section.

  1. If WP#/ACC = V IL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection

Unprotection”. If WP#/ACC = VHH, all sectors will be unprotected.

0.3 V H High-Z High-Z

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Table 2. Device Bus Operations — Flash Word Mode, CIOf = VIH; SRAM Byte Mode, CIOs = VSS

  1. Other operations except for those indicated in this column are inhibited.

IL, CE1#s = VIL and CE2s = VIH at the same time.

  1. Don ’t care or open LB#s or UB#s.
  2. If WP#/ACC = V IL , the boot sectors will be protected. If WP#/ACC = VIH the boot sectors protection will be removed.

If WP#/ACC = VACC (9V), the program time will be reduced by 40%.

  1. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector

Block Protection and Unprotection” section.

  1. If WP#/ACC = V IL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection

Unprotection”. If WP#/ACC = VHH, all sectors will be unprotected.

Table 3. Device Bus Operations — Flash Byte Mode, CIOf = VSS; SRAM Word Mode, CIOs = VCC

  1. Other operations except for those indicated in this column are inhibited.
  2. Do not apply CE#f = V IL, CE1#s = VIL and CE2s = VIH at the same time.
  3. Don ’t care or open LB#s or UB#s.
  4. If WP#/ACC = V IL , the boot sectors will be protected. If WP#/ACC = VIH the boot sectors protection will be removed.

If WP#/ACC = VACC (9V), the program time will be reduced by 40%.

  1. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector

Block Protection and Unprotection” section.

  1. If WP#/ACC = V IL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection

Unprotection”. If WP#/ACC = VHH, all sectors will be unprotected.

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Table 4. Device Bus Operations — Flash Byte Mode, CIOf = VIL; SRAM Byte Mode, CIOs = VSS

  1. Other operations except for those indicated in this column are inhibited.

IL, CE1#s = VIL and CE2s = VIH at the same time.

  1. Don ’t care or open LB#s or UB#s.
  2. If WP#/ACC = V IL , the boot sectors will be protected. If WP#/ACC = VIH the boot sectors protection will be removed.

If WP#/ACC = VACC (9V), the program time will be reduced by 40%.

  1. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector

Block Protection and Unprotection”.

  1. If WP#/ACC = V IL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection

Unprotection”. If WP#/ACC = VHH, all sectors will be unprotected.

February 13, 2002 Am41DL3208G 15 PRELIMINARY Word/Byte Configuration The CIOf pin controls whether the device data I/O pins operate in the byte or word configuration. If the CIOf pin is set at logic ‘1’, the device is in word configura- tion, DQ15–DQ0 are active and controlled by CE# and OE#. If the CIOf pin is set at logic ‘0’, the device is in byte configuration, and only data I/O pins DQ7 –DQ0 are active and controlled by CE# and OE#. The data I/O pins DQ14 –DQ8 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function. Requirements for Reading Array Data To read array data from the outputs, the system must drive the CE#f and OE# pins to V IL. CE#f is the power control and selects the device. OE# is the output con- trol and gates array data to the output pins. WE# should remain at V IH . The CIOf pin determines whether the device outputs array data in words or bytes. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No com- mand is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. Each bank remains enabled for read access until the command register contents are altered. See “Requirements for Reading Array Data ” for more information. Refer to the AC Flash Read-Only Opera- tions table for timing specifications and to Figure 14 for the timing diagram. I CC1 in the DC Characteristics table represents the active current specification for reading array data. Writing Commands/Command Sequences To write a command or command sequence (which in- cludes programming data to the device and erasing sectors of memory), the system must drive WE# and CE#f to V IL, and OE# to VIH. For program operations, the CIOf pin determines whether the device accepts program data in bytes or words. Refer to “Word/Byte Configuration ” for more information. The device features an Unlock Bypass mode to facil- itate faster programming. Once a bank enters the Unlock Bypass mode, only two write cycles are re- quired to program a word or byte, instead of four. The “Word/Byte Configuration ” section has details on pro- gramming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sec- tors, or the entire device. Tables 6 –8 indicate the address space that each sector occupies. The device address space is divided into two banks: Bank 1 con- tains the boot/parameter sectors, and Bank 2 contains the larger, code sectors of uniform size. A “bank ad- dress” is the address bits required to uniquely select a bank. Similarly, a “sector address ” is the address bits required to uniquely select a sector. I CC2 in the DC Characteristics table represents the ac- tive current specification for the write mode. The AC Characteristics section contains timing specification tables and timing diagrams for write operations. Accelerated Program Operation The device offers accelerated program operations through the ACC function. This is one of two functions provided by the WP#/ACC pin. This function is prima- rily intended to allow faster manufacturing throughput at the factory. If the system asserts V HH on this pin, the device auto- matically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing V HH from the WP#/ACC pin returns the device to nor- mal operation. Note that the WP#/ACC pin must not be at V HH for operations other than accelerated pro- gramming, or device damage may result. In addition, the WP#/ACC pin must not be left floating or uncon- nected; inconsistent behavior of the device may result. Autoselect Functions If the system writes the autoselect command se- quence, the device enters the autoselect mode. The system can then read autoselect codes from the inter- nal register (which is separate from the memory array) on DQ7 –DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode and Autose- lect Command Sequence sections for more information. Simultaneous Read/Write Operations with Zero Latency This device is capable of reading data from one bank of memory while programming or erasing in the other bank of memory. An erase operation may also be sus- pended to read from or program to another location within the same bank (except the sector being erased). Figure 21 shows how read and write cycles may be initiated for simultaneous operation with zero latency. I CC6 and I CC7 in the DC Characteristics table represent the current specifications for read-while-pro- gram and read-while-erase, respectively.

16 Am41DL3208G February 13, 2002

state, independent of the OE# input. modes, before it is ready to read data. standby current specification. data is latched and always available to the system. automatic sleep mode current specification. the RESET# pin returns to VIH. rameters and to Figure 15 for the timing diagram. Table 5. Device Bank Division

Table 6. Top Boot Sector Addresses

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Note: The address range is A20:A-1 in byte mode (BYTE#=VIL) or A20:A0 in word mode (BYTE#=VIH). The bank address bits are A20–A18. Table 7. Top Boot SecSi  Sector Addresses Table 6. Top Boot Sector Addresses (Continued)

Table 8. Bottom Boot Sector Addresses

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Table 9. Bottom Boot SecSi  Sector Addresses Table 8. Bottom Boot Sector Addresses (Continued)

accessed in-system through the command register. Command Sequence section for more information. Table 10. Top Boot Sector/Sector Block Sector/Sector Block Unprotect ”. The device is shipped with all sectors unprotected. sectors were last set to be protected or unprotected. tor/Sector Block Protection and Unprotection ”.

22 Am41DL3208G February 13, 2002

Figure 1. Temporary Sector Unprotect Operation

  1. All protected sectors unprotected (If WP#/ACC = V IL,

outermost boot sectors will remain protected).

  1. All previously protected sectors are protected once

Note: The term “sector” in the figure applies to both sectors and sector blocks. Figure 2. In-System Sector/Sector Block Protect and Unprotect Algorithms

24 Am41DL3208G February 13, 2002

SecSi (Secured Silicon) Sector Flash Memory Region The SecSi (Secured Silicon) Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The SecSi Sector uses a SecSi Sector Indica- tor Bit to indicate whether or not the SecSi Sector is locked when shipped from the factory. This bit is per- manently set at the factory and cannot be changed, which prevents cloning of a factory locked part. This ensures the security of the ESN once the product is shipped to the field. AMD offers the device with the SecSi Sector either factory locked or customer lockable. The fac- tory-locked version is always protected when shipped from the factory, and has the SecSi Sector Indicator Bit permanently set to a “1.” The customer-lockable version is shipped with the unprotected, allowing cus- tomers to utilize the that sector in any manner they choose. The customer-lockable version has the SecSi Sector Indicator Bit permanently set to a “0.” Thus, the SecSi Sector Indicator Bit prevents customer-lockable devices from being used to replace devices that are factory locked. The system accesses the SecSi Sector through a command sequence (see “Enter SecSi Sector/Exit SecSi Sector Command Sequence ”). After the system has written the Enter SecSi Sector command se- quence, it may read the SecSi Sector by using the addresses normally occupied by the boot sectors. This mode of operation continues until the system issues the Exit SecSi Sector command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to send- ing commands to the boot sectors. Factory Locked: SecSi Sector Programmed and Protected At the Factory In a factory locked device, the SecSi Sector is pro- tected when the device is shipped from the factory. The SecSi Sector cannot be modified in any way. The device is available preprogrammed with a random, se- cure ESN only. In the Top Boot device the ESN will be at addresses 1FF000h –1FF007h in word mode (or addresses 3FE000h–3FE00Fh in byte mode). Customer Lockable: SecSi Sector NOT Programmed or Protected At the Factory If the security feature is not required, the SecSi Sector can be treated as an additional Flash memory space, expanding the size of the available Flash array. The SecSi Sector can be read any number of times, but can be programmed and locked only once, and cannot be erased. Note that the accelerated programming (ACC) and unlock bypass functions are not available when programming the SecSi Sector. The SecSi Sector area can be protected using one of the following procedures: I Write the three-cycle Enter SecSi Sector Region command sequence, and then follow the in-system sector protect algorithm as shown in Figure 2, ex- cept that RESET# may be at either V IH or VID. This allows in-system protection of the without raising any device pin to a high voltage. Note that this method is only applicable to the SecSi Sector. I Write the three-cycle Enter SecSi Sector Region command sequence, and then use the alternate method of sector protection described in the “Sec- tor/Sector Block Protection and Unprotection ”. Once the SecSi Sector is locked and verified, the sys- tem must write the Exit SecSi Sector Region command sequence to return to reading and writing the remainder of the array. The SecSi Sector protection must be used with cau- tion since, once protected, there is no procedure available for unprotecting the SecSi Sector area and none of the bits in the SecSi Sector memory space can be modified in any way. Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Tables 15 and 16 for command definitions). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during V CC power-up and power-down transitions, or from system noise. Low V CC Write Inhibit When V CC is less than V LKO, the device does not ac- cept any write cycles. This protects data during V CC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to reading array data. Subse- quent writes are ignored until V CC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when V CC is greater than VLKO. Write Pulse “Glitch” Protection Noise pulses of less than 5 ns (typical) on OE#, CE#f or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE#f = V IH or WE# = V IH. To initiate a write cycle,

cally reset to reading array data on power-up. interfaces for long-term compatibility. an Embedded Program or embedded erase algorithm. vice to the autoselect mode. AMD representative for copies of these documents. Table 11. CFI Query Identification String

26 Am41DL3208G February 13, 2002

Table 12. System Interface String Table 13. Device Geometry Definition

Table 14. Primary Vendor-Specific Extended Query

28 Am41DL3208G February 13, 2002

Writing specific address and data commands or se- quences into the command register initiates device operations. Tables 15 and 16 define the valid register command sequences. Writing incorrect address and data values or writing them in the improper se- quence resets the device to reading array data. All addresses are latched on the falling edge of WE# or CE#f, whichever happens later. All data is latched on the rising edge of WE# or CE#f, whichever hap- pens first. Refer to the AC Characteristics section for timing diagrams. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. Each bank is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the corresponding bank enters the erase-sus- pend-read mode, after which the system can read data from any non-erase-suspended sector within the same bank. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See the Erase Suspend/Erase Resume Commands sec- tion for more information. The system must issue the reset command to return a bank to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase opera- tion, or if the bank is in the autoselect mode. See the next section, Reset Command, for more information. See also Requirements for Reading Array Data in the Device Bus Operations section for more information. The Flash Read-Only Operations table provides the read parameters, and Figure 14 shows the timing diagram. Reset Command Writing the reset command resets the banks to the read or erase-suspend-read mode. Address bits are don’t cares for this command. The reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. This resets the bank to which the sys- tem was writing to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the bank to which the system was writing to reading array data. If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset command returns that bank to the erase-sus- pend-read mode. Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the se- quence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data. If a bank entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the banks to read- ing array data (or erase-suspend-read mode if that bank was in Erase Suspend). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. Tables 15 and 16 show the address and data require- ments. The autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the device is ac- tively programming or erasing in the other bank. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the bank address and the au- toselect command. The bank then enters the autoselect mode. The system may read at any ad- dress within the same bank any number of times without initiating another autoselect command sequence: I A read cycle at address (BA)XX00h (where BA is the bank address) returns the manufacturer code. I A read cycle at address (BA)XX01h in word mode (or (BA)XX02h in byte mode) returns the device code. I A read cycle to an address containing a sector ad- dress (SA) within the same bank, and the address 02h on A7–A0 in word mode (or the address 04h on A6–A-1 in byte mode) returns 01h if the sector is protected, or 00h if it is unprotected. (Refer to Ta- bles 6–8 for valid sector addresses). The system must write the reset command to return to reading array data (or erase-suspend-read mode if the bank was previously in Erase Suspend).

February 13, 2002 Am41DL3208G 29 PRELIMINARY Enter SecSi Sector/Exit SecSi Sector Command Sequence The system can access the SecSi Sector region by is- suing the three-cycle Enter SecSi Sector command sequence. The device continues to access the SecSi Sector region until the system issues the four-cycle Exit SecSi Sector command sequence. The Exit SecSi Sector command sequence returns the device to nor- mal operation. Tables 15 and 16 show the address and data requirements for both command sequences. See also “SecSi (Secured Silicon) Sector Flash Mem- ory Region ” for further information. Note that a hardware reset (RESET#=V IL) will reset the device to reading array data. Byte/Word Program Command Sequence The system may program the device by word or byte, depending on the state of the CIOf pin. Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cy- cles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the pro- grammed cell margin. Tables 15 and 16 show the address and data requirements for the byte program command sequence. When the Embedded Program algorithm is complete, that bank then returns to reading array data and ad- dresses are no longer latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY/BY#. Refer to the Write Oper- ation Status section for information on these status bits. Any commands written to the device during the Em- bedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from “0” back to a “1.” Attempting to do so may cause that bank to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was success- ful. However, a succeeding read will show that the data is still “0.” Only erase operations can convert a “0” to a “1.” Unlock Bypass Command Sequence The unlock bypass feature allows the system to pro- gram bytes or words to a bank faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. That bank then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass pro- gram command, A0h; the second cycle contains the program address and data. Additional data is pro- grammed in the same manner. This mode dispenses with the initial two unlock cycles required in the stan- dard program command sequence, resulting in faster total programming time. Tables 15 and 16 show the re- quirements for the command sequence. During the unlock bypass mode, only the Unlock By- pass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset com- mand sequence. The first cycle must contain the bank address and the data 90h. The second cycle need only contain the data 00h. The bank then returns to the reading array data. The device offers accelerated program operations through the WP#/ACC pin. When the system asserts V HH on the WP#/ACC pin, the device automatically en- ters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program command sequence. The device uses the higher voltage on the WP#/ACC pin to accelerate the operation. Note that the WP#/ACC pin must not be at V HH any operation other than accelerated programming, or device dam- age may result. In addition, the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Figure 3 illustrates the algorithm for the program oper- ation. Refer to the Flash Erase and Program Operations table in the AC Characteristics section for parameters, and Figure 18 for timing diagrams.

30 Am41DL3208G February 13, 2002

Figure 3. Program Operation chip erase command sequence. section for information on these status bits. array data, to ensure data integrity. ings during these operations. quence and any additional addresses and commands. Note: Seefor program command sequence.

32 Am41DL3208G February 13, 2002

Table 15. Command Definitions (Flash Word Mode) RA = Address of the memory location to be read. RD = Data read from location RA during read operation. edge of WE# or CE#f pulse, whichever happens first. erased. Address bits A20–A12 uniquely select any sector. in bypass mode, or is being erased.

  1. See Table 1 for description of bus operations.
  2. All values are in hexadecimal.
  3. Except for the read cycle and the fourth cycle of the autoselect

command sequence, all bus cycles are write cycles.

  1. Data bits DQ15 –DQ8 are don’t care in command sequences,
  2. Unless otherwise noted, address bits A20 –A12 are don’t cares.
  3. No unlock or command cycles required when bank is in read
  4. The Reset command is required to return to reading array data

high (while the bank is providing status information).

  1. The fourth cycle of the autoselect command sequence is a read
  2. The device ID must be read across three cycles. The device ID is

00h for top boot and 01h for bottom boot.

  1. The data is 80h for factory locked and 00h for not factory locked.
  2. The data is 00h for an unprotected sector/sector block and 01h

for a protected sector/sector block.

  1. The Unlock Bypass command is required prior to the Unlock
  2. The Unlock Bypass Reset command is required to return to

reading array data when the bank is in the unlock bypass mode.

  1. The system may read and program in non-erasing sectors, or

enter the autoselect mode, when in the Erase Suspend mode. operation, and requires the bank address.

  1. The Erase Resume command is valid only during the Erase

Suspend mode, and requires the bank address.

  1. Command is valid when device is ready to read array data or when

device is in autoselect mode.

Table 16. Command Definitions (Flash Byte Mode) RA = Address of the memory location to be read. RD = Data read from location RA during read operation. edge of WE# or CE#f pulse, whichever happens first. erased. Address bits A20–A12 uniquely select any sector. in bypass mode, or is being erased.

  1. See Table 1 for description of bus operations.
  2. All values are in hexadecimal.
  3. Except for the read cycle and the fourth cycle of the autoselect

command sequence, all bus cycles are write cycles.

  1. Data bits DQ15 –DQ8 are don’t care in command sequences,
  2. Unless otherwise noted, address bits A20 –A12 are don’t cares.
  3. No unlock or command cycles required when bank is in read
  4. The Reset command is required to return to reading array data

high (while the bank is providing status information).

  1. The fourth cycle of the autoselect command sequence is a read

Autoselect Command Sequence section for more information.

  1. The device ID must be read across three cycles. The device ID is

00h for top boot and 01h for bottom boot.

  1. The data is 80h for factory locked and 00h for not factory locked.
  2. The data is 00h for an unprotected sector/sector block and 01h

for a protected sector/sector block.

  1. The Unlock Bypass command is required prior to the Unlock
  2. The Unlock Bypass Reset command is required to return to

reading array data when the bank is in the unlock bypass mode.

  1. The system may read and program in non-erasing sectors, or

enter the autoselect mode, when in the Erase Suspend mode. operation, and requires the bank address.

  1. The Erase Resume command is valid only during the Erase

Suspend mode, and requires the bank address.

  1. Command is valid when device is ready to read array data or when

device is in autoselect mode.

34 Am41DL3208G February 13, 2002

gram or erase operation is complete or in progress. Suspend mode, Data# Polling produces a “1” on DQ7. sector, the status may not be valid. Table 17 shows the outputs for Data# Polling on DQ7. Figure 5. Data# Polling Algorithm

  1. VA = Valid address for programming. During a sector

valid address is any non-protected sector address.

  1. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

36 Am41DL3208G February 13, 2002

DQ2: Toggle Bit II The “Toggle Bit II” on DQ2, when used with DQ6, indi- cates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for era- sure. (The system may use either OE# or CE#f to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-sus- pended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for era- sure. Thus, both status bits are required for sector and mode information. Refer to Table 17 to compare out- puts for DQ2 and DQ6. Figure 6 shows the toggle bit algorithm in flowchart form, and the section “DQ2: Toggle Bit II” explains the algorithm. See also the DQ6: Toggle Bit I subsection. Figure 23 shows the toggle bit timing diagram. Figure 24 shows the differences between DQ2 and DQ6 in graphical form. Reading Toggle Bits DQ6/DQ2 Refer to Figure 6 for the following discussion. When- ever the system initially begins reading toggle bit status, it must read DQ7 –DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the tog- gle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7 –DQ0 on the fol- lowing read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the sys- tem also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is tog- gling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the de- vice did not completed the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially de- termines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cy- cles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it re- turns to determine the status of the operation (top of Figure 6). DQ5: Exceeded Timing Limits DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a “1,” indicating that the program or erase cycle was not successfully completed. The device may output a “1” on DQ5 if the system tries to program a “1” to a location that was previously pro- grammed to “0. ” Only an erase operation can change a “0” back to a “1.” Under this condition, the device halts the operation, and when the timing limit has been exceeded, DQ5 produces a “1.” Under both these conditions, the system must write the reset command to return to reading array data (or to the erase-suspend-read mode if a bank was previ- ously in the erase-suspend-program mode). DQ3: Sector Erase Timer After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase com- mand. When the time-out period is complete, DQ3 switches from a “0” to a “1.” If the time between addi- tional sector erase commands from the system can be assumed to be less than 50 µs, the system need not monitor DQ3. See also the Sector Erase Command Sequence section. After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is “1,” the Embedded Erase algorithm has begun; all fur- ther commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is “0,” the device will accept additional sector erase commands. To ensure the command has been accepted, the sys- tem software should check the status of DQ3 prior to and following each subsequent sector erase com- mand. If DQ3 is high on the second status check, the last command might not have been accepted. Table 17 shows the status of DQ3 relative to the other status bits.

Table 17. Write Operation Status

  1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

Refer to the section on DQ5 for more information.

  1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further
  2. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm

is in progress. The device outputs array data if the system addresses a non-busy bank.

38 Am41DL3208G February 13, 2002

  1. Minimum DC voltage on input or I/O pins is –0.5 V.

SS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is V CC +0.5 V.

  1. Minimum DC input voltage on pins OE#, RESET#, and

overshoot to +12.0 V for periods up to 20 ns.

  1. No more than one output may be shorted to ground at a

operational sections of this data sheet is not implied. conditions for extended periods may affect device reliability. tionality of the device is guaranteed. Figure 7. Maximum Negative Figure 8. Maximum Positive

February 13, 2002 Am41DL3208G 39 PRELIMINARY DC CHARACTERISTICS CMOS Compatible Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit ILI Input Load Current VIN = VSS to VCC, VCC = VCC max ±1.0 µA ILIT RESET# Input Load Current V CC = VCC max; RESET# = 12.5 V 35 µA ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC max ±1.0 µA ILIA ACC Input Leakage Current VCC = VCC max, WP#/ACC = VACC max 35 µA ICC1f Flash VCC Active Read Current (Notes 1, 2) CE#f = VIL, OE# = VIH, Byte Mode

5 MHz 10 16

1 MHz 2 4

CE#f = VIL, OE# = VIH, Word Mode ICC2f Flash VCC Active Write Current (Notes 2, 3) CE#f = VIL, OE# = VIH, WE# = VIL 15 30 mA ICC3fF l a s h V CC Standby Current (Note 2) VCCf = VCC max, CE#f, RESET#, WP#/ACC = VCCf ± 0.3 V 0.2 5 µA ICC4fF l a s h V CC Reset Current (Note 2) VCCf = VCC max, RESET# = VSS ± 0.3 V, WP#/ACC = VCCf ± 0.3 V 0.2 5 µA ICC5f Flash VCC Current Automatic Sleep Mode (Notes 2, 4) VCCf = VCC max, VIH = VCC ± 0.3 V; VIL = VSS ± 0.3 V 0.2 5 µA ICC6f Flash VCC Active Read-While-Program Current (Notes 1, 2) CE#f = V IL, OE# = VIH Byte 21 45 mA Word 21 45 ICC7f Flash VCC Active Read-While-Erase Current (Notes 1, 2) CE#f = VIL, OE# = VIH Byte 21 45 mA Word 21 45 ICC8f Flash VCC Active Program-While-Erase-Suspended Current (Notes 2, 5) CE#f = V IL, OE#f = VIH 17 35 mA IACC ACC Accelerated Program Current, Word or Byte CE#f = VIL, OE# = VIH ACC pin 5 10 mA VCC pin 15 30 mA VIL Input Low Voltage –0.2 0.8 V VIH Input High Voltage 2.4 V CC + 0.2 V VHH Voltage for WP#/ACC Program Acceleration and Sector Protection/Unprotection 8.5 9.5 V V ID Voltage for Sector Protection, Autoselect and Temporary Sector Unprotect 11.5 12.5 V V OL Output Low Voltage IOL = 4.0 mA, VCCf = VCCs = VCC min 0.45 V VOH1 Output High Voltage IOH = –2.0 mA, VCCf = VCCs = VCC min 0.85 x VCC V VOH2 IOH = –100 µA, VCC = VCC min VCC–0.4 VLKO Flash Low VCC Lock-Out Voltage (Note 5) 2.3 2.5 V

40 Am41DL3208G February 13, 2002

Notes: 1. The I CC current listed is typically less than 2 mA/MHz, with OE# at V IH. 2. Maximum I CC specifications are tested with VCC = VCCmax. 3. I CC active while Embedded Erase or Embedded Program is in progress. 4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is 200 nA. 5. Not 100% tested. SRAM DC AND OPERATING CHARACTERISTICS Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit ILI Input Leakage Current V IN = VSS to VCC –1.0 1.0 µA ILO Output Leakage Current CE1#s = VIH, CE2s = VIL or OE# = VIH or WE# = VIL, VIO= VSS to VCC –1.0 1.0 µA ICC Operating Power Supply Current IIO = 0 mA, CE1#s = V IL, CE2s = WE# = VIH, VIN = VIH or VIL 3m A ICC1s Average Operating Current Cycle time = 1 µs, 100% duty, IIO = 0 mA, CE1#s ≤ 0.2 V, CE2 ≥ VCC – 0.2 V, VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V 3m A ICC2s Average Operating Current Cycle time = Min., IIO = 0 mA, 100% duty, CE1#s = VIL, CE2s = VIH, VIN = VIL = or VIH 30 mA VOL Output Low Voltage I OL = 2.1 mA 0.4 V VOH Output High Voltage I OH = –1.0 mA 2.4 V ISB Standby Current (TTL) CE1#s = VIH, CE2 = VIL, Other inputs = VIH or VIL 0.3 mA ISB1 Standby Current (CMOS) CE1#s ≥ VCC – 0.2 V, CE2 ≥ VCC –

0.2 V (CE1#s controlled) or CE2 ≤

0.2 V (CE2s controlled), CIOs =

V SS or VCC, Other input = 0 ~ V CC 15 µA

42 Am41DL3208G February 13, 2002

Table 18. Test Specifications Figure 11. Test Setup Figure 12. Input Waveforms and Measurement Levels

February 13, 2002 Am41DL3208G 43 PRELIMINARY AC CHARACTERISTICS SRAM CE#s Timing Figure 13. Timing Diagram for Alternating Between SRAM to Flash

Description

Test Setup All Speeds Unit JEDEC Std — tCCR CE#s Recover Time — Min 0 ns CE#f tCCR tCCR CE1#s CE2s tCCR tCCR

44 Am41DL3208G February 13, 2002

Flash Read-Only Operations Notes: 1. Not 100% tested. 2. See Figure 11 and Table 18 for test specifications. Parameter tAVAV tRC Read Cycle Time (Note 1) Min 70 85 ns tAVQV tACC Address to Output Delay CE#f, OE# = V IL Max 70 85 ns tELQV tCE Chip Enable to Output Delay OE# = V IL Max 70 85 ns tGLQV tOE Output Enable to Output Delay Max 30 40 ns tEHQZ tDF Chip Enable to Output High Z (Note 1) Max 16 ns tGHQZ tDF Output Enable to Output High Z (Note 1) Max 16 ns tAXQX tOH Output Hold Time From Addresses, CE#f or OE#, Whichever Occurs First Min 0 ns tOEH Output Enable Hold Time (Note 1) Read Min 0 ns Toggle and Data# Polling Min 10 ns tOH tCE Outputs WE# Addresses CE#f OE# HIGH Z Output Valid HIGH Z Addresses Stable tRC tACC tOEH tRH tOE tRH

0 VRY/BY#

RESET# tDF Figure 14. Read Operation Timings

Figure 15. Reset Timings

46 Am41DL3208G February 13, 2002

Figure 16. CIOf Timings for Read Operations Note: Refer to the Erase/Program Operations table for t AS and tAH specifications. Figure 17. CIOf Timings for Write Operations

February 13, 2002 Am41DL3208G 47 PRELIMINARY AC CHARACTERISTICS Flash Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Flash Erase And Programming Performance ” section for more information. Parameter Speed Options Unit JEDEC Std Description 70 85 tAVAV tWC Write Cycle Time (Note 1) Min 70 85 ns tAVWL tAS Address Setup Time (WE# to Address) Min 0 ns tASO Address Setup Time to OE# or CE#f Low During Toggle Bit Polling Min 15 ns tWLAX tAH Address Hold Time (WE# to Address) Min 45 ns tAHT Address Hold Time From CE#f or OE# High During Toggle Bit Polling Min 0 ns tDVWH tDS Data Setup Time Min 35 45 ns tWHDX tDH Data Hold Time Min 0 ns tOEH OE# Hold Time Read Min 0 ns Toggle and Data# Polling Min 10 ns tOEPH Output Enable High During Toggle Bit Polling Min 20 ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to CE#f Low) Min 0 ns tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tWLEL tWS WE# Setup Time (CE#f to WE#) Min 0 ns tELWL tCS CE#f Setup Time (WE# to CE#f) Min 0 ns tEHWH tWH WE# Hold Time (CE#f to WE#) Min 0 ns tWHEH tCH CE#f Hold Time (CE#f to WE#) Min 0 ns tWLWH tWP Write Pulse Width Min 30 35 ns tELEH tCP CE#f Pulse Width Min 30 35 ns tWHDL tWPH Write Pulse Width High Min 30 ns tSR/W Latency Between Read and Write Operations Min 0 ns tWHWH1 tWHWH1 Programming Operation (Note 2) Byte Typ 5 µs Word Typ 7 tWHWH1 tWHWH1 Accelerated Programming Operation, Word or Byte (Note 2) Typ 4 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.4 sec tVCS VCCf Setup Time (Note 1) Min 50 µs tRB Write Recovery Time From RY/BY# Min 0 ns tBUSY Program/Erase Valid To RY/BY# Delay Max 90 ns

48 Am41DL3208G February 13, 2002

Figure 19. Accelerated Program Timing Diagram

  1. PA = program address, PD = program data, D OUT is the true data at the program address.
  2. Illustration shows device in word mode.

Figure 18. Program Operation Timings

  1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status ”).
  2. These waveforms are for the word mode.

Figure 20. Chip/Sector Erase Operation Timings

50 Am41DL3208G February 13, 2002

Figure 21. Back-to-back Read/Write Cycle Timings Figure 22. Data# Polling Timings (During Embedded Algorithms)

52 Am41DL3208G February 13, 2002

54 Am41DL3208G February 13, 2002

Alternate CE#f Controlled Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Flash Erase And Programming Performance ” section for more information. Parameter Speed Options Unit JEDEC Std Description 70 85 tAVAV tWC Write Cycle Time (Note 1) Min 70 85 ns tAVWL tAS Address Setup Time (WE# to Address) Min 0 ns tASO Address Setup Time to CE#f Low During Toggle Bit Polling Min 15 ns tELAX tAH Address Hold Time Min 45 ns tAHT Address Hold time from CE#f or OE# High During Toggle Bit Polling Min 0 ns tDVEH tDS Data Setup Time Min 35 45 ns tEHDX tDH Data Hold Time Min 0 ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tWLEL tWS WE# Setup Time Min 0 ns tEHWH tWH WE# Hold Time Min 0 ns tELEH tCP CE#f Pulse Width Min 30 35 ns tEHEL tCPH CE#f Pulse Width High Min 30 ns tWHWH1 tWHWH1 Programming Operation (Note 2) Byte Typ 5 µs Word Typ 7 tWHWH1 tWHWH1 Accelerated Programming Operation, Word or Byte (Note 2) Typ 4 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.4 sec

  1. Figure indicates last two bus cycles of a program or erase operation.
  2. PA = program address, SA = sector address, PD = program data.
  3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device.
  4. Waveforms are for the word mode.

Figure 27. Flash Alternate CE#f Controlled Write (Erase/Program) Operation Timings

56 Am41DL3208G February 13, 2002

Figure 28. SRAM Read Cycle — Address Controlled

Figure 29. SRAM Read Cycle

  1. WE# = V IH, if CIOs is low, ignore UB#s/LB#s timing.
  2. t HZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output
  3. At any given temperature and voltage condition, tHZ (Max.) is less than tLZ (Min.) both for a given device and from device to device

58 Am41DL3208G February 13, 2002

  1. WE# controlled, if CIOs is low, ignore UB#s and LB#s timing.
  2. t CW is measured from CE1#s going low to the end of write.
  3. t WR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high.
  4. t AS is measured from the address valid to the beginning of write.
  5. A write occurs during the overlap (tWP) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when

Figure 30. SRAM Write Cycle — WE# Control

  1. CE1#s controlled, if CIOs is low, ignore UB#s and LB#s timing.
  2. t CW is measured from CE1#s going low to the end of write.
  3. t WR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high.
  4. t AS is measured from the address valid to the beginning of write.
  5. A write occurs during the overlap (tWP) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when

Figure 31. SRAM Write Cycle — CE1#s Control

60 Am41DL3208G February 13, 2002

  1. UB#s and LB#s controlled, CIOs must be high.
  2. t CW is measured from CE1#s going low to the end of write.
  3. t WR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high.
  4. t AS is measured from the address valid to the beginning of write.
  5. A write occurs during the overlap (tWP) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when

Figure 32. SRAM Write Cycle — UB#s and LB#s Control

February 13, 2002 Am41DL3208G 61 PRELIMINARY Flash Erase And Programming Performance Notes: 1. Typical program and erase times assume the following conditions: 25 °C, 3.0 V VCC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Tables 15 and 16 for further information on command definitions. 6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles. FLASH LATCHUP CHARACTERISTICS Note: Includes all pins except V CC. Test conditions: VCC = 3.0 V, one pin at a time. PACKAGE PIN CAPACITANCE Note: 7.Test conditions TA = 25°C, f = 1.0 MHz. FLASH DATA RETENTION Parameter Typ (Note 1) Max (Note 2) Unit Comments Sector Erase Time 0.4 5 sec Excludes 00h programming prior to erasure (Note 4)Chip Erase Time 28 sec Byte Program Time 5 150 µs Excludes system level overhead (Note 5) Word Program Time 7 210 µs Accelerated Byte/Word Program Time 4 120 µs Chip Program Time (Note 3) Byte Mode 21 63 sec Word Mode 14 42 Description Min Max Input voltage with respect to V SS on all pins except I/O pins (including OE#, and RESET#) –1.0 V 12.5 V Input voltage with respect to V SS on all I/O pins –1.0 V V CC + 1.0 V VCC Current –100 mA +100 mA Parameter Symbol Description Test Setup Typ Max Unit CIN Input Capacitance V IN = 0 1 11 4p F COUT Output Capacitance V OUT = 0 1 21 6p F CIN2 Control Pin Capacitance V IN = 0 1 41 6p F CIN3 WP#/ACC Pin Capacitance V IN = 0 1 72 0p F Parameter Description Test Conditions Min Unit Minimum Pattern Data Retention Time 150°C 10 Years 125°C 20 Years

62 Am41DL3208G February 13, 2002

  1. Typical values are not 100% tested.

Figure 33. CE1#s Controlled Data Retention Mode Figure 34. CE2s Controlled Data Retention Mode

February 13, 2002 Am41DL3208G 63 PRELIMINARY PHYSICAL DIMENSIONS FLB073— 73-Ball Fine-Pitch Grid Array 8 x 11.6 mm

64 Am41DL3208G February 13, 2002

Revision A (January 3, 2002) Initial release. Trademarks Copyright © 2002 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.