AM3517BZCN

AM3517_1005 TI | Alldatasheet

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PRODUCT□PREVIEW AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 AM3517/05ARM Microprocessor Check forSamples: AM3517 ,AM3505

1 AM3517/05 ARM Microprocessor

1.1 Features

– SIDETONE Core Support (McBSP2 and• AM3517/05 ARM Microprocessor:

3 Only)For Filter,Gain,and Mix– SoftwareCompatible withOMAP TM 3 OperationsProcessors

– 128-ChannelTransmit/ReceiveMode– MPU Subsystem – DirectInterfacetoI2Sand PCM Device• 600-MHz ARM Cortex-A8Core and TDM Buses• NEON SIMD Coprocessor and Vector • HDQ/1-Wire Interfacefloatingpoint(FP)co-processor

• 4 UARTs (One withInfraredData– Memory Interfaces: Association[IrDA]and Consumer Infrared• 16/32-bitmDDR/DDR2 Interfacewith1 [CIR]Modes)GByte totaladdressablespace • 3 Master/SlaveHigh-Speed• GeneralPurpose Memory Interface Inter-IntegratedCircuit(I2C)Controllerssupporting16-bitWide Multiplexed • 12 32-bitGeneralPurpose TimersAddress/Databus
• 1 32-bitWatchdog Timer• 64 K-Byte SRAM
• 1 32-bit32-kHz Sync Timer• 3 Removable Media Interfaces
• Up to186 General-PurposeI/O(GPIO)[MMC/SD/SDIO] Pins– IO Voltage:
• Displaysubsystem• mDDR/DDR2 IOs:1.8V – ParallelDigitalOutput• Other IOs:1.8Vand 3.3V – Up to24-BitRGB– Core Voltage:1.2V – Supports Up to2 LCD Panels– Commercial and IndustrialTemperature – Support forRemote Frame BufferInterfaceGrade (RFBI)LCD Panels(operatingrestrictionsapply) – Two 10-bitDigital-to-AnalogConverters– 16-bitVideo InputPortcapableofcapturing (DACs) SupportingHD video
• Composite NTSC/PAL Video– HD resolutionDisplaySubsystem
• Luma/Chroma SeparateVideo (S-Video)– SerialCommunication – Rotation90,180,and 270 degrees• High-End CAN Controller – ResizeImages From 1/4xto8x• 10/100MbitEthernetMAC – ColorSpace Converter• USB OTG subsystem withstandard DP/DM interface[HS/FS/LS] – 8-bitAlpha Blending
• MultiportUSB Host Subsystem • Video ProcessingFrontEnd (VPFE) 16-bit [HS/FS/LS] Video InputPort – 12-pinULPI or 6/4/3-pinSerial – RAW Data Interface Interface – 75-MHz Maximum PixelClock
• Four Master/SlaveMultichannelSerial – Supports REC656/CCIR656 Standard PortInterface(McSPI)Ports – Supports YCbCr422 Format (8-bitor 16-bit
• FiveMultichannelBufferedSerialPorts With DiscreteHorizontaland VerticalSync – 512-ByteTransmit/ReceiveBuffer Signals) (McBSP1/3/4/5) – Generates OpticalBlack Clamping Signals – 5K-Byte Transmit/ReceiveBuffer – Built-inDigitalClamping and Black Level (McBSP2) Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsofTexas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2POWERVR SGX isa trademarkofImaginationTechnologiesLtd. 3Allothertrademarksarethepropertyoftheirrespectiveowners. PRODUCT PREVIEW informationconcernsproductsintheformative Copyright© 2009–2010,Texas InstrumentsIncorporatedor design phase of development.Characteristicdata and other specificationsaredesigngoals.Texas Instrumentsreservestheright tochange ordiscontinuetheseproductswithoutnotice.

PRODUCT□PREVIEW AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Compensation – ARM Instructions-LittleEndian – 10-bitto8-bitA-law Compression Hardware – ARM Data – Configurable – Supports up to16K Pixels(Image Size)in • SDRC Memory Controller Horizontaland VerticalDirections – 16/32-bitMemory ControllerWith 1G-Byte

• System DirectMemory Access (sDMA) TotalAddress Space Controller(32LogicalChannels With – Double Data Rate (DDR2) SDRAM, mobile ConfigurablePriority) Double Data Rate (mDDR)SDRAM
• Comprehensive Power, Reset and Clock – SDRAM Memory Scheduler(SMS) and Management RotationEngine
• ARM CortexTM -A8 Memory Architecture • GeneralPurpose Memory Controller(GPMC) – ARMv7 Architecture – 16-bitWide MultiplexedAddress/DataBus
• TrustZone – Up to8 Chip SelectPins With 128M-Byte
• Thumb-2 Address Space per Chip SelectPin
• MMU Enhancements – GluelessInterfacetoNOR Flash,NAND Flash(WithECC Hamming Code– In-Order,Dual-Issue,Superscalar Calculation),SRAM and Pseudo-SRAMMicroprocessorCore – FlexibleAsynchronous ProtocolControlfor– NEON MultimediaArchitecture InterfacetoCustom Logic (FPGA, CPLD,– Over 2x Performance ofARMv6 SIMD ASICs, etc.)– Supports Both Integerand FloatingPoint – NonmultiplexedAddress/DataMode (LimitedSIMD 2K-Byte Address Space)– JAZELLE RCT ExecutionEnvironment • TestInterfacesArchitecture – IEEE-1149.1(JTAG) Boundary-Scan– Dynamic Branch PredictionwithBranch CompatibleTargetAddress Cache, Globalhistorybuffer – Embedded Trace Macro Interface(ETM)and 8 entryreturnstack
• 65-nm CMOS technology– Embedded Trace Macrocell[ETM] support forNon_invasiveDebug • Package s: – 16K-Byte instructionCache (4-Way set- – 491-pinBGA (17x17,0.65mm pitch) associative) [ZCN suffix] withviachannel arraytechnology– 16K-Byte Data Cache (4-Way Set-Associative) – 484-pinPBGA (23x23,1mm pitch) [ZER suffix]– 256K-Byte L2 Cache
• Applications:• POWERVR SGX ™ Graphics Accelerator – SingleBoard Computers– TileBased ArchitectureDeliveringup to10 MPoly/sec – Industrialand Home Automation – UniversalScalableShader Engine: – DigitalSignage Multi-threadedEngine IncorporatingPixel – PointofService and VertexShader Functionality – PortableMedia Player – IndustryStandard API Support:OpenGLES – PortableIndustrial1.1and 2.0,OpenVG1.0 – Transportation– FineGrained Task Switching,Load – NavigationBalancing,and Power Management – Smart White Goods– Programmable, High-QualityImage – DigitalTVAnti-Aliasing – DigitalVideo Camera• Endianess – Gaming

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1.2 Description

AM3517/05 high-performance,industrialapplicationsprocessorswith video,image, and graphics processingsufficienttosupportthefollowing:

• SingleBoard Computers
• Home and Industrialautomation
• DigitalSignage The devicesupportshigh-leveloperatingsystems(OSs),such as:
• Linux
• Windows CE The followingsubsystemsarepartofthedevice:
• Microprocessorunit(MPU) subsystembased on theARM Cortex-A8microprocessor
• POWERVR SGX ™ GraphicsAccelerator(AM3517 Deviceonly)Subsystem for3D graphics accelerationtosupportdisplayand gaming effects(AM3517 only)
• Displaysubsystemwithseveralfeaturesformultipleconcurrentimage manipulation,and a programmableinterfacesupportinga widevarietyofdisplays.The displaysubsystemalsosupports NTSC/PAL videoout.
• Highperformanceinterconnectsprovidehigh-bandwidthdatatransfersformultipleinitiatorstothe internaland externalmemory controllersand toon-chipperipherals.The devicealsooffersa comprehensiveclock-managementscheme. AM3517/05 devicesareavailableina 491-pinBGA package and a 484-pinPBGA package. ThisAM3517/05 data manual presentsthe electricaland mechanicalspecificationsforthe AM3517/05 ARM Microprocessor. Copyright© 2009–2010,Texas InstrumentsIncorporated AM3517/05 ARM Microprocessor 3 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW 64 64 Async 64 64 L2$ 256K MPU Subsystem ARM Cortex- A8TM Core 16K/16K L1$ POWERVR SGX Graphics Accelerator ( only) TM AM3517 3232 Channel System DMA 3232 Analog DAC LCD Panel CVBS or S-Video Dual Output 3-Layer Display Processor (1xGraphics, 2xVideo) Temporal Dithering SDTV → QCIF Support HS/FS/ LS USB Host L3 Interconnect Network-Hierarchial, Performance, and Power Driven 64K On-Chip RAM 132K On-Chip BOOT ROM SMS: SDRAM Memory Scheduler/ Rotation EMIF Controller L4 Interconnect System Controls PRCM External Peripherals Interfaces Peripherals: 4xUART, 3xHigh-Speed I2C, 5xMcBSP (2x with Sidetone/Audio Buffer) 4xMcSPI, 186xGPIO, 3xHigh-Speed MMC/SDIO, HDQ/1 Wire, 12xGPTimers, 1xWDT, 32K Sync Timer GPMC: General Purpose Memory Controller Emulation Debug: ETM, JTAGExternal DDR2/ mDDR SPRS550-006 Parallel HECC EMAC VPFE USB PHY USB OTG Controller DDR PHY NAND/NOR/ FLASH, SRAM USB transceivers / device ports [3] AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com

1.3 FunctionalBlock Diagram

Figure1-1shows thefunctionalblockdiagramoftheAM3517/05 ARM Microprocessor. Figure1-1.AM3517/05 FunctionalBlock Diagram

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1.4 ZCN and ZER Package Differences

Table1-1shows theZER and ZCN package differenceson thedevice. Table1-1.ZCN and ZER Package Differences FEATURE ZCN PACKAGE ZER PACKAGE PinAssignments ForZCN package pinassignments,see ForZER package pinassignments,see TerminalDescription TerminalDescription VideoInterfaces TV signalsavailable TV signalsnotavailable Copyright© 2009–2010,Texas InstrumentsIncorporated AM3517/05 ARM Microprocessor 5 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

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6 Contents Copyright© 2009–2010,Texas InstrumentsIncorporated

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PRODUCT□PREVIEW AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 RevisionHistory NOTE: Page numbers forpreviousrevisionsmay differfrompage numbers inthecurrentversion. This data manual revisionhistorytablehighlightsthe technicalchanges made to the SPRS550 device-specificdatamanual tomake itan SPRS550A revision. Scope:AM3517/05 devicenow supportsZER package. SEE ADDITIONS/MODIFICATIONS/DELETIONS Global • Added ZER package informationthroughoutdocument.

• Removed allinstancesofSDTI (notsupported).
• Removed allinstancesofCoresightTM . Section1.1 Updated/ChangedFeaturesSection:
• Added SDRC Memory Controller
• Changed 500-MHz ARM Cortex-A8to600-MHz ARM Cortex-A8 Section1.3 Updated/ChangedFunctionalBlockDiagram. Section1.4 Added ZCN and ZER Package Differencessection. Section2 Updated/Changedthefollowing:
• Figure2-1,Figure2-2,Figure2-3,Figure2-4
• Table2-1,BallCharacteristics(ZCN Package)
• Table2-3,MultiplexingCharacteristics
• Section2.4,SignalDescription-alltables Section3 Updated/Changedthefollowing:
• Table3-1,AbsoluteMaximum RatingsOver OperatingJunctionTemperatureRange
• Table3-2,EstimatedPower ConsumptionatBallLevel
• Table3-3,Recommended OperatingConditions
• Table3-4,DC ElectricalCharacteristics
• Section3.5,Power-upand Power-down-sequence and diagram Section4 Updated/Changedthefollowing:
• Added ,Oscillator
• Updated Section4.2,InputClockSpecifications
• Updated Section4.3,OutputClockSpecifications Section6 Updated/ChangedallpreviousTBD valuesinTimingConditionsand SwitchingCharacteristicstables throughoutentiresection. Section7.2.1 Updated/ChangedFigure7-1,DeviceNomenclaturetoincludeZER package information. Section7.1 Updated/ChangedTable7-1,AM3517/05 ThermalResistanceCharacteristics. Copyright© 2009–2010,Texas InstrumentsIncorporated Contents 7 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

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2 TERMINAL DESCRIPTION

2.1 Pin Assignments

2.1.1 Pin Map (Top View)

The followingillustrationsshow thetopand bottomviewsofthe484-pin[ZER]and 491-pin[ZCN]package pinassignmentsinfourquadrants(A,B,C, and D). Note: A pinwithan "NC" designatorindicatesNo Connection.For properdeviceoperation,thesepins must be leftunconnected.

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PRODUCT□PREVIEW N P R T U V 1415162223 N P W Y 2425 AA AB T U R 21 17181920 NC VDDS VSS VSS NCSYS_ CLKOUT1 VDDS_ DPLL_MPU _USBHOST VDDSHV 151617181920212223 AC 2425 AD AE VSS V W Y AA AB VSS AC AD AE VDDSHV VDDSHV VDDSHV VSS VSSVSS VDDS_DPLL_ PER_CORE VDDSHV VSS VDDSHV VDDSHV VSSVSS VSSVSS VSS VDD_CORE VDD_CORE VSSVSS VSS VDD_CORE VSSVDD_COREVDD_COREVSS VDD_COREVSSVSS VDD_COREVDD_CORE VDDSHV VDDSHVVDDSHV VDDS DSS_ACBIAS DSS_PCLK ETK_D15 ETK_D12 ETK_D8 ETK_D5 ETK_CTL MCSPI2_ CS1 MCSPI1_ CS3 MCSPI1_ CS2 MCSPI1_ CLK DSS_DA T A1 DSS_DA T A0 DSS_VSYNC DSS_HSYNC ETK_D13 ETK_D9 ETK_D6 ETK_D0 ETK_CLK MCSPI2_ CLK MCSPI1_ SIMO MCSPI1_ CS1 DSS_DA T A4 DSS_DA T A3 DSS_DA T A2 ETK_D14 ETK_D10 ETK_D1 MCSPI2_ SIMO MCSPI1_ SOMI DSS_DA T A6 DSS_DA T A5 ETK_D1 1 ETK_D7 ETK_D2 MCSPI2_ SOMI MCSPI1_CS0 DSS_DA T A9 DSS_DA T A8 DSS_DA T A7 UART1_TX ETK_D3 MCSPI2_ CS0 DSS_DA T A13 DSS_DA T A12DSS_DA T A1 1DSS_DA T A10 UART1_CTS UART1_RTS ETK_D4 DSS_DA T A18 DSS_DA T A17 DSS_DA T A16DSS_DA T A15 DSS_DA T A14 UART1_RX DSS_DA T A20 DSS_DA T A19 JT AG_TCK JT AG_NTRST DSS_ DA T A23 DSS_ DA T A22 DSS_ DA T A21 JT AG_EMU0 JT AG_TDO JT AG_TDI JT AG_TMS _TMSC JT AG_RTCK MCBSP1_ CLKR JT AG_ EMU1 MCBSP_ CLKS MCBSP1_ FSX MCBSP1_ DR MCBSP1_ DX MCBSP1_ FSR MCBSP1_ CLKX M MSYS_ CLKOUT2 VSS VSSVDD_CORESYS_ CLKREQ VSS VSS AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Figure2-1.ZCN Pin Map [QuadrantA] Copyright© 2009–2010,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 9 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW P R Y AA AB AC AD U V W T 10 9 8 P R T U V W Y AA AB AC ADCCDC_ PCLK 13 12 1 1 6 5 M N 4 37 M N 2 1 CCDC_ FIELD CCDC_ VD CCDC_ DA T A0 CCDC_ DA T A3 RMII_MDIO _CLKRMII_TXD0RMII_TXEN MMC1_ DA T1 MMC1_ DA T6MMC2_CLKMMC2_ DA T2 MMC2_ DA T6 VSS VSS VSS VSS VSS VSS VSS VSS VDDSHV VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDSHV VDDSHV VDDSHV VDDSHV VDDSHV GPMC_ NCS5 GPMC_ NCS4 GPMC_ NCS3 GPMC_ NCS2 GPMC_ NCS7 GPMC_ NCS6 GPMC_CLKUART3_CTS _RCTX UART3_RTS _SD UART3_RX _IRRX UART3_TX _IRTX GPMC_NADV _ALE GPMC_ NBE1 GPMC_ WAIT3 I2C2_SCL SYS_NIRQ SYS_ BOOT1 SYS_ BOOT4 SYS_ BOOT6 SYS_ BOOT7 SYS_ BOOT5 SYS_ BOOT2 SYS _NRES PWRON SYS_ BOOT8 13 12 1 1 10 9 8 7 6 5 4 3 AE 2 1 AECCDC_ HD VSSCCDC_ WEN CCDC_ DA T A1 CCDC_ DA T A4 RMII_MDIO _DA T ARMII_TXD1RMII_50MHZ _CLK MMC1_ DA T2 MMC1_ DA T7 MMC2_ CMD MMC2_ DA T3 MMC2_ DA T7 MMC2_ DA T1 MMC2_ DA T5 MMC2_ DA T0 MMC2_ DA T4 VDDS_SRAM _MPU CAP_VDD_ SRAM_MPU VDDSHV VDDSHV VDDSHV MMC1_ DA T0 MMC1_ DA T5 MMC1_ CMD MMC1_ DA T4 MMC1_CLKMMC1_ DA T3 VDDSHV VDDSHV VDDSHV VDDS VDD_CORE VDD_CORE VDD_CORE VDD_CORE VSS VSS VSS VSS VDD_CORE VDD_CORE VDD_CORE VDD_CORE VSS VSS VSS VSSVSS VSS VSS VSS CCDC_ DA T A2 CCDC_ DA T A7 CCDC_ DA T A6 CCDC_ DA T A5 VDDSHV VDDSHV VDDSHV VDDSHV RMII_RXER RMII_CRS_ DV RMII_RXD1 RMII_RXD0 VDDSHV VDDSHV VDDSHV I2C3_SDA I2C1_SDA I2C3_SCL I2C1_SCL SYS_ BOOT3 SYS _NRES WARM SYS_ BOOT0 I2C2_SDA HECC1_ TXD HECC1_ RXD GPMC_ NWP GPMC_ WAIT0 GPMC_ WAIT1 GPMC_ WAIT2 VDDS GPMC_NBE0 _CLE GPMC_ NWE GPMC_ NOE RESERVED RESERVED AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Figure2-2.ZCN Pin Map [QuadrantB]

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PRODUCT□PREVIEW L K J H G F E 2223 151617181920212223 E D D C C 2425 2425 B B A A 151617181920 L K J H G F VSSHDQ_ SIO NC NC NC VDDSHV VDD_CORE VSS VSS VSS NC NC TV_ OUT1 VSS VSS VSS VDD_CORE VDD_CORE VDD_CORE VDD_COREVDD_COREVDDSHV VSS VSS VDDSHV VDDS VDDS VDDS VDDS VDDS NCUART2_RTS SYS_ XT ALIN SYS_32K VSSOSC SYS_ XT ALOUT TV_ OUT2 TV_VFB2 VSSA_DAC VDDA_DAC TV_VFB1 VSSVSSUSB0_ID USB0_DP USB0_ DRVVBUS MCBSP2_ FSX MCBSP2_ CLKX MCBSP2_DR VSS MCBSP3_ CLKX MCBSP3_DX MCBSP3_ DR MCBSP2_ DX UART2 _TX MCBSP4_ DR MCBSP4_ CLKX MCBSP3_ FSX UART2_RX VDDA3P3V _USBPHY VDDA1P8V _USBPHY CAP_ VDDA1P2LDO _USBPHY MCBSP4_ FSX SDRC_ SDRC_ DQS0N SDRC_ STRBEN0 SDRC_ STRBEN _DL Y0 SDRC_ DQS1N SDRC_ D14 SDRC_ D15 SDRC_ NCS1 SDRC_ NWE SDRC_ DM1 SDRC_ D13 SDRC_ DQS1P SDRC_ SDRC_ SDRC_ DQS0P SDRC_ MCBSP4_ DX SDRC_DM0 SDRC_D3 SDRC_D6 SDRC_D10 SDRC_D12 SDRC_NRAS SDRC_CKE0 SDRC_NCAS VREFSSTL SDRC_D2 SDRC_D5 SDRC_D9 SDRC_D1 1 SDRC_D4 VDDS_SRAM _CORE_BG CAP_VDD_ SRAM_CORE USB0_DM UART2_CTS USB0_ VBUS VDDSHV VDDSOSCNC NCTV_VREF AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Figure2-3.ZCN Pin Map [QuadrantC] Copyright© 2009–2010,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 11 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW L K J H G F E 13 12 1 1 6 5 13 12 1 1 10 9 8 7 6 5 L K E DD CC 4 3 4 3 BB 10 9 8 H G F J 7 2 1 2 1 VSS VSS VSS AA VSS VSS VSS VSS VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDDSHV VDDSHV VDDSHV VDDSHVVSSVSS VDDSVSS VDDS VDDS GPMC_ NCS0 GPMC_ NCS1 GPMC_D12 GPMC_D13 GPMC_D14 GPMC_D15 GPMC_D1 1GPMC_D10GPMC_D8 GPMC_D9GPMC_D7 GPMC_D6GPMC_D5 GPMC_D4GPMC_D3GPMC_D1 GPMC_D2GPMC_D0 GPMC_A9GPMC_A8GPMC_A7GPMC_A6GPMC_A5GPMC_A4 GPMC_A3GPMC_A2GPMC_A1 SDRC_DM3 VSS VSS VDD_CORE VDD_COREVSS VSS VDD_CORE VDD_CORE VDDSVDDS VDDS VDDS VDDS VDDS SDRC_BA0SDRC_CLK SDRC_ NCLK SDRC_BA1 SDRC_BA2 SDRC_ NCS0 DDR_ P ADREF SDRC_A0 SDRC_A1 SDRC_A2 SDRC_A3 SDRC_ SDRC_ SDRC_A8 SDRC_A7 SDRC_A6 SDRC_A5 SDRC_A1 1 SDRC_ A10 SDRC_ A12 SDRC_ A13 SDRC_ ODT SDRC_A14 SDRC_DM2 SDRC_D19 SDRC_D18 SDRC_ D17 SDRC_ D16 GPMC_A10 SDRC_D21 SDRC_D20 SDRC_ DQS2N SDRC_ DQS2P SDRC_ STRBEN1 SDRC_D22 SDRC_D23 SDRC_24 SDRC_ STRBEN _DL Y1 SDRC_D25 SDRC_D26 SDRC_D27 SCRC_D29 SDRC_D28 SDRC_ DQS3N SDRC_ DQS3P SDRC_D30 SDRC_D31 AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Figure2-4.ZCN Pin Map [QuadrantD]

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PRODUCT□PREVIEW VSS VSS MMC2_DA T4 VDDS_DPLL_ MPU_ USBHOST LKJHGFEDC BA

22 VSS

VDDS_ SRAM_MPU VSS VDDS VSS VDD_CORE VSS VDD_CORE VSS VSSVDD_COREVSS VDD_COREVDD_COREVSS VSSVSS VSS VDDSHVVSS VDDSHV DSS_PCLK UART1_TX ETK_D8 ETK_D10 ETK_D1 ETK_CLK MCSPI2_ SOMI MCSPI2_CLK MCSPI1_CLK VDDSHV VDDSHV DSS_HSYNC UART1_RTS ETK_D9 ETK_D7 ETK_D5 ETK_CTL MCSPI2_CS0 MCSPI1_CS3 MMC2_DA T3 MMC2_DA T6 DSS_DA T A0 DSS_VSYNC UART1_RX ETK_D1 1 ETK_D2 MCSPI2_ SIMO MMC2_DA T0 MMC2_DA T5 DSS_DA T A1 DSS_ACBIAS ETK_D6 ETK_D3 MCSPI2_CS1 MCSPI1_SIMO MMC2_DA T1 DSS_DA T A2 DSS_DA T A3 DSS_DA T A5 VSS VDDSHV MCSPI1_CS0 DSS_DA T A4 DSS_DA T A8 DSS_DA T A9 DSS_DA T A6 VSS VDDSHV VSS DSS_DA T A13 DSS_DA T A7 DSS_DA T A10 DSS_DA T A1 1 VSS VDDS DSS_DA T A16 DSS_DA T A15 DSS_DA T A17 DSS_DA T A23 DSS_DA T A22 DSS_DA T A12 JT AG_TCK DSS_DA T A20 DSS_DA T A21 DSS_DA T A18 JT AG_NTRST JT AG_EMU0 JT AG_TMS_ TMSC JT AG_TDI LKJHGFEDCBA ETK_D13 ETK_D0 MCSPI1_CS1 UART1_CTS ETK_D14 ETK_D4 MCSPI1_CS2 ETK_D15 ETK_D12 VDDSHV MCSPI1_ SOMI VDDSHV VDDSHV VSS VDD_CORE DSS_DA T A19 DSS_DA T A14 VDDSHV VSS VDDS VDD_CORE VSS JT AG_RTCK JT AG_TDO JT AG_EMU1 VDDSHV VDDSHV AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Figure2-5.ZER Pin Map [QuadrantA] Copyright© 2009–2010,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 13 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW CCDC_FIELD CCDC_ PCLKCCDC_HDCCDC_WENCCDC_ DA T A2 RMII_ MDIO_DA T A RMII_ CRS_DV RMII_ 50MHZ_CLKMMC1_DA T0MMC1_CMDMMC2_CLK VSS GPMC_CLK GPMC_NOE HECC1_TXD HECC1_RXD I2C1_SDA SYS_NIRQ SYS_BOOT0 SYS_BOOT1SYS_BOOT7 SYS_BOOT3 SYS_NRES PWRON I2C1_SCL SYS_BOOT8 M N P R T U V W Y AA AB VDDSHV VSSCCDC_VDCCDC_ DA T A0 CCDC_ DA T A4 RMII_ MDIO_CLKRMII_TXD0RMII_RXERMMC1_CLKMMC1_DA T4VSS MMC1_DA T3MMC1_DA T1 MMC1_DA T2MMC1_DA T5 MMC1_DA T7MMC1_DA T6 VSS VDDSHV VSS VDDSHV VDD_CORE VDD_CORE VSS VDD_CORE VSS VSS VDD_CORE VSS VDD_CORE VSS VDD_CORE VDD_COREVSS VSS CCDC_ DA T A6 CCDC_ DA T A5 CCDC_ DA T A7 VSS VDDSHV VSS VSS VDDSHV RMII_RXD1 RMII_RXD0 VSS VDDSHV VDDS VDDSHV VSS RESERVED RESERVED I2C3_SCL UART3_CTS _RCTX SYS_NRE SWARM I2C2_SCLI2C3_SDA GPMC_ WAIT1 GPMC_NWEGPMC_NBE1 GPMC_ NADV_ALE UART3_RX _IRRX UART3_TX _IRTX UART3_RTS _SD GPMC_ WAIT0 GPMC_NCS3 GPMC_NCS5 GPMC_NCS2 GPMC_NCS6 M N P R T U V W Y AA AB MMC2_CMD RMII_TXD1 CCDC_ DA T A1 MMC2_DA T7 RMII_TXEN CCDC_ DA T A3 SYS_BOOT6 SYS_BOOT5 MMC2_DA T2 VDDSHV VDDSHV SYS_BOOT4 SYS_BOOT2 CAP_VDD _SRAM_MPU VSS VDDSHV VSS VDDSHV VSS I2C2_SDA VSS VDDSHV GPMC_ WAIT3 GPMC_NWP GPMC_ WAIT2 VDD_CORE VSS AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Figure2-6.ZER Pin Map [QuadrantB]

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PRODUCT□PREVIEW DC BA LKJHGF 1 1 E VSS MCBSP1 _CLKR MCBSP1_FSX MCBSP1_FSR MCBSP_CLKS VSS VSS VSS VDD_CORE VSS MCBSP1_DX NC SYS_ CLKOUT2 VSS VDD_CORE VDD_CORE VDD_COREVSSVDDSHV VSS VSS VDD_CORE VSS VDDS VDDS NC VDDS_SRAM _CORE_BGNC SYS_XT ALIN VSSOSC SYS_ XT ALOUT SYS_32K SYS_CLKREQ MCBSP1 _CLKX NC NC NC NC VDDA3P3V _USBPHY CAP_VDDA1 P2LDO_ USBPHY USB0_ DRVVBUS USB0_DP UART2_CTS MCBSP3_FSX MCBSP4 _CLKX MCBSP4_DX VSS VDDSHV MCBSP4_FSX MCBSP4_DR MCBSP3_DR UART2_RTS SDRC_D6 SDRC_D3 SDRC_D2 MCBSP2_DR UART2_RX VDDA1P8V _USBPHY UART2_TX SDRC_D7 SDRC_DQS0N SDRC_ STRBEN _DL Y0 SDRC_D13 SDRC_DQS1N SDRC_D15 SDRC_NRAS SDRC_CLK SDRC_NCLKSDRC_NWESDRC_DM1SDRC_DQS1PSDRC_D8SDRC_ STRBEN0SDRC_DQS0PSDRC_D5 SDRC_D0 SDRC_D4 SDRC_D9 SDRC_D14 SDRC_CKE0 SDRC_DM0 SDRC_D1 1 SDRC_NCS0 SDRC_NCS1 VSS SDRC_BA2 SDRC_BA1 USB0_DM VSS USB0_ID VSS DCBA LKJHGFE 1 1 VDDS_ DPLL_PER _CORE VSS VDD_CORE HDQ_SIO MCBSP1_DR NC SYS_ CLKOUT1 NC VDDSOSC VSS VDDSHV USB0_VBUS VSS VSS VSS VSS CAP_VDD_ SRAM_CORE MCBSP2 _CLKX MCBSP2_FSX VDDS VDDS VREFSSTL MCBSP3_DX MCBSP3 _CLKX MCBSP2_DX SDRC_D12 SDRC_BA0 SDRC_D1 SDRC_D10 SDRC_NCAS AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Figure2-7.ZER Pin Map [QuadrantC] Copyright© 2009–2010,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 15 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW M N P W Y 1 1 AA AB R T U V VDD_CORE VSS VDD_CORE VSS VSS VDD_CORE VDDSHV VSS VSS VDDSHV GPMC_D14 GPMC_D8 GPMC_NCS0 GPMC_D15VSSVDDSHV VDDSHVVSS VDDS VDDS GPMC_D12 GPMC_D10 GPMC_D3 GPMC_D9GPMC_D13 GPMC_D0 GPMC_A9GPMC_D1 GPMC_A6GPMC_A7GPMC_A8VSS GPMC_A5 VSS VDD_CORE VDD_CORE VSSVSS VDD_CORE VSS VDD_CORE VDD_COREVDD_CORE VDDS VSS VSS VDDS VDDSVSS DDR_ P ADREF SDRC_A0 SDRC_A1 SDRC_A2 SDRC_A4 SDRC_A8 SDRC_A7 SDRC_A6 SDRC_A9 VDDS VSS SDRC_A13 SDRC_A12 SDRC_A1 1 SDRC_A10 SDRC_A14 SDRC_ ODT SDRC_ DQS2P SDRC_ DQS2N SDRC_D17 SDRC_D18 VSS SDRC_D22 SDRC_D19 SDRC_D21 SDRC_ D20 GPMC_D2 SDRC_D25 SDRC_D24 SDRC_ STRBEN _DL Y1 SDRC_ STRBEN1 SDRC_ DQS3P SDRC_ DQS3N SDRC_D26 SDRC_D28 VDDS VSS SDRC_D31 SDRC_DM3 M N P W Y AA ABR T U V 1 1 GPMC_NCS7 GPMC_ NBE0_CLE GPMC_NCS1 GPMC_NCS4 VDDSHV VDD_COREVSS GPMC_D1 1 VDDSHV GPMC_D5 GPMC_D6GPMC_D4GPMC_D7 VSS VSS VDDSHV GPMC_A10VSSVSS VDDS VDDS GPMC_A1 GPMC_A2 GPMC_A4 GPMC_A3SDRC_D27 SDRC_D30SDRC_DM2SDRC_A5 SDRC_A3 SDRC_D16 SDRC_D23 SDRC_D29 AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Figure2-8.ZER Pin Map [QuadrantD]

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PRODUCT□PREVIEW AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010

2.2 BallCharacteristics

Table2-1describestheterminalcharacteristicsand thesignalsmultiplexedon each pinfortheZCN/ZER package.The followinglistdescribesthetablecolumn headers. 1. BALL LOCATION: Ballnumber(s)on thebottomsideassociatedwitheach signal(s)on thebottom. 2. PIN NAME: Names ofsignalsmultiplexedon each ball(alsonoticethatthename ofthepinisthe signalname inmode 0). Note:The BallCharacteristicstabledoes nottakeintoaccountsubsystempinmultiplexingoptions. Subsystem pinmultiplexingoptionsaredescribedinSection2.4,SignalDescriptions. 3. MODE: Multiplexingmode number. (a) Mode 0 istheprimarymode; thismeans thatwhen mode 0 isset,thefunctionmapped on thepin correspondstothename ofthepin.Thereisalwaysa functionmapped on theprimarymode. Noticethatprimarymode isnotnecessarilythedefaultmode. Note: The defaultmode isthe mode which isautomaticallyconfiguredon releaseof the internal GLOBAL_PWRON reset;alsosee theRESET REL. MODE column. (b) Modes 1 to7 arepossiblemodes foralternatefunctions.On each pin,some modes areeffectively used foralternatefunctions,whilesome modes arenotused and do notcorrespondtoa functional configuration. 4. TYPE: Signaldirection – I= Input – O = Output – I/O= Input/Output – D = Open drain – DS = Differential – A = Analog Note:Inthesafe_mode,thebufferisconfiguredinhigh-impedance. 5. BALL RESET STATE: The stateoftheterminalatreset(powerup). – 0:The bufferdrivesVOL (pulldown/pullupresistornotactivated) 0(PD):The bufferdrivesVOL withan activepulldownresistor. – 1:The bufferdrivesVOH (pulldown/pullupresistornotactivated) 1(PU):The bufferdrivesVOH withan activepullupresistor. – Z:High-impedance – L:High-impedancewithan activepulldownresistor – H :High-impedancewithan activepullupresistor 6. BALL RESET REL. STATE: The stateoftheterminalatresetrelease. – 0:The bufferdrivesVOL (pulldown/pullupresistornotactivated) 0(PD):The bufferdrivesVOL withan activepulldownresistor. – 1:The bufferdrivesVOH (pulldown/pullupresistornotactivated) 1(PU):The bufferdrivesVOH withan activepullupresistor. – Z:High-impedance – L:High-impedancewithan activepulldownresistor – H :High-impedancewithan activepullupresistor 7. RESET REL. MODE: Thismode isautomaticallyconfiguredon releaseoftheinternal GLOBAL_PWRON reset. 8. POWER: The voltagesupplythatpowers theterminal’s I/Obuffers. 9. VOLTAGE :Supplyvoltageforassociatedpin. 10. HYS :Indicatesiftheinputbufferiswithhysteresis. 11. LOAD: Load capacitanceoftheassociatedoutputbuffer. 12. PULL U/D -TYPE: Denotesthepresenceofan internalpulluporpulldownresistor.Pullupand pulldownresistorscan be enabledordisabledviasoftware. Copyright© 2009–2010,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 17 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com 13. IO CELL: IO cellinformation. Note:Configuringtwo pinstothesame inputsignalisnotsupportedas itcan yieldunexpectedresults. Thiscan be easilypreventedwiththepropersoftwareconfiguration. Table2-1.BallCharacteristics(ZCN Pkg.) BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13] LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12] [1] STATE [5] STATE [6] B21 sdrc_d0 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS A21 sdrc_d1 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS D20 sdrc_d2 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS C20 sdrc_d3 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS E19 sdrc_d4 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS D19 sdrc_d5 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS C19 sdrc_d6 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS B19 sdrc_d7 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS B18 sdrc_d8 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS D17 sdrc_d9 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS C17 sdrc_d10 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS D16 sdrc_d11 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS C16 sdrc_d12 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS B16 sdrc_d13 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS A16 sdrc_d14 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS A15 sdrc_d15 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS A7 sdrc_d16 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS B7 sdrc_d17 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS D7 sdrc_d18 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS E7 sdrc_d19 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS C6 sdrc_d20 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS D6 sdrc_d21 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS B5 sdrc_d22 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS C5 sdrc_d23 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS B4 sdrc_d24 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS A3 sdrc_d25 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS B3 sdrc_d26 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS C3 sdrc_d27 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS C2 sdrc_d28 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS D2 sdrc_d29 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS B1 sdrc_d30 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS C1 sdrc_d31 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS A12 sdrc_ba0 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS C13 sdrc_ba1 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS D13 sdrc_ba2 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS A11 sdrc_a0 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS B11 sdrc_a1 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS C11 sdrc_a2 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS D11 sdrc_a3 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS E11 sdrc_a4 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS A10 sdrc_a5 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS B10 sdrc_a6 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS C10 sdrc_a7 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS D10 sdrc_a8 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS E10 sdrc_a9 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS A9 sdrc_a10 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS B9 sdrc_a11 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS A8 sdrc_a12 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS B8 sdrc_a13 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS

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PRODUCT□PREVIEW AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Table2-1.BallCharacteristics(ZCN Pkg.)(continued) BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13] LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12] [1] STATE [5] STATE [6] D8 sdrc_a14 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS E13 sdrc_ncs0 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS A14 sdrc_ncs1 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS A13 sdrc_clk 0 O L Z 0 VDDS 1.8V Yes 8 PU/ PD LVCMOS B13 sdrc_nclk 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS D14 sdrc_cke0 0 O L PD 7 VDDS 1.8V Yes 8 PU/ PD LVCMOS sdrc_cke0_s 7 L afe C14 sdrc_nras 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS E14 sdrc_ncas 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS B14 sdrc_nwe 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS C21 sdrc_dm0 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS B15 sdrc_dm1 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS E8 sdrc_dm2 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS D1 sdrc_dm3 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS B20 sdrc_dqs0p 0 IO L Z 0 VDDS 1.8V Yes 8 PU/ PD LVCMOS B17 sdrc_dqs1p 0 IO L Z 0 VDDS 1.8V Yes 8 PU/ PD LVCMOS A6 sdrc_dqs2p 0 IO L Z 0 VDDS 1.8V Yes 8 PU/ PD LVCMOS A2 sdrc_dqs3p 0 IO L Z 0 VDDS 1.8V Yes 8 PU/ PD LVCMOS A20 sdrc_dqs0n 0 IO L Z 0 VDDS 1.8V 8 PU/ PD LVCMOS A17 sdrc_dqs1n 0 IO L Z 0 VDDS 1.8V 8 PU/ PD LVCMOS B6 sdrc_dqs2n 0 IO L Z 0 VDDS 1.8V 8 PU/ PD LVCMOS B2 sdrc_dqs3n 0 IO L Z 0 VDDS 1.8V 8 PU/ PD LVCMOS C8 sdrc_odt 0 L Z 0 VDDS 1.8V 8 PU/ PD LVCMOS A19 sdrc_strben00 L Z 0 VDDS 1.8V 8 PU/ PD LVCMOS A18 sdrc_strben_0 L Z 0 VDDS 1.8V 8 PU/ PD LVCMOS dly0 A5 sdrc_strben10 L Z 0 VDDS 1.8V 8 PU/ PD LVCMOS A4 sdrc_strben_0 L Z 0 VDDS 1.8V 8 PU/ PD LVCMOS dly1 B12 ddr_padref 0 A VDDS 1.8V E3 gpmc_a1 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_34 4 IO safe_mode 7 E2 gpmc_a2 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_35 4 IO safe_mode 7 E1 gpmc_a3 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_36 4 IO safe_mode 7 F7 gpmc_a4 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_37 4 IO safe_mode 7 F6 gpmc_a5 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_38 4 IO safe_mode 7 F4 gpmc_a6 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_39 4 IO safe_mode 7 F3 gpmc_a7 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_40 4 IO safe_mode 7 F2 gpmc_a8 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_41 4 IO safe_mode 7 Copyright© 2009–2010,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 19 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Table2-1.BallCharacteristics(ZCN Pkg.)(continued) BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13] LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12] [1] STATE [5] STATE [6] F1 gpmc_a9 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS sys_ 1 I ndmareq2 gpio_42 4 IO safe_mode 7 G6 gpmc_a10 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS sys_ 1 I ndmareq3 gpio_43 4 IO safe_mode 7 G5 gpmc_d0 0 IO H PU 0 VDDSHV 1.8V/3.3V 30 PU/ PD LVCMOS G4 gpmc_d1 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS G3 gpmc_d2 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS G2 gpmc_d3 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS G1 gpmc_d4 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS H2 gpmc_d5 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS H1 gpmc_d6 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS J5 gpmc_d7 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS J4 gpmc_d8 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_44 4 IO J3 gpmc_d9 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_45 4 IO J2 gpmc_d10 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_46 4 IO J1 gpmc_d11 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_47 4 IO K4 gpmc_d12 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_48 4 IO K3 gpmc_d13 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_49 4 IO K2 gpmc_d14 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_50 4 IO K1 gpmc_d15 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_51 4 IO L2 gpmc_ncs0 0 O H Z 0 VDDSHV 1.8V/3.3V No 30 NA LVCMOS L1 gpmc_ncs1 0 O H Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_52 4 IO M4 gpmc_ncs2 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpt9_pwm_e 2 IO vt gpio_53 4 IO safe_mode 7 M3 gpmc_ncs3 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS sys_ 1 I ndmareq0 gpt10_pwm_ 2 IO evt gpio_54 4 IO safe_mode 7 M2 gpmc_ncs4 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS sys_ 1 I ndmareq1 gpt9_pwm_e 3 IO vt gpio_55 4 IO safe_mode 7

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PRODUCT□PREVIEW AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Table2-1.BallCharacteristics(ZCN Pkg.)(continued) BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13] LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12] [1] STATE [5] STATE [6] M1 gpmc_ncs5 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS sys_ 1 I ndmareq2 gpt10_pwm_ 3 IO evt gpio_56 4 IO safe_mode 7 N5 gpmc_ncs6 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS sys_ 1 I ndmareq3 gpt11_pwm_ 3 IO evt gpio_57 4 IO safe_mode 7 N4 gpmc_ncs7 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpmc_io_dir 1 O gpt8_pwm_e 3 IO vt gpio_58 4 IO safe_mode 7 N1 gpmc_clk 0 O L Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_59 4 IO R1 gpmc_nadv_ 0 O L Z 0 VDDSHV 1.8V/3.3V No 30 PU/ PD LVCMOS ale R2 gpmc_noe 0 O H Z 0 VDDSHV 1.8V/3.3V No 30 PU/ PD LVCMOS R3 gpmc_nwe 0 O H Z 0 VDDSHV 1.8V/3.3V No 30 PU/ PD LVCMOS R4 gpmc_nbe0_ 0 O L Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS cle gpio_60 4 IO T1 gpmc_nbe1 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_61 4 IO safe_mode 7 T2 gpmc_nwp 0 O L Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_62 4 IO T3 gpmc_wait0 0 I H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS T4 gpmc_wait1 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS uart4_tx 1 O gpio_63 4 IO safe_mode 7 T5 gpmc_wait2 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS uart4_rx 1 I gpio_64 4 IO safe_mode 7 U1 gpmc_wait3 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS sys_ 1 I ndmareq1 uart3_cts_rct2 I x gpio_65 4 IO safe_mode 7 AE23 dss_pclk 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS gpio_66 4 IO safe_mode 7 AD22 dss_hsync 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS gpio_67 4 IO safe_mode 7 AD23 dss_vsync 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS gpio_68 4 IO Copyright© 2009–2010,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 21 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Table2-1.BallCharacteristics(ZCN Pkg.)(continued) BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13] LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12] [1] STATE [5] STATE [6] safe_mode 7 AE24 dss_acbias 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS gpio_69 4 IO safe_mode 7 AD24 dss_data0 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS uart1_cts 2 I dssvenc656_ 3 I data0 gpio_70 4 IO safe_mode 7 AD25 dss_data1 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS uart1_rts 2 O dssvenc656_ 3 I data1 gpio_71 4 IO safe_mode 7 AC23 dss_data2 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS dssvenc656_ 3 I data2 gpio_72 4 IO safe_mode 7 AC24 dss_data3 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS dssvenc656_ 3 I data3 gpio_73 4 IO safe_mode 7 AC25 dss_data4 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS uart3_rx_irrx2 I dssvenc656_ 3 I data4 gpio_74 4 IO safe_mode 7 AB24 dss_data5 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS uart3_tx_irtx2 O dssvenc656_ 3 I data5 gpio_75 4 IO safe_mode 7 AB25 dss_data6 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS uart1_tx 2 O dssvenc656_ 3 I data6 gpio_76 4 IO safe_mode 7 AA23 dss_data7 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS uart1_rx 2 I dssvenc656_ 3 I data7 gpio_77 4 IO safe_mode 7 AA24 dss_data8 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS gpio_78 4 IO safe_mode 7 AA25 dss_data9 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS gpio_79 4 IO safe_mode 7 Y22 dss_data10 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS

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PRODUCT□PREVIEW AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Table2-1.BallCharacteristics(ZCN Pkg.)(continued) BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13] LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12] [1] STATE [5] STATE [6] gpio_80 4 IO safe_mode 7 Y23 dss_data11 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS gpio_81 4 IO safe_mode 7 Y24 dss_data12 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS gpio_82 4 IO safe_mode 7 Y25 dss_data13 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS gpio_83 4 IO safe_mode 7 W21 dss_data14 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS gpio_84 4 IO safe_mode 7 W22 dss_data15 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS gpio_85 4 IO safe_mode 7 W23 dss_data16 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS gpio_86 4 IO safe_mode 7 W24 dss_data17 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS gpio_87 4 IO safe_mode 7 W25 dss_data18 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS mcspi3_clk 2 IO dss_data4 3 O gpio_88 4 IO safe_mode 7 V24 dss_data19 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS mcspi3_ 2 IO simo dss_data3 3 O gpio_89 4 IO safe_mode 7 V25 dss_data20 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS mcspi3_ 2 IO somi dss_data2 3 O gpio_90 4 IO safe_mode 7 U21 dss_data21 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS mcspi3_cs0 2 IO dss_data1 3 O gpio_91 4 IO safe_mode 7 U22 dss_data22 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS mcspi3_cs1 2 O dss_data0 3 O gpio_92 4 IO safe_mode 7 U23 dss_data23 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS dss_data5 3 O gpio_93 4 IO safe_mode 7 H24 tv_out2 0 O 0 VDDA_DAC 1.8V NA 10-bitDAC Copyright© 2009–2010,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 23 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Table2-1.BallCharacteristics(ZCN Pkg.)(continued) BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13] LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12] [1] STATE [5] STATE [6] K21 tv_out1 0 O 0 VDDA_DAC 1.8V NA 10-bitDAC K20 tv_vfb1 0 O Z NA 0 VDDA_DAC 1.8V NA 10-bitDAC H23 tv_vfb2 0 O Z NA 0 VDDA_DAC 1.8V NA 10-bitDAC H20 tv_vref 0 I Z NA 0 VDDA_DAC 1.8V NA 10-bitDAC AD2 ccdc_pclk 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/ PD LVCMOS gpio_94 4 IO safe_mode 7 AD1 ccdc_field 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/ PD LVCMOS ccdc_data8 1 I uart4_tx 2 O i2c3_scl 3 IOD gpio_95 4 IO safe_mode 7 AE2 ccdc_hd 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/ PD LVCMOS uart4_rts 2 O gpio_96 4 IO safe_mode 7 AD3 ccdc_vd 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/ PD LVCMOS uart4_cts 2 I gpio_97 4 IO safe_mode 7 AE3 ccdc_wen 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/PD LVCMOS ccdc_data9 1 I uart4_rx 2 I gpio_98 4 IO safe_mode 7 AD4 ccdc_data0 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/PD LVCMOS i2c3_sda 3 IOD gpio_99 4 I safe_mode 7 AE4 ccdc_data1 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/PD LVCMOS gpio_100 4 I safe_mode 7 AC5 ccdc_data2 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/ PD LVCMOS gpio_101 4 IO safe_mode 7 AD5 ccdc_data3 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/ PD LVCMOS gpio_102 4 IO safe_mode 7 AE5 ccdc_data4 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/ PD LVCMOS gpio_103 4 IO safe_mode 7 Y6 ccdc_data5 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/ PD LVCMOS gpio_104 4 IO safe_mode 7 AB6 ccdc_data6 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/PD LVCMOS gpio_105 4 IO safe_mode 7 AC6 ccdc_data7 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/PD LVCMOS gpio_106 4 IO safe_mode 7 AE6 rmii_mdio_da0 IO H PU 7 VDDSHV 1.8V/3.3V Yes 25 PU/PD LVCMOS ta ccdc_data8 1 I gpio_107 4 IO

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PRODUCT□PREVIEW AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Table2-1.BallCharacteristics(ZCN Pkg.)(continued) BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13] LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12] [1] STATE [5] STATE [6] safe_mode 7 AD6 rmii_mdio_cl0 O H PU 7 VDDSHV 1.8V/3.3V Yes 25 PU/PD LVCMOS k ccdc_data9 1 I gpio_108 4 IO safe_mode 7 Y7 rmii_rxd0 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 25 PU/ PD LVCMOS ccdc_data10 1 I gpio_109 4 IO safe_mode 7 AA7 rmii_rxd1 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 25 PU/ PD LVCMOS ccdc_data11 1 I gpio_110 4 IO safe_mode 7 AB7 rmii_crs_dv 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 25 PU/ PD LVCMOS ccdc_data12 1 I gpio_111 4 IO safe_mode 7 AC7 rmii_rxer 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 25 PU/ PD LVCMOS ccdc_data13 1 I gpio_167 4 IO safe_mode 7 AD7 rmii_txd0 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 25 PU/ PD LVCMOS ccdc_data14 1 I gpio_126 4 IO safe_mode 7 AE7 rmii_txd1 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 25 PU/PD LVCMOS ccdc_data15 1 I gpio_112 4 I safe_mode 7 AD8 rmii_txen 0 O H PU 7 VDDSHV 1.8V/3.3V 25 PU/PD LVCMOS gpio_113 4 I NA safe_mode 7 AE8 rmii_50mhz_ 0 I H PU 7 VDDSHV 1.8V/3.3V 25 PU/ PD LVCMOS clk gpio_114 4 I NA safe_mode 7 D25 mcbsp2_fsx 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_116 4 IO safe_mode 7 C25 mcbsp2_ 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS clkx gpio_117 4 IO safe_mode 7 B25 mcbsp2_dr 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_118 4 IO safe_mode 7 D24 mcbsp2_dx 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_119 4 IO safe_mode 7 AA9 mmc1_clk 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_120 4 IO safe_mode 7 AB9 mmc1_cmd 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_121 4 IO Copyright© 2009–2010,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 25 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Table2-1.BallCharacteristics(ZCN Pkg.)(continued) BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13] LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12] [1] STATE [5] STATE [6] safe_mode 7 AC9 mmc1_dat0 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS mcspi2_clk 1 IO gpio_122 4 IO safe_mode 7 AD9 mmc1_dat1 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS mcspi2_simo 1 IO gpio_123 4 IO safe_mode 7 AE9 mmc1_dat2 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS mcspi2_somi 1 IO gpio_124 4 IO safe_mode 7 AA10 mmc1_dat3 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS mcspi2_cs0 1 O gpio_125 4 IO safe_mode 7 AB10 mmc1_dat4 0 IO L PD 7 VDDSHV 1.8V/3.3V No 30 PU/ PD LVCMOS gpio_126 4 IO safe_mode 7 AC10 mmc1_dat5 0 IO L PD 7 VDDSHV 1.8V/3.3V No 30 PU/ PD LVCMOS gpio_127 4 IO safe_mode 7 AD10 mmc1_dat6 0 IO L PD 7 VDDSHV 1.8V/3.3V No 30 PU/ PD LVCMOS gpio_128 4 IO safe_mode 7 AE10 mmc1_dat7 0 IO L PD 7 VDDSHV 1.8V/3.3V No 30 PU/ PD LVCMOS gpio_129 4 IO safe_mode 7 AD11 mmc2_clk 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS mcspi3_clk 1 IO uart4_cts 2 I gpio_130 4 IO safe_mode 7 AE11 mmc2_ cmd 0 IO H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS mcspi3_ 1 IO simo uart4_rts 2 O gpio_131 4 IO safe_mode 7 AB12 mmc2_ dat0 0 IO H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS mcspi3_ 1 IO somi uart4_tx 2 O gpio_132 4 IO safe_mode 7 AC12 mmc2_ dat1 0 IO H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS uart4_rx 2 I gpio_133 4 IO safe_mode 7 AD12 mmc2_ dat2 0 IO H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS mcspi3_cs1 1 O gpio_134 4 IO safe_mode 7 AE12 mmc2_ dat3 0 IO H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

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PRODUCT□PREVIEW AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Table2-1.BallCharacteristics(ZCN Pkg.)(continued) BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13] LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12] [1] STATE [5] STATE [6] mcspi3_cs0 1 IO gpio_135 4 IO safe_mode 7 AB13 mmc2_ dat4 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS mmc2_dir_da 1 O mmc3_dat0 3 IO gpio_136 4 IO safe_mode 7 AC13 mmc2_ dat5 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS mmc2_dir_da 1 O mmc3_dat1 3 IO gpio_137 4 IO mm_fsusb3_r 6 IO xdp safe_mode 7 AD13 mmc2_ dat6 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS mmc2_dir_ 1 O cmd mmc3_dat2 3 IO gpio_138 4 IO safe_mode 7 AE13 mmc2_ dat7 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS mmc2_ clkin1 I mmc3_dat3 3 IO gpio_139 4 IO mm_fsusb3_r 6 IO xdm safe_mode 7 B24 mcbsp3_dx 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS uart2_cts 1 I gpio_140 4 IO safe_mode 7 C24 mcbsp3_dr 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS uart2_rts 1 O gpio_141 4 IO safe_mode 7 A24 mcbsp3_ 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS clkx uart2_tx 1 O gpio_142 4 IO safe_mode 7 C23 mcbsp3_fsx 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS uart2_rx 1 I gpio_143 4 IO safe_mode 7 F20 uart2_cts 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS mcbsp3_dx 1 IO gpt9_pwm_e 2 IO vt gpio_144 4 IO safe_mode 7 F19 uart2_rts 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS mcbsp3_dr 1 I gpt10_pwm_ 2 IO evt Copyright© 2009–2010,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 27 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Table2-1.BallCharacteristics(ZCN Pkg.)(continued) BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13] LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12] [1] STATE [5] STATE [6] gpio_145 4 IO safe_mode 7 E24 uart2_tx 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS mcbsp3_ 1 IO clkx gpt11_pwm 2 IO _evt gpio_146 4 IO safe_mode 7 E23 uart2_rx 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS mcbsp3_fsx 1 IO gpt8_pwm_e 2 IO vt gpio_147 4 IO safe_mode 7 AA19 uart1_tx 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_148 4 IO safe_mode 7 Y19 uart1_rts 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_149 4 IO safe_mode 7 Y20 uart1_cts 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_150 4 IO safe_mode 7 W20 uart1_rx 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS mcbsp1_ clkr2 I mcspi4_clk 3 IO gpio_151 4 IO safe_mode 7 B23 mcbsp4_ 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS clkx gpio_152 4 IO mm_fsusb3_t 6 IO xse0 safe_mode 7 A23 mcbsp4_dr 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_153 4 IO mm_fsusb3_r 6 IO xrcv safe_mode 7 B22 mcbsp4_dx 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_154 4 IO mm_fsusb3_t 6 IO xdat safe_mode 7 A22 mcbsp4_fsx 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_155 4 IO mm_fsusb3_t 6 IO xen_ n safe_mode 7 R25 mcbsp1_ clkr0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS mcspi4_clk 1 IO gpio_156 4 IO safe_mode 7 P21 mcbsp1_fsr 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_157 4 IO safe_mode 7

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PRODUCT□PREVIEW AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Table2-1.BallCharacteristics(ZCN Pkg.)(continued) BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13] LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12] [1] STATE [5] STATE [6] P22 mcbsp1_dx 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS mcspi4_ 1 IO simo mcbsp3_dx 2 IO gpio_158 4 IO safe_mode 7 P23 mcbsp1_dr 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS mcspi4_ 1 IO somi mcbsp3_dr 2 I gpio_159 4 IO safe_mode 7 P25 mcbsp_clks 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_160 4 IO uart1_cts 5 I safe_mode 7 P24 mcbsp1_fsx 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS mcspi4_cs0 1 IO mcbsp3_fsx 2 IO gpio_161 4 IO safe_mode 7 N24 mcbsp1_ 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS clkx mcbsp3_ 2 IO clkx gpio_162 4 IO safe_mode 7 N2 uart3_cts_ 0 IO H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS rctx gpio_163 4 IO safe_mode 7 N3 uart3_rts_sd 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_164 4 IO safe_mode 7 P1 uart3_rx_irrx0 I H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_165 4 IO safe_mode 7 P2 uart3_tx_irtx0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_166 4 IO safe_mode 7 F25 usb0_dp 0 IO 5.0V Yes PU/ PD LVCMOS uart3_tx_irtx1 O F24 usb0_dm 0 IO 5.0V Yes PU/ PD LVCMOS uart3_rx_irrx1 I G24 usb0_vbus 0 A VDDA3P3V_ 5.0V Yes PU/ PD LVCMOS USBPHY G25 usb0_id 0 A VDDA3P3V_ 3.3V Yes PU/ PD LVCMOS USBPHY E25 usb0_drvvbu 0 O L PD 7 VDDSHV 1.8V/3.3V 30 s uart3_tx_irtx2 O gpio_125 4 IO safe_mode 7 V2 hecc1_ txd 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 24 PU/ PD LVCMOS uart3_rx_irrx2 I gpio_130 4 IO safe_mode 7 Copyright© 2009–2010,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 29 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Table2-1.BallCharacteristics(ZCN Pkg.)(continued) BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13] LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12] [1] STATE [5] STATE [6] V3 hecc1_ rxd 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 24 PU/ PD LVCMOS uart3_rts_sd 2 O gpio_131 4 IO safe_mode 7 V4 i2c1_scl 0 IOD H PU 0 VDDSHV 1.8V/3.3V Yes 40 PU/ PD Open Drain V5 i2c1_sda 0 IOD H PU 0 VDDSHV 1.8V/3.3V Yes 40 PU/ PD Open Drain W1 i2c2_scl 0 IOD H PU 7 VDDSHV 1.8V/3.3V Yes 40 PU/ PD Open Drain gpio_168 4 IO safe_mode 7 W2 i2c2_sda 0 IOD H PU 7 VDDSHV 1.8V/3.3V Yes 40 PU/ PD Open Drain gpio_183 4 IO safe_mode 7 W4 i2c3_scl 0 IOD H PU 7 VDDSHV 1.8V/3.3V Yes 40 PU/ PD Open Drain gpio_184 4 IO safe_mode 7 W5 i2c3_sda 0 IOD H PU 7 VDDSHV 1.8V/3.3V Yes 40 PU/ PD Open Drain gpio_185 4 IO safe_mode 7 L25 hdq_sio 0 IO H PU 7 VDDSHV 1.8V/3.3V Yes 40 PU/ PD LVCMOS sys_altclk 1 I i2c2_sccbe 2 O i2c3_sccbe 3 O gpio_170 4 IO safe_mode 7 AE14 mcspi1_clk 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS mmc2_dat4 1 IO gpio_171 4 IO safe_mode 7 AD15 mcspi1_ 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS simo mmc2_dat5 1 IO gpio_172 4 IO safe_mode 7 AC15 mcspi1_ 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS somi mmc2_dat6 1 IO gpio_173 4 IO safe_mode 7 AB15 mcspi1_cs0 0 IO H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS mmc2_dat7 1 IO gpio_174 4 IO safe_mode 7 AD14 mcspi1_cs1 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS mmc3_cmd 3 IO gpio_175 4 IO safe_mode 7 AE15 mcspi1_cs2 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS mmc3_clk 3 O gpio_176 4 IO safe_mode 7 AE16 mcspi1_cs3 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS hsusb2_ 3 IO data2 gpio_177 4 IO mm_fsusb2_t 5 IO xdat

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PRODUCT□PREVIEW AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Table2-1.BallCharacteristics(ZCN Pkg.)(continued) BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13] LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12] [1] STATE [5] STATE [6] safe_mode 7 AD16 mcspi2_clk 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS hsusb2_ 3 IO data7 gpio_178 4 IO safe_mode 7 AC16 mcspi2_ 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS simo gpt9_pwm_e 1 IO vt hsusb2_ 3 IO data4 gpio_179 4 IO safe_mode 7 AB16 mcspi2_ 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS somi gpt10_pwm_ 1 IO evt hsusb2_ 3 IO data5 gpio_180 4 IO safe_mode 7 AA16 mcspi2_cs0 0 IO H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpt11_pwm_ 1 IO evt hsusb2_ 3 IO data6 gpio_181 4 IO safe_mode 7 AE17 mcspi2_cs1 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpt8_pwm_e 1 IO vt hsusb2_ 3 IO data3 gpio_182 4 IO mm_fsusb2_t 5 IO xen_ n safe_mode 7 K24 sys_32k 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS K25 sys_xtalin 0 I Z Z 0 VDDSOSC 1.8V NA PU/ PD LVCMOS H25 sys_xtalout 0 O Z Z 0 VDDSOSC 1.8V NA PU/ PD LVCMOS M24 sys_clkreq 0 IO L Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_1 4 IO Y1 sys_nirq 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_0 4 IO safe_mode 7 Y2 sys_ 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS nrespwron Y3 sys_ 0 IO L PD 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS nreswarm gpio_30 4 IO Open Drain Y4 sys_boot0 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_2 4 IO AA1 sys_boot1 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_3 4 IO AA2 sys_boot2 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_4 4 IO AA3 sys_boot3 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_5 4 IO AB1 sys_boot4 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS Copyright© 2009–2010,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 31 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Table2-1.BallCharacteristics(ZCN Pkg.)(continued) BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13] LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12] [1] STATE [5] STATE [6] mmc2_dir_da 1 O gpio_6 4 IO AB2 sys_boot5 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS mmc2_dir_da 1 O gpio_7 4 IO AC1 sys_boot6 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_8 4 IO AC2 sys_boot7 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/PD LVCMOS AC3 sys_boot8 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/PD LVCMOS N25 sys_clkout1 0 O H PD 0/7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_10 4 IO safe_mode 7 M25 sys_clkout2 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 10 PU/ PD LVCMOS gpio_186 4 IO safe_mode 7 U24 jtag_ntrst 0 I L PD 0 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS U25 jtag_tck 0 I L PD 0 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS T21 jtag_rtck 0 O L Z 0 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS T22 jtag_tms_tms0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS c T23 jtag_tdi 0 I H PU 0 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS T24 jtag_tdo 0 O L Z 0 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS T25 jtag_emu0 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS gpio_11 4 IO R24 jtag_emu1 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS gpio_31 4 IO AD17 etk_clk 0 O H PU 4 VDDSHV 1.8V/3.3V Yes 9,25 PU/ PD LVCMOS mcbsp5_ 1 IO clkx mmc3_clk 2 O hsusb1_stp 3 O gpio_12 4 IO AE18 etk_ctl 0 O H PU 4 VDDSHV 1.8V/3.3V Yes 9,25 PU/ PD LVCMOS mmc3_cmd 2 IO hsusb1_clk 3 O gpio_13 4 IO mm_fsusb1_r 5 IO xdp AD18 etk_d0 0 O H PU 4 VDDSHV 1.8V/3.3V Yes 9,25 PU/ PD LVCMOS mcspi3_ 1 IO simo mmc3_dat4 2 IO hsusb1_ 3 IO data0 gpio_14 4 IO mm_fsusb1_r 5 IO xrcv AC18 etk_d1 0 O H PU 4 VDDSHV 1.8V/3.3V Yes 9,25 PU/ PD LVCMOS mcspi3_ 1 IO somi hsusb1_ 3 IO data1 gpio_15 4 IO mm_fsusb1_t 5 IO xse0 AB18 etk_d2 0 O H PU 4 VDDSHV 1.8V/3.3V Yes 9,25 PU/ PD LVCMOS

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PRODUCT□PREVIEW AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Table2-1.BallCharacteristics(ZCN Pkg.)(continued) BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13] LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12] [1] STATE [5] STATE [6] mcspi3_cs0 1 IO hsusb1_ 3 IO data2 gpio_16 4 IO mm_fsusb1_t 5 IO xdat AA18 etk_d3 0 O L PU 4 VDDSHV 1.8V/3.3V Yes 9,25 PU/ PD LVCMOS mcspi3_clk 1 IO mmc3_dat3 2 IO hsusb1_ 3 IO data7 gpio_17 4 IO Y18 etk_d4 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9,25 PU/ PD LVCMOS mcbsp5_dr 1 I mmc3_dat0 2 IO hsusb1_ 3 IO data4 gpio_18 4 IO AE19 etk_d5 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9,25 PU/ PD LVCMOS mcbsp5_fsx 1 IO mmc3_dat1 2 IO hsusb1_ 3 IO data5 gpio_19 4 IO AD19 etk_d6 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9,25 PU/ PD LVCMOS mcbsp5_dx 1 IO mmc3_dat2 2 IO hsusb1_ 3 IO data6 gpio_20 4 IO AB19 etk_d7 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9,25 PU/ PD LVCMOS mcspi3_cs1 1 O mmc3_dat7 2 IO hsusb1_ 3 IO data3 gpio_21 4 IO mm_fsusb1_t 5 IO xen_n AE20 etk_d8 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9,25 PU/ PD LVCMOS mmc3_dat6 2 IO hsusb1_dir 3 I gpio_22 4 IO AD20 etk_d9 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9,25 PU/ PD LVCMOS mmc3_dat5 2 IO hsusb1_nxt 3 I gpio_23 4 IO mm_fsusb1_r 5 IO xdm AC20 etk_d10 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9,25 PU/ PD LVCMOS uart1_rx 2 I hsusb2_clk 3 O gpio_24 4 IO AB20 etk_d11 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9,25 PU/ PD LVCMOS mcspi3_clk 1 IO hsusb2_stp 3 O gpio_25 4 IO mm_fsusb2_r 5 IO xdp Copyright© 2009–2010,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 33 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Table2-1.BallCharacteristics(ZCN Pkg.)(continued) BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13] LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12] [1] STATE [5] STATE [6] AE21 etk_d12 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9,25 PU/ PD LVCMOS hsusb2_dir 3 I gpio_26 4 IO AD21 etk_d13 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9,25 PU/ PD LVCMOS hsusb2_nxt 3 I gpio_27 4 IO mm_fsusb2_r 5 IO xdm AC21 etk_d14 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9,25 PU/ PD LVCMOS hsusb2_ 3 IO data0 gpio_28 4 IO mm_fsusb2_r 5 IO xrcv AE22 etk_d15 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9,25 PU/ PD LVCMOS hsusb2_ 3 IO data1 gpio_29 4 IO mm_fsusb2_t 5 IO xse0 V16,V15, VDD_CORE 0 PWR 1.2V V11,V10, U16, U15, U11, U10, T18,T17,T9, T8,R18, R17, R9, R8, M18, L18, L9,L8,K18, K17,K9,K8, J16,J15, J11,J10, H15, H11, H10 AA13 VDDS_SRA 0 PWR 1.8V M_MPU E17 VDDS_SRA 0 PWR 1.8V M_CORE_B G AA12 CAP_VDD_S 0 PWR 1.2V RAM_MPU E16 CAP_VDD_S 0 PWR 1.2V RAM_CORE AA15 VDDS_DPLL 0 PWR 1.8V _MPU_USB HOST N20 VDDS_DPLL 0 PWR 1.8V _PER_CORE H21 VDDA_DAC 0 PWR 1.8V F23 VDDA3P3V_ 0 PWR 3.3V USBPHY G22 VDDA1P8V_ 0 PWR 1.8V USBPHY F22 CAP_VDDA1 0 PWR 1.2V P2LDO_USB PHY Y16,Y15, VDDSHV 0 PWR 1.8V/3.3V Y13,Y12, Y10,W16, W15, W13, W12,W10, W9, W6, V7, V6,U19, T20,T19,T7, T6,R7, R6, P20,P19, N19, N7, N6, M7, M6, M5, L19,K19, K7,K6,K5, J7,H18, H17

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PRODUCT□PREVIEW AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Table2-1.BallCharacteristics(ZCN Pkg.)(continued) BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13] LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12] [1] STATE [5] STATE [6] Y9,W18, VDDS 0 PWR 1.8V U20, R5, H16, H8, G17, G16, G14, G13, G11, G10, G8, F16, F13,F11, F10,F8 F14 VREFSSTL 0 I L20 VDDSOSC 0 PWR 1.8V J25 VSSOSC O GND 1.8V AE25, AE1, VSS 0 GND V18,V17, V14,V13, V12,V9,V8, U18, U17, U14, U13, U12, U9, U8, T14,T13, T12,R16, R15, R14, R13, R12, R11, R10, P18,P17, P16,P15, P14,P13, P12,P11, P10,P9,P8, N18, N17, N14, N13, N12, N9, N8, M17, M16, M15, M14, M13,M12, M11, M10, M9, M8, L17, L16,L15, L14,L13, L12,L11, L10,K14, K13,K12, J18,J17, J14,J13, J12,J9,J8, H14, H13, H12, H9, A25,A1, N23, G20, G21 H22 VSSA_DAC 0 GND L24,L23, NC (1) L22,L21, K23,K22, H19, N22,N21,F17 U2 (2) Reserved V1 (2) Reserved (1) "NC "indicates"No Connect".Forproperdeviceoperation,thesepinsmust be leftunconnected. (2) Forproperdeviceoperation,thispinmust be pulledup viaa 10k-Ω resistor. Copyright© 2009–2010,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 35 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Table2-2.BallCharacteristics(ZER Pkg.) BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13] LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12] [1] STATE [5] STATE [6] E3 sdrc_d0 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS D3 sdrc_d1 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS C3 sdrc_d2 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS C2 sdrc_d3 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS F3 sdrc_d4 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS D2 sdrc_d5 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS C1 sdrc_d6 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS D1 sdrc_d7 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS G2 sdrc_d8 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS G3 sdrc_d9 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS H3 sdrc_d10 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS G4 sdrc_d11 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS H4 sdrc_d12 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS G1 sdrc_d13 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS J3 sdrc_d14 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS J1 sdrc_d15 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS T3 sdrc_d16 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS U3 sdrc_d17 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS U4 sdrc_d18 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS V4 sdrc_d19 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS V1 sdrc_d20 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS V2 sdrc_d21 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS V5 sdrc_d22 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS V3 sdrc_d23 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS W3 sdrc_d24 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS W4 sdrc_d25 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS Y3 sdrc_d26 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS Y4 sdrc_d27 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS AA2 sdrc_d28 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS AA3 sdrc_d29 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS AA4 sdrc_d30 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS AB2 sdrc_d31 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS L4 sdrc_ba0 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS K5 sdrc_ba1 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS J5 sdrc_ba2 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS M3 sdrc_a0 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS M4 sdrc_a1 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS M5 sdrc_a2 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS N3 sdrc_a3 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS N2 sdrc_a4 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS N4 sdrc_a5 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS P3 sdrc_a6 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS P2 sdrc_a7 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS P1 sdrc_a8 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS P4 sdrc_a9 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS R1 sdrc_a10 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS R2 sdrc_a11 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS R3 sdrc_a12 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS R4 sdrc_a13 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS T2 sdrc_a14 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS J4 sdrc_ncs0 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS K4 sdrc_ncs1 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS L1 sdrc_clk 0 O L Z 0 VDDS 1.8V Yes 8 PU/ PD LVCMOS L2 sdrc_nclk 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS

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PRODUCT□PREVIEW AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Table2-2.BallCharacteristics(ZER Pkg.)(continued) BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13] LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12] [1] STATE [5] STATE [6] K3 sdrc_cke0 0 O L PD 7 VDDS 1.8V Yes 8 PU/ PD LVCMOS K1 sdrc_nras 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS L3 sdrc_ncas 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS K2 sdrc_nwe 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS F4 sdrc_dm0 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS J2 sdrc_dm1 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS T4 sdrc_dm2 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS AB3 sdrc_dm3 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS E2 sdrc_dqs0p 0 IO L Z 0 VDDS 1.8V Yes 8 PU/ PD LVCMOS H2 sdrc_dqs1p 0 IO L Z 0 VDDS 1.8V Yes 8 PU/ PD LVCMOS U1 sdrc_dqs2p 0 IO L Z 0 VDDS 1.8V Yes 8 PU/ PD LVCMOS Y1 sdrc_dqs3p 0 IO L Z 0 VDDS 1.8V Yes 8 PU/ PD LVCMOS E1 sdrc_dqs0n 0 IO L Z 0 VDDS 1.8V 8 PU/ PD LVCMOS H1 sdrc_dqs1n 0 IO L Z 0 VDDS 1.8V 8 PU/ PD LVCMOS U2 sdrc_dqs2n 0 IO L Z 0 VDDS 1.8V 8 PU/ PD LVCMOS Y2 sdrc_dqs3n 0 IO L Z 0 VDDS 1.8V 8 PU/ PD LVCMOS T1 sdrc_odt 0 L Z 0 VDDS 1.8V 8 PU/ PD LVCMOS F2 sdrc_strben00 L Z 0 VDDS 1.8V 8 PU/ PD LVCMOS F1 sdrc_strben_0 L Z 0 VDDS 1.8V 8 PU/ PD LVCMOS dly0 W1 sdrc_strben10 L Z 0 VDDS 1.8V 8 PU/ PD LVCMOS W2 sdrc_strben_0 L Z 0 VDDS 1.8V 8 PU/ PD LVCMOS dly1 W5 gpmc_a1 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_34 4 IO Y5 gpmc_a2 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_35 4 IO AB4 gpmc_a3 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_36 4 IO AA5 gpmc_a4 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_37 4 IO AB5 gpmc_a5 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_38 4 IO AB6 gpmc_a6 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_39 4 IO AA6 gpmc_a7 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_40 4 IO W6 gpmc_a8 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_41 4 IO AB7 gpmc_a9 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS sys_ 1 I ndmareq2 gpio_42 4 IO Y6 gpmc_a10 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS sys_ 1 I ndmareq3 gpio_43 4 IO AA7 gpmc_d0 0 IO H PU 0 VDDSHV 1.8V/3.3V 30 PU/ PD LVCMOS Y7 gpmc_d1 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS W7 gpmc_d2 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS AA9 gpmc_d3 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS Y8 gpmc_d4 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS AA8 gpmc_d5 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS AB8 gpmc_d6 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS W8 gpmc_d7 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS W10 gpmc_d8 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS Copyright© 2009–2010,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 37 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Table2-2.BallCharacteristics(ZER Pkg.)(continued) BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13] LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12] [1] STATE [5] STATE [6] gpio_44 4 IO AB9 gpmc_d9 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_45 4 IO AB10 gpmc_d10 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_46 4 IO W9 gpmc_d11 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_47 4 IO AA10 gpmc_d12 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_48 4 IO Y9 gpmc_d13 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_49 4 IO V10 gpmc_d14 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_50 4 IO V9 gpmc_d15 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_51 4 IO Y10 gpmc_ncs0 0 O H Z 0 VDDSHV 1.8V/3.3V No 30 NA LVCMOS Y11 gpmc_ncs1 0 O H Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_52 4 IO Y12 gpmc_ncs2 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpt9_pwm_e 2 IO vt gpio_53 4 IO V12 gpmc_ncs3 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS sys_ 1 I ndmareq0 gpt10_pwm_ 2 IO evt gpio_54 4 IO AA11 gpmc_ncs4 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS sys_ 1 I ndmareq1 gpt9_pwm_e 3 IO vt gpio_55 4 IO W12 gpmc_ncs5 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS sys_ 1 I ndmareq2 gpt10_pwm_ 3 IO evt gpio_56 4 IO AA12 gpmc_ncs6 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS sys_ 1 I ndmareq3 gpt11_pwm_ 3 IO evt gpio_57 4 IO V11 gpmc_ncs7 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpmc_io_dir 1 O gpt8_pwm_e 3 IO vt gpio_58 4 IO AB13 gpmc_clk 0 O L Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_59 4 IO AA14 gpmc_nadv_ 0 O L Z 0 VDDSHV 1.8V/3.3V No 30 PU/ PD LVCMOS ale AB14 gpmc_noe 0 O H Z 0 VDDSHV 1.8V/3.3V No 30 PU/ PD LVCMOS AA15 gpmc_nwe 0 O H Z 0 VDDSHV 1.8V/3.3V No 30 PU/ PD LVCMOS W11 gpmc_nbe0_ 0 O L Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS cle

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PRODUCT□PREVIEW AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Table2-2.BallCharacteristics(ZER Pkg.)(continued) BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13] LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12] [1] STATE [5] STATE [6] gpio_60 4 IO Y15 gpmc_nbe1 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_61 4 IO W14 gpmc_nwp 0 O L Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_62 4 IO V13 gpmc_wait0 0 I H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS AA16 gpmc_wait1 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS uart4_tx 1 O gpio_63 4 IO Y14 gpmc_wait2 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS uart4_rx 1 I gpio_64 4 IO V14 gpmc_wait3 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS sys_ 1 I ndmareq1 uart3_cts_rct2 I x gpio_65 4 IO B22 dss_pclk 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS gpio_66 4 IO B21 dss_hsync 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS gpio_67 4 IO B20 dss_vsync 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS gpio_68 4 IO B19 dss_acbias 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS gpio_69 4 IO A20 dss_data0 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS gpio_70 4 IO A19 dss_data1 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS gpio_71 4 IO A18 dss_data2 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS gpio_72 4 IO B18 dss_data3 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS gpio_73 4 IO A17 dss_data4 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS gpio_74 4 IO C18 dss_data5 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS gpio_75 4 IO D17 dss_data6 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS gpio_76 4 IO B16 dss_data7 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS gpio_77 4 IO B17 dss_data8 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS gpio_78 4 IO C17 dss_data9 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS gpio_79 4 IO C16 dss_data10 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS gpio_80 4 IO D16 dss_data11 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS gpio_81 4 IO D14 dss_data12 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS gpio_82 4 IO A16 dss_data13 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS gpio_83 4 IO D15 dss_data14 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS Copyright© 2009–2010,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 39 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Table2-2.BallCharacteristics(ZER Pkg.)(continued) BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13] LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12] [1] STATE [5] STATE [6] gpio_84 4 IO B15 dss_data15 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS gpio_85 4 IO A15 dss_data16 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS gpio_86 4 IO A14 dss_data17 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS gpio_87 4 IO C13 dss_data18 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS mcspi3_clk 2 IO gpio_88 4 IO C15 dss_data19 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS mcspi3_ 2 IO simo gpio_89 4 IO A13 dss_data20 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS mcspi3_ 2 IO somi gpio_90 4 IO B13 dss_data21 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS mcspi3_cs0 2 IO gpio_91 4 IO C14 dss_data22 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS mcspi3_cs1 2 O gpio_92 4 IO B14 dss_data23 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS gpio_93 4 IO AB21 ccdc_pclk 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/ PD LVCMOS gpio_94 4 IO AA21 ccdc_field 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/ PD LVCMOS ccdc_data8 1 I uart4_tx 2 O gpio_95 4 IO Y21 ccdc_hd 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/ PD LVCMOS uart4_rts 2 O gpio_96 4 IO Y22 ccdc_vd 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/ PD LVCMOS uart4_cts 2 I gpio_97 4 IO W21 ccdc_wen 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/PD LVCMOS ccdc_data9 1 I uart4_rx 2 I gpio_98 4 IO W22 ccdc_data0 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/PD LVCMOS gpio_99 4 I W20 ccdc_data1 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/PD LVCMOS gpio_100 4 I V21 ccdc_data2 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/ PD LVCMOS gpio_101 4 IO V19 ccdc_data3 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/ PD LVCMOS gpio_102 4 IO V22 ccdc_data4 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/ PD LVCMOS gpio_103 4 IO U20 ccdc_data5 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/ PD LVCMOS gpio_104 4 IO V20 ccdc_data6 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/PD LVCMOS

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PRODUCT□PREVIEW AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Table2-2.BallCharacteristics(ZER Pkg.)(continued) BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13] LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12] [1] STATE [5] STATE [6] gpio_105 4 IO U19 ccdc_data7 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/PD LVCMOS gpio_106 4 IO U21 rmii_mdio_da0 IO H PU 7 VDDSHV 1.8V/3.3V Yes 25 PU/PD LVCMOS ta ccdc_data8 1 I gpio_107 4 IO 8 U22 rmii_mdio_clk0 O H PU 7 VDDSHV 1.8V/3.3V Yes 25 PU/PD LVCMOS ccdc_data9 1 I 8 gpio_108 4 IO T19 rmii_rxd0 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 25 PU/ PD LVCMOS ccdc_data10 1 I gpio_109 4 IO T20 rmii_rxd1 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 25 PU/ PD LVCMOS ccdc_data11 1 I gpio_110 4 IO T21 rmii_crs_dv 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 25 PU/ PD LVCMOS ccdc_data12 1 I gpio_111 4 IO R22 rmii_rxer 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 25 PU/ PD LVCMOS ccdc_data13 1 I gpio_167 4 IO T22 rmii_txd0 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 25 PU/ PD LVCMOS ccdc_data14 1 I gpio_126 4 IO R20 rmii_txd1 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 25 PU/PD LVCMOS ccdc_data15 1 I gpio_112 4 I R19 rmii_txen 0 O H PU 7 VDDSHV 1.8V/3.3V 25 PU/PD LVCMOS gpio_113 4 I NA R21 rmii_50mhz_ 0 I H PU 7 VDDSHV 1.8V/3.3V 25 PU/ PD LVCMOS clk gpio_114 4 I NA E5 mcbsp2_fsx 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_116 4 IO D5 mcbsp2_ clkx0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_117 4 IO C5 mcbsp2_dr 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_118 4 IO E4 mcbsp2_dx 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_119 4 IO P22 mmc1_clk 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_120 4 IO N21 mmc1_cmd 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_121 4 IO P21 mmc1_dat0 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS mcspi2_clk 1 IO gpio_122 4 IO N20 mmc1_dat1 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS mcspi2_simo 1 IO gpio_123 4 IO P19 mmc1_dat2 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS mcspi2_somi 1 IO gpio_124 4 IO P20 mmc1_dat3 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS Copyright© 2009–2010,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 41 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Table2-2.BallCharacteristics(ZER Pkg.)(continued) BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13] LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12] [1] STATE [5] STATE [6] mcspi2_cs0 1 O gpio_125 4 IO N22 mmc1_dat4 0 IO L PD 7 VDDSHV 1.8V/3.3V No 30 PU/ PD LVCMOS gpio_126 4 IO N19 mmc1_dat5 0 IO L PD 7 VDDSHV 1.8V/3.3V No 30 PU/ PD LVCMOS gpio_127 4 IO N18 mmc1_dat6 0 IO L PD 7 VDDSHV 1.8V/3.3V No 30 PU/ PD LVCMOS gpio_128 4 IO P18 mmc1_dat7 0 IO L PD 7 VDDSHV 1.8V/3.3V No 30 PU/ PD LVCMOS gpio_129 4 IO M21 mmc2_clk 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS mcspi3_clk 1 IO uart4_cts 2 I gpio_130 4 IO M20 mmc2_ cmd 0 IO H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS mcspi3_ 1 IO simo uart4_rts 2 O gpio_131 4 IO K20 mmc2_ dat0 0 IO H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS mcspi3_ 1 IO somi uart4_tx 2 O gpio_132 4 IO L19 mmc2_ dat1 0 IO H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS uart4_rx 2 I gpio_133 4 IO M18 mmc2_ dat2 0 IO H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS mcspi3_cs1 1 O gpio_134 4 IO K21 mmc2_ dat3 0 IO H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS mcspi3_cs0 1 IO gpio_135 4 IO L18 mmc2_ dat4 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS mmc3_dat0 3 IO gpio_136 4 IO L20 mmc2_ dat5 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS mmc3_dat1 3 IO gpio_137 4 IO fsusb3_rxdp 6 IO L21 mmc2_ dat6 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS mmc3_dat2 3 IO gpio_138 4 IO M19 mmc2_ dat7 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS mmc3_dat3 3 IO gpio_139 4 IO fsusb3_rxdm 6 IO C4 mcbsp3_dx 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS uart2_cts 1 I gpio_140 4 IO B4 mcbsp3_dr 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS uart2_rts 1 O gpio_141 4 IO D4 mcbsp3_ clkx0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS uart2_tx 1 O

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PRODUCT□PREVIEW AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Table2-2.BallCharacteristics(ZER Pkg.)(continued) BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13] LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12] [1] STATE [5] STATE [6] gpio_142 4 IO A4 mcbsp3_fsx 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS uart2_rx 1 I gpio_143 4 IO A5 uart2_cts 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpt9_pwm_e 2 IO vt gpio_144 4 IO B5 uart2_rts 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpt10_pwm_ 2 IO evt gpio_145 4 IO D6 uart2_tx 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpt11_pwm 2 IO _evt gpio_146 4 IO C6 uart2_rx 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpt8_pwm_e 2 IO vt gpio_147 4 IO C22 uart1_tx 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_148 4 IO C21 uart1_rts 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_149 4 IO C19 uart1_cts 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_150 4 IO C20 uart1_rx 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS mcbsp1_ clkr2 I gpio_151 4 IO A3 mcbsp4_ clkx0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_152 4 IO fsusb3_txse06 IO B3 mcbsp4_dr 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_153 4 IO fsusb3_rxrcv6 IO A2 mcbsp4_dx 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_154 4 IO fsusb3_txdat6 IO B2 mcbsp4_fsx 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_155 4 IO fsusb3_txen_6 IO n B11 mcbsp1_ clkr0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS mcspi4_clk 1 IO gpio_156 4 IO D11 mcbsp1_fsr 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_157 4 IO C10 mcbsp1_dx 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS mcspi4_ 1 IO simo gpio_158 4 IO C9 mcbsp1_dr 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS mcspi4_ 1 IO somi gpio_159 4 IO E11 mcbsp_clks 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_160 4 IO Copyright© 2009–2010,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 43 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Table2-2.BallCharacteristics(ZER Pkg.)(continued) BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13] LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12] [1] STATE [5] STATE [6] C11 mcbsp1_fsx 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS mcspi4_cs0 1 IO gpio_161 4 IO C8 mcbsp1_ clkx0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_162 4 IO W15 uart3_cts_rct0 IO H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS x gpio_163 4 IO W13 uart3_rts_sd0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_164 4 IO AA13 uart3_rx_irrx0 I H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_165 4 IO Y13 uart3_tx_irtx0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_166 4 IO A6 usb0_dp 0 IO 5.0V Yes PU/ PD LVCMOS B6 usb0_dm 0 IO 5.0V Yes PU/ PD LVCMOS C7 usb0_vbus 0 A VDDA3P3V_ 3.3V Yes PU/ PD LVCMOS USBPHY B7 usb0_id 0 A VDDA3P3V_ 3.3V Yes PU/ PD LVCMOS USBPHY A7 usb0_drvvbu 0 O L PD 7 VDDSHV 1.8V/3.3V 30 s gpio_125 4 IO AB15 hecc1_ txd 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 24 PU/ PD LVCMOS gpio_130 4 IO AB16 hecc1_ rxd 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 24 PU/ PD LVCMOS gpio_131 4 IO AA17 i2c1_scl 0 IOD H PU 0 VDDSHV 1.8V/3.3V Yes 40 PU/ PD Open Drain AB17 i2c1_sda 0 IOD H PU 0 VDDSHV 1.8V/3.3V Yes 40 PU/ PD Open Drain Y17 i2c2_scl 0 IOD H PU 7 VDDSHV 1.8V/3.3V Yes 40 PU/ PD Open Drain gpio_168 4 IO Y16 i2c2_sda 0 IOD H PU 7 VDDSHV 1.8V/3.3V Yes 40 PU/ PD Open Drain gpio_183 4 IO W16 i2c3_scl 0 IOD H PU 7 VDDSHV 1.8V/3.3V Yes 40 PU/ PD Open Drain gpio_184 4 IO W17 i2c3_sda 0 IOD H PU 7 VDDSHV 1.8V/3.3V Yes 40 PU/ PD Open Drain gpio_185 4 IO B9 hdq_sio 0 IO H PU 7 VDDSHV 1.8V/3.3V Yes 40 PU/ PD LVCMOS sys_altclk 1 I i2c2_sccbe 2 O i2c3_sccbe 3 O gpio_170 4 IO K22 mcspi1_clk 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS mmc2_dat4 1 IO gpio_171 4 IO K19 mcspi1_ 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS simo mmc2_dat5 1 IO gpio_172 4 IO J18 mcspi1_ 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS somi mmc2_dat6 1 IO gpio_173 4 IO K18 mcspi1_cs0 0 IO H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS mmc2_dat7 1 IO gpio_174 4 IO J20 mcspi1_cs1 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

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PRODUCT□PREVIEW AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Table2-2.BallCharacteristics(ZER Pkg.)(continued) BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13] LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12] [1] STATE [5] STATE [6] mmc3_cmd 3 IO gpio_175 4 IO J19 mcspi1_cs2 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS mmc3_clk 3 O gpio_176 4 IO J21 mcspi1_cs3 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS hsusb2_ 3 IO data2 gpio_177 4 IO mm_fsusb2_t 5 IO xdat J22 mcspi2_clk 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS hsusb2_ 3 IO data7 gpio_178 4 IO H20 mcspi2_ 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS simo gpt9_pwm_e 1 IO vt hsusb2_ 3 IO data4 gpio_179 4 IO H22 mcspi2_ 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS somi gpt10_pwm_ 1 IO evt hsusb2_ 3 IO data5 gpio_180 4 IO H21 mcspi2_cs0 0 IO H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpt11_pwm_ 1 IO evt hsusb2_ 3 IO data6 gpio_181 4 IO H19 mcspi2_cs1 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpt8_pwm_e 1 IO vt hsusb2_ 3 IO data3 gpio_182 4 IO fsusb2_txen_5 IO n A8 sys_32k 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS A10 sys_xtalin 0 I Z Z 0 VDDSOSC 1.8V NA PU/ PD LVCMOS A9 sys_xtalout 0 O Z Z 0 VDDSOSC 1.8V NA PU/ PD LVCMOS B8 sys_clkreq 0 IO L Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_1 4 IO AB18 sys_nirq 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_0 4 IO AA18 sys_ 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS nrespwron Y18 sys_ 0 IO L PD 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS nreswarm gpio_30 4 IO Open Drain AB19 sys_boot0 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_2 4 IO AB20 sys_boot1 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_3 4 IO W18 sys_boot2 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS Copyright© 2009–2010,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 45 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Table2-2.BallCharacteristics(ZER Pkg.)(continued) BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13] LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12] [1] STATE [5] STATE [6] gpio_4 4 IO AA19 sys_boot3 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_5 4 IO V18 sys_boot4 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_6 4 IO Y19 sys_boot5 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_7 4 IO W19 sys_boot6 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_8 4 IO AA20 sys_boot7 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/PD LVCMOS Y20 sys_boot8 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/PD LVCMOS E9 sys_clkout1 0 O H PD 0/7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS gpio_10 4 IO E10 sys_clkout2 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 10 PU/ PD LVCMOS gpio_186 4 IO D13 jtag_ntrst 0 I L PD 0 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS E14 jtag_tck 0 I L PD 0 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS C12 jtag_rtck 0 O L Z 0 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS A12 jtag_tms_tms0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS c B12 jtag_tdi 0 I H PU 0 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS D12 jtag_tdo 0 O L Z 0 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS E13 jtag_emu0 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS gpio_11 4 IO E12 jtag_emu1 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS gpio_31 4 IO G22 etk_clk 0 O H PU 4 VDDSHV 1.8V/3.3V Yes 9,25 PU/ PD LVCMOS mcbsp5_ clkx1 IO mmc3_clk 2 O hsusb1_stp 3 O gpio_12 4 IO G21 etk_ctl 0 O H PU 4 VDDSHV 1.8V/3.3V Yes 9,25 PU/ PD LVCMOS mmc3_cmd 2 IO hsusb1_clk 3 O gpio_13 4 IO fsusb1_rxdp 5 IO G20 etk_d0 0 O H PU 4 VDDSHV 1.8V/3.3V Yes 9,25 PU/ PD LVCMOS mcspi3_ 1 IO simo mmc3_dat4 2 IO hsusb1_ 3 IO data0 gpio_14 4 IO fsusb1_rxrcv5 IO F22 etk_d1 0 O H PU 4 VDDSHV 1.8V/3.3V Yes 9,25 PU/ PD LVCMOS mcspi3_ 1 IO somi hsusb1_ 3 IO data1 gpio_15 4 IO fsusb1_txse05 IO F20 etk_d2 0 O H PU 4 VDDSHV 1.8V/3.3V Yes 9,25 PU/ PD LVCMOS mcspi3_cs0 1 IO hsusb1_ 3 IO data2 gpio_16 4 IO fsusb1_txdat5 IO

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PRODUCT□PREVIEW AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Table2-2.BallCharacteristics(ZER Pkg.)(continued) BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13] LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12] [1] STATE [5] STATE [6] G19 etk_d3 0 O L PU 4 VDDSHV 1.8V/3.3V Yes 9,25 PU/ PD LVCMOS mcspi3_clk 1 IO mmc3_dat3 2 IO hsusb1_ 3 IO data7 gpio_17 4 IO E19 etk_d4 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9,25 PU/ PD LVCMOS mcbsp5_dr 1 I mmc3_dat0 2 IO hsusb1_ 3 IO data4 gpio_18 4 IO F21 etk_d5 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9,25 PU/ PD LVCMOS mcbsp5_fsx 1 IO mmc3_dat1 2 IO hsusb1_ 3 IO data5 gpio_19 4 IO F19 etk_d6 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9,25 PU/ PD LVCMOS mcbsp5_dx 1 IO mmc3_dat2 2 IO hsusb1_ 3 IO data6 gpio_20 4 IO E21 etk_d7 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9,25 PU/ PD LVCMOS mcspi3_cs1 1 O mmc3_dat7 2 IO hsusb1_ 3 IO data3 gpio_21 4 IO fsusb1_txen_5 IO n D22 etk_d8 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9,25 PU/ PD LVCMOS mmc3_dat6 2 IO hsusb1_dir 3 I gpio_22 4 IO D21 etk_d9 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9,25 PU/ PD LVCMOS mmc3_dat5 2 IO hsusb1_nxt 3 I gpio_23 4 IO fsusb1_rxdm 5 IO E22 etk_d10 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9,25 PU/ PD LVCMOS uart1_rx 2 I hsusb2_clk 3 O gpio_24 4 IO E20 etk_d11 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9,25 PU/ PD LVCMOS mcspi3_clk 1 IO hsusb2_stp 3 O gpio_25 4 IO fsusb2_rxdp 5 IO E18 etk_d12 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9,25 PU/ PD LVCMOS hsusb2_dir 3 I gpio_26 4 IO D20 etk_d13 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9,25 PU/ PD LVCMOS hsusb2_nxt 3 I gpio_27 4 IO fsusb2_rxdm 5 IO Copyright© 2009–2010,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 47 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Table2-2.BallCharacteristics(ZER Pkg.)(continued) BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13] LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12] [1] STATE [5] STATE [6] D19 etk_d14 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9,25 PU/ PD LVCMOS hsusb2_ 3 IO data0 gpio_28 4 IO fsusb2_rxrcv5 IO D18 etk_d15 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9,25 PU/ PD LVCMOS hsusb2_ 3 IO data1 gpio_29 4 IO fsusb2_txse05 IO M2 ddr_padref 0 A VDDS 1.8V J8,J10, VDD_CORE 0 PWR 1.2V J12,J14, J16,K9, K11,K13, K15,L8, L10,L12, L14,M7, M9, M11, M13, M15, N8, N10, N12, N14, P7,P9, P11,P13, P15,R8, R10, R12, R14 L17 VDDS_SRA 0 PWR 1.8V M_MPU J6 VDDS_SRA 0 PWR 1.8V M_CORE_B G M17 CAP_VDD_S 0 PWR 1.2V RAM_MPU K6 CAP_VDD_S 0 PWR 1.2V RAM_CORE K17 VDDS_DPLL 0 PWR 1.8V _MPU_USBH OST F11 VDDS_DPLL 0 PWR 1.8V _PER_CORE F7 VDDA3P3V_ 0 PWR 3.3V USBPHY D7 VDDA1P8V_ 0 PWR 1.8V USBPHY E7 CAP_VDDA1 0 PWR 1.2V P2LDO_USB PHY A21,B1, VDDSHV 0 PWR 1.8V/3.3V E15,E17, F12,F14, F18,G10, G12, G13, G8, G17, H18, J17, L22,N16, P17,R16, R18, T9, T11,T13, T17,U8, U10, U12, U14, U16, U18, V7, V8,V17, AA22, AB11 F5,F16, VDDS 0 PWR 1.8V G15, H5, K7,L6, L16,N1, N5, N6, P5, R6, T5,T7, T15,U6, AA1

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PRODUCT□PREVIEW AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Table2-2.BallCharacteristics(ZER Pkg.)(continued) BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13] LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12] [1] STATE [5] STATE [6] L5 VREFSSTL 0 I G9 VDDSOSC O PWR 1.8V A1,A11, VSS 0 GND A22,E6, E16,F6, F13,F15, F17,G5, G7, G11, G14, G16, G18, H6, H7, H8, H9, H10, H11, H12, H13, H14, H15, H16, H17, J9,J11, J13,J15, K8,K10, K12,K14, K16,L7, L9,L11, L13,L15, M1, M6, M8, M10, M12, M14, M16, M22, N7, N9, N11, N13, N15, N17, P6,P8, P10,P12, P14,P16, R5, R7, R9, R11, R13, R15, R17, T6,T8, T10,T12, T14,T16, T18,U5, U7, U9, U11, U13, U15, U17, V6,AB1, AB12, AB22 B10 VSSOSC 0 GND D8, D9, NC (1) D10, E8, F8,F9, F10,J7,G6 V15 Reserved(2) V16 Reserved(2) (1) "NC "indicates"No Connect".Forproperdeviceoperation,thesepinsmust be leftunconnected. (2) Forproperdeviceoperation,thispinmust be pulledup viaa 10k-Ω resistor. Copyright© 2009–2010,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 49 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com

2.3 MultiplexingCharacteristics

Table2-3providesdescriptionsoftheAM3517/05 pinmultiplexingon theZCN and ZER packages. Table2-3.MultiplexingCharacteristics ZER ZCN MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MODE 6 MODE 7 BALL NO BALL NO E3 B21 sdrc_d0 D3 A21 sdrc_d1 C3 D20 sdrc_d2 C2 C20 sdrc_d3 F3 E19 sdrc_d4 D2 D19 sdrc_d5 C1 C19 sdrc_d6 D1 B19 sdrc_d7 G2 B18 sdrc_d8 G3 D17 sdrc_d9 H3 C17 sdrc_d10 G4 D16 sdrc_d11 H4 C16 sdrc_d12 G1 B16 sdrc_d13 J3 A16 sdrc_d14 J1 A15 sdrc_d15 T3 A7 sdrc_d16 U3 B7 sdrc_d17 U4 D7 sdrc_d18 V4 E7 sdrc_d19 V1 C6 sdrc_d20 V2 D6 sdrc_d21 V5 B5 sdrc_d22 V3 C5 sdrc_d23 W3 B4 sdrc_d24 W4 A3 sdrc_d25 Y3 B3 sdrc_d26 Y4 C3 sdrc_d27 AA2 C2 sdrc_d28 AA3 D2 sdrc_d29 AA4 B1 sdrc_d30 AB2 C1 sdrc_d31 L4 A12 sdrc_ba0 K5 C13 sdrc_ba1 J5 D13 sdrc_ba2 M3 A11 sdrc_a0 M4 B11 sdrc_a1 M5 C11 sdrc_a2 N3 D11 sdrc_a3 N2 E11 sdrc_a4 N4 A10 sdrc_a5 P3 B10 sdrc_a6 P2 C10 sdrc_a7 P1 D10 sdrc_a8 P4 E10 sdrc_a9 R1 A9 sdrc_a10 R2 B9 sdrc_a11 R3 A8 sdrc_a12 R4 B8 sdrc_a13 T2 D8 sdrc_a14

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PRODUCT□PREVIEW AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Table2-3.MultiplexingCharacteristics(continued) ZER ZCN MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MODE 6 MODE 7 J4 E13 sdrc_ncs0 K4 A14 sdrc_ncs1 L1 A13 sdrc_clk L2 B13 sdrc_nclk K3 D14 sdrc_cke0 sdrc_cke0_safe K1 C14 sdrc_nras L3 E14 sdrc_ncas K2 B14 sdrc_nwe F4 C21 sdrc_dm0 J2 B15 sdrc_dm1 T4 E8 sdrc_dm2 AB3 D1 sdrc_dm3 E2 B20 sdrc_dqs0p H2 B17 sdrc_dqs1p U1 A6 sdrc_dqs2p Y1 A2 sdrc_dqs3p E1 A20 sdrc_dqs0n H1 A17 sdrc_dqs1n U2 B6 sdrc_dqs2n Y2 B2 sdrc_dqs3n T1 C8 sdrc_odt F2 A19 sdrc_strben0 F1 A18 sdrc_strben_dly0 W1 A5 sdrc_strben1 W2 A4 sdrc_strben_dly1 W5 E3 gpmc_a1 gpio_34 safe_mode Y5 E2 gpmc_a2 gpio_35 safe_mode AB4 E1 gpmc_a3 gpio_36 safe_mode AA5 F7 gpmc_a4 gpio_37 safe_mode AB5 F6 gpmc_a5 gpio_38 safe_mode AB6 F4 gpmc_a6 gpio_39 safe_mode AA6 F3 gpmc_a7 gpio_40 safe_mode W6 F2 gpmc_a8 gpio_41 safe_mode AB7 F1 gpmc_a9 sys_ndmareq2 gpio_42 safe_mode Y6 G6 gpmc_a10 sys_ndmareq3 gpio_43 safe_mode AA7 G5 gpmc_d0 Y7 G4 gpmc_d1 W7 G3 gpmc_d2 AA9 G2 gpmc_d3 Y8 G1 gpmc_d4 AA8 H2 gpmc_d5 AB8 H1 gpmc_d6 W8 J5 gpmc_d7 W10 J4 gpmc_d8 gpio_44 AB9 J3 gpmc_d9 gpio_45 AB10 J2 gpmc_d10 gpio_46 W9 J1 gpmc_d11 gpio_47 AA10 K4 gpmc_d12 gpio_48 Y9 K3 gpmc_d13 gpio_49 V10 K2 gpmc_d14 gpio_50 V9 K1 gpmc_d15 gpio_51 Y10 L2 gpmc_ncs0 Y11 L1 gpmc_ncs1 gpio_52 Y12 M4 gpmc_ncs2 gpt9_pwm_evt gpio_53 safe_mode V12 M3 gpmc_ncs3 sys_ndmareq0 gpt10_pwm_evt gpio_54 safe_mode AA11 M2 gpmc_ncs4 sys_ndmareq1 gpt9_pwm_evt gpio_55 safe_mode Copyright© 2009–2010,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 51 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Table2-3.MultiplexingCharacteristics(continued) ZER ZCN MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MODE 6 MODE 7 W12 M1 gpmc_ncs5 sys_ndmareq2 gpt10_pwm_evt gpio_56 safe_mode AA12 N5 gpmc_ncs6 sys_ndmareq3 gpt11_pwm_evt gpio_57 safe_mode V11 N4 gpmc_ncs7 gpmc_io_dir gpt8_pwm_evt gpio_58 safe_mode AB13 N1 gpmc_clk gpio_59 AA14 R1 gpmc_nadv_ale AB14 R2 gpmc_noe AA15 R3 gpmc_nwe W11 R4 gpmc_nbe0_cle gpio_60 Y15 T1 gpmc_nbe1 gpio_61 safe_mode W14 T2 gpmc_nwp gpio_62 V13 T3 gpmc_wait0 AA16 T4 gpmc_wait1 uart4_tx gpio_63 safe_mode Y14 T5 gpmc_wait2 uart4_rx gpio_64 safe_mode V14 U1 gpmc_wait3 sys_ndmareq1 uart3_cts_rctx gpio_65 safe_mode B22 AE23 dss_pclk gpio_66 hw_dbg12 safe_mode B21 AD22 dss_hsync gpio_67 hw_dbg13 safe_mode B20 AD23 dss_vsync gpio_68 safe_mode B19 AE24 dss_acbias gpio_69 safe_mode A20 AD24 dss_data0 uart1_cts gpio_70 safe_mode A19 AD25 dss_data1 uart1_rts gpio_71 safe_mode A18 AC23 dss_data2 gpio_72 safe_mode B18 AC24 dss_data3 gpio_73 safe_mode A17 AC25 dss_data4 uart3_rx_irrx gpio_74 safe_mode C18 AB24 dss_data5 uart3_tx_irtx gpio_75 safe_mode D17 AB25 dss_data6 uart1_tx gpio_76 hw_dbg14 safe_mode B16 AA23 dss_data7 uart1_rx gpio_77 hw_dbg15 safe_mode B17 AA24 dss_data8 gpio_78 hw_dbg16 safe_mode C17 AA25 dss_data9 gpio_79 hw_dbg17 safe_mode C16 Y22 dss_data10 gpio_80 safe_mode D16 Y23 dss_data11 gpio_81 safe_mode D14 Y24 dss_data12 gpio_82 safe_mode A16 Y25 dss_data13 gpio_83 safe_mode D15 W21 dss_data14 gpio_84 safe_mode B15 W22 dss_data15 gpio_85 safe_mode A15 W23 dss_data16 gpio_86 safe_mode A14 W24 dss_data17 gpio_87 safe_mode C13 W25 dss_data18 mcspi3_clk dss_data4 gpio_88 safe_mode C15 V24 dss_data19 mcspi3_simo dss_data3 gpio_89 safe_mode A13 V25 dss_data20 mcspi3_somi dss_data2 gpio_90 safe_mode B13 U21 dss_data21 mcspi3_cs0 dss_data1 gpio_91 safe_mode C14 U22 dss_data22 mcspi3_cs1 dss_data0 gpio_92 safe_mode B14 U23 dss_data23 dss_data5 gpio_93 safe_mode NA K20 tv_vfb1 NA K21 tv_out1 NA H23 tv_vfb2 NA H24 tv_out2 NA H20 tv_vref AB21 AD2 ccdc_pclk gpio_94 hw_dbg0 safe_mode AA21 AD1 ccdc_field ccdc_data8 uart4_tx i2c3_scl gpio_95 hw_dbg1 safe_mode Y21 AE2 ccdc_hd uart4_rts gpio_96 safe_mode Y22 AD3 ccdc_vd uart4_cts gpio_97 hw_dbg2 safe_mode W21 AE3 ccdc_wen ccdc_data9 uart4_rx gpio_98 hw_dbg3 safe_mode W22 AD4 ccdc_data0 i2c3_sda gpio_99 safe_mode W20 AE4 ccdc_data1 gpio_100 safe_mode V21 AC5 ccdc_data2 gpio_101 hw_dbg4 safe_mode V19 AD5 ccdc_data3 gpio_102 hw_dbg5 safe_mode

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PRODUCT□PREVIEW AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Table2-3.MultiplexingCharacteristics(continued) ZER ZCN MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MODE 6 MODE 7 V22 AE5 ccdc_data4 gpio_103 hw_dbg6 safe_mode U20 Y6 ccdc_data5 gpio_104 hw_dbg7 safe_mode V20 AB6 ccdc_data6 gpio_105 safe_mode U19 AC6 ccdc_data7 gpio_106 safe_mode U21 AE6 rmii_mdio_data ccdc_data8 gpio_107 safe_mode U22 AD6 rmii_mdio_clk ccdc_data9 gpio_108 safe_mode T19 Y7 rmii_rxd0 ccdc_data10 gpio_109 hw_dbg8 safe_mode T20 AA7 rmii_rxd1 ccdc_data11 gpio_110 hw_dbg9 safe_mode T21 AB7 rmii_crs_dv ccdc_data12 gpio_111 safe_mode R22 AC7 rmii_rxer ccdc_data13 gpio_167 hw_dbg10 safe_mode T22 AD7 rmii_txd0 ccdc_data14 gpio_126 hw_dbg11 safe_mode R20 AE7 rmii_txd1 ccdc_data15 gpio_112 safe_mode R19 AD8 rmii_txen gpio_113 safe_mode R21 AE8 rmii_50mhz_clk gpio_114 safe_mode E5 D25 mcbsp2_fsx gpio_116 safe_mode D5 C25 mcbsp2_clkx gpio_117 safe_mode C5 B25 mcbsp2_dr gpio_118 safe_mode E4 D24 mcbsp2_dx gpio_119 safe_mode P22 AA9 mmc1_clk gpio_120 safe_mode N21 AB9 mmc1_cmd gpio_121 safe_mode P21 AC9 mmc1_dat0 mcspi2_clk gpio_122 safe_mode N20 AD9 mmc1_dat1 mcspi2_simo gpio_123 safe_mode P19 AE9 mmc1_dat2 mcspi2_somi gpio_124 safe_mode P20 AA10 mmc1_dat3 mcspi2_cs0 gpio_125 safe_mode N22 AB10 mmc1_dat4 gpio_126 safe_mode N19 AC10 mmc1_dat5 gpio_127 safe_mode N18 AD10 mmc1_dat6 gpio_128 safe_mode P18 AE10 mmc1_dat7 gpio_129 safe_mode M21 AD11 mmc2_clk mcspi3_clk uart4_cts gpio_130 safe_mode M20 AE11 mmc2_cmd mcspi3_simo uart4_rts gpio_131 safe_mode K20 AB12 mmc2_dat0 mcspi3_somi uart4_tx gpio_132 safe_mode L19 AC12 mmc2_dat1 uart4_rx gpio_133 safe_mode M18 AD12 mmc2_dat2 mcspi3_cs1 gpio_134 safe_mode K21 AE12 mmc2_dat3 mcspi3_cs0 gpio_135 safe_mode L18 AB13 mmc2_dat4 mmc2_dir_dat0 mmc3_dat0 gpio_136 safe_mode L20 AC13 mmc2_dat5 mmc2_dir_dat1 mmc3_dat1 gpio_137 mm_fsusb3_rxdp safe_mode L21 AD13 mmc2_dat6 mmc2_dir_cmd mmc3_dat2 gpio_138 safe_mode M19 AE13 mmc2_dat7 mmc2_clkin mmc3_dat3 gpio_139 mm_fsusb3_rxdm safe_mode C4 B24 mcbsp3_dx uart2_cts gpio_140 safe_mode B4 C24 mcbsp3_dr uart2_rts gpio_141 safe_mode D4 A24 mcbsp3_clkx uart2_tx gpio_142 safe_mode A4 C23 mcbsp3_fsx uart2_rx gpio_143 safe_mode A5 F20 uart2_cts mcbsp3_dx gpt9_pwm_evt gpio_144 safe_mode B5 F19 uart2_rts mcbsp3_dr gpt10_pwm_evt gpio_145 safe_mode D6 E24 uart2_tx mcbsp3_clkx gpt11_pwm_evt gpio_146 safe_mode C6 E23 uart2_rx mcbsp3_fsx gpt8_pwm_evt gpio_147 safe_mode C22 AA19 uart1_tx gpio_148 safe_mode C21 Y19 uart1_rts gpio_149 safe_mode C19 Y20 uart1_cts gpio_150 safe_mode C20 W20 uart1_rx mcbsp1_clkr mcspi4_clk gpio_151 safe_mode A3 B23 mcbsp4_clkx gpio_152 mm_fsusb3_txse safe_mode B3 A23 mcbsp4_dr gpio_153 mm_fsusb3_rxrcvsafe_mode A2 B22 mcbsp4_dx gpio_154 mm_fsusb3_txdatsafe_mode B2 A22 mcbsp4_fsx gpio_155 mm_fsusb3_txen safe_mode Copyright© 2009–2010,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 53 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Table2-3.MultiplexingCharacteristics(continued) ZER ZCN MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MODE 6 MODE 7 B11 R25 mcbsp1_clkr mcspi4_clk gpio_156 safe_mode D11 P21 mcbsp1_fsr gpio_157 safe_mode C10 P22 mcbsp1_dx mcspi4_simo mcbsp3_dx gpio_158 safe_mode C9 P23 mcbsp1_dr mcspi4_somi mcbsp3_dr gpio_159 safe_mode E11 P25 mcbsp_clks gpio_160 uart1_cts safe_mode C11 P24 mcbsp1_fsx mcspi4_cs0 mcbsp3_fsx gpio_161 safe_mode C8 N24 mcbsp1_clkx mcbsp3_clkx gpio_162 safe_mode W15 N2 uart3_cts_crtx gpio_163 safe_mode W13 N3 uart3_rts_sd gpio_164 safe_mode AA13 P1 uart3_rx_irrx gpio_165 safe_mode Y13 P2 uart3_tx_irtx gpio_166 A6 F25 usb0_dp uart3_rx_irrx B6 F24 usb0_dm uart3_tx_irtx C7 G24 usb0_vbus B7 G25 usb0_id A7 E25 usb0_drvvbus uart3_tx_irtx gpio_125 safe_mode AB15 V2 hecc1_txd uart3_rx_irrx gpio_130 safe_mode AB16 V3 hecc1_rxd uart3_rts_sd gpio_131 safe_mode AA17 V4 i2c1_scl AB17 V5 i2c1_sda Y17 W1 i2c2_scl gpio_168 safe_mode Y16 W2 i2c2_sda gpio_183 safe_mode W16 W4 i2c3_scl gpio_184 safe_mode W17 W5 i2c3_sda gpio_185 safe_mode B9 L25 hdq_sio sys_altclk i2c2_sccbe i2c3_sccbe gpio_170 safe_mode K22 AE14 mcspi1_clk mmc2_dat4 gpio_171 safe_mode K19 AD15 mcspi1_simo mmc2_dat5 gpio_172 safe_mode J18 AC15 mcspi1_somi mmc2_dat6 gpio_173 safe_mode K18 AB15 mcspi1_cs0 mmc2_dat7 gpio_174 safe_mode J20 AD14 mcspi1_cs1 mmc3_cmd gpio_175 safe_mode J19 AE15 mcspi1_cs2 mmc3_clk gpio_176 safe_mode J21 AE16 mcspi1_cs3 hsusb2_data2 gpio_177 mm_fsusb2_txdat safe_mode J22 AD16 mcspi2_clk hsusb2_data7 gpio_178 safe_mode H20 AC16 mcspi2_simo gpt9_pwm_evt hsusb2_data4 gpio_179 safe_mode H22 AB16 mcspi2_somi gpt10_pwm_evt hsusb2_data5 gpio_180 safe_mode H21 AA16 mcspi2_cs0 gpt11_pwm_evt hsusb2_data6 gpio_181 safe_mode H19 AE17 mcspi2_cs1 gpt8_pwm_evt hsusb2_data3 gpio_182 mm_fsusb2_txen safe_mode AB18 Y1 sys_nirq gpio_0 safe_mode E10 M25 sys_clkout2 gpio_186 safe_mode G22 AD17 etk_clk mcbsp5_clkx mmc3_clk hsusb1_stp gpio_12 hw_dbg0 G21 AE18 etk_ctl mmc3_cmd hsusb1_clk gpio_13 mm_fsusb1_rxdp hw_dbg1 G20 AD18 etk_d0 mcspi3_simo mmc3_dat4 hsusb1_data0 gpio_14 mm_fsusb1_rxrcv hw_dbg2 F22 AC18 etk_d1 mcspi3_somi hsusb1_data1 gpio_15 mm_fsusb1_txse hw_dbg3 F20 AB18 etk_d2 mcspi3_cs0 hsusb1_data2 gpio_16 mm_fsusb1_txdat hw_dbg4 G19 AA18 etk_d3 mcspi3_clk mmc3_dat3 hsusb1_data7 gpio_17 hw_dbg5 E19 Y18 etk_d4 mcbsp5_dr mmc3_dat0 hsusb1_data4 gpio_18 hw_dbg6 F21 AE19 etk_d5 mcbsp5_fsx mmc3_dat1 hsusb1_data5 gpio_19 hw_dbg7 F19 AD19 etk_d6 mcbsp5_dx mmc3_dat2 hsusb1_data6 gpio_20 hw_dbg8 E21 AB19 etk_d7 mcspi3_cs1 mmc3_dat7 hsusb1_data3 gpio_21 mm_fsusb1_txen hw_dbg9 D22 AE20 etk_d8 mmc3_dat6 hsusb1_dir gpio_22 hw_dbg10 D21 AD20 etk_d9 mmc3_dat5 hsusb1_nxt gpio_23 mm_fsusb1_rxdm hw_dbg11 E22 AC20 etk_d10 uart1_rx hsusb2_clk gpio_24 hw_dbg12 E20 AB20 etk_d11 mcspi3_clk hsusb2_stp gpio_25 mm_fsusb2_rxdp hw_dbg13 E18 AE21 etk_d12 hsusb2_dir gpio_26 hw_dbg14

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PRODUCT□PREVIEW AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Table2-3.MultiplexingCharacteristics(continued) ZER ZCN MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MODE 6 MODE 7 D20 AD21 etk_d13 hsusb2_nxt gpio_27 mm_fsusb2_rxdm hw_dbg15 D19 AC21 etk_d14 hsusb2_data0 gpio_28 mm_fsusb2_rxrcv hw_dbg16 D18 AE22 etk_d15 hsusb2_data1 gpio_29 mm_fsusb2_txse hw_dbg17 A8 K24 sys_32k A10 K25 sys_xtalin A9 H25 sys_xtalout B8 M24 sys_clkreq gpio_1 AA18 Y2 sys_nrespwron Y18 Y3 sys_nreswarm gpio_30 AB19 Y4 sys_boot0 gpio_2 AB20 AA1 sys_boot1 gpio_3 W18 AA2 sys_boot2 gpio_4 AA19 AA3 sys_boot3 gpio_5 V18 AB1 sys_boot4 mmc2_dir_dat2 gpio_6 Y19 AB2 sys_boot5 mmc2_dir_dat3 gpio_7 W19 AC1 sys_boot6 gpio_8 AA20 AC2 sys_boot7 Y20 AC3 sys_boot8 E9 N25 sys_clkout1 gpio_10 safe_mode D13 U24 jtag_ntrst E14 U25 jtag_tck C12 T21 jtag_rtck A12 T22 jtag_tms_tmsc B12 T23 jtag_tdi D12 T24 jtag_tdo E13 T25 jtag_emu0 gpio_11 E12 R24 jtag_emu1 gpio_31 M2 B12 ddr_padref Copyright© 2009–2010,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 55 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

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2.4 SignalDescription

Many signalsareavailableon multiplepinsaccordingtothesoftwareconfigurationofthepinmultiplexing options. 1. SIGNAL NAME: The signalname 2. DESCRIPTION: Descriptionofthesignal 3. TYPE: Type = Balltypeforthisspecificfunction: – I= Input – O = Output – Z = High-impedance – D = Open Drain – DS = Differential – A = Analog 4. BALL: Associatedballlocation 5. SUBSYSTEM PIN MULTIPLEXING: Containsa listofthepinmultiplexingoptionsatthe module/subsystemlevel.The pinfunctionisselectedatthemodule/systemlevel. Note:The Subsystem MultiplexingSignalsarenotdescribedinTable2-1throughTable2-2.

2.4.1 ExternalMemory Interfaces

Table2-4.ExternalMemory Interfaces-GPMC SignalsDescription SIGNAL NAME DESCRIPTION TYPE ZCN BALL ZER BALL SUBSYSTEM PIN MULTIPLEXING gpmc_a1 GPMC Addressbit1 O E3/G5 W5/AA7 gpmc_a17 gpmc_a2 GPMC Addressbit2 O E2/G4 Y5/Y7 gpmc_a18 gpmc_a3 GPMC Addressbit3 O E1/G3 AB4/W7 gpmc_a19 gpmc_a4 GPMC Addressbit4 O F7/G2 AA5/AA9 gpmc_a20 gpmc_a5 GPMC Addressbit5 O F6/G1 AB5/Y8 gpmc_a21 gpmc_a6 GPMC Addressbit6 O F4/H2 AB6/AA8 gpmc_a22 gpmc_a7 GPMC Addressbit7 O F3/H1 AA6/AB8 gpmc_a23 gpmc_a8 GPMC Addressbit8 O F2/J5 W6/W8 gpmc_a24 gpmc_a9 GPMC Addressbit9 O F1/J4 AB7/W10 gpmc_a25 gpmc_a10 GPMC Addressbit10 O G6/J3 Y6/AB9 gpmc_a26 gpmc_a11 GPMC Addressbit11 O J2 AB10 multiplexedon gpmc_d10 gpmc_a12 GPMC Addressbit12 O J1 W9 multiplexedon gpmc_d11 gpmc_a13 GPMC Addressbit13 O K4 AA10 multiplexedon gpmc_d12 gpmc_a14 GPMC Addressbit O K3 Y9 14multiplexedon gpmc_d13 gpmc_a15 GPMC Addressbit15 O K2 V10 multiplexedon gpmc_d14 gpmc_a16 GPMC Addressbit16 O K1 V9 multiplexedon gpmc_d15 gpmc_a17 GPMC Addressbit17 O E3 W5 multiplexedon gpmc_a1

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PRODUCT□PREVIEW AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Table2-4.ExternalMemory Interfaces-GPMC SignalsDescription(continued) SIGNAL NAME DESCRIPTION TYPE ZCN BALL ZER BALL SUBSYSTEM PIN MULTIPLEXING gpmc_a18 GPMC Addressbit18 O E2 Y5 multiplexedon gpmc_a2 gpmc_a19 GPMC Addressbit19 O E1 AB4 multiplexedon gpmc_a3 gpmc_a20 GPMC Addressbit20 O F7 AA5 multiplexedon gpmc_a4 gpmc_a21 GPMC Addressbit21 O F6 AB5 multiplexedon gpmc_a5 gpmc_a22 GPMC Addressbit22 O F4 AB6 multiplexedon gpmc_a6 gpmc_a23 GPMC Addressbit23 O F3 AA6 multiplexedon gpmc_a7 gpmc_a24 GPMC Addressbit24 O F2 W6 multiplexedon gpmc_a8 gpmc_a25 GPMC Addressbit25 O F1 AB7 multiplexedon gpmc_a9 gpmc_a26 GPMC Addressbit26 O G6 Y6 multiplexedon gpmc_a10 gpmc_d0 GPMC Data bit0 IO G5 AA7 gpmc_a1/gpmc_d0 gpmc_d1 GPMC Data bit1 IO G4 Y7 gpmc_a2/gpmc_d1 gpmc_d2 GPMC Data bit2 IO G3 W7 gpmc_a3/gpmc_d2 gpmc_d3 GPMC Data bit3 IO G2 AA9 gpmc_a4/gpmc_d3 gpmc_d4 GPMC Data bit4 IO G1 Y8 gpmc_a5/gpmc_d4 gpmc_d5 GPMC Data bit5 IO H2 AA8 gpmc_a6/gpmc_d5 gpmc_d6 GPMC Data bit6 IO H1 AB8 gpmc_a7/gpmc_d6 gpmc_d7 GPMC Data bit7 IO J5 W8 gpmc_a8/gpmc_d7 gpmc_d8 GPMC Data bit8 IO J4 W10 gpmc_a9/gpmc_d8 gpmc_d9 GPMC Data bit9 IO J3 AB9 gpmc_a10/gpmc_d9 gpmc_d10 GPMC Data bit10 IO J2 AB10 gpmc_a11/gpmc_d10 gpmc_d11 GPMC Data bit11 IO J1 W9 gpmc_a12/gpmc_d11 gpmc_d12 GPMC Data bit12 IO K4 AA10 gpmc_a13/gpmc_d12 gpmc_d13 GPMC Data bit13 IO K3 Y9 gpmc_a14/gpmc_d13 gpmc_d14 GPMC Data bit14 IO K2 V10 gpmc_a15/gpmc_d14 gpmc_d15 GPMC Data bit15 IO K1 V9 gpmc_a16/gpmc_d15 gpmc_ncs0 GPMC ChipSelect0 O L2 Y10 gpmc_ncs1 GPMC ChipSelect1 O L1 Y11 gpmc_ncs2 GPMC ChipSelect2 O M4 Y12 gpmc_ncs3 GPMC ChipSelect3 O M3 V12 gpmc_ncs4 GPMC ChipSelect4 O M2 AA11 gpmc_ncs5 GPMC ChipSelect5 O M1 W12 gpmc_ncs6 GPMC ChipSelect6 O N5 AA12 gpmc_ncs7 GPMC ChipSelect7 O N4 V11 gpmc_clk GPMC clock O N1 AB13 Copyright© 2009–2010,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 57 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Table2-4.ExternalMemory Interfaces-GPMC SignalsDescription(continued) SIGNAL NAME DESCRIPTION TYPE ZCN BALL ZER BALL SUBSYSTEM PIN MULTIPLEXING gpmc_nadv_ale AddressValidor O R1 AA14 AddressLatch Enable gpmc_noe OutputEnable O R2 AB14 gpmc_nwe WriteEnable O R3 AA15 gpmc_nbe0_cle Lower ByteEnable. O R4 W11 Alsoused for Command Latch Enable gpmc_nbe1 Upper ByteEnable O T1 Y15 gpmc_nwp FlashWriteProtect O T2 W14 gpmc_wait0 Externalindicationof I T3 V13 wait gpmc_wait1 Externalindicationof I T4 AA16 wait gpmc_wait2 Externalindicationof I T5 Y14 wait gpmc_wait3 Externalindicationof I U1 V14 wait Table2-5.EXTERNAL MEMORY INTERFACES -SDRC SIGNALS DESCRIPTION SIGNAL NAME DESCRIPTION TYPE ZCN BALL ZER BALL sdrc_d0 SDRAM databit0 IO B21 E3 sdrc_d1 SDRAM databit1 IO A21 D3 sdrc_d2 SDRAM databit2 IO D20 C3 sdrc_d3 SDRAM databit3 IO C20 C2 sdrc_d4 SDRAM databit4 IO E19 F3 sdrc_d5 SDRAM databit5 IO D19 D2 sdrc_d6 SDRAM databit6 IO C19 C1 sdrc_d7 SDRAM databit7 IO B19 D1 sdrc_d8 SDRAM databit8 IO B18 G2 sdrc_d9 SDRAM databit9 IO D17 G3 sdrc_d10 SDRAM databit10 IO C17 H3 sdrc_d11 SDRAM databit11 IO D16 G4 sdrc_d12 SDRAM databit12 IO C16 H4 sdrc_d13 SDRAM databit13 IO B16 G1 sdrc_d14 SDRAM databit14 IO A16 J3 sdrc_d15 SDRAM databit15 IO A15 J1 sdrc_d16 SDRAM databit16 IO A7 T3 sdrc_d17 SDRAM databit17 IO B7 U3 sdrc_d18 SDRAM databit18 IO D7 U4 sdrc_d19 SDRAM databit19 IO E7 V4 sdrc_d20 SDRAM databit20 IO C6 V1 sdrc_d21 SDRAM databit21 IO D6 V2 sdrc_d22 SDRAM databit22 IO B5 V5 sdrc_d23 SDRAM databit23 IO C5 V3 sdrc_d24 SDRAM databit24 IO B4 W3 sdrc_d25 SDRAM databit25 IO A3 W4 sdrc_d26 SDRAM databit26 IO B3 Y3

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PRODUCT□PREVIEW AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Table2-5.EXTERNAL MEMORY INTERFACES -SDRC SIGNALS DESCRIPTION (continued) SIGNAL NAME DESCRIPTION TYPE ZCN BALL ZER BALL sdrc_d27 SDRAM databit27 IO C3 Y4 sdrc_d28 SDRAM databit28 IO C2 AA2 sdrc_d29 SDRAM databit29 IO D2 AA3 sdrc_d30 SDRAM databit30 IO B1 AA4 sdrc_d31 SDRAM databit31 IO C1 AB2 sdrc_ba0 SDRAM bank select0 O A12 L4 sdrc_ba1 SDRAM bank select1 O C13 K5 sdrc_ba2 SDRAM bank select2 O D13 J5 sdrc_a0 SDRAM addressbit0 O A11 M3 sdrc_a1 SDRAM addressbit1 O B11 M4 sdrc_a2 SDRAM addressbit2 O C11 M5 sdrc_a3 SDRAM addressbit3 O D11 N3 sdrc_a4 SDRAM addressbit4 O E11 N2 sdrc_a5 SDRAM addressbit5 O A10 N4 sdrc_a6 SDRAM addressbit6 O B10 P3 sdrc_a7 SDRAM addressbit7 O C10 P2 sdrc_a8 SDRAM addressbit8 O D10 P1 sdrc_a9 SDRAM addressbit9 O E10 P4 sdrc_a10 SDRAM addressbit10 O A9 R1 sdrc_a11 SDRAM addressbit11 O B9 R2 sdrc_a12 SDRAM addressbit12 O A8 R3 sdrc_a13 SDRAM addressbit13 O B8 R4 sdrc_a14 SDRAM addressbit14 O D8 T2 sdrc_ncs0 Chipselect0 O E13 J4 sdrc_ncs1 Chipselect1 O A14 K4 sdrc_clk Clock O A13 L1 sdrc_nclk ClockInvert O B13 L2 sdrc_cke0 ClockEnable0 O D14 K3 sdrc_nras SDRAM Row Access O C14 K1 sdrc_ncas SDRAM column address O E14 L3 strobe sdrc_nwe SDRAM writeenable O B14 K2 sdrc_dm0 Data Mask 0 O C21 F4 sdrc_dm1 Data Mask 1 O B15 J2 sdrc_dm2 Data Mask 2 O E8 T4 sdrc_dm3 Data Mask 3 O D1 AB3 sdrc_strben0 PCB layouttraceloop0 A A19 F2 pin0 sdrc_strben_dly0 PCB layouttraceloop0 A A18 F1 pin1 sdrc_strben1 PCB layouttraceloop1 A A5 W1 pin0 sdrc_strben_dly1 PCB layouttraceloop1 A A4 W2 pin1 sdrc_odt On-dieterminationoutput O C8 T1 forsdrc_ncs0only sdrc_dqs0p Data Strobe0 IO B20 E2 sdrc_dqs0n Data Strobe0 IO A20 E1 sdrc_dqs1p Data Strobe1 IO B17 H2 Copyright© 2009–2010,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 59 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Table2-5.EXTERNAL MEMORY INTERFACES -SDRC SIGNALS DESCRIPTION (continued) SIGNAL NAME DESCRIPTION TYPE ZCN BALL ZER BALL sdrc_dqs1n Data Strobe1 IO A17 H1 sdrc_dqs2p Data Strobe2 IO A6 U1 sdrc_dqs2n Data Strobe2 IO B6 U2 sdrc_dqs3p Data Strobe3 IO A2 Y1 sdrc_dqs3n Data Strobe3 IO B2 Y2 ddr_padref Impedance controlfor A B12 M2 DDR2 output.Thispin must be connectedto groundviaa 50-ohm (± 2%) resistor. VREFSSTL 0.9-VDDR dataPHY0 IO F14 L5 referencevoltageinput.

2.4.2 Video Interfaces

Table2-6.VIDEO INTERFACES -CCDC SINGALS DESCRIPTION SIGNAL NAME DESCRIPTION TYPE ZCN BALL ZER BALL SYSTEM MUX MODE (1) ccdc_pclk CCDC pixelclock IO AD2 AB21 mode0 ccdc_field CCDC fieldID signal IO AD1 AA21 mode0 ccdc_hd CCDC horizontal IO AE2 Y21 mode0 sync ccdc_vd CCDC verticalsync IO AD3 Y22 mode0 ccdc_wen CCDC writeenable I AE3 W21 mode0 ccdc_data0 CCDC databit0 I AD4 W22 mode0 ccdc_data1 CCDC databit1 I AE4 W20 mode0 ccdc_data2 CCDC databit2 I AC5 V21 mode0 ccdc_data3 CCDC databit3 I AD5 V19 mode0 ccdc_data4 CCDC databit4 I AE5 V22 mode0 ccdc_data5 CCDC databit5 I Y6 U20 mode0 ccdc_data6 CCDC databit6 I AB6 V20 mode0 ccdc_data7 CCDC databit7 I AC6 U19 mode0 ccdc_data8 CCDC databit8 I AE6 U21 mode1 ccdc_data9 CCDC databit9 I AD6 U22 mode1 ccdc_data10 CCDC databit10 I Y7 T19 mode1 ccdc_data11 CCDC databit11 I AA7 T20 mode1 ccdc_data12 CCDC databit12 I AB7 T21 mode1 ccdc_data13 CCDC databit13 I AC7 R22 mode1 ccdc_data14 CCDC databit14 I AD7 T22 mode1 ccdc_data15 CCDC databit15 I AE7 R20 mode1 (1) See MultiplexingCharacteristicstableformore information. Table2-7.Video Interfaces-DSS SignalsDescription SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL ZER BALL dss_pclk LCD PixelClock O AE23 B22 dss_hsync LCD Horizontal O AD22 B21 Synchronization dss_vsync LCD Vertical O AD23 B20 Synchronization

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PRODUCT□PREVIEW AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Table2-7.Video Interfaces-DSS SignalsDescription(continued) SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL ZER BALL dss_acbias AC biascontrol(STN) or O AE24 B19 pixeldataenable(TFT) output dss_data0 LCD PixelData bit0 IO AD24 A20 dss_data1 LCD PixelData bit1 IO AD25 A19 dss_data2 LCD PixelData bit2 IO AC23 A18 dss_data3 LCD PixelData bit3 IO AC24 B18 dss_data4 LCD PixelData bit4 IO AC25 A17 dss_data5 LCD PixelData bit5 IO AB24 C18 dss_data6 LCD PixelData bit6 IO AB25 D17 dss_data7 LCD PixelData bit7 IO AA23 B16 dss_data8 LCD PixelData bit8 IO AA24 B17 dss_data9 LCD PixelData bit9 IO AA25 C17 dss_data10 LCD PixelData bit10 IO Y22 C16 dss_data11 LCD PixelData bit11 IO Y23 D16 dss_data12 LCD PixelData bit12 IO Y24 D14 dss_data13 LCD PixelData bit13 IO Y25 A16 dss_data14 LCD PixelData bit14 IO W21 D15 dss_data15 LCD PixelData bit15 IO W22 B15 dss_data16 LCD PixelData bit16 IO W23 A15 dss_data17 LCD PixelData bit17 IO W24 A14 dss_data18 LCD PixelData bit18 IO W25 C13 dss_data19 LCD PixelData bit19 IO V24 C15 dss_data20 LCD PixelData bit20 O V25 A13 dss_data21 LCD PixelData bit21 O U21 B13 dss_data22 LCD PixelData bit22 O U22 C14 dss_data23 LCD PixelData bit23 O U23 B14 Table2-8.Video Interfaces– RFBI SignalsDescription SIGNAL NAME [1] DESCRIPTION [2[ TYPE [3] ZCN BALL ZER BALL SUBSYSTEM PIN MULTIPLEXING [5] rfbi_a0 RFBI command/data O AE24 B19 dss_acbias control rfbi_cs0 1stLCD chipselect O AD22 B21 dss_hsync rfbi_da0 RFBI databus 0 IO AD24 A20 dss_data0 rfbi_da1 RFBI databus 1 IO AD25 A19 dss_data1 rfbi_da2 RFBI databus 2 IO AC23 A18 dss_data2 rfbi_da3 RFBI databus 3 IO AC24 B18 dss_data3 rfbi_da4 RFBI databus 4 IO AC25 A17 dss_data4 rfbi_da5 RFBI databus 5 IO AB24 C18 dss_data5 rfbi_da6 RFBI databus 6 IO AB25 D17 dss_data6 rfbi_da7 RFBI databus 7 IO AA23 B16 dss_data7 rfbi_da8 RFBI databus 8 IO AA24 B17 dss_data8 rfbi_da9 RFBI databus 9 IO AA25 C17 dss_data9 rfbi_da10 RFBI databus 10 IO Y22 C16 dss_data10 rfbi_da11 RFBI databus 11 IO Y23 D16 dss_data11 rfbi_da12 RFBI databus 12 IO Y24 D14 dss_data12 rfbi_da13 RFBI databus 13 IO Y25 A16 dss_data13 Copyright© 2009–2010,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 61 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Table2-8.Video Interfaces– RFBI SignalsDescription(continued) SIGNAL NAME [1] DESCRIPTION [2[ TYPE [3] ZCN BALL ZER BALL SUBSYSTEM PIN MULTIPLEXING [5] rfbi_da14 RFBI databus 14 IO W21 D15 dss_data14 rfbi_da15 RFBI databus 15 IO W22 B15 dss_data15 rfbi_rd Read enableforRFBI O AE23 B22 dss_pclk rfbi_wr WriteEnablefor O AD23 B20 dss_vsync RFBI rfbi_te_vsync0 tearingeffectremoval I W23 A15 dss_data16 and Vsync inputfrom 1stLCD rfbi_hsync0 Hsync for1stLCD I W24 A14 dss_data17 rfbi_te_vsync1 tearingeffectremoval I W25 C13 dss_data18 and Vsync inputfrom 2nd LCD rfbi_hsync1 Hsync for2nd LCD I V24 C15 dss_data19 rfbi_cs1 2nd LCD chipselect O V25 A13 dss_data20 Table2-9.Video Interfaces– TV SignalsDescription SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL ZER BALL tv_out1 TV analogoutput O K21 NA Composite:tv_out1 tv_out2 TV analogoutput O H24 NA S-VIDEO: tv_out2 tv_vfb1 tv_vfb1:Feedback O K20 NA throughexternalresistor tocomposite tv_vfb2 tv_vfb2:Feedback O H23 NA throughexternalresistor toS-VIDEO tv_vref Externalcapacitor I H20 NA

2.4.3 SerialCommunication Interfaces

Table2-10.HDQ SignalsDescription SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL ZER BALL hdq_sio BidirectionalHDQ 1-Wire IO L25 NA controland dataInterface. Outputisopen drain. Table2-11.SerialCommunication Interfaces– I2C SignalsDescription(I2C1) SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL ZER BALL i2c1_scl I2C MasterSerialclock. IOD V4 AA17 Outputisopen drain. i2c1_sda I2C SerialBidirectional IOD V5 AB17 Data.Outputisopen drain. Table2-12.SerialCommunication Interfaces-I2C SignalsDescription(I2C2) SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL ZER BALL i2c2_scl I2C MasterSerialclock. IOD W1 Y17 Outputisopen drain.

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PRODUCT□PREVIEW AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Table2-12.SerialCommunication Interfaces-I2C SignalsDescription(I2C2)(continued) SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL ZER BALL i2c2_sda I2C SerialBidirectional IOD W2 Y16 Data.Outputisopen drain. Table2-13.SerialCommunication Interfaces-I2C SignalsDescription(I2C3) SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL ZER BALL i2c3_scl I2C MasterSerialclock. IOD W4 W16 Outputisopen drain. i2c3_sda I2C SerialBidirectional IOD W5 W17 Data.Outputisopen drain. Table2-14.SerialCommunication Interfaces– McBSP LP SignalsDescription SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL ZER BALL MULTICHANNEL BUFFERED SERIAL PORT (McBSP LP 1) mcbsp1_dr Receivedserialdata I P23 C9 mcbsp1_clkr ReceiveClock IO R25 B11 mcbsp1_fsr Receiveframe IO P21 D11 synchronization mcbsp1_dx Transmittedserialdata IO P22 C10 mcbsp1_clkx Transmitclock IO N24 C8 mcbsp1_fsx Transmitframe IO P24 C11 synchronization mcbsp_clks Externalclockinput I P25 E11 (sharedby McBSP1, 2,3, 4,and 5) MULTICHANNEL BUFFERED SERIAL PORT (McBSP LP 2) mcbsp2_dr Receivedserialdata I B25 C5 mcbsp2_dx Transmittedserialdata IO D24 E4 mcbsp2_clkx Combined serialclock IO C25 D5 mcbsp2_fsx Combined frame IO D25 E5 synchronization MULTICHANNEL BUFFERED SERIAL PORT (McBSP LP 3) mcbsp3_dr Receivedserialdata I C24 B4 mcbsp3_dx Transmittedserialdata IO B24 C4 mcbsp3_clkx Combined serialclock IO A24 D4 mcbsp3_fsx Combined frame IO C23 A4 synchronization MULTICHANNEL BUFFERED SERIAL PORT (McBSP LP 4) mcbsp4_dr Receivedserialdata I A23 B3 mcbsp4_dx Transmittedserialdata IO B22 A2 mcbsp4_clkx Combined serialclock IO B23 A3 mcbsp4_fsx Combined frame IO A22 B2 synchronization MULTICHANNEL BUFFERED SERIAL PORT (McBSP LP 5) mcbsp5_dr Receivedserialdata I Y18 E19 mcbsp5_dx Transmittedserialdata IO AD19 F19 mcbsp5_clkx Combined serialclock IO AD17 G22 mcbsp5_fsx Combined frame IO AE19 F21 synchronization Copyright© 2009–2010,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 63 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Table2-15.SerialCommunication Interfaces– McSPI SignalsDescription SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL ZER BALL MULTICHANNEL SERIAL PORT INTERFACE (McSPI1) mcspi1_clk SPI Clock IO AE14 K22 mcspi1_simo Slavedatain,masterdata IO AD15 K19 out mcspi1_somi Slavedataout,master IO AC15 J18 datain mcspi1_cs0 SPI Enable0,polarity IO AB15 K18 configuredby software mcspi1_cs1 SPI Enable1,polarity O AD14 J20 configuredby software mcspi1_cs2 SPI Enable2,polarity O AE15 J19 configuredby software mcspi1_cs3 SPI Enable3,polarity O AE16 J21 configuredby software MULTICHANNEL SERIAL PORT INTERFACE (McSPI2) mcspi2_clk SPI Clock IO AD16,AC9 J22 mcspi2_simo Slavedatain,masterdata IO AC16,AD9 H20 out mcspi2_somi Slavedataout,master IO AB16,AE9 H22 datain mcspi2_cs0 SPI Enable0,polarity IO AA16,AA10 H21 configuredby software mcspi2_cs1 SPI Enable1,polarity O AE17 H19 configuredby software MULTICHANNEL SERIAL PORT INTERFACE (McSPI3) mcspi3_clk SPI Clock IO W25,AD11,AA18 C13, M21, G19, E20 mcspi3_simo Slavedatain,masterdata IO V24,AE11,AD18 C15, M20, G20 out mcspi3_somi Slavedataout,master IO V25,AB12, AC18 A13,K20,F22 datain mcspi3_cs0 SPI Enable0,polarity IO U21,AE12,AB18 B13,K21,F20 configuredby software mcspi3_cs1 SPI Enable1,polarity O U22, AD12, AB19 C14, M18, E21 configuredby software MULTICHANNEL SERIAL PORT INTERFACE (McSPI4) mcspi4_clk SPI Clock IO W20, R25 C20, B11 mcspi4_simo Slavedatain,masterdata IO P22 C10 out mcspi4_somi Slavedataout,master IO P23 C9 datain mcspi4_cs0 SPI Enable0,polarity IO P24 C11 configuredby software Table2-16.SerialCommunication Interfaces– HECC SignalsDescription SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL ZER BALL hecc1_txd Transmitserialdatapin O V2 AB15 hecc1_rxd Receiveserialdatapin I V3 AB16 Table2-17.SerialCommunication Interfaces– EMAC (RMII)SignalsDescription SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL ZER BALL rmii_mdio_data Management dataI/O IO AE6 U21 rmii_mdio_clk Management dataclock O AD6 U22

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PRODUCT□PREVIEW AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Table2-17.SerialCommunication Interfaces– EMAC (RMII)SignalsDescription(continued) SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL ZER BALL rmii_rxd0 EMAC receivedatapin0 I Y7 T19 rmii_rxd1 EMAC receivedatapin1 I AA7 T20 rmii_crs_dv EMAC carrier I AB7 T21 sense/receivedatavalid rmii_rxer EMAC receiveerror I AC7 R22 rmii_txd0 EMAC transmitdatapin0 O AD7 T22 rmii_txd1 EMAC transmitdatapin1 O AE7 R20 rmii_txen EMAC transmitenable O AD8 R19 rmii_50mhz_clk EMAC RMII 50 MHz clock I AE8 R21 Table2-18.SerialCommunication Interfaces– UARTs SignalsDescription SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL ZER BALL UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART1) uart1_cts UART1 ClearTo Send I AD24,Y20,P25 C19 uart1_rts UART1 RequestTo Send O AD25,Y19 C21 uart1_rx UART1 Receivedata I AA23,W20,AC20 C20 uart1_tx UART1 Transmitdata O AB25,AA19 C22 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART2) uart2_cts UART2 ClearTo Send I B24,F20 A5 uart2_rts UART2 RequestTo Send O C24,F19 B5 uart2_rx UART2 Receivedata I C23,E23 C6 uart2_tx UART2 Transmitdata O A24,E24 D6 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART3) /IrDA uart3_cts_rctx UART3 ClearTo Send IO U1,N2 W15 (input),Remote TX (output) uart3_rts_sd UART3 RequestTo Send O N3,V3 W13 ,IR enable uart3_rx_irrx UART3 Receivedata,IR I AC25,P1,F25,V2 AA13 and Remote RX uart3_tx_irtx UART3 Transmitdata,IR O AB24,P2,F24,E25 Y13 TX UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART4) uart4_cts UART4 ClearTo Send I AD3,AD11 Y22,M21 uart4_rts UART4 RequestTo Send O AE2,AE11 Y21,M20 uart4_rx UART4 Receivedata I T5,AE3,AC12 Y14,W21,L19 uart4_tx UART4 Transmitdata O T4,AD1,AB12 AA16,AA21,K20 Table2-19.SerialCommunication Interfaces– USB SignalsDescription SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL ZER BALL UNIVERSAL SERIAL BUS INTERFACE (USB0) usb0_dp USB D+ (differentialsignalA F25 A6 pair) usb0_dm USB D- (differentialsignal A F24 B6 pair) usb0_drvvbus Digitaloutputtocontrol O E25 A7 externalsupply usb0_id USB operatingmode A G25 B7 identificationpin Copyright© 2009–2010,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 65 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Table2-19.SerialCommunication Interfaces– USB SignalsDescription(continued) SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL ZER BALL usb0_vbus Forhostordevicemode A G24 C7 operation,tiethe VBUS/USB power signal totheUSB connector. When used inOTG mode operation,tieVBUS tothe externalchargepump and totheVBUS signalon the USB connector. MM_FSUSB3 mm_fsusb3_rxdm Vminus receivedata(not IO AE13 M19 used in3-or4-pin configurations) mm_fsusb3_rxdp Vplusreceivedata(not IO AC13 L20 used in3-or4-pin configurations) mm_fsusb3_rxrcv Differentialreceiversignal IO A23 B3 input(notused in3-pin mode) mm_fsusb3_txse0 Single-endedzero.Used IO B23 A3 as VM in4-pinVP_VM mode. mm_fsusb3_txdat USB data.Used as VP in IO B22 A2 4-pinVP_VM mode. mm_fsusb3_txen_n Transmitenable IO A22 B2 MM_FSUSB2 mm_fsusb2_rxdm Vminus receivedata(not IO AD21 D20 used in3-or4-pin configurations) mm_fsusb2_rxdp Vplusreceivedata(not IO AB20 E20 used in3-or4-pin configurations) mm_fsusb2_rxrcv Differentialreceiversignal IO AC21 D19 input(notused in3-pin mode) mm_fsusb2_txse0 Single-endedzero.Used IO AE22 D18 as VM in4-pinVP_VM mode. mm_fsusb2_txdat USB data.Used as VP in IO AE16 J21 4-pinVP_VM mode. mm_fsusb2_txen_n Transmitenable IO AE17 H19 MM_FSUSB1 mm_fsusb1_rxdm Vminus receivedata(not IO AD20 D21 used in3-or4-pin configurations) mm_fsusb1_rxdp Vplusreceivedata(not IO AE18 G21 used in3-or4-pin configurations) mm_fsusb1_rxrcv Differentialreceiversignal IO AD18 G20 input(notused in3-pin mode) mm_fsusb1_txse0 Single-endedzero.Used IO AC18 F22 as VM in4-pinVP_VM mode. mm_fsusb1_txdat USB data.Used as VP in IO AB18 F20 4-pinVP_VM mode. mm_fsusb1_txen_n Transmitenable IO AB19 E21 HSUSB2

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PRODUCT□PREVIEW AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Table2-19.SerialCommunication Interfaces– USB SignalsDescription(continued) SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL ZER BALL hsusb2_clk Dedicatedforexternal O AC20 E22 transceiver60-MHz clock inputfromPHY hsusb2_stp Dedicatedforexternal O AB20 E20 transceiverStopsignal hsusb2_dir Dedicatedforexternal I AE21 E18 transceiverData direction controlfromPHY hsusb2_nxt Dedicatedforexternal I AD21 D20 transceiverNextsignal fromPHY hsusb2_data0 Dedicatedforexternal IO AC21 D19 transceiverBidirectional databus hsusb2_data1 Dedicatedforexternal IO AE22 D18 transceiverBidirectional databus hsusb2_data2 Dedicatedforexternal IO AE16 J21 transceiverBidirectional databus hsusb2_data3 Dedicatedforexternal IO AE17 H19 transceiverBidirectional databus hsusb2_data4 Dedicatedforexternal IO AC16 H20 transceiverBidirectional databus additionalsignals for12-pinULPI operation. hsusb2_data5 Dedicatedforexternal IO AB16 H22 transceiverBidirectional databus additionalsignals for12-pinULPI operation. hsusb2_data6 Dedicatedforexternal IO AA16 H21 transceiverBidirectional databus additionalsignals for12-pinULPI operation. hsusb2_data7 Dedicatedforexternal IO AD16 J22 transceiverBidirectional databus HSUSB1 hsusb1_clk Dedicatedforexternal O AE18 G21 transceiver60-MHz clock inputfromPHY hsusb1_stp Dedicatedforexternal O AD17 G22 transceiverStopsignal hsusb1_dir Dedicatedforexternal I AE20 D22 transceiverData direction controlfromPHY hsusb1_nxt Dedicatedforexternal I AD20 D21 transceiverNextsignal fromPHY hsusb1_data0 Dedicatedforexternal IO AD18 G20 transceiverBidirectional databus hsusb1_data1 Dedicatedforexternal IO AC18 F22 transceiverBidirectional databus hsusb1_data2 Dedicatedforexternal IO AB18 F20 transceiverBidirectional databus Copyright© 2009–2010,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 67 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Table2-19.SerialCommunication Interfaces– USB SignalsDescription(continued) SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL ZER BALL hsusb1_data3 Dedicatedforexternal IO AB19 E21 transceiverBidirectional databus hsusb1_data4 Dedicatedforexternal IO Y18 E19 transceiverBidirectional databus additionalsignals for12-pinULPI operation hsusb1_data5 Dedicatedforexternal IO AE19 F21 transceiverBidirectional databus additionalsignals for12-pinULPI operation hsusb1_data6 Dedicatedforexternal IO AD19 F19 transceiverBidirectional databus additionalsignals for12-pinULPI operation hsusb1_data7 Dedicatedforexternal IO AA18 G19 transceiverBidirectional databus additionalsignals for12-pinULPI operation

2.4.4 Removable Media Interfaces

Table2-20.Removable Media Interfaces– MMC/SDIO SignalsDescription SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL ZER BALL MULTIMEDIA MEMORY CARD (MMC1) /SECURE DIGITAL IO (SDIO1) mmc1_clk MMC/SD OutputClock O AA9 P22 mmc1_cmd MMC/SD command signal IO AB9 N21 mmc1_dat0 MMC/SD Card Data bit0 / IO AC9 P21 SPI SerialInput mmc1_dat1 MMC/SD Card Data bit1 IO AD9 N20 mmc1_dat2 MMC/SD Card Data bit2 IO AE9 P19 mmc1_dat3 MMC/SD Card Data bit3 IO AA10 P20 mmc1_dat4 MMC/SD Card Data bit4 IO AB10 N22 mmc1_dat5 MMC/SD Card Data bit5 IO AC10 N19 mmc1_dat6 MMC/SD Card Data bit6 IO AD10 N18 mmc1_dat7 MMC/SD Card Data bit7 IO AE10 P18 MULTIMEDIA MEMORY CARD (MMC2) /SECURE DIGITAL IO (SDIO2) mmc2_clk MMC/SD OutputClock O AD11 M21 mmc2_dir_dat0 DirectioncontrolforDAT0 O AB13 L18 signalcase an external transceiverused mmc2_dir_dat1 DirectioncontrolforDAT1 O AC13 L20 and DAT3 signalscase an externaltransceiverused mmc2_dir_dat2 DirectioncontrolforDAT2 O AB1 V18 signalcase an external transceiverused mmc2_dir_dat3 DirectioncontrolforDAT4, O AB2 Y19 DAT5, DAT6, and DAT7 signalscase an external transceiverused mmc2_clkin MMC/SD inputclock I AE13 NA mmc2_dat0 MMC/SD Card Data bit0 IO AB12 K20 mmc2_dat1 MMC/SD Card Data bit1 IO AC12 L19 mmc2_dat2 MMC/SD Card Data bit2 IO AD12 M18

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PRODUCT□PREVIEW AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Table2-20.Removable Media Interfaces– MMC/SDIO SignalsDescription(continued) SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL ZER BALL mmc2_dat3 MMC/SD Card Data bit3 IO AE12 K21 mmc2_dat4 MMC/SD Card Data bit4 IO AB13 L18 mmc2_dat5 MMC/SD Card Data bit5 IO AC13 L20 mmc2_dat6 MMC/SD Card Data bit6 IO AD13 L21 mmc2_dat7 MMC/SD Card Data bit7 IO AE13 M19 mmc2_dir_cmd DirectioncontrolforCMD O AD13 NA signalcase an external transceiverisused mmc2_cmd MMC/SD command signal IO AE11 M20 MULTIMEDIA MEMORY CARD (MMC3) /SECURE DIGITAL IO (SDIO3) mmc3_clk MMC/SD OutputClock O AD15,AE17 J19 mmc3_cmd MMC/SD command signal IO AD14,AE18 J20 mmc3_dat0 MMC/SD Card Data bit0 / IO AB13,Y18 E19 SPI SerialInput mmc3_dat1 MMC/SD Card Data bit1 IO AC13,AE19 L20,F21 mmc3_dat2 MMC/SD Card Data bit2 IO AD13,AD19 L21,F19 mmc3_dat3 MMC/SD Card Data bit3 IO AE13,AA18 M19,G19 mmc3_dat4 MMC/SD Card Data bit4 IO AD18 G20 mmc3_dat5 MMC/SD Card Data bit5 IO AD20 D21 mmc3_dat6 MMC/SD Card Data bit6 IO AE20 D22 mmc3_dat7 MMC/SD Card Data bit7 IO AB19 E21 Copyright© 2009–2010,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 69 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

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2.4.5 TestInterfaces

Table2-21.TestInterfaces– ETK SignalsDescription SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL ZER BALL etk_ctl ETK tracectl O AE18 G21 etk_clk ETK traceclock O AD17 G22 etk_d0 ETK data0 O AD18 G20 etk_d1 ETK data1 O AC18 F22 etk_d2 ETK data2 O AB18 F20 etk_d3 ETK data3 O AA18 G19 etk_d4 ETK data4 O Y18 E19 etk_d5 ETK data5 O AE19 F21 etk_d6 ETK data6 O AD19 F19 etk_d7 ETK data7 O AB19 E21 etk_d8 ETK data8 O AE20 D22 etk_d9 ETK data9 O AD20 D21 etk_d10 ETK data10 O AC20 E22 etk_d11 ETK data11 O AB20 E20 etk_d12 ETK data12 O AE21 E18 etk_d13 ETK data13 O AD21 D20 etk_d14 ETK data14 O AC21 D19 etk_d15 ETK data15 O AE22 D18 Table2-22.TestInterfaces– JTAG SignalsDescription SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL ZER BALL jtag_ntrst TestReset I U24 D13 jtag_tck TestClock I U25 E14 jtag_rtck ARM ClockEmulation O T21 C12 jtag_tms_tmsc TestMode Select IO T22 A12 jtag_tdi TestData Input I T23 B12 jtag_tdo TestData Output O T24 D12 jtag_emu0 Testemulation0 IO T25 E13 jtag_emu1 Testemulation1 IO R24 E12 Table2-23.TestInterfaces– HWDBG SignalsDescription SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL ZER BALL hw_dbg0 Debug signal0 O AD2,AD17 G22 hw_dbg1 Debug signal1 O AD1,AE18 G21 hw_dbg2 Debug signal2 O AD3,AD18 G20 hw_dbg3 Debug signal3 O AE3,AC18 F22 hw_dbg4 Debug signal4 O AC5,AC18 F20 hw_dbg5 Debug signal5 O AD5,AA18 G19 hw_dbg6 Debug signal6 O Y18,AE5 E19 hw_dbg7 Debug signal7 O Y6,AE19 F21 hw_dbg8 Debug signal8 O Y7,AD19 F19 hw_dbg9 Debug signal9 O AA7,AB19 E21 hw_dbg10 Debug signal10 O AC7,AE20 D22 hw_dbg11 Debug signal11 O AD7,AD20 D21 hw_dbg12 Debug signal12 O AE23,AC20 E22

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PRODUCT□PREVIEW AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Table2-23.TestInterfaces– HWDBG SignalsDescription(continued) SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL ZER BALL hw_dbg13 Debug signal13 O AD22,AB20 E20 hw_dbg14 Debug signal14 O AB25,AE21 E18 hw_dbg15 Debug signal15 O AA23,AD21 D20 hw_dbg16 Debug signal16 O AA24,AC21 D19 hw_dbg17 Debug signal17 O AA25,AE22 D18

2.4.6 Miscellaneous

Table2-24.Miscellaneous– GP Timer SignalsDescription SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL ZER BALL gpt8_pwm_evt PWM oreventforGP IO N4,E23,AE17 V11,C6,H19 timer8 gpt9_pwm_evt PWM oreventforGP IO M4,M2,F20,AC16 Y12,AA11,A5,H20 timer9 gpt10_pwm_evt PWM oreventforGP IO M3,M1,F19,AB16 V12,W12,B5,H22 timer10 gpt11_pwm_evt PWM oreventforGP IO N5,E24,AA16,AA12 AA12,D6,H21 timer11 Copyright© 2009–2010,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 71 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

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2.4.7 General-PurposeIOs

Table2-25.General-PurposeIOs SignalsDescription SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL ZER BALL gpio_0 General-purposeIO 0 IO Y1 AB18 gpio_1 General-purposeIO 1 IO M24 B8 gpio_2 General-purposeIO 2 IO Y4 AB19 gpio_3 General-purposeIO 3 IO AA1 AB20 gpio_4 General-purposeIO 4 IO AA2 W18 gpio_5 General-purposeIO 5 IO AA3 AA19 gpio_6 General-purposeIO 6 IO AB1 V18 gpio_7 General-purposeIO 7 IO AB2 Y19 gpio_8 General-purposeIO 8 IO AC1 W19 gpio_10 General-purposeIO 10 IO N25 E9 gpio_11 General-purposeIO 11 IO T25 E13 gpio_12 General-purposeIO 12 IO AD17 G22 gpio_13 General-purposeIO 13 IO AE18 G21 gpio_14 General-purposeIO 14 IO AD18 G20 gpio_15 General-purposeIO 15 IO AC18 F22 gpio_16 General-purposeIO 16 IO AB18 F20 gpio_17 General-purposeIO 17 IO AA18 G19 gpio_18 General-purposeIO 18 IO Y18 E19 gpio_19 General-purposeIO 19 IO AE19 F21 gpio_20 General-purposeIO 20 IO AD19 F19 gpio_21 General-purposeIO 21 IO AB19 E21 gpio_22 General-purposeIO 22 IO AE20 D22 gpio_23 General-purposeIO 23 IO AD20 D21 gpio_24 General-purposeIO 24 IO AC20 E22 gpio_25 General-purposeIO 25 IO AB20 E20 gpio_26 General-purposeIO 26 IO AE21 E18 gpio_27 General-purposeIO 27 IO AD21 D20 gpio_28 General-purposeIO 28 IO AC21 D19 gpio_29 General-purposeIO 29 IO AE22 D18 gpio_30 General-purposeIO 30 IO Y3 Y18 gpio_31 General-purposeIO 31 IO R24 E12 gpio_34 General-purposeIO 34 IO E3 W5 gpio_35 General-purposeIO 35 IO E2 Y5 gpio_36 General-purposeIO 36 IO E1 AB4 gpio_37 General-purposeIO 37 IO F7 AA5 gpio_38 General-purposeIO 38 IO F6 AB5 gpio_39 General-purposeIO 39 IO F4 AB6 gpio_40 General-purposeIO 40 IO F3 AA6 gpio_41 General-purposeIO 41 IO F2 W6 gpio_42 General-purposeIO 42 IO F1 AB7 gpio_43 General-purposeIO 43 IO G6 Y6 gpio_44 General-purposeIO 44 IO J4 W10 gpio_45 General-purposeIO 45 IO J3 AB9 gpio_46 General-purposeIO 46 IO J2 AB10 gpio_47 General-purposeIO 47 IO J1 W9

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PRODUCT□PREVIEW AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Table2-25.General-PurposeIOs SignalsDescription(continued) SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL ZER BALL gpio_48 General-purposeIO 48 IO K4 AA10 gpio_49 General-purposeIO 49 IO K3 Y9 gpio_50 General-purposeIO 50 IO K2 V10 gpio_51 General-purposeIO 51 IO K1 V9 gpio_52 General-purposeIO 52 IO L1 Y11 gpio_53 General-purposeIO 53 IO M4 Y12 gpio_54 General-purposeIO 54 IO M3 V12 gpio_55 General-purposeIO 55 IO M2 AA11 gpio_56 General-purposeIO 56 IO M1 W12 gpio_57 General-purposeIO 57 IO N5 AA12 gpio_58 General-purposeIO 58 IO N4 V11 gpio_59 General-purposeIO 59 IO N1 AB13 gpio_60 General-purposeIO 60 IO R4 W11 gpio_61 General-purposeIO 61 IO T1 Y15 gpio_62 General-purposeIO 62 IO T2 W14 gpio_63 General-purposeIO 63 IO T4 AA16 gpio_64 General-purposeIO 64 IO T5 Y14 gpio_65 General-purposeIO 65 IO U1 V14 gpio_66 General-purposeIO 66 IO AE23 B22 gpio_67 General-purposeIO 67 IO AD22 B21 gpio_68 General-purposeIO 68 IO AD23 B20 gpio_69 General-purposeIO 69 IO AE24 B19 gpio_70 General-purposeIO 70 IO AD24 A20 gpio_71 General-purposeIO 71 IO AD25 A19 gpio_72 General-purposeIO 72 IO AC23 A18 gpio_73 General-purposeIO 73 IO AC24 B18 gpio_74 General-purposeIO 74 IO AC25 A17 gpio_75 General-purposeIO 75 IO AB24 C18 gpio_76 General-purposeIO 76 IO AB25 D17 gpio_77 General-purposeIO 77 IO AA23 B16 gpio_78 General-purposeIO 78 IO AA24 B17 gpio_79 General-purposeIO 79 IO AA25 C17 gpio_80 General-purposeIO 80 IO Y22 C16 gpio_81 General-purposeIO 81 IO Y23 D16 gpio_82 General-purposeIO 82 IO Y24 D14 gpio_83 General-purposeIO 83 IO Y25 A16 gpio_84 General-purposeIO 84 IO W21 D15 gpio_85 General-purposeIO 85 IO W22 B15 gpio_86 General-purposeIO 86 IO W23 A15 gpio_87 General-purposeIO 87 IO W24 A14 gpio_88 General-purposeIO 88 IO W25 C13 gpio_89 General-purposeIO 89 IO V24 C15 gpio_90 General-purposeIO 90 IO V25 A13 gpio_91 General-purposeIO 91 IO U21 B13 gpio_92 General-purposeIO 92 IO U22 C14 gpio_93 General-purposeIO 93 IO U23 B14 gpio_94 General-purposeIO 94 IO AD2 AB21 Copyright© 2009–2010,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 73 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Table2-25.General-PurposeIOs SignalsDescription(continued) SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL ZER BALL gpio_95 General-purposeIO 95 IO AD1 AA21 gpio_96 General-purposeIO 96 IO AE2 Y21 gpio_97 General-purposeIO 97 IO AD3 Y22 gpio_98 General-purposeIO 98 IO AE3 W21 gpio_99 General-purposeIO 99 I AD4 W22 gpio_100 General-purposeIO 100 I AE4 W20 gpio_101 General-purposeIO 101 IO AC5 V21 gpio_102 General-purposeIO 102 IO AD5 V19 gpio_103 General-purposeIO 103 IO AE5 V22 gpio_104 General-purposeIO 104 IO Y6 U20 gpio_105 General-purposeIO 105 IO AB6 V20 gpio_106 General-purposeIO 106 IO AC6 U19 gpio_107 General-purposeIO 107 IO AE6 U21 gpio_108 General-purposeIO 108 IO AD6 U22 gpio_109 General-purposeIO 109 IO Y7 T19 gpio_110 General-purposeIO 110 IO AA7 T20 gpio_111 General-purposeIO 111 IO AB7 T21 gpio_112 General-purposeIO 112 I AE7 R20 gpio_113 General-purposeIO 113 I AD8 R19 gpio_114 General-purposeIO 114 I AE8 R21 gpio_116 General-purposeIO 116 IO D25 E5 gpio_117 General-purposeIO 117 IO C25 D5 gpio_118 General-purposeIO 118 IO B25 C5 gpio_119 General-purposeIO 119 IO D24 E4 gpio_120 General-purposeIO 120 IO AA9 P22 gpio_121 General-purposeIO 121 IO AB9 N21 gpio_122 General-purposeIO 122 IO AC9 P21 gpio_123 General-purposeIO 123 IO AD9 N20 gpio_124 General-purposeIO 124 IO AE9 P19 gpio_125 General-purposeIO 125 IO AA10 P20 gpio_126 General-purposeIO 126 IO AB10 N22 gpio_127 General-purposeIO 127 IO AC10 N19 gpio_128 General-purposeIO 128 IO AD10 N18 gpio_129 General-purposeIO 129 IO AE10 P18 gpio_130 General-purposeIO 130 IO AD11 M21 gpio_131 General-purposeIO 131 IO AE11 M20 gpio_132 General-purposeIO 132 IO AB12 K20 gpio_133 General-purposeIO 133 IO AC12 L19 gpio_134 General-purposeIO 134 IO AD12 M18 gpio_135 General-purposeIO 135 IO AE12 K21 gpio_136 General-purposeIO 136 IO AB13 L18 gpio_137 General-purposeIO 137 IO AC13 L20 gpio_138 General-purposeIO 138 IO AD13 L21 gpio_139 General-purposeIO 139 IO AE13 M19 gpio_140 General-purposeIO 140 IO B24 C4 gpio_141 General-purposeIO 141 IO C24 B4 gpio_142 General-purposeIO 142 IO A24 D4

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PRODUCT□PREVIEW AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Table2-25.General-PurposeIOs SignalsDescription(continued) SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL ZER BALL gpio_143 General-purposeIO 143 IO C23 A4 gpio_144 General-purposeIO 144 IO F20 A5 gpio_145 General-purposeIO 145 IO F19 B5 gpio_146 General-purposeIO 146 IO E24 D6 gpio_147 General-purposeIO 147 IO E23 C6 gpio_148 General-purposeIO 148 IO AA19 C22 gpio_149 General-purposeIO 149 IO Y19 C21 gpio_150 General-purposeIO 150 IO Y20 C19 gpio_151 General-purposeIO 151 IO W20 C20 gpio_152 General-purposeIO 152 IO B23 A3 gpio_153 General-purposeIO 153 IO A23 B3 gpio_154 General-purposeIO 154 IO B22 A2 gpio_155 General-purposeIO 155 IO A22 B2 gpio_156 General-purposeIO 156 IO R25 B11 gpio_157 General-purposeIO 157 IO P21 D11 gpio_158 General-purposeIO 158 IO P22 C10 gpio_159 General-purposeIO 159 IO P23 C9 gpio_160 General-purposeIO 160 IO P25 E11 gpio_161 General-purposeIO 161 IO P24 C11 gpio_162 General-purposeIO 162 IO N24 C8 gpio_163 General-purposeIO 163 IO N2 W15 gpio_164 General-purposeIO 164 IO N3 W13 gpio_165 General-purposeIO 165 IO P1 AA13 gpio_166 General-purposeIO 166 IO P2 Y13 gpio_167 General-purposeIO 167 IO AC7 R22 gpio_168 General-purposeIO 168 IO W1 Y17 gpio_170 General-purposeIO 170 IO L25 B9 gpio_171 General-purposeIO 171 IO AE14 K22 gpio_172 General-purposeIO 172 IO AD15 K19 gpio_173 General-purposeIO 173 IO AC15 J18 gpio_174 General-purposeIO 174 IO AB15 K18 gpio_175 General-purposeIO 175 IO AD14 J20 gpio_176 General-purposeIO 176 IO AE15 J19 gpio_177 General-purposeIO 177 IO AE16 J21 gpio_178 General-purposeIO 178 IO AD16 J22 gpio_179 General-purposeIO 179 IO AC16 H20 gpio_180 General-purposeIO 180 IO AB16 H22 gpio_181 General-purposeIO 181 IO AA16 H21 gpio_182 General-purposeIO 182 IO AE17 H19 gpio_183 General-purposeIO 183 IO W2 Y16 gpio_184 General-purposeIO 184 IO W4 W16 gpio_185 General-purposeIO 185 IO W5 W17 gpio_186 General-purposeIO 186 IO M25 E10 Copyright© 2009–2010,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 75 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

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2.4.8 System and MiscellaneousTerminals

Table2-26.System and MiscellaneousSignalsDescription SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL ZER BALL sys_32k 32-kHzclockinput I K24 A8 sys_xtalin Main inputclock.Oscillatorinput I K25 A10 sys_xtalout Outputofoscillator O H25 A9 sys_altclk Alternateclocksourceselectablefor I L25 B9 GPTIMERs (maximum 54 MHz), USB (48 MHz) ,orNTSC/PAL (54MHz) sys_clkreq Requestfromdeviceforsystemclock(open IO M24 B8 sourcetype) sys_clkout1 Configurableoutputclock1 O N25 E9 sys_clkout2 Configurableoutputclock2 O M25 E10 sys_boot0 Bootconfigurationmode bit0 I Y4 AB19 sys_boot1 Bootconfigurationmode bit1 I AA1 AB20 sys_boot2 Bootconfigurationmode bit2 I AA2 W18 sys_boot3 Bootconfigurationmode bit3 I AA3 AA19 sys_boot4 Bootconfigurationmode bit4 I AB1 V18 sys_boot5 Bootconfigurationmode bit5 I AB2 Y19 sys_boot6 Bootconfigurationmode bit6 I AC1 W19 sys_boot7 Bootconfigurationmode bit7 I AC2 AA20 sys_boot8 Bootconfigurationmode bit8 I AC3 Y20 sys_nrespwron Power On Reset I Y2 AA18 sys_nreswarm Warm BootReset(opendrainoutput) I Y3 Y18 sys_nirq ExternalFIQ input I Y1 AB18 sys_ndmareq0 ExternalDMA request0 (system I M3 V12 expansion).Level(activelow)oredge (falling)selectable. sys_ndmareq1 ExternalDMA request1 (system I M2,U1 AA11 expansion).Level(activelow)oredge (falling)selectable. sys_ndmareq2 ExternalDMA request2 (system I F1,M1 W12 expansion).Level(activelow)oredge (falling)selectable. sys_ndmareq3 ExternalDMA request3 (system I G6,N5 AA12 expansion).Level(activelow)oredge (falling)selectable.

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2.4.9 Power Supplies

Table2-27.Power SuppliesDescription BALL BALLSIGNAL NAME [1] DESCRIPTION [2] (ZCN Pkg.) (ZER Pkg.) V16,V15,V11, V10,U16, U15, U11, U10, T18, T17,T9,T8, J8,J10,J12,J14,J16,K9,K11,K13, R18, R17, R9, K15,L8,L10,L12,L14,M7, M9, VDD_CORE 1.2-Vcoreand oscillatormacros power supply. R8, M18, L18, M11, M13, M15, N8, N10, N12, N14, L9,L8,K18, P7,P9,P11,P13,P15,R8, R10, K17,K9,K8, R12, R14 J16,J15,J11, J10,H15, H11, H10 AE25, AE1, V18,V17,V14, V13,V12,V9, V8,U18, U17, U14, U13, U12, U9, U8, T14, T13,T12,R16, R15, R14, R13, A1,A11,A22,E6,E16,F6,F13,F15,R12, R11, R10, F17,G5, G7, G11, G14, G16, G18,P18,P17,P16, H6, H7, H8, H9, H10, H11, H12, H13,P15,P14,P13, H14, H15, H16, H17, J9,J11,J13,P12,P11,P10, J15,K8,K10,K12,K14,K16,L7,L9,P9,P8,N18, L11,L13,L15,M1, M6, M8, M10,VSS Core and I/Ocommon ground. N17, N14, N13, M12, M14, M16, M22, N7, N9, N11,N12, N9, N8, N13, N15, N17, P6,P8,P10,P12,M17, M16, M15, P14,P16,R5, R7, R9, R11, R13,M14, M13,M12, R15, R17, T6,T8,T10,T12,T14,M11, M10, M9, T16,T18,U5, U7, U9, U11, U13,M8, L17,L16, U15, U17, V6,AB1, AB12, AB22L15,L14,L13, L12,L11,L10, K14,K13,K12, J18,J17,J14, J13,J12,J9,J8, H14, H13, H12, H9, A25,A1, N23, G20, G21 VDDS_SRAM_MPU 1.8-VMPU SLDO analogpower supply. AA13 L17 1.8-VCore SLDO and VDDA ofBandGap analogVDDS_SRAM_CORE_BG E17 J6power supply. 1.2-VSRAMOUT forMPU SLDO. CAP_VDD_SRAM_MPU Forproperdeviceoperation,connecttoa 1mF AA12 M17 decouplingcapacitor. 1.2-VSRAMOUT forCore SLDO. CAP_VDD_SRAM_CORE Forproperdeviceoperation,connecttoa 1mF E16 K6 decouplingcapacitor. VDDS_DPLL_MPU_USBH 1.8-VMPUSS DPLL and USBHOST DPLL analog AA15 K17OST power supply. 1.8-VDPLL and HSDIVIDER/ CORE andVDDS_DPLL_PER_CORE N20 F11HSDIVIDER analogpower supply. VDDA_DAC 1.8-VDAC analogpower supply. H21 NA VSSA_DAC DAC analogground. H22 NA VDDA3P3V_USBPHY 3.3-VUSB transceiveranalogpower supply. F23 F7 VDDA1P8V_USBPHY 1.8-VUSB transceiverpower supply. G22 D7 Outputofthe1.2-VinternalLDO.CAP_VDDA1P2LDO_USB Forproperdeviceoperation,connecta 0.22uF F22 E7PHY capacitorbetween thispinand VSSA. Copyright© 2009–2010,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 77 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Table2-27.Power SuppliesDescription(continued) BALL BALLSIGNAL NAME [1] DESCRIPTION [2] (ZCN Pkg.) (ZER Pkg.) Y16,Y15,Y13, Y12,Y10,W16, W15, W13, W12,W10, W9, A21,B1,E15,E17,F12,F14,F18,W6, V7,V6, G10, G12, G13, G8, G17, H18, J17,U19, T20,T19,VDDSHV 1.8/3.3-Vpower supply. L22,N16, P17,R16, R18, T9,T11,T7,T6,R7, R6, T13,T17,U8, U10, U12, U14, U16,P20,P19,N19, U18, V7,V8,V17,AA22, AB11N7, N6, M7, M6, M5, L19,K19, K7,K6,K5,J7, H18, H17 Y9,W18, U20, R5, H16, H8, F5,F16,G9, G15, H5, K7,L6,L16,G17, G16, G14,VDDS 1.8-Vpower supply. N1, N5, N6, P5,R6, T5,T7,T15,U6,G13, G11, G10, AA1G8, F16,F13, F11,F10,F8 VDDSOSC 1.8-Voscillatorpower supply. L20 G9 VSSOSC Oscillatorground. J25 B10

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3 ELECTRICAL CHARACTERISTICS

3.1 AbsoluteMaximum Ratings

The followingtablespecifiestheabsolutemaximum ratingsovertheoperatingjunctiontemperaturerange ofcommercialand extendedtemperaturedevices.Stressesbeyond thoselistedunderabsolutemaximum ratingsmay cause permanent damage to the device.These are stressratingsonly and functional operationof the deviceat these or any otherconditionsbeyond those indicatedunder recommended operatingconditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiods may affectdevicereliability. Notes:

• Logicfunctionsand parametervaluesarenotassuredoutoftherangespecifiedintherecommended operatingconditions.
• The AM3517/05 device adheres to EIA/JESD22−A114, ElectrostaticDischarge(ESD) Sensitivity TestingHuman Body Model (HBM).Minimum pass levelforHBM is2 kV. Table3-1.AbsoluteMaximum RatingsOver OperatingJunctionTemperature Range PARAMETER MIN MAX UNIT VDD_CORE Supplyvoltagerangeforcoremacros -0.5 1.6 V VDDS Second supplyvoltagerangefor1.8-VI/Omacros -0.5 2.25 V VDDSHV Supplyvoltagerangefor1.8/3.3VI/Omacros -0.5 3.8 V VDDS_SRAM_MPU AnalogSupplyvoltagerangefor1.8-VMPU SLDO -0.5 2.25 V VDDS_SRAM_CORE_BG AnalogSupplyvoltagerangefor1.8-VCore SLDO and -0.5 2.25 V VDDA ofBandGap VDDS_DPLL_MPU_USB Analogpower supplyfor1.8-VMPUSS DPLL and -0.5 2.1 V HOST USBHOST DPLL VDDS_DPLL_PER_COR Analogpower supplyfor1.8-VDPLL and HSDIVIDER/ -0.5 2.1 V E CORE and HSDIVIDER VDDA_DAC AnalogPower Supplyfor1.8-VDAC -0.5 2.43 V VDDA3P3V_USBPHY Analogpower supplyfor3.3-VUSB transceiver -0.5 3.6 V VDDA1P8V_USBPHY Power Supplyfor1.8-VUSB transceiver -0.5 2.0 V VDDSOSC Power Supplyfor1.8-Voscillator -0.5 2.1 V VPAD Voltagerangeat Oscillatorinput(sys_xtalin) -0.3 VDDSOSC + 0.3 V PAD VDDS 1.8-VI/Omacros -0.3 VDDS + 0.3 Dual-voltageLVCMOS inputs, -0.3 VDDSHV + 0.3 VDDSHV = 1.8V Dual-voltageLVCMOS inputs, -0.3 3.8 VDDSHV = 3.3V USB VBUS pin(usb0_vbus) 5.5 USB 5V TolerantIOs (usb0_dp, 5.25 usb0_dm, usb0_id) VESD ESD stress HBM (human body model)(2) 1000 V voltage(1) CDM (chargeddevicemodel)(3) 500 IIOI Current-pulseinjectionon each I/Opin(4) 200 mA Iclamp Clamp currentforan inputoroutput -20 20 mA Tstg Storagetemperaturerange(5) -65 150 °C (1) Electrostaticdischarge(ESD) tomeasure devicesensitivity/immunitytodamage caused by electrostaticdischargesintothedevice. (2) JEDEC JESD22 −A114 D withthefollowingexception-noconnectpinsarenotstressed.2000V Human Body Model (HBM) (3) JEDEC JESD22 −C101C withthefollowingexception-splitoutpingroupingstoeliminatecumulativestresseffect (4) Each deviceistestedwithI/Opininjectionof200 mA witha stressvoltageof1.5timesmaximum vdd atroom temperature. (5) These temperaturesextremedo notsimulateactualoperatingconditionsbutexaggerateany faultsthatmightexist. Copyright© 2009–2010,Texas InstrumentsIncorporated ELECTRICAL CHARACTERISTICS 79 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com The supplyvoltagesand power consumptionestimatesaredetailedinTable3-2. Table3-2.EstimatedPower Consumption atBallLevel MAX CURRENTSIGNAL NAME DESCRIPTION (mA) VDD_CORE 1.2-Vcoreand oscillatormacros power supply 1500 mA VDDS_SRAM_MPU 1.8-VMPU SLDO analogpower supply 40 mA VDDS_SRAM_CORE_BG 1.8-VCore SLDO and VDDA ofBandGap analogpower supply 40 mA VDDS_DPLL_MPU_USBHOST 1.8-VMPUSS DPLL and USBHOST DPLL analogpower supply 25 mA VDDS_DPLL_PER_CORE 1.8-VDPLL and HSDIVIDER/ CORE and HSDIVIDER analogpower supply 25 mA VDDA_DAC 1.8-VDAC analogpower supply 65 mA VDDA3P3V_USBPHY 3.3-VUSB transceiveranalogpower supply 10 mA VDDA1P8V_USBPHY 1.8-VUSB transceiverpower supply 50 mA VDDSHV 3.3-/1.8--Vpower supply 300 mA VDDS 1.8-Vpower supply 200 mA VDDSOSC 1.8-Voscillatorpower supply 20 mA

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3.2 Recommended OperatingConditions

AllAM3517/05 modules areused undertheoperatingconditionscontainedinTable3-3. Note: Logicfunctionsand parametervaluesare not assuredifthe deviceisoperatedout of the range specifiedintherecommended operatingconditions. Table3-3.Recommended OperatingConditions PARAMETER DESCRIPTION MIN NOM MAX UNIT VDD_CORE Core and oscillatormacros power supply 1.152 1.20 1.248 V Noise(peak-peak) 24.00 mVpp VDDS_SRAM_ MPU SRAM LDO analogpower supply 1.71 1.80 1.89 V MPU Noise(peak-peak) 50.00 mVpp VDDS_SRAM_ Core SRAM LDO and BandGap analogpower 1.71 1.80 1.89 V CORE_BG supply Noise(peak-peak) 50.00 mVpp VDDS_DPLL_ MPU and USBHOST DPLL analogpower supply 1.71 1.80 1.89 V MPU_ Noise(peak-peak) 35.00 mVppUSBHOST VDDS_DPLL_ Peripheralsand Core DPLLs analogpower supply 1.71 1.80 1.89 V PER_CORE Noise(peak-peak) 35.00 mVpp VDDA_DAC DAC analogpower supply 1.71 1.80 1.89 V Noise(peak-peak) 30.00 mVpp VSSA_DAC DAC analogground 0.00 V VDDA3P3V_ Analogpower supplyfor3.3-VUSB transceiver 3.14 3.30 3.47 V USBPHY Noise(peak-peak) 70.00 mVpp VDDA1P8V_ Power Supplyfor1.8-VUSB transceiver 1.71 1.80 1.89 V USBPHY Noise(peak-peak) 50.00 mVpp 3.3V Mode 3.14 3.30 3.47 V VDDS 1.8-Vpower supply 1.71 1.80 1.89 V Tj Operatingjunctiontemperature Commercial 0 90 °C range Temperature Extended -40 105 °C Temperature Device 500 MHz ARM ClockFreq. < 90°C TJ 100K hrs. OperatingLife 90 -105 °C TJ 100KPower-On 600 MHz ARM ClockFreq. < 90°C TJ 100KHours (POH) (1) 90 -105 °C TJ 50K (2) (1) The POH informationisprovidedsolelyforyourconvenienceand does notextendormodifythewarrantyprovidedunderTI’s standard termsand conditionsforTIsemiconductorproducts. (2) Maximum lifetimewillbe 100k Power On Hours as longas no more than50k isgreaterthan90°C. Copyright© 2009–2010,Texas InstrumentsIncorporated ELECTRICAL CHARACTERISTICS 81 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW MPU Core Periph1 vdd_core domain DPLL_MPU LDO in 1.8 V out 1.2 V Dual Video DAC SRAM2 ARRAYSRAM 2 LDO 0 V/1.0 V/1.2 V SRAM1 ARRAY SRAM 1 LDO 0 V/1.0 V/1.2 VDPLL_CORE LDO in 1.8 V out 1.2 V DPLL4 LDO in 1.8 V out 1.2 V LDO3 1.0 V/1.2 V vdds Periph2 DPLL5 LDO in 1.8 V out 1.2 V BandGap BCK MEM vss DLL/DCDL HSDIVIDER LDO HSDIVIDER LDO cap_vdd_sram_core tv_ref (for capacitor) vssa_dac vdds_dpll_mpu_usbhost vddshv Device vdd_core vdds_dpll_per_core vdda_dac 030-003 VDDSHV VDDS AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com The followingdiagramillustratesthepower domains: Figure3-1.AM3517/05 VoltageDomains

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3.3 DC ElectricalCharacteristics

summarizesthedc electricalcharacteristics. Table3-4.DC ElectricalCharacteristics PARAMETER MIN NOM MAX UNIT LVCMOS Pin Buffers VIH High-levelinputvoltage 0.65x VHHSHV VVDDSHV = 1.8V(1) 2VDDSHV = 3.3V(1) sys_xtalin 0.8x VDDOSC VIL Low-levelinputvoltage 0.3x VDDSHV VVDDSHV = 1.8V(1) 0.6VDDSHV = 3.3V(1) sys_xtalin 0.2x VDDOSC VOH High-leveloutputvoltage VDDSHV -0.45 VVDDSHV = 1.8V(1) 2.4VDDSHV = 3.3V(1) VOL Low-leveloutputvoltage 0.45 VVDDSHV = 1.8V(1) 0.4VDDSHV = 3.3V(1) tT Inputtransitiontime(rise 860 psVDDSHV = 1.8V(1) time,tR orfalltime,tF 860VDDSHV = 3.3V(1) evaluatedbetween 10% and 90% atPAD) II InputcurrentwithV I= VI ± 5 mA max Capacitance Inputcapacitance 3 pF (dual-voltageLVCMOS I/Os) Outputcapacitance 3 pF (dual-voltageLVCMOS I/Os) Complex IO DedicatedtoUSB :USB0_DM and USB0_DP VIH High-levelinputvoltage Low/Fullspeed 2.0 V Highspeed (2)VIL Low-levelinputvoltage Low/Fullspeed 0.8 V Highspeed (2) VOH High-leveloutputvoltage Low/Fullspeed 2.8 VDDA3P3V_ V USBPHY Highspeed 360 440 mV VOL Low-leveloutputvoltage Low/Fullspeed 0.0 0.3 V Highspeed -10 10 mV (1) These IO specificationsapplytothedual-voltageIOs onlyand do notapplytotheDDR2/mDDR interfaces.DDR2/mDDR IOs are1.8V IOs and adheretotheJESD79-2A standard. Copyright© 2009–2010,Texas InstrumentsIncorporated ELECTRICAL CHARACTERISTICS 83 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

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3.4 Core VoltageDecoupling

For module performance,decouplingcapacitorsare requiredtosuppresstheswitchingnoisegenerated by highfrequencyand tostabilizethesupplyvoltage.A decouplingcapacitorismost effectivewhen itis closetothedevicebecause thisminimizestheinductanceofthecircuitboardwiringand interconnects. Table3-5summarizesthepower suppliesdecouplingcharacteristics. Table3-5.Core VoltageDecoupling Characteristics PARAMETER MIN TYP MAX UNIT Cvdd_core(1) 50 100 120 nF Ccap_vdd_sram_core 100 nF Cvdds_dpll_mpu_usbhost 100 nF Cvdds_dpll_per_core 100 nF Cvdda_dac 100 nF Cvdd_sram_core 100 nF Cvdd_sram_core_bg 100 nF Cvdds_sram_mpu 100 nF Cvddshv 100 nF Cvdda3p3v_usbphy 100 nF Cvdda1p8v_usbphy 100 nF (1) 1 capacitorper2 to4 balls

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PRODUCT□PREVIEW SRAM_LDO1 SRAM_LDO2 WKUP_LDO DPLL_MPU DPLL_CORE vdds_dpll_mpu _usbhost vdds_sram_mpu DPLL5 DPLL4 vdds_dpll_per_core Video DAC vdda_dac Device VSS vssa_dac Cvdds_sram_mpu vdds_sram_core_bg Ccap_vdd_sram_core Cvdds_dpll_mpu_usbhost Cvdds_dpll_per_core Cvdda_dac vdda_dac vdds_dpll_per_core vdds_dpll_mpu_usbhost Core vdd_core Cvdd_core Vdd_core 030-004 MPU BG Cvdds_sram_core_bg Cvdd_sram_core cap_vdd_sram_mpu Ccap_vdd_sram_mpu vdd_sram_core cap_vdd_sram _core vdds_sram_mpu vdd_sram_core vdds_sram_core_bg AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 The followingillustratesan example ofpower supplydecoupling. (1) Decouplingcapacitorsmust be placedas closedas possibletothepower ball.Choose thegroundlocatedclosesttothepower pin foreach decouplingcapacitor.Place the decouplingcapacitorCi in a group of 1, 2, or 3 balls;the totalmust be equal to the decouplingrequirement.Incase you interconnectpowers,firstinsertthedecouplingcapacitorand theninterconnectthepowers. (2) The decouplingcapacitorvaluedepends on theboardcharacteristics. Figure3-2.Power Supply Decoupling Copyright© 2009–2010,Texas InstrumentsIncorporated ELECTRICAL CHARACTERISTICS 85 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

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3.5 Power-up and Power-down

ThissectionprovidesthetimingrequirementsfortheAM3517/05 hardwaresignals.

3.5.1 Power-up Sequence

The followingstepsgivean example ofpower-upsequence supportedby theAM3517/05 . 1. IO 1.8Vsupply(VDDS),Band-gap and LDO supplies(VDDS_SRAM_CORE_BG, VDDS_SRAM_MPU) and oscillatorsupply(VDDSOSC) shouldcome up firsttoa stablestate. 2. IO 3.3V(VDDSHV) supplyshouldbe ramped up nexttoa stablestate. 3. Core (VDD_CORE) supplyfollowsnexttoa stablestate. 4. AllthePLL supplies(VDDS_DPLL_PER_CORE, VDDS_DPLL_MPU_USBHOST) and 1.8V complex IO supplies(VDDA_DAC, VDDA1P8V_USBPHY) shouldbe ramped up nexttoa stablestate. 5. Finally,3.3V complexIO (VDDA_3P3V_USBPHY) shouldbe ramped up. 6. sys_nrespwronmust be heldlowatthetimethepower suppliesareramped up tillthetimethe sys_32kand sys_xtalinclocksarestable. Note:InVDDSHV 1.8V operationmode, VDDSHV can be groupedand powered up togetherwithVDDS, VDDS_SRAM_CORE_BG, VDDS_SRAM_MPU and VDDSOSC.

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PRODUCT□PREVIEW VDDS, VDDS_SRAM_CORE_BG VDDS_SRAM_MPU VDDSOSC 1.8V VDDSHV 3.3V 1.2VVDD_CORE VDDS_DPLL_PER_CORE VDDS_DPLL_MPU_USBHOST , VDDA_DAC, VDDA1P8V_USBPHY 1.8V VDDA3P3V_USBPHY 3.3V sys_nrespwron sys_32k sys_xtalin AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Figure3-3shows thepower-upsequence. Figure3-3.Power-up Sequence Copyright© 2009–2010,Texas InstrumentsIncorporated ELECTRICAL CHARACTERISTICS 87 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

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3.5.2 Power-down Sequence

The AM3517/05 deviceproceedswiththepower-down sequence shown below. The followingsteps give an example of the power-down sequence supportedby the AM3517/05 device. 1. ResetAM3517/05 device. 2. StopallsignalsdriventoAM3517/05 . 3. Option1:Power down alldomains simutaneously. 4. Option2:Ifalldomains cannotbe powered down simultaneously,followthebelowsequence: (a) Power offallcomplexI/Odomains (b) Power offcoredomain (VDD_CORE) (c) Power offallPLL domains (VDDS_DPLL_MPU_USBHOST and VDDS_DPLL_PER_CORE) (d) Power offallSRAM LDOs (e) Power offallstandardI/Odomains (VDDS and VDDSHV)

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PRODUCT□PREVIEW AM35x Power ICsys_32k sys_altclk sys_clkout1 Alternate Clock Source Selectable (54, 48 MHz or other [up to 59 MHz]) To Quartz (Oscillator output) or Unconnected From Quartz (Oscillator input), Square Clock, or Crystal Clock Request. To Square Clock Source or from Peripherals Oscillator is Used Oscillator is Bypassed Unconnected Square Clock Source To Peripherals (From OSC_CLK: 26 MHz, core_clk [DPLL, up to 166 MHz], DPLL-96 MHZ or DPLL-54 MHz outputs with a divider of 1, 2, 4, 8, or 16) GPin To Peripherals (From OSC_CLK: 26 MHz) sys_clkout2 sys_xtalout sys_xtalin sys_clkreq sys_xtalout sys_xtalin sys_clkreq sys_xtalout sys_xtalin sys_clkreq 030-007 Ethernet input 50-MHz clockrmii_50mhz_clk AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010

4 CLOCK SPECIFICATIONS

The AM3517/05 devicehas threeexternalinputclocks,a low frequency(sys_32k),a high frequency (sys_xtalin),and an optional(sys_altclk).The AM3517/05 devicehas two configurableoutputclocks, sys_clkout1and sys_clkout2. Figure4-1shows theinterfacetotheexternalclocksourcesand clockoutputs. Figure4-1.Clock Interface The AM3517/05 deviceoperationrequiresthefollowingthreeinputclocks:

• The 32-kHzclockcan be generatedusingone ofthefollowingoptionsand can be selectedviathe sys_boot7pin.See Figure4-2. – External:Suppliedby an oscillatoron thesys_32kpin. – Internal:32-kHzclockgenerationusinga fixeddivideron theHS systemclock(26MHz).
• The systemalternativeclockcan be used (throughthesys_altclkpin)toprovidealternative48 or54 MHz orotherclocksource(upto54 MHz).
• The systemclockinput(26MHz) isused togeneratethemain sourceclockoftheAM3517/05 device. ItsuppliestheDPLLs as wellas severalAM3517/05 modules.The systemclockinputcan be connectedtoeither: – A crystaloscillatorclockmanaged by sys_xtalinand sys_xtalout.Inthiscase,thesys_clkreqis used as an input(GPIN). – A CMOS digitalclockthroughthesys_xtalinpin.Inthiscase,thesys_clkreqisused as an outputto requesttheexternalsystemclock. Copyright© 2009–2010,Texas InstrumentsIncorporated CLOCK SPECIFICATIONS 89 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW Sys_32k_in 32.5 kHz Fixed Divider /800 Latch Sys_clk=

26 MHz

Sys_clk PowerOn Reset Sys_32k Sys_xtalin Sys_xtalout Sys_boot7 AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Figure4-2.32-kHz Clock Generation The AM3517/05 outputsexternallytwo clocks:

• sys_clkout1can outputtheoscillatorclock(26MHz) atany time.
• sys_clkout2can outputtheoscillatorclock,core_clk,96 MHz or54 MHz. Itcan be dividedby 2,4,8, or16 and itsoffstatepolarityisprogrammable.

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PRODUCT□PREVIEW C1 C2 sys_xtalin sys_xtalout VSSOSC Crystal AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010

4.1 Oscillator

The sys_xtalin(26 MHz) oscillatorprovidesthe primaryreferenceclockforthe AM3517 device.The on-chiposcillatorrequiresan externalcrystalconnectedacrossthesys_xtalinand sys_xtaloutpins,along withtwo loadcapacitors,as shown inFigure4-3.The externalcrystalloadcapacitorsmust be connected onlytotheoscillatorgroundpin(VSSOSC). Do notconnecttoboardground(VSS). Note:Ifan externaloscillatoristobe used,theexternaloscillatorclocksignalshouldbe connectedtothe sys_xtalinpinwitha 1.8V amplitude.The sys_xtaloutshouldbe leftunconnectedand theVSSOSC signal shouldbe connectedtoboardground(VSS). Figure4-3.AM3517/05 OscillatorConnections The loadcapacitors,C1 and C2, shouldbe chosen such thattheequationissatisfied(typicalvaluesare C1 = C2 = 10 pF).CL in the equationisthe load specifiedby the crystalmanufacturer.Alldiscrete components used to implement the oscillatorcircuitshould be placed as close as possibleto the associatedoscillatorpins(sys_xtalinand sys_xtalout)and totheVSS pin. Table4-1.CrystalElectricalCharacteristics PARAMETER MIN TYP MAX UNIT Oscillationfrequency 26 MHz CrystalESR 50 Ω Frequencystability +/-50 ppm ParallelLoad Capacitance 20 pF (C1 and C2) ShuntCapacitance 5 pF

4.2 InputClock Specifications

The clocksystemacceptsthreeinputclocksources:

• 32-kHzdigitalCMOS clock
• CrystaloscillatorclockorCMOS digitalclock(26MHz)
• Alternateclock(48or54 MHz, orotherup to54 MHz) Table4-2.26Mhz sys_clkInputClock Timing Requirements PARAMETER DESCRIPTION MIN TYP MAX UNIT f(xtalin) Frequency,sys_xtalin 26 MHz tw(xtalin) DutyCycle, 45 55 % sys_xtalin Copyright© 2009–2010,Texas InstrumentsIncorporated CLOCK SPECIFICATIONS 91 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Table4-2.26Mhz sys_clkInputClock Timing Requirements (continued) PARAMETER DESCRIPTION MIN TYP MAX UNIT tj(xtalin) Jitter,sys_xtalin -1 1 % tt(xtalin) Transitiontime, 5 ns sys_xtalin Table4-3.32-kHz InputClock Source ElectricalCharacteristics PARAMET DESCRIPTION MIN TYP MAX UNIT ER f Frequency,sys_32k 32.768 kHz C i Inputcapacitance 0.45 pF R i Inputresistance 0.25 106 G Ω Table4-4detailstheinputrequirementsofthe32-kHzinputclock. Table4-4.32-kHz InputClock Source Timing Requirements(1) PARAMETE DESCRIPTION MIN TYP MAX UNIT R 1 /tc(32k) Frequency,sys_32k 32 kHz tR(32k) Risetransitiontime,sys_32k 20 ns tF(32k) Falltransitiontime,sys_32k 20 ns tJ(32k) Frequencystability,sys_32k +/-200 ppm (1) See ElectricalCharacteristicsforStandardLVCMOS IOs partforsys_32kVIH/VILparameters. Table4-5.48-MHz, 54-MHz, or up to59-MHz InputClock Source ElectricalCharacteristics NAME DESCRIPTION MIN MAX UNIT f Frequency,sys_altclk 48,54,orup to59 MHz C i Inputcapacitance 0.74 pF R i Inputresistance 0.25 106 G Ω Table4-6detailstheinputrequirementsofthe48-or54-MHz inputclock. Table4-6.48-MHz, 54-MHz, or up to59-MHz InputClock Source Timing Requirements(1)(2) PARAMETER DESCRIPTION MIN MAX UNIT 1 /tc(sys_altclk) Frequency,sys_altclk 48,54,orup to59 MHz tw(sys_altclk) Dutycycle 45 60 % tj(sys_altclk) Jitter -1 1 % tr(sys_altclk) Risetransitiontime 10 ns tf(sys_altclk) Falltransitiontime 10 ns ft(sys_altclk) Frequencytolerance -50 50 ppm (1) Peak-to-peakjitterisdefinedas thedifferencebetween themaximum and theminimum outputperiodson a statisticalpopulationof300 periodsamples.The sinusoidalnoiseisadded on topofthevdds supplyvoltage. (2) See ,ElectricalCharacteristics,forsys_altclkVIH/VILparameters.

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PRODUCT□PREVIEW sys_clkout1 CO0 CO1 CO1 030-014 AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010

4.3 Output Clock Specifications

Two outputclocks(pinsys_clkout1and pinsys_clkout2)areavailable:

• sys_clkout1can outputtheoscillatorclock(26MHz) atany time.Itcan be controlledby softwareor externallyusingsys_clkreqcontrol.When thedeviceisintheoffstate,thesys_clkreqcan be asserted toenabletheoscillatorand activatethesys_clkout1withoutwakingup thedevice.The offstatepolarity ofsys_clkout1isprogrammable.
• sys_clkout2can outputsys_clk(26MHz), core_clk(coreDPLL output),APLL-96 MHz, orAPLL-54 MHz. Itcan be dividedby 2,4,8,or16 and itsoffstatepolarityisprogrammable.Thisoutputisactive onlywhen thecoredomain isactive. Table4-7summarizesthesys_clkout1outputclockelectricalcharacteristics. Table4-7.sys_clkout1Output Clock ElectricalCharacteristics NAME DESCRIPTION MIN TYP MAX UNIT f Frequency 26 MHz C I Load capacitance(1) f(max)= 38.4MHz 70 pF f(max)= 26 MHz 125 (1) The loadcapacitanceisadaptedtoa frequency. Table4-8detailsthesys_clkout1outputclocktimingcharacteristics. Table4-8.sys_clkout1Output Clock SwitchingCharacteristics NAME DESCRIPTION MIN TYP MAX UNIT f 1 /CO0 Frequency 26 MHz CO1 tw(CLKOUT1) Pulseduration,sys_clkout1loworhigh 0.40* 0.60* ns tc(CLKOUT1) tc(CLKOUT1) CO2 tR(CLKOUT1) Risetime,sys_clkout1(1) 3.31 ns CO3 tF(CLKOUT1) Falltime,sys_clkout1(1) 3.31 ns (1) Witha loadcapacitanceof25 pF. Figure4-4.sys_clkout1System Output Clock Table4-9summarizesthesys_clkout2outputclockelectricalcharacteristics. Table4-9.sys_clkout2Output Clock ElectricalCharacteristics NAME DESCRIPTION MIN TYP MAX UNIT f Frequency,sys_clkout2(1) 166 MHz C L Load capacitance(2) f(max)= 166 MHz 2 8 12 pF (1) The maximum frequencysupportediscore_clk/2MHz. (2) The loadcapacitanceisadaptedtoa frequency. Copyright© 2009–2010,Texas InstrumentsIncorporated CLOCK SPECIFICATIONS 93 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW sys_clkout2 CO0 CO1 CO1 030-015 AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Table4-10detailsthesys_clkout2outputclocktimingcharacteristics. Table4-10.sys_clkout2Output Clock SwitchingCharacteristics NAME DESCRIPTION MIN TYP MAX UNIT f 1 /CO0 Frequency 166 MHz CO1 tw(CLKOUT2) Pulseduration,sys_clkout2loworhigh 0.40*tc(CLKOUT2) 0.60*tc(CLKOUT2) ns CO2 tR(CLKOUT2) Risetime,sys_clkout2(1) 3.7 ns CO3 tF(CLKOUT2) Falltime,sys_clkout2(1) 4.3 ns (1) Witha loadcapacitanceof25 pF. Figure4-5.sys_clkout2System Output Clock

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PRODUCT□PREVIEW Device VDDS_DPLL_MPU_USBHOST Power Rail DPLL4 DPLL1 DPLL3 VDDS_DPLL_PER_CORE DPLL5 030-016 AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010

4.4 DPLL Specifications

The AM3517/05 integratesfourDPLLs. The PRM and CM drivethem. The fourmain DPLLs are:

• DPLL1 (MPU)
• DPLL3 (Core)
• DPLL4 (Peripherals)
• DPLL5 (SecondPeripheralsDPLL) Figure4-6illustratestheDPLL implementation. Figure4-6.DPLL Implementation

4.4.1 DigitalPhase-Locked Loop (DPLL)

The DPLL providesallinterfaceclocksand some functionalclocks(suchas theprocessorclocks)ofthe AM3517/05 device. DPLL1 getsan always-onclockused to produce the synthesizedclock.They get a high-speedbypass clockused toswitchtheDPLL outputclockon thishigh-speedclockduringbypassmode. The high-speedbypass clockisan L3 dividedclock(programmableby 1 or2)thatsaves DPLL processor power consumptionwhen theprocessordoes notneed torunfasterthantheL3 clockspeed,oroptimizes performanceduringfrequencyscaling. Each DPLL synthesizedfrequencyissetby programmingM (multiplier)and N (divider)factors.Inaddition, allDPLL outputscan be controlledby an independentdivider(M2 toM6). The clockgeneratingDPLLs oftheAM3517/05 devicehave followingfeatures:

• Independentpower domain perDPLL
• Controlledby clock-manager(CM)
• Fed withalways-onsystemclockwithindependentgatingcontrolperDPLL
• Analogpartsuppliedthroughdedicatedpower supply(1.8V) and an embedded LDO togetridof 1-MHz noise
• Up tofourindependentoutputdividersforsimultaneousgenerationofmultipleclockfrequencies Copyright© 2009–2010,Texas InstrumentsIncorporated CLOCK SPECIFICATIONS 95 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

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4.4.1.1 DPLL1 (MPU)

DPLL1 islocatedinthe MPU subsystem and suppliesallclocksof the subsystem.AllMPU subsystem clocksare internallygeneratedinthe subsystem.When the core domain ison, itcan use the DPLL3 (CORE DPLL) outputas a high-frequencybypassinputclock.

4.4.1.2 DPLL3 (CORE)

DPLL3 suppliesallinterfaceclocksand alsoa few module functionalclocks.Itcan be alsosourceofthe emulationtraceclock.Itis locatedin the core domain area.Allinterfaceclocksand a few module functionalclocksaregeneratedintheCM. When thecoredomain ison,itcan be used as a bypass input toDPLL1.

4.4.1.3 DPLL4 (Peripherals)

DPLL4 generatesclocksforthe peripherals.Itsuppliesfiveclocksources:96-MHz functionalclocksto subsystems and peripherals, 54 MHz to TV DAC, displayfunctionalclock,camera sensorclock,and emulationtraceclock.Itislocatedinthecoredomain area.Allinterfaceclocksand few module functional clocksare generatedinthe CM. Itsoutputsto the DSS, PER, and EMU domains are propagatedwith always-onclocktrees.

4.4.1.4 DPLL5 (Second peripheralsDPLL)

DPLL5 suppliesthe120-MHz functionalclocktotheCM.

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PRODUCT□PREVIEW DPLL_MPU DPLL_CORE DLL DPLL5 DPLL4 VDDS_DPLL_MPU_USBHOST VDDS_DPLL_PER_CORE C Noise Filter C Noise Filter 030-017 AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010

4.4.2 DPLL Noise Isolation

The DPLL requiresdedicatedpower supplypinstoisolatethecoreanalogcircuitfromtheswitchingnoise generatedby thecorelogicthatcan cause jitteron theclockoutputsignal.Guard ringsareadded tothe celltoisolateitfromsubstratenoiseinjection. The vdd suppliesare the most sensitiveto noise;decouplingcapacitanceisrecommended below the supplyrails.The maximum inputnoiselevelallowedis30 mV PP forfrequenciesbelow1 MHz. Figure4-7illustratesan example ofa noisefilter. Figure4-7.DPLL Noise Filter Table4-11specifiesthenoisefilterrequirements. Table4-11.DPLL Noise FilterRequirements NAME MIN TYP MAX UNIT Filteringcapacitor 100 nF (1) The capacitorsmust be insertedbetween power and groundas closeas possible. (2) Thiscircuitisprovidedonlyas an example. (3) The filtermust be locatedas closeas possibletothedevice. (4) No filteringrequiredifnoiseisbelow10 mV PP . Copyright© 2009–2010,Texas InstrumentsIncorporated CLOCK SPECIFICATIONS 97 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW Device DSS tv_vref DIN1[9:0] vssa_dacvdda_dac Video DAC 1 TV DCT Video DAC 2 TVOUT BUFFER DIN2[9:0] TVOUT BUFFER TVOUT BUFFER tv_vfb1 tv_out1 CBG tv_out2 tv_vfb2 V_ref 030-018 R OUT1 R OUT2 AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com

5 VIDEO DAC SPECIFICATIONS

A dual-displayinterfaceequipstheAM3517/05 processor.Thisdisplaysubsystemprovidesthenecessary controlsignalstointerfacethememory frame bufferdirectlytotheexternaldisplays(TV-set).Two (one perchannel)10-bitcurrentsteeringDACs areinsertedbetween theDSS and theTV settogeneratethe videoanalogsignal.One ofthevideoDACs alsoincludesTV detectionand power-down mode. Figure5-1 illustratestheAM3517/05 DAC architecture. Figure5-1.Video DAC Architecture The followingparagraphsdetailthe 10-bitDAC interfacepinout,staticand dynamic specifications,and noiserequirements.The operatingconditionsand absolutemaximum ratingsaredetailedinTable5-2and Table5-4.

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5.1 InterfaceDescription

Table5-1summarizestheexternalpinsofthevideoDAC. Table5-1.ExternalPins of10-bitVideo DAC PIN NAME I/O DESCRIPTION tv_out1 O TV analogoutputcomposite DAC1 videooutput.An externalresistorisconnectedbetween this node and tv_vfb1.The nominalvalueofROUT1 is1650 .Finally,note thatthisistheoutputnode thatdrivestheload(75). tv_out2 O TV analogoutputS-VIDEO DAC2 videooutput.An externalresistorisconnectedbetween this node and tv_vfb2.The nominalvalueofROUT2 is1650 .Finally,note thatthisistheoutputnode thatdrivestheload(75). tv_vref I Referenceoutputvoltagefrominternal A decouplingcapacitor(CBG) needs tobe connectedforoptimum bandgap performance. tv_vfb1 O Amplifierfeedbacknode Amplifierfeedbacknode.An externalresistorisconnectedbetween thisnode and tv_out1.The nominalvalueofROUT1 is1650 (1%). tv_vfb2 O Amplifierfeedbacknode Amplifierfeedbacknode.An externalresistorisconnectedbetween thisnode and tv_out2.The nominalvalueofROUT2 is1650 (1%). Copyright© 2009–2010,Texas InstrumentsIncorporated VIDEO DAC SPECIFICATIONS 99 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

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5.2 ElectricalSpecificationsOver Recommended OperatingConditions

(TMIN toTMAX ,vdda_dac = 1.8V,R OUT1/2 = 1650 ,R LOAD = 75 ,unlessotherwisenoted) Table5-2.DAC StaticElectricalSpecification PARAMETER CONDITIONS/ASSUMPTIONS MIN TYP MAX UNIT R Resolution 10 Bits DC ACCURACY INL(1) Integralnonlinearity 1 1 LSB DNL (2) Differentialnonlinearity 1 1 LSB ANALOG OUTPUT - Full-scaleoutputvoltage R LOAD = 75Ω 0,7 0.88 1 V - Outputoffsetvoltage 50 mV - Outputoffsetvoltagedrift 20 mV/C - Gain error 17 19 % FS R VOUT Outputimpedance 67.5 75 82.5 REFERENCE VREF Referencevoltagerange 0.525 0.55 0.575 V - Referencenoisedensity 100-kHzreferencenoise 129 bandwidth R SET Full-scalecurrentadjustresistor 3700 4000 4200 PSRR ReferencePSRR (3)(Up to6 MHz) 40 dB POWER CONSUMPTION Ivdda-up AnalogSupplyCurrent(4) 2 channels,no load 8 mA - Analogsupplydrivinga 75-load 2 channels 50 mA (RMS) Ivdda-up(peak) Peak analogsupplycurrent: Lastslessthan1 ns 60 mA Ivdd-up Digitalsupplycurrent(5) Measured atfCLK = 54 MHz, fOUT 2 mA = 2 MHz sinewave,vdd = 1.3V Ivdd-up(peak) Peak digitalsupplycurrent(6) Lastslessthan1 ns 2.5 mA Ivdda-down Analogpower atpower-down T = 30C, vdda = 1.8V 1.5 mA Ivdd-down Digitalpower atpower-down T = 30C, vdd = 1.3V 1 mA (1) The INL ismeasured attheoutputoftheDAC (accessibleatan externalpinduringbypassmode). (2) The DNL ismeasured attheoutputoftheDAC (accessibleatan externalpinduringbypassmode). (3) Assuming a capacitorof0.1F atthetv_refnode. (4) The analogsupplycurrentIvdda isdirectlyproportionaltothefull-scaleoutputcurrentIFS and isinsensitivetofCLK (5) The digitalsupplycurrentIVDD isdependenton thedigitalinputwaveform,theDAC updateratefCLK ,and thedigitalsupplyVDD. (6) The peak digitalsupplycurrentoccursatfull-scaletransitionfordurationlessthan1 ns.

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PRODUCT□PREVIEW AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 (TMIN toTMAX ,vdda_dac = 1.8V,R OUT1/2 = 1650 ,R LOAD = 75 ,unlessotherwisenoted) Table5-3.Video DAC Dynamic ElectricalSpecification PARAMETER CONDITIONS/ASSUMPTIONS MIN TYP MAX UNIT fCLK (1) Outputupdaterate Equaltoinputclockfrequency 54 MHz Clockjitter rms clockjitterrequiredinordertoassure 40 ps 10-bitaccuracy Attenuationat5.1MHz Cornerfrequencyforsignal 0.1 0.5 1.5 dB Attenuationat54 MHz (1) Image frequency 25 30 33 dB tST Outputsettlingtime Time fromthestartoftheoutputtransitionto 85 ns outputwithin1 LSB offinalvalue. tRout Outputrisetime Measured from10% to90% offull-scale 25 ns transition tFout Outputfalltime Measured from10% to90% offull-scale 25 ns transition BW Signalbandwidth 6 MHz Differentialgain(2) 1.5% Differentialphase(2) 1 deg. SFDR Withinbandwidth fCLK = 54 MHz, fOUT = 1 MHz 45 dB SNR Signal-to-noiseratio fCLK = 54 MHz, fOUT = 1 MHz 55(3) dB 1 kHz to6 MHz bandwidth PSRR Power supplyrejectionratio Up to6 MHz 20(4) dB Crosstalk Between thetwo video 50 40 dB channels (1) Forinternalinputclockinformation,Formore information,see theDeviceDisplayInterfaceSubsystem ReferenceGuide [literature number SPRUFV2 ]. (2) The differentialgainand phase valueisfordc coupling.Note thatthereisdegradationfortheac coupling. (3) The SNR valueisfordc coupling.Note thatthereisa 6-dB degradationforac coupling. (4) The PSSR valueisfordc coupling.Note thatthereisa 10-dB degradationforac coupling. Copyright© 2009–2010,Texas InstrumentsIncorporated VIDEO DAC SPECIFICATIONS 101 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW AC OUTFS OUT DAC V I I PSRR /c68/c215 /c61 100 %□□FSR V 100□kHz 1□MHz PSRR□(%□FSR/V) f First□pole□of DAC□output□load 030-019 AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com

5.3 Analog Supply (vdda_dac)Noise Requirements

Inordertoassure10-bitaccuracyoftheDAC analogoutput,theanalogsupplyvdda_dac has tomeet the noiserequirementsstatedinthissection. The DAC Power SupplyRejectionRatioisdefinedas therelativevariationofthefull-scaleoutputcurrent dividedby thesupplyvariation.Thus,itisexpressedinpercentageofFull-ScaleRange (FSR) pervoltof supplyvariationas shown inthefollowingequation: Dependingon frequency,thePSRR isdefinedinTable5-4. Table5-4.Video DAC Power Supply RejectionRatio Supply Noise Frequency PSRR % FSR/V 0 to100 kHz 1 > 100 kHz The rejectiondecreases20 dB/dec. Example:at1 MHz thePSRR is10% ofFSR/V A graphicrepresentationisshown inFigure5-2. Figure5-2.Video DAC Power Supply RejectionRatio To ensure thatthe DAC SFDR specificationismet, the PSRR valuesand the clockjitterrequirements translatetothefollowinglimitson vdda_dac (fortheVideoDAC). The maximum peak-to-peaknoiseon vdda (ripple)isdefinedinTable5-5: Table5-5.Video DAC Maximum Peak-to-PeakNoise on vdda_dac Tone Frequency Maximum Peak-to-PeakNoise on vdda_dac 0 to100 kHz < 30 mVpp > 100 kHz Decreases20 dB/dec. Example:at1 MHz themaximum is3 mVpp The maximum noisespectraldensity(whitenoise)isdefinedinTable5-6: Table5-6.Video DAC Maximum Noise SpectralDensity Supply Noise Bandwidth Maximum Supply Noise Density 0 to100 kHz < 20 V /Hz > 100 kHz Decreases20 dB/dec. Example:at1 MHz themaximum noisedensityis2 /Hz

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PRODUCT□PREVIEW AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Because theDAC PSRR deterioratesata rateof20 dB/dec after100 kHz, itishighlyrecommended to have vdda_dac low pass filtered(properdecoupling)(seetheillustratedapplication:Section5.4,External Component ValueChoice).

5.4 ExternalComponent Value Choice

The full-scaleoutputvoltageVOUTMAX isregulatedby the referenceamplifier,and issetby an internal resistorR SET .IOUTMAX can be expressedas: IOUTMAX = IREF /8*(63+ 15/16) (2) Where: VREF = 0.5V (3) IREF = VREF /RSET (4) The outputcurrentIOUT appearingatDAC outputisa functionofboththeinputcode and IOUTMAX and can be expressedas: IOUT = (DAC_CODE/1023) *IOUTMAX (5) Where: DAC_CODE = 0 to1023 istheDAC inputcode indecimal. (6) The outputvoltageis: VOUT = IOUT *N*R CABLE (7) Where: (N = amplifiergain= 21) (8) R CABLE Ω (cabletypicalimpedance) (9) The TV-outbufferrequiresa per channelexternalresistors:R OUT1/2 .The equationbelow can be used to selectdifferentresistorvalues(ifnecessary): R OUT = (N+1)R CABLE = 1650Ω (10) Recommended parametervaluesare: Table5-7.Video DAC Recommended ExternalComponents Values Recommended Value UNIT C BG 100 nF R OUT1/2 1650 Ω In orderto limitthe referencenoisebandwidthand to suppresstransientson VREF , itisnecessaryto connecta largedecouplingcapacitor© BG )between thetv_vrefand vssa_dacpins. Copyright© 2009–2010,Texas InstrumentsIncorporated VIDEO DAC SPECIFICATIONS 103 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW Cycle□(or□Period)□Jitter Tn-1 Tn Tn+1 Max.□Cycle□Jitter□=□Max□(T )i Min.□Cycle□Jitter□=□Min□(T )i Jitter□Standard□Deviation□(or□rms□Jitter)□=□Standard□Deviation□(T )i 030-020 AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com

6 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS

Note:The timingdatashown ispreliminarydataand issubjecttochange infuturerevisions.

6.1 Timing TestConditions

Alltimingrequirementsand switchingcharacteristicsarevalidovertherecommended operatingconditions ofTable3-3,unlessotherwisespecified.

6.2 InterfaceClock Specifications

6.2.1 InterfaceClock Terminology

The Interfaceclockisused atthesystem leveltosequence thedataand/orcontroltransfersaccordingly withtheinterfaceprotocol.

6.2.2 InterfaceClock Frequency

The two interfaceclockcharacteristicsare:

• The maximum clockfrequency
• The maximum operatingfrequency The interfaceclockfrequencydocumented in thisdocument is the maximum clockfrequency,which correspondsto the maximum frequencyprogrammable on thisoutputclock.Thisfrequencydefinesthe maximum limitsupportedby theAM3517/05 IC and doesn'ttakeintoaccountany system consideration (PCB, peripherals). The system designerwillhave to considerthese system considerationsand AM3517/05 IC timings characteristicsas well,to defineproperlythe maximum operatingfrequency,which correspondsto the maximum frequencysupportedtotransferthedataon thisinterface.

6.2.3 Clock JitterSpecifications

Jitterisa phase noise,whichmay alterdifferentcharacteristicsofa clocksignal.The jitterspecifiedinthis document isthetimedifferencebetween thetypicalcycleperiodand theactualcycleperiodaffectedby noisesourceson theclock.The cycle(orperiod)jitterterminologyidentifiesthistypeofjitter. Figure6-1.Cycle (orPeriod)Jitter

6.2.4 Clock Duty Cycle Error

The maximum dutycycleerroristhe differencebetween the absolutevalueof the maximum high-level pulsedurationorthemaximum low-levelpulsedurationand thetypicalpulsedurationvalue:

• Maximum pulseduration= typicalpulseduration+ maximum dutycycleerror

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• Minimum pulseduration= typicalpulseduration-maximum dutycycleerror

6.3 Timing Parameters

The timingparametersymbols used in the timingrequirementand switchingcharacteristictablesare createdinaccordancewithJEDEC Standard100. To shortenthe symbols,some pinnames and other relatedterminologieshave been abbreviatedas follows: Table6-1.Timing Parameters LOWERCASE SUBSCRIPTS Symbols Parameter c Cycletime(period) d Delaytime dis Disabletime en Enabletime h Holdtime su Setuptime START Startbit t Transitiontime v Validtime w Pulseduration(width) X Unknown, changing,ordontcarelevel H High L Low V Valid IV Invalid AE ActiveEdge FE FirstEdge LE LastEdge Z Highimpedance Copyright© 2009–2010,Texas InstrumentsIncorporated TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 105 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

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6.4 ExternalMemory Interfaces

The AM3517/05 processorincludesthefollowingexternalmemory interfaces:

• General-purposememory controller(GPMC)
• SDRAM controller(SDRC)

6.4.1 General-PurposeMemory Controller(GPMC)

The GPMC istheAM3517/05 unifiedmemory controllerused tointerfaceexternalmemory devicessuch as:

• AsynchronousSRAM-likememories and ASIC devices
• Asynchronouspage mode and synchronousburstNOR flash
• NAND flash

6.4.1.1 GPMC/NOR FlashInterfaceSynchronous Timing

The followingtablesassume testingover the recommended operatingconditionsand electrical characteristicconditions. Table6-2.GPMC/NOR FlashSynchronous Mode Timing Conditions TIMING CONDITION PARAMETER 1.8V,3.3V UNIT MIN MAX InputConditions tR Inputsignalrisetime 0.3 1.8 ns tF Inputsignalfalltime 0.3 1.8 ns Output Conditions C LOAD Outputloadcapacitance 30 pF Table6-3.GPMC/NOR FlashInterfaceTiming Requirements Synchronous Mode NO. PARAMETER 1.8V,3.3V UNIT MIN MAX F12 tsu(DV-CLKH) Setuptime,readgpmc_d[15:0]validbefore 2.021 ns gpmc_clkhigh F13 th(CLKH-DV) Holdtime,gpmc_d[15:0]validaftergpmc_clkhigh 3.403 ns F21 tsu(WAITV-CLKH) Setuptime,gpmc_waitx(1)validbeforegpmc_clk 3.782 ns high F22 th(CLKH-WAITV) HoldTime,gpmc_waitx(1)validaftergpmc_clk 3.343 ns high (1) Waitmonitoringsupportislimitedtoa WaitMonitoringTimevalue> 0. Table6-4.GPMC/NOR FlashInterfaceSwitchingCharacteristicsSynchronous Mode NO. PARAMETER 1.8V,3.3V UNIT MIN MAX F0 tc(CLK) Cycletime(1),outputclockgpmc_clk 10 ns period F1 tw(CLKH) Typicalpulseduration,outputclock 0.5P (2) 0.5P (2) ns gpmc_clkhigh F1 tw(CLKL) Typicalpulseduration,outputclock 0.5P (2) 0.5P (2) ns gpmc_clklow tdc(CLK) Dutycycleerror,outputclkgpmc_clk -500 500 ps (1) Relatedtothegpmc_clkoutputclockmaximum and minimum frequenciesprogrammableintheI/Fmodule by settingthe GPMC_CONFIG1_CSx configurationregisterbitfieldGpmcFCLKDivider. (2) P = gpmc_clkperiod

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PRODUCT□PREVIEW AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Table6-4.GPMC/NOR FlashInterfaceSwitchingCharacteristicsSynchronous Mode (continued) NO. PARAMETER 1.8V,3.3V UNIT MIN MAX tj(CLK) Jitterstandarddeviation(3),outputclock 33.30 ps gpmc_clk tR(CLK) Risetime,outputclockgpmc_clk 1.6 ns tF(CLK) Falltime,outputclockgpmc_clk 1.6 ns tR(DO) Risetime,outputdata 2 ns tF(DO) Falltime,outputdata 2 ns F2 td(CLKH-nCSV) Delaytime,gpmc_clkrisingedge to F (5)-1.9 F(5)+ 3.3 ns gpmc_ncsx (4)transition F3 td(CLKH-nCSIV) Delaytime,gpmc_clkrisingedge to E (6)-1.9 E (6)+ 3.3 ns gpmc_ncsx(4)invalid F4 td(ADDV-CLK) Delaytime,addressbus validto B (7)-4.1 B (7)+ 2.1 ns gpmc_clkfirstedge F5 td(CLKH-ADDIV) Delaytime,gpmc_clkrisingedge to -2.103 ns gpmc_a[16:1]invalid F6 td(nBEV-CLK) Delaytime,gpmc_nbe0_cle,gpmc_nbe1 B (7)-1.37 B (7)+ 2.1 ns validtogpmc_clkfirstedge F7 td(CLKH-nBEIV) Delaytime,gpmc_clkrisingedge to D (8)-2.1 D (8)+ 1.1 ns gpmc_nbe0_cle,gpmc_nbe1 invalid (3) The jitterprobabilitydensitycan be approximatedby a Gaussianfunction. (4) Ingpmc_ncsx,x isequalto0,1,2,3,4,5,6,or7.Ingpmc_waitx,x isequalto0,1,2,or3. (5) For nCS fallingedge (CS activated):

• Case GpmcFCLKDivider = 0:
• F = 0.5*CSExtraDelay*GPMC_FCLK
• Case GpmcFCLKDivider = 1:
• F = 0.5*CSExtraDelay*GPMC_FCLK if(ClkActivationTimeand CSOnTime areodd)or(ClkActivationTimeand CSOnTime are even)
• F = (1+ 0.5*CSExtraDelay)*GPMC_FCLK otherwise
• Case GpmcFCLKDivider = 2:
• F = 0.5*CSExtraDelay*GPMC_FCLK if((CSOnTime ClkActivationTime)isa multipleof3)
• F = (1+ 0.5*CSExtraDelay)*GPMC_FCLK if((CSOnTime ClkActivationTime1)isa multipleof3)
• F = (2+ 0.5*CSExtraDelay)*GPMC_FCLK if((CSOnTime ClkActivationTime2)isa multipleof3) (6) For singleread:E = (CSRdOffTime AccessTime)*(TimeParaGranularity+ 1)*GPMC_FCLK For burstread:E = (CSRdOffTime AccessTime)*(TimeParaGranularity+ 1)*GPMC_FCLK For burstwrite:E = (CSWrOffTime AccessTime)*(TimeParaGranularity+ 1)*GPMC_FCLK (7) B = ClkActivationTime*GPMC_FCLK (8) For singleread:D = (RdCycleTimeAccessTime)*(TimeParaGranularity+ 1)*GPMC_FCLK For burstread:D = (RdCycleTimeAccessTime)*(TimeParaGranularity+ 1)*GPMC_FCLK For burstwrite:D = (WrCycleTimeAccessTime)*(TimeParaGranularity+ 1)*GPMC_FCLK Copyright© 2009–2010,Texas InstrumentsIncorporated TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 107 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Table6-4.GPMC/NOR FlashInterfaceSwitchingCharacteristicsSynchronous Mode (continued) NO. PARAMETER 1.8V,3.3V UNIT MIN MAX F8 td(CLKH-nADV) Delaytime,gpmc_clkrisingedge to G (9)-1.9 G (9)+ 4.1 ns gpmc_nadv_aletransition F9 td(CLKH-nADVIV) Delaytime,gpmc_clkrisingedge to D (10)-1.9 D (10)+ 4.1 ns gpmc_nadv_aleinvalid (9) For ADV fallingedge (ADV activated):

• Case GpmcFCLKDivider = 0:
• G = 0.5*ADVExtraDelay*GPMC_FCLK
• Case GpmcFCLKDivider = 1:
• G = 0.5*ADVExtraDelay*GPMC_FCLK if(ClkActivationTimeand ADVOnTime areodd)or(ClkActivationTimeand ADVOnTime areeven)
• G = (1+ 0.5*ADVExtraDelay)*GPMC_FCLK otherwise
• Case GpmcFCLKDivider = 2:
• G = 0.5*ADVExtraDelay*GPMC_FCLK if((ADVOnTime ClkActivationTime)isa multipleof3)
• G = (1+ 0.5*ADVExtraDelay)*GPMC_FCLK if((ADVOnTime ClkActivationTime1)isa multipleof3)
• G = (2+ 0.5*ADVExtraDelay)*GPMC_FCLK if((ADVOnTime ClkActivationTime2)isa multipleof3) For ADV risingedge (ADV deactivated)inReading mode:
• Case GpmcFCLKDivider = 0:
• G = 0.5*ADVExtraDelay*GPMC_FCLK
• Case GpmcFCLKDivider = 1:
• G = 0.5*ADVExtraDelay*GPMC_FCLK if(ClkActivationTimeand ADVRdOffTime areodd)or(ClkActivationTimeand ADVRdOffTime areeven)
• G = (1+ 0.5*ADVExtraDelay)*GPMC_FCLK otherwise
• Case GpmcFCLKDivider = 2:
• G = 0.5*ADVExtraDelay*GPMC_FCLK if((ADVRdOffTimeClkActivationTime)isa multipleof3)
• G = (1+ 0.5*ADVExtraDelay)*GPMC_FCLK if((ADVRdOffTimeClkActivationTime1)isa multipleof3)
• G = (2+ 0.5*ADVExtraDelay)*GPMC_FCLK if((ADVRdOffTimeClkActivationTime2)isa multipleof3) For ADV risingedge (ADV deactivated)inWritingmode:
• Case GpmcFCLKDivider = 0:
• G = 0.5*ADVExtraDelay*GPMC_FCLK
• Case GpmcFCLKDivider = 1:
• G = 0.5*ADVExtraDelay*GPMC_FCLK if(ClkActivationTimeand ADVWrOffTime areodd)or(ClkActivationTimeand ADVWrOffTime areeven)
• G = (1+ 0.5*ADVExtraDelay)*GPMC_FCLK otherwise
• Case GpmcFCLKDivider = 2:
• G = 0.5*ADVExtraDelay*GPMC_FCLK if((ADVWrOffTimeClkActivationTime)isa multipleof3)
• G = (1+ 0.5*ADVExtraDelay)*GPMC_FCLK if((ADVWrOffTimeClkActivationTime1)isa multipleof3)
• G = (2+ 0.5*ADVExtraDelay)*GPMC_FCLK if((ADVWrOffTimeClkActivationTime2)isa multipleof3) (10) For singleread:D = (RdCycleTimeAccessTime)*(TimeParaGranularity+ 1)*GPMC_FCLK For burstread:D = (RdCycleTimeAccessTime)*(TimeParaGranularity+ 1)*GPMC_FCLK For burstwrite:D = (WrCycleTimeAccessTime)*(TimeParaGranularity+ 1)*GPMC_FCLK

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PRODUCT□PREVIEW AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Table6-4.GPMC/NOR FlashInterfaceSwitchingCharacteristicsSynchronous Mode (continued) NO. PARAMETER 1.8V,3.3V UNIT MIN MAX F10 td(CLKH-nOE) Delaytime,gpmc_clkrisingedge to H (11)-2.1 H (11)+ 2.1 ns gpmc_noe transition F11 td(CLKH-nOEIV) Delaytime,gpcm risingedge to E (12)-2.1 E (12)+ 2.1 ns gpmc_noe invalid F14 td(CLKH-nWE) Delaytime,gpmc_clkrisingedge to I(13)-1.9 I(13)+ 4.1 ns gpmc_nwe transition F15 td(CLKH-Data) Delaytime,gpmc_clkrisingedge todata J(14)-2.1 J(14)+ 1.1 ns bus transition F17 td(CLKH-nBE) Delaytime,gpmc_clkrisingedge to J(14)-2.1 J(14)+ 1.1 ns gpmc_nbex_cletransition (11) For OE fallingedge (OE activated)/IO DIR risingedge (DataBus inputdirection):

• Case GpmcFCLKDivider = 0:
• H = 0.5*OEExtraDelay*GPMC_FCLK
• Case GpmcFCLKDivider = 1:
• H = 0.5*OEExtraDelay*GPMC_FCLK if(ClkActivationTimeand OEOnTime areodd)or(ClkActivationTimeand OEOnTime are even)
• H = (1+ 0.5*OEExtraDelay)*GPMC_FCLK otherwise
• Case GpmcFCLKDivider = 2:
• H = 0.5*OEExtraDelay*GPMC_FCLK if((OEOnTime ClkActivationTime)isa multipleof3)
• H = (1+ 0.5*OEExtraDelay)*GPMC_FCLK if((OEOnTime ClkActivationTime1)isa multipleof3)
• H = (2+ 0.5*OEExtraDelay)*GPMC_FCLK if((OEOnTime ClkActivationTime2)isa multipleof3) For OE risingedge (OE deactivated):
• GpmcFCLKDivider = 0:
• H = 0.5*OEExtraDelay*GPMC_FCLK
• Case GpmcFCLKDivider = 1:
• H = 0.5*OEExtraDelay*GPMC_FC if(ClkActivationTimeand OEOffTime areodd)or(ClkActivationTimeand OEOffTime are even)
• H = (1+ 0.5*OEExtraDelay)*GPMC_FCLK otherwise
• Case GpmcFCLKDivider = 2:
• H = 0.5*OEExtraDelay*GPMC_FCLK if((OEOffTimeClkActivationTime)isa multipleof3)
• H = (1+ 0.5*OEExtraDelay)*GPMC_FCLK if((OEOffTimeClkActivationTime1)isa multipleof3)
• H = (2+ 0.5*OEExtraDelay)*GPMC_FCLK if((OEOffTimeClkActivationTime2)isa multipleof3) (12) For singleread:E = (CSRdOffTime AccessTime)*(TimeParaGranularity+ 1)*GPMC_FCLK For burstread:E = (CSRdOffTime AccessTime)*(TimeParaGranularity+ 1)*GPMC_FCLK For burstwrite:E = (CSWrOffTime AccessTime)*(TimeParaGranularity+ 1)*GPMC_FCLK (13) For WE fallingedge (WE activated):
• Case GpmcFCLKDivider = 0:
• I= 0.5*WEExtraDelay*GPMC_FCLK
• Case GpmcFCLKDivider = 1:
• I= 0.5*WEExtraDelay*GPMC_FCLK if(ClkActivationTimeand WEOnTime areodd)or(ClkActivationTimeand WEOnTime are even)
• I= (1+ 0.5*WEExtraDelay)*GPMC_FCLK otherwise
• Case GpmcFCLKDivider = 2:
• I= 0.5*WEExtraDelay*GPMC_FCLK if((WEOnTime ClkActivationTime)isa multipleof3)
• I= (1+ 0.5*WEExtraDelay)*GPMC_FCLK if((WEOnTime ClkActivationTime1)isa multipleof3)
• I= (2+ 0.5*WEExtraDelay)*GPMC_FCLK if((WEOnTime ClkActivationTime2)isa multipleof3) For WE risingedge (WE deactivated):
• Case GpmcFCLKDivider = 0:
• I= 0.5*WEExtraDelay*GPMC_FCLK
• Case GpmcFCLKDivider = 1:
• I= 0.5*WEExtraDelay*GPMC_FCLK if(ClkActivationTimeand WEOffTime areodd)or(ClkActivationTimeand WEOffTime are even)
• I= (1+ 0.5*WEExtraDelay)*GPMC_FCLK otherwise
• Case GpmcFCLKDivider = 2:
• I= 0.5*WEExtraDelay*GPMC_FCLK if((WEOffTimeClkActivationTime)isa multipleof3)
• I= (1+ 0.5*WEExtraDelay)*GPMC_FCLK if((WEOffTimeClkActivationTime1)isa multipleof3)
• I= (2+ 0.5*WEExtraDelay)*GPMC_FCLK if((WEOffTimeClkActivationTime2)isa multipleof3) (14)J = GPMC_FCLK period Copyright© 2009–2010,Texas InstrumentsIncorporated TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 109 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Table6-4.GPMC/NOR FlashInterfaceSwitchingCharacteristicsSynchronous Mode (continued) NO. PARAMETER 1.8V,3.3V UNIT MIN MAX F18 tW(nCSV) Pulseduration, Read A (16) ns gpmc_ncsx (15)low Write A (16) ns F19 tW(nBEV) Pulseduration, Read C (17) ns gpmc_nbe0_cle, Write C (17) nsgpmc_nbe1 low F20 tW(nADVV) Pulseduration, Read K (18) ns gpmc_nadv_alelow Write K (18) ns F23 td(CLKH-IODIR) Delaytime,gpmc_clkrisingedge to H (11)-2.1 H (11)+ 4.1 ns gpmc_io_dirhigh(INdirection) F24 td(CLKH-IODIRIV) Delaytime,gpmc_clkrisingedge to M (19)-2.1 M (19)+ 4.1 ns gpmc_io_dirlow(OUT direction) (15)Ingpmc_ncsx,x isequalto0,1,2,3,4,5,6,or7.Ingpmc_waitx,x isequalto0,1,2,or3. (16) For singleread:A = (CSRdOffTime CSOnTime) *(TimeParaGranularity+ 1)*GPMC_FCLK period For burstread:A = (CSRdOffTime CSOnTime + (n1)*PageBurstAccessTime)*(TimeParaGranularity+ 1)*GPMC_FCLK period For burstwrite:A = (CSWrOffTime CSOnTime + (n1)*PageBurstAccessTime)*(TimeParaGranularity+ 1)*GPMC_FCLK period withn beingthepage burstaccessnumber. (17) For singleread:C = RdCycleTime *(TimeParaGranularity+ 1)*GPMC_FCLK For burstread:C = (RdCycleTime+ (n1)*PageBurstAccessTime)*(TimeParaGranularity+ 1)*GPMC_FCLK For burstwrite:C = (WrCycleTime+ (n1)*PageBurstAccessTime)*(TimeParaGranularity+ 1)*GPMC_FCLK withn beingthepage burstaccessnumber. (18) For read:K = (ADVRdOffTime ADVOnTime) *(TimeParaGranularity+ 1)*GPMC_FCLK For write:K = (ADVWrOffTime ADVOnTime) *(TimeParaGranularity+ 1)*GPMC_FCLK (19)M = (RdCycleTime-AccessTime)*(TimeParaGranularity+ 1)*GPMC_FCLK Above M parameterexpressionisgivenas one example ofGPMC programming.IO DIR signalwillgo fromIN toOUT afterboth RdCycleTime and BusTurnAroundcompletion.BehaviorofIO directionsignaldoes depend on kindofsuccessiveRead/Writeaccesses performedtoMemory and multiplexedornon-multiplexedmemory addressingscheme, bus keepingfeatureenabledornot.IO DIR behaviorisautomaticallyhandledby GPMC controller.

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PRODUCT□PREVIEW gpmc_clk gpmc_ncsx gpmc_a[10:1] gpmc_nbe0_cle gpmc_nbe1 gpmc_nadv_ale gpmc_noe gpmc_d[15:0] gpmc_waitx gpmc_io_dir Valid Address D□0 OUTOUT IN OUT F12 F13 F11 F19 F18 F20 F10 F19 030-021 F23 F24 AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Ingpmc_ncsx,x isequalto0,1,2,3,4,5,6,or7.Ingpmc_waitx,x isequalto0,1,2,or3. Figure6-2.GPMC/NOR FlashSynchronous SingleRead (GpmcFCLKDivider = 0) Copyright© 2009–2010,Texas InstrumentsIncorporated TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 111 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW gpmc_clk gpmc_ncsx gpmc_a[10:1] gpmc_nbe0_cle gpmc_nbe1 gpmc_nadv_ale gpmc_noe gpmc_d[15:0] gpmc_waitx gpmc_io_dir Valid Address D□0 D□1 D□2 D□3 OUTOUT IN OUT F12 F13 F13 F12 F8 F8 F9 F10 F11 F21 F22 030-022 F23 F24 AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Ingpmc_ncsx,x isequalto0,1,2,3,4,5,6,or7.Ingpmc_waitx,x isequalto0,1,2,or3. Figure6-3.GPMC/NOR FlashSynchronous BurstRead 4x16-bit(GpmcFCLKDivider = 0)

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PRODUCT□PREVIEW gpmc_clk gpmc_ncsx gpmc_a[10:1] gpmc_nbe0_cle gpmc_nbe1 gpmc_nadv_ale gpmc_nwe gpmc_d[15:0] gpmc_waitx gpmc_io_dir Valid Address D□0 D□1 D□2 D□3 OUT F15 F15 F15 F8F8 F14F14 F17 F17 F17 F9F6 F17 F17 F17 030-023 AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Ingpmc_ncsx,x isequalto0,1,2,3,4,5,6,or7.Ingpmc_waitx,x isequalto0,1,2,or3. Figure6-4.GPMC/NOR FlashSynchronous BurstWrite(GpmcFCLKDivider = 0) Copyright© 2009–2010,Texas InstrumentsIncorporated TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 113 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW gpmc_clk gpmc_ncsx gpmc_nbe0_cle gpmc_nbe1 gpmc_a[26:17] gpmc_a[16:1]_d[15:0] gpmc_nadv_ale gpmc_noe gpmc_waitx gpmc_io_dir Valid Valid Address□(MSB) Address□(LSB) D0 D1 D2 D3 OUTOUT IN OUT F8 F8 F10 F13 F12 F12 F11 F0 F1 F6 F7 030-024 F23 F24 AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Ingpmc_ncsx,x isequalto0,1,2,3,4,5,6,or7.Ingpmc_waitx,x isequalto0,1,2,or3. Figure6-5.GPMC/Multiplexed NOR FlashSynchronous BurstRead

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PRODUCT□PREVIEW gpmc_clk gpmc_ncsx gpmc_a[26:17] gpmc_nbe0_cle gpmc_nbe1 gpmc_nadv_ale gpmc_nwe gpmc_d[15:0] gpmc_waitx gpmc_io_dir Address□(MSB) Address□(LSB) D□0 D□1 D□2 D□3 OUT F15 F15 F15 F8F8 F17 F17 F17 F9F6 F17 F17 F17 F14F14 030-025 AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Ingpmc_ncsx,x isequalto0,1,2,3,4,5,6,or7.Ingpmc_waitx,x isequalto0,1,2,or3. Figure6-6.GPMC/Multiplexed NOR FlashSynchronous BurstWrite

6.4.1.2 GPMC/NOR FlashInterfaceAsynchronous Timing

The followingtablesassume testingover the recommended operatingconditionsand electrical characteristicconditions. Table6-5.GPMC/NOR FlashAsynchronous Mode Timing Conditions TIMING CONDITION PARAMETER VALUE UNIT InputConditions tR Inputsignalrisetime 1.8 ns tF Inputsignalfalltime 1.8 ns Output Conditions C LOAD Outputloadcapacitance 30 pF Table6-6.GPMC/NOR FlashInterfaceAsynchronous Timing – InternalParameters(1)(2) NO. PARAMETER 1.8V,3.3V UNIT MIN MAX FI1 Maximum outputdatagenerationdelayfrominternalfunctionalclock 6.5 ns FI2 Maximum inputdatacapturedelayby internalfunctionalclock 4 ns FI3 Maximum deviceselectgenerationdelayfrominternalfunctionalclock 6.5 ns FI4 Maximum addressgenerationdelayfrominternalfunctionalclock 6.5 ns FI5 Maximum addressvalidgenerationdelayfrominternalfunctionalclock 6.5 ns FI6 Maximum byteenablegenerationdelayfrominternalfunctionalclock 6.5 ns (1) The internalparameterstablemust be used tocalculateData Access Time storedinthecorrespondingCS registerbitfield. (2) InternalparametersarereferredtotheGPMC functionalinternalclockwhichisnotprovidedexternally. Copyright© 2009–2010,Texas InstrumentsIncorporated TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 115 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Table6-6.GPMC/NOR FlashInterfaceAsynchronous Timing – InternalParameters (1)(2) (continued) NO. PARAMETER 1.8V,3.3V UNIT MIN MAX FI7 Maximum outputenablegenerationdelayfrominternalfunctionalclock 6.5 ns FI8 Maximum writeenablegenerationdelayfrominternalfunctionalclock 6.5 ns FI9 Maximum functionalclockskew 100 ps Table6-7.GPMC/NOR FlashInterfaceTiming Requirements – Asynchronous Mode NO. PARAMETER 1.8V,3.3V UNIT MIN MAX FA5 (1) tacc(DAT) Data maximum accesstime H (2) GPMC_FCLK cycles FA20 (3) tacc1-pgmode(DAT) Page mode successivedatamaximum P (4) GPMC_FCLK cycles accesstime FA21 (5) tacc2-pgmode(DAT) Page mode firstdatamaximum access H (2) GPMC_FCLK cycles time (1) The FA5 parameterillustratestheamount oftimerequiredtointernallysample inputData.Itisexpressedinnumber ofGPMC functional clockcycles.From startofreadcycleand afterFA5 functionalclockcycles,inputData isinternallysampled by activefunctionalclock edge.FA5 valuemust be storedinsidetheAccessTime registerbitfield. (2) H = AccessTime *(TimeParaGranularity+ 1) (3) The FA20 parameterillustratesamount oftimerequiredtointernallysample successiveinputPage Data.Itisexpressedinnumber of GPMC functionalclockcycles.Aftereach accesstoinputPage Data,nextinputPage Data isinternallysampled by activefunctional clockedge afterFA20 functionalclockcycles.The FA20 valuemust be storedinthePageBurstAccessTimeregisterbitfield. (4) P = PageBurstAccessTime*(TimeParaGranularity+ 1) (5) The FA21 parameterillustratesamount oftimerequiredtointernallysample firstinputPage Data.Itisexpressedinnumber ofGPMC functionalclockcycles.From startofreadcycleand afterFA21 functionalclockcycles,FirstinputPage Data isinternallysampled by activefunctionalclockedge.FA21 valuemust be storedinsidetheAccessTime registerbitfield. Table6-8.GPMC/NOR FlashInterfaceSwitchingCharacteristics– Asynchronous Mode NO. PARAMETER 1.8V/3.3V UNIT MIN MAX tR(DO) Risetime,outputdata 2.0 ns tF(DO) Falltime,outputdata 2.0 ns FA0 tW(nBEV) Pulseduration, Read N (12) ns gpmc_nbe0_cle, Write N (12) nsgpmc_nbe1 validtime FA1 tW(nCSV) Pulseduration, Read A(1) ns gpmc_ncsx(13)v low Write A(1) ns FA3 td(nCSV-nADVIV) Delaytime, Read B(2)– 0.2 B(2)+ 2.0 ns gpmc_ncsx(13)validto Write B(2)– 0.2 B(2)+ 2.0 nsgpmc_nadv_aleinvalid FA4 td(nCSV-nOEIV) Delaytime,gpmc_ncsx(13)validto C (3)– 0.2 C (3)+ 2.0 ns gpmc_noe invalid(Singleread) FA9 td(AV-nCSV) Delaytime,addressbus validto J(9)– 0.2 J(9)+ 2.0 ns gpmc_ncsx(13)valid FA10 td(nBEV-nCSV) Delaytime,gpmc_nbe0_cle, J(9)– 0.2 J(9)+ 2.0 ns gpmc_nbe1 validtogpmc_ncsx(13) valid FA12 td(nCSV-nADVV) Delaytime,gpmc_ncsx(13)validto K(10)– 0.2 K(10)+ 2.0 ns gpmc_nadv_alevalid FA13 td(nCSV-nOEV) Delaytime,gpmc_ncsx(13)validto L(11)– 0.2 L(11)+ 2.0 ns gpmc_noe valid FA14 td(nCSV-IODIR) Delaytime,gpmc_ncsx(13)validto L(11)– 0.2 L(11)+ 2.0 ns gpmc_io_dirhigh FA15 td(nCSV-IODIR) Delaytime,gpmc_ncsx(13)validto M (14)– 0.2 M (14)+ 2.0 ns gpmc_io_dirlow

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PRODUCT□PREVIEW AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Table6-8.GPMC/NOR FlashInterfaceSwitchingCharacteristics– Asynchronous Mode (continued) NO. PARAMETER 1.8V/3.3V UNIT MIN MAX FA16 tw(AIV) Addressinvaliddurationbetween 2 G (7) ns successiveR/W accesses FA18 td(nCSV-nOEIV) Delaytime,gpmc_ncsx(13)validto I(8)– 0.2 I(8)+ 2.0 ns gpmc_noe invalid(Burstread) FA20 tw(AV) Pulseduration,addressvalid– 2nd,3rd, D (4) ns and 4thaccesses FA25 td(nCSV-nWEV) Delaytime,gpmc_ncsx(13)validto E(5)– 0.2 E(5)+ 2.0 ns gpmc_nwe valid FA27 td(nCSV-nWEIV) Delaytime,gpmc_ncsx(13)validto F(6)– 0.2 F(6)+ 2.0 ns gpmc_nwe invalid FA28 td(nWEV-DV) Delaytime,gpmc_ new validtodatabus 2.0 ns valid FA29 td(DV-nCSV) Delaytime,databus validto J(9)– 0.2 J(9)+ 2.0 ns gpmc_ncsx(13)valid FA37 td(nOEV-AIV) Delaytime,gpmc_noe validto 2.0 ns gpmc_a[16:1]_d[15:0]addressphase end (1) For singleread:A = (CSRdOffTime – CSOnTime) *(TimeParaGranularity+ 1)*GPMC_FCLK For singlewrite:A = (CSWrOffTime – CSOnTime) *(TimeParaGranularity+ 1)*GPMC_FCLK For burstread:A = (CSRdOffTime – CSOnTime + (n– 1)*PageBurstAccessTime)*(TimeParaGranularity+ 1)*GPMC_FCLK For burstwrite:A = (CSWrOffTime – CSOnTime + (n– 1)*PageBurstAccessTime)*(TimeParaGranularity+ 1)*GPMC_FCLK withn beingthepage burstaccessnumber (2) For reading:B = ((ADVRdOffTime– CSOnTime) *(TimeParaGranularity+ 1)+ 0.5*(ADVExtraDelay– CSExtraDelay))*GPMC_FCLK For writing:B = ((ADVWrOffTime– CSOnTime) *(TimeParaGranularity+ 1)+ 0.5*(ADVExtraDelay– CSExtraDelay))*GPMC_FCLK (3) C = ((OEOffTime– CSOnTime) *(TimeParaGranularity+ 1)+ 0.5*(OEExtraDelay– CSExtraDelay))*GPMC_FCLK (4) D = PageBurstAccessTime*(TimeParaGranularity+ 1)*GPMC_FCLK (5) E = ((WEOnTime – CSOnTime) *(TimeParaGranularity+ 1)+ 0.5*(WEExtraDelay– CSExtraDelay))*GPMC_FCLK (6) F = ((WEOffTime– CSOnTime) *(TimeParaGranularity+ 1)+ 0.5*(WEExtraDelay– CSExtraDelay))*GPMC_FCLK (7) G = Cycle2CycleDelay*GPMC_FCLK (8) I= ((OEOffTime+ (n– 1)*PageBurstAccessTime– CSOnTime) *(TimeParaGranularity+ 1)+ 0.5*(OEExtraDelay– CSExtraDelay))* GPMC_FCLK (9) J = (CSOnTime *(TimeParaGranularity+ 1)+ 0.5*CSExtraDelay)*GPMC_FCLK (10)K = ((ADVOnTime – CSOnTime) *(TimeParaGranularity+ 1)+ 0.5*(ADVExtraDelay– CSExtraDelay))*GPMC_FCLK (11)L = ((OEOnTime – CSOnTime) *(TimeParaGranularity+ 1)+ 0.5*(OEExtraDelay– CSExtraDelay))*GPMC_FCLK (12) For singleread:N = RdCycleTime *(TimeParaGranularity+ 1)*GPMC_FCLK For singlewrite:N = WrCycleTime *(TimeParaGranularity+ 1)*GPMC_FCLK For burstread:N = (RdCycleTime+ (n– 1)*PageBurstAccessTime)*(TimeParaGranularity+ 1)*GPMC_FCLK For burstwrite:N = (WrCycleTime+ (n– 1)*PageBurstAccessTime)*(TimeParaGranularity+ 1)*GPMC_FCLK (13)Ingpmc_ncsx,x isequalto0,1,2,3,4,5,6,or7. (14)M = ((RdCycleTime-CSOnTime) *(TimeParaGranularity+ 1)-0.5*CSExtraDelay)*GPMC_FCLK Above M parameterexpressionisgivenas one example ofGPMC programming.IO DIR signalwillgo fromIN toOUT afterboth RdCycleTime and BusTurnAroundcompletion.BehaviorofIO directionsignaldoes depend on kindofsuccessiveRead/Writeaccesses performedtoMemory and multiplexedornon-multiplexedmemory addressingscheme, bus keepingfeatureenabledornot.IO DIR behaviorisautomaticallyhandledby GPMC controller. Copyright© 2009–2010,Texas InstrumentsIncorporated TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 117 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW GPMC_FCLK gpmc_clk gpmc_ncsx gpmc_a[10:1] gpmc_nbe0_cle gpmc_nbe1 gpmc_nadv_ale gpmc_noe gpmc_d[15:0] gpmc_waitx gpmc_io_dir Valid Address Valid Valid Data□IN□0 Data□IN□0 OUTOUT IN OUT FA0 FA9 FA10 FA3 FA1 FA4 FA12 FA13 FA0 FA10 FA5 030-026 FA15FA14 AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Figure6-7.GPMC/NOR Flash– Asynchronous Read – SingleWord Timing(1)(2)(3) (1) Ingpmc_ncsx,x isequalto0,1,2,3,4,5,6,or7.Ingpmc_waitx,x isequalto0,1,2,or3. (2) FA5 parameterillustratesamount oftimerequiredtointernallysample inputdata.Itisexpressedinnumber ofGPMC functionalclock cycles.From startofreadcycleand afterFA5 functionalclockcycles,inputdataisinternallysampled by activefunctionalclockedge. FA5 valuemust be storedinsideAccessTime registerbitfield. (3) GPMC_FCLK isan internalclock(GPMC functionalclock)notprovidedexternally.

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PRODUCT□PREVIEW GPMC_FCLK gpmc_clk gpmc_ncsx gpmc_a[10:1] gpmc_nbe0_cle gpmc_nbe1 gpmc_nadv_ale gpmc_noe gpmc_d[15:0] gpmc_waitx gpmc_io_dir Address□0 Address□1 Valid Valid Valid Valid Data□Upper OUTOUT IN OUT IN FA9 FA10 FA3 FA9 FA3 FA13 FA13 FA1 FA1 FA4 FA4 FA12 FA12 FA10 FA0 FA0 FA16 FA0 FA0 FA10 FA10 FA5 FA5 030-027 FA15 FA15 FA14FA14 AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Figure6-8.GPMC/NOR Flash– Asynchronous Read – 32-bitTiming(1)(2)(3) (1) Ingpmc_ncsx,x isequalto0,1,2,3,4,5,6,or7.Ingpmc_waitx,x isequalto0,1,2,or3. (2) FA5 parameterillustratesamount oftimerequiredtointernallysample inputdata.Itisexpressedinnumber ofGPMC functionalclock cycles.From startofreadcycleand afterFA5 functionalclockcycles,inputdataisinternallysampled by activefunctionalclockedge. FA5 valuemust be storedinsideAccessTime registerbitfield. (3) GPMC_FCLK isan internalclock(GPMC functionalclock)notprovidedexternally. Copyright© 2009–2010,Texas InstrumentsIncorporated TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 119 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW GPMC_FCLK gpmc_clk gpmc_ncsx gpmc_a[10:1] gpmc_nbe0_cle gpmc_nbe1 gpmc_nadv_ale gpmc_noe gpmc_d[15:0] gpmc_waitx gpmc_io_dir Add0 Add1 Add2 Add3 Add4 D0 D1 D2 D3 D3 OUT IN OUT FA1 FA0 FA18 FA13 FA12 FA0 FA9 FA10 FA10 FA21 FA20 FA20 FA20 030-028 FA15 FA14 AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Figure6-9.GPMC/NOR Flash– Asynchronous Read – Page Mode 4x16-bitTiming(1)(2)(3)(4) (1) Ingpmc_ncsx,x isequalto0,1,2,3,4,5,6,or7.Ingpmc_waitx,x isequalto0,1,2,or3. (2) FA21 parameterillustratesamount oftimerequiredtointernallysample firstinputpage data.Itisexpressedinnumber ofGPMC functionalclockcycles.From startofreadcycleand afterFA21 functionalclockcycles,firstinputpage dataisinternallysampled by activefunctionalclockedge.FA21 valuemust be storedinsideAccessTime registerbitfield. (3) FA20 parameterillustratesamount oftimerequiredtointernallysample successiveinputpage data.Itisexpressedinnumber ofGPMC functionalclockcycles.Aftereach accesstoinputpage data,nextinputpage dataisinternallysampled by activefunctionalclockedge afterFA20 functionalclockcycles.FA20 isalsothedurationofaddressphases forsuccessiveinputpage data(excludingfirstinput page data).FA20 valuemust be storedinPageBurstAccessTimeregisterbitfield. (4) GPMC_FCLK isan internalclock(GPMC functionalclock)notprovidedexternally.

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PRODUCT□PREVIEW gpmc_fclk gpmc_clk gpmc_ncsx gpmc_a[10:1] gpmc_nbe0_cle gpmc_nbe1 gpmc_nadv_ale gpmc_nwe gpmc_d[15:0] gpmc_waitx gpmc_io_dir Valid Address Data□OUT OUT FA0 FA1 FA10 FA3 FA25 FA29 FA9 FA12 FA27 FA0 FA10 030-029 AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Ingpmc_ncsx,x isequalto0,1,2,3,4,5,6,or7.Ingpmc_waitx,x isequalto0,1,2,or3. Figure6-10.GPMC/NOR Flash– Asynchronous Write– SingleWord Timing Copyright© 2009–2010,Texas InstrumentsIncorporated TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 121 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW GPMC_FCLK gpmc_clk gpmc_ncsx gpmc_a[26:17] gpmc_nbe0_cle gpmc_nbe1 gpmc_nadv_ale gpmc_noe gpmc_a[16:1]_d[15:0] gpmc_io_dir gpmc_waitx Address□(MSB) Valid Valid Address□(LSB) Data□IN Data□IN OUT IN OUT FA0 FA9 FA10 FA3 FA13 FA29 FA1 FA37 FA12 FA4 FA10 FA0 FA5 030-030 FA15FA14 AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Figure6-11.GPMC/Multiplexed NOR Flash– Asynchronous Read – SingleWord Timing(1)(2)(3) (1) Ingpmc_ncsx,x isequalto0,1,2,3,4,5,6,or7.Ingpmc_waitx,x isequalto0,1,2,or3. (2) FA5 parameterillustratesamount oftimerequiredtointernallysample inputdata.Itisexpressedinnumber ofGPMC functionalclock cycles.From startofreadcycleand afterFA5 functionalclockcycles,inputdataisinternallysampled by activefunctionalclockedge. FA5 valuemust be storedinsideAccessTime registerbitfield. (3) GPMC_FCLK isan internalclock(GPMC functionalclock)notprovidedexternally.

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PRODUCT□PREVIEW gpmc_fclk gpmc_clk gpmc_ncsx gpmc_a[26:17] gpmc_nbe0_cle gpmc_nbe1 gpmc_nadv_ale gpmc_nwe gpmc_a[16:1]_d[15:0] gpmc_waitx gpmc_io_dir Address□(MSB) Valid Address□(LSB) Data□OUT OUT FA0 FA1 FA9 FA10 FA3 FA25 FA29 FA12 FA27 FA28 FA0 FA10 030-031 AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Ingpmc_ncsx,x isequalto0,1,2,3,4,5,6,or7.Ingpmc_waitx,x isequalto0,1,2,or3. Figure6-12.GPMC/Multiplexed NOR Flash– Asynchronous Write– SingleWord Timing

6.4.1.3 GPMC/NAND FlashInterfaceTiming

The followingtablesassume testingover the recommended operatingconditionsand electrical characteristicconditions. Table6-9.GPMC/NAND FlashAsynchronous Mode Timing Conditions TIMING CONDITION PARAMETER 1.8V,3.3V UNIT MIN MAX InputConditions tR Inputsignalrisetime 1.8 ns tF Inputsignalfalltime 1.8 ns C LOAD Outputloadcapacitance 30 pF Table6-10.GPMC/NAND FlashInterfaceAsynchronous Timing InternalParameters(1)(2) NO. PARAMETER 1.8V,3.3V UNIT MIN MAX GNFI1 Maximum outputdatagenerationdelayfrominternalfunctionalclock 6.5 ns GNFI2 Maximum inputdatacapturedelayby internalfunctionalclock 4 ns GNFI3 Maximum deviceselectgenerationdelayfrominternalfunctionalclock 6.5 ns (1) Internalparameterstablemust be used tocalculatedataaccesstimestoredinthecorrespondingCS registerbitfield. (2) InternalparametersarereferredtotheGPMC functionalinternalclockwhichisnotprovidedexternally. Copyright© 2009–2010,Texas InstrumentsIncorporated TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 123 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Table6-10.GPMC/NAND FlashInterfaceAsynchronous Timing InternalParameters (1)(2) (continued) NO. PARAMETER 1.8V,3.3V UNIT MIN MAX GNFI4 Maximum addresslatchenablegenerationdelayfrominternalfunctional 6.5 ns clock GNFI5 Maximum command latchenablegenerationdelayfrominternal 6.5 ns functionalclock GNFI6 Maximum outputenablegenerationdelayfrominternalfunctionalclock 6.5 ns GNFI7 Maximum writeenablegenerationdelayfrominternalfunctionalclock 6.5 ns GNFI8 Maximum functionalclockskew 100 ps Table6-11.GPMC/NAND FlashInterfaceTiming Requirements NO. PARAMETER 1.8V,3.3V UNIT MIN MAX GNF12 (1) tacc(DAT) Data maximum accesstime J(2) GPMC_FCLK cycles (1) The GNF12 parameterillustratestheamount oftimerequiredtointernallysample inputdata.Itisexpressedinnumber ofGPMC functionalclockcycles.From startofthereadcycleand afterGNF12 functionalclockcycles,inputdataisinternallysampled by the activefunctionalclockedge.The GNF12 valuemust be storedinsideAccessTime registerbitfield. (2) J = AccessTime *(TimeParaGranularity+ 1) Table6-12.GPMC/NAND FlashInterfaceSwitchingCharacteristics NO. PARAMETER 1.8V,3.3V UNIT MIN MAX tR(DO) Risetime,outputdata 2.0 ns tF(DO) Falltime,outputdata 2.0 ns GNF0 tw(nWEV) Pulseduration,gpmc_nwe A(1) ns validtime GNF1 td(nCSV-nWEV) Delaytime,gpmc_ncsx(13) B(2)-0.2 B(2)+ 2.0 ns validtogpmc_nwe valid GNF2 tw(CLEH-nWEV) Delaytime,gpmc_nbe0_cle C (3)-0.2 C (3)+ 2.0 ns hightogpmc_nwe valid GNF3 tw(nWEV-DV) Delaytime,gpmc_d[15:0] D (4)-0.2 D (4)+ 2.0 ns validtogpmc_nwe valid GNF4 tw(nWEIV-DIV) Delaytime,gpmc_nwe invalid E(5)-0.2 E(5)+ 2.0 ns togpmc_d[15:0]invalid GNF5 tw(nWEIV-CLEIV) Delaytime,gpmc_nwe invalid F(6)-0.2 F(6)+ 2.0 ns togpmc_nbe0_cleinvalid GNF6 tw(nWEIV-nCSIV) Delaytime,gpmc_nwe invalid G (7)-0.2 G (7)+ 2.0 ns togpmc_ncsx(13)invalid GNF7 tw(ALEH-nWEV) Delaytime,gpmc_nadv_ale C (3)-0.2 C (3)+ 2.0 ns Hightogpmc_nwe valid GNF8 tw(nWEIV-ALEIV) Delaytime,gpmc_nwe invalid F(6)-0.2 F(6)+ 2.0 ns togpmc_nadv_aleinvalid GNF9 tc(nWE) Cycletime,Writecycletime H (8) ns GNF10 td(nCSV-nOEV) Delaytime,gpmc_ncsx(13) I(9)-0.2 I(9)+ 2.0 ns validtogpmc_noe valid GNF13 tw(nOEV) Pulseduration,gpmc_noe K(10) ns validtime GN F14 tc(nOE) Cycletime,Read cycletime L(11) ns GNF15 tw(nOEIV-nCSIV) Delaytime,gpmc_noe invalid M (12)-0.2 M (12)+ 2.0 ns togpmc_ncsx(13)invalid

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PRODUCT□PREVIEW GPMC_FCLK gpmc_ncsx gpmc_nbe0_cle gpmc_nadv_ale gpmc_noe gpmc_nwe gpmc_a[16:1]_d[15:0] Command GNF0 GNF1 GNF2 GNF3 GNF4 GNF5 GNF6 030-032 GPMC_FCLK gpmc_ncsx gpmc_nbe0_cle gpmc_nadv_ale gpmc_noe gpmc_nwe gpmc_a[16:1]_d[15:0] Address GNF0 GNF1 GNF7 GNF3 GNF4 GNF6 GNF8 GNF9 030-033 AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 (1) A = (WEOffTime – WEOnTime) *(TimeParaGranularity+ 1)*GPMC_FCLK (2) B = ((WEOnTime – CSOnTime) *(TimeParaGranularity+ 1)+ 0.5*(WEExtraDelay– CSExtraDelay))*GPMC_FCLK (3) C = ((WEOnTime – ADVOnTime) *(TimeParaGranularity+ 1)+ 0.5*(WEExtraDelay– ADVExtraDelay))*GPMC_FCLK (4) D = (WEOnTime *(TimeParaGranularity+ 1)+ 0.5*WEExtraDelay)*GPMC_FCLK (5) E = (WrCycleTime– WEOffTime *(TimeParaGranularity+ 1)– 0.5*WEExtraDelay)*GPMC_FCLK (6) F = (ADVWrOffTime – WEOffTime *(TimeParaGranularity+ 1)+ 0.5*(ADVExtraDelay– WEExtraDelay)*GPMC_FCLK (7) G = (CSWrOffTime – WEOffTime *(TimeParaGranularity+ 1)+ 0.5*(CSExtraDelay– WEExtraDelay)*GPMC_FCLK (8) H = WrCycleTime *(1+ TimeParaGranularity)*GPMC_FCLK (9) I= ((OEOnTime – CSOnTime) *(TimeParaGranularity+ 1)+ 0.5*(OEExtraDelay– CSExtraDelay))*GPMC_FCLK (10)K = (OEOffTime– OEOnTime) *(1+ TimeParaGranularity)*GPMC_FCLK (11)L = RdCycleTime *(1+ TimeParaGranularity)*GPMC_FCLK (12)M = (CSRdOffTime – OEOffTime *(TimeParaGranularity+ 1)+ 0.5*(CSExtraDelay– OEExtraDelay)*GPMC_FCLK (13)Ingpmc_ncsx,x isequalto0,1,2,3,4,5,6,or7. Ingpmc_ncsx,x isequalto0,1,2,3,4,5,6,or7. Figure6-13.GPMC/NAND Flash– Command Latch Cycle Timing Ingpmc_ncsx,x isequalto0,1,2,3,4,5,6,or7. Figure6-14.GPMC/NAND Flash– Address Latch Cycle Timing Copyright© 2009–2010,Texas InstrumentsIncorporated TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 125 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW GPMC_FCLK gpmc_ncsx gpmc_nbe0_cle gpmc_nadv_ale gpmc_noe gpmc_a[16:1]_d[15:0] gpmc_waitx DA T A GNF10 GNF13 GNF14 GNF15 GNF12 030-034 GPMC_FCLK gpmc_ncsx gpmc_nbe0_cle gpmc_nadv_ale gpmc_noe gpmc_nwe gpmc_a[16:1]_d[15:0] DA T A GNF0 GNF1 GNF4 GNF6 GNF9 GNF3 030-035 AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Figure6-15.GPMC/NAND Flash– Data Read Cycle Timing(1)(2)(3) (1) The GNF12 parameterillustratesamount oftimerequiredtointernallysample inputdata.Itisexpressedinnumber ofGPMC functional clockcycles.From startofreadcycleand afterGNF12 functionalclockcycles,inputdataisinternallysampled by activefunctionalclock edge.The GNF12 valuemust be storedinsideAccessTime registerbitfield. (2) GPMC_FCLK isan internalclock(GPMC functionalclock)notprovidedexternally. (3) Ingpmc_ncsx,x isequalto0,1,2,3,4,5,6,or7.Ingpmc_waitx,x isequalto0 ,1,2,or3. Ingpmc_ncsx,x isequalto0,1,2,3,4,5,6,or7.Ingpmc_waitx,x isequalto0 or1. Figure6-16.GPMC/NAND Flash– Data WriteCycle Timing

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6.4.2 SDRAM Controller(SDRC)

The SDRC isa dedicatedinterfacetoDDR2/LPDDR1 SDRAM thatperformsthefollowingfunctions:

• Bufferingofinputimage datafromsensorsorvideosources
• Intermediatebufferingforprocessing/resizingofimage dataintheVPFE
• Numerous OSD displaybuffers
• Intermediatebufferingforlargeraw Bayer data image fileswhileperformingimage processing functions
• Bufferingforintermediatedatawhileperformingvideoencode and decode functions
• Storageofexecutablecode fortheARM The main featuresofthecontrollerare:
• Open Core Protocol2.2(OCP) compliant[7].
• SupportsJEDEC standardcompliantDDR2 [2]and LPDDR1 [4]devices. – SDRAM addressrangeover2 chipselects. – Supportsfollowingdatabus widths: OCP Data Bus Width SDRAM Data Bus Width 64 and 128-Bit 16,32,and 64-Bit – SupportsfollowingCAS latencies: SDRAM Type CAS Latencies DDR2 2,3,4,5,and 6 LPDDR1 2 and 3 – Supportsfollowingnumber ofinternalbanks: SDRAM Type InternalBanks DDR2 1,2,4,and 8 LPDDR1 1,2,and 4 – Supports256,512,1024,and 2048-wordpage sizes. – Supportsfollowingburstlengths: SDRAM Type BurstLength DDR2 8 (4notsupported) LPDDR1 8 (2and 4 notsupported) – Supportssequentialbursttype. – SDRAM autoinitializationfromresetorconfigurationchange. – SupportsBank Interleavingacrossboththechipselects. – SupportsClockStopmode forLPDDR1 forlowpower. – SupportsSelfRefreshand PrechargePower-Down modes forlowpower. – SupportsPartialArraySelfRefreshand TemperatureControlledSelfRefreshmodes forlowpower inLPDDR1. – TemperatureControlledSelfRefreshisonlysupportedformobileSDRAM havingon-chip temperaturesensor. – SupportsODT on DDR2. – Supportsprioritizedrefresh. – Programmable SDRAM refreshrateand backlogcounter. – Programmable SDRAM timingparameters. – Supportsonlylittleendian. Copyright© 2009–2010,Texas InstrumentsIncorporated TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 127 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW sdrc_d0 sdrc_d7 sdrc_dm0 sdrc_dqs0p sdrc_d8 sdrc_d15 sdrc_dm1 sdrc_dqs1p sdrc_d16 sdrc_d23 sdrc_dm2 sdrc_dqs2p sdrc_d24 sdrc_d31 sdrc_dm3 sdrc_dqs3p sdrc_ba0 sdrc_ba1 sdrc_a0 sdrc_a14 sdrc_ncs0 sdrc_ncas sdrc_nras sdrc_nwe sdrc_cke0 sdrc_clk sdrc_nclk T T T T T T T T T T T T T T T T T T T DQ0 DQ7 LDM LDQS DQ8 DQ15 UDM UDQS BA0 BA1 A14 CS CAS RAS WE CKE CK CK BA0 BA1 A14 CS CAS RAS WE CKE CK CK T T T T T T T T LPDDR AM35x DQ0 DQ7 LDM LDQS DQ8 DQ15 UDM UDQS LPDDR AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com

6.4.2.1 LPDDR Interface

ThissectionprovidesthetimingspecificationfortheLPDDR interfaceas a PCB designand manufacturing specification.The designrulesconstrainPCB tracelength,PCB traceskew, signalintegrity,cross-talk, and signaltiming.These rules,when followed,resultina reliableLPDDR memory system withoutthe need fora complex timingclosureprocess.For more informationregardingguidelinesforusing this LPDDR specification,see the UnderstandingTI'sPCB RoutingRule-Based DDR Timing Specification 6.4.2.1.1LPDDR InterfaceSchematic Figure6-17and Figure6-18show theLPDDR interfaceschematicsfora LPDDR memory system.The 1 x16 LPDDR system schematicisidenticalto Figure6-17 exceptthatthe highword LPDDR deviceis deleted. Figure6-17.AM35x LPDDR High LevelSchematic (x16memories)

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PRODUCT□PREVIEW sdrc_d0 sdrc_d7 sdrc_dm0 sdrc_dqs0p sdrc_d8 sdrc_d15 sdrc_dm1 sdrc_dqs1p sdrc_d16 sdrc_d23 sdrc_dm2 sdrc_dqs2p sdrc_d24 sdrc_d31 sdrc_dm3 sdrc_dqs3p sdrc_ba0 sdrc_ba1 sdrc_a0 sdrc_a14 sdrc_ncs0 sdrc_ncas sdrc_nras sdrc_nwe sdrc_cke0 sdrc_clk sdrc_nclk T T T T T T T T T T T T T T T T T T T BA0 BA1 A14 CS CAS RAS WE CKE CK CK T T T T T T T T AM35x DQ0 DQ7 DM0 DQS0 DQ8 DQ15 DM1 DQS1 LPDDR DQ16 DQ23 DM2 DQS2 DQ24 DQ31 DM3 DQS3 AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Figure6-18.AM35x LPDDR High LevelSchematic (x32memory) 6.4.2.1.2Compatible JEDEC LPDDR Devices Table6-13 shows theparametersoftheJEDEC LPDDR devicesthatare compatiblewiththisinterface. Generally,theLPDDR interfaceiscompatiblewithx16 and x32 LPDDR333 speed gradeLPDDR devices. Table6-13.Compatible JEDEC LPDDR Devices NO. PARAMETER MIN MAX UNIT NOTES JEDEC LPDDR DeviceSpeed1 LPDDR333 See Note (1) Grade

2 JEDEC LPDDR DeviceBitWidth 16 32 Bits

3 JEDEC LPDDR DeviceCount 1 2 Devices See Note (2)

JEDEC LPDDR DeviceBall4 60 90 BallsCount (1) HigherLPDDR speed gradesoperatingatthespecifiedspeeds aresupporteddue toinherentJEDEC LPDDR backwardscompatibility. (2) 1 x16 LPDDR deviceisused for16 bitLPDDR memory system.1x32 or2x16 LPDDR devicesareused fora 32-bitLPDDR memory system. Copyright© 2009–2010,Texas InstrumentsIncorporated TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 129 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com 6.4.2.1.3PCB Stackup The minimum stackuprequiredforroutingthe AM35x is a sixlayerstackas shown in Table 6-14. Additionallayersmay be added tothePCB stackup toaccommodate othercircuityortoreducethesize ofthePCB footprint. Table6-14.Minimum PCB Stack Up LAYER TYPE DESCRIPTION

1 Signal Top RoutingMostlyHorizontal

2 Plane Ground

3 Plane Power

4 Signal InternalRouting

5 Plane Ground

6 Signal BottomRoutingMostlyVertical

Table6-15.PCB Stack Up Specifications NO. PARAMETER MIN TYP MAX UNIT NOTES

1 PCB Routing/PlaneLayers 6

2 SignalRoutingLayers 3

3 FullgroundlayersunderLPDDR routingregion 2

4 Number ofgroundplanecutsallowedwithinLPDDR routingregion 0

Number ofgroundreferenceplanesrequiredforeach LPDDR routing15 1layer Number oflayersbetween LPDDR routinglayerand referenceground06 0plane

7 PCB RoutingFeatureSize 4 Mils

8 PCB TraceWidthw 4 Mils

9 PCB BGA escape viapad size 18 Mils

10 PCB BGA escape viaholesize 8 Mils

11 DeviceBGA Pad Size See Note(1)

12 LPDDR DeviceBGA Pad Size See Note(2)

13 SingleEnded Impedance,ZO 50 75 Ω

14 Impedance Control Z-5 Z Z + 5 Ω See Note(3)

(1) Pleasesee theFlipChipBallGridArrayPackage ReferenceGuide (literaturenumber SPRU811 )fordeviceBGA pad size. (2) Pleasesee theLPDDR devicemanufacturerdocumentationfortheLPDDR deviceBGA pad size. (3) Z isthenominalsingledended impedance selectedforthePCB specifiedby item12. 6.4.2.1.4Placement Figure6-19 shows the requiredplacementforthe AM35x deviceas wellas the LPDDR devices.The dimensionsforFigure6-19aredefinedinTable6-16.The placementdoes notrestrictthesideofthePCB thatthe devicesare mounted on. The ultimatepurpose of the placementisto limitthe maximum trace lengthsand allowforproperroutingspace.For 1x16 and 1x32 LPDDR memory systems,the second LPDDR deviceisomittedfromtheplacement.

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PRODUCT□PREVIEW X Y OFFSET Recommended LPDDR Device Orientation Y Y OFFSET LPDDR Device LPDDRControllerAM35x AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Figure6-19.AM35x and LPDDR Device Placement Table6-16.Placement Specifications NO. PARAMETER MIN MAX UNIT NOTES

1 X 1440 Mils See Notes(1),(2)

2 Y 1030 Mils See Notes(1),(2)

3 Y Offset 525 Mils See Notes(1),(2),(3)

4 LPDDR KeepoutRegion See Note(4)

Clearancefromnon-LPDDR signaltoLPDDR5 4 w See Note(5) KeepoutRegion (1) See Figure6-17fordimensiondefinitions. (2) Measurements fromcenterofdevicetocenterofLPDDR device. (3) For16 bitmemory systemsitisrecommended thatY Offsetbe as smallas possible. (4) LPDDR keepoutregiontoencompass entireLPDDR routingarea. (5) Non-LPDDR signalsallowedwithinLPDDR keepoutregionprovidedtheyareseparatedfromLPDDR routinglayersby a groundplane. 6.4.2.1.5LPDDR Keep Out Region The regionof the PCB used forthe LPDDR circuitrymust be isolatedfrom othersignals.The LPDDR keep outregionisdefinedforthispurposeand isshown inFigure6-20.The sizeofthisregionvarieswith theplacementand LPDDR routing.Additionalclearancesrequiredforthekeep outregionare shown in Table6-16. Copyright© 2009–2010,Texas InstrumentsIncorporated TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 131 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW LPDDR□Controller LPDDR□Device Region□should□encompass□all□LPDDR□circuitry□and□varies□depending on□placement.□Non-LPDDR□signals□should□not□be□routed□on□the LPDDR□signal□layers□within□the□LPDDR□keep□out□region.□Non-LPDDR signals□may□be□routed□in□the□region□provided□they□are□routed□on layers□separated□from□LPDDR□signal□layers□by□a□ground□layer.□No breaks□should□be□allowed□in□the□□reference□ground□layers□in□this region.□In□addition,□the□1.8□V□power□plane□should□cover□the□entire□keep out□region. AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Figure6-20.LPDDR Keepout Region 6.4.2.1.6Net Classes Table6-17liststheclocknetclassesfortheLPDDR interface.Table6-18liststhesignalnetclasses,and associatedclocknetclasses,forthesignalsintheLPDDR interface.These netclassesare used forthe terminationand routingrulesthatfollow. Table6-17.Clock Net Class Definitions CLOCK NET CLASS PIN NAMES CK sdrc_clk/sdrc_nclk DQS0 sdrc_dqs0 DQS1 sdrc_dqs1 DQS2 sdrc_dqs2 DQS3 sdrc_dqs3 Table6-18.SignalNet Class Definitions CLOCK NET CLASS ASSOCIATED CLOCK NET CLASS PIN NAMES sdrc_ba,sdrc_a,sdrc_ncs0,sdrc_ncas,ADDR_CTRL CK sdrc_nras,sdrc_nwe,sdrc_cke0 DQ0 DQS0 sdrc_d,sdrc_dm0 DQ1 DQS1 sdrc_d,sdrc_dm1 DQ2 DQS2 sdrc_d,sdrc_dm2 DQ3 DQS3 sdrc_d,sdrc_dm3 6.4.2.1.7LPDDR SignalTermination No terminationsof any kindare requiredinorderto meet signalintegrityand overshootrequirements. Serialterminatorsare permitted,ifdesired,toreduceEMI risk;however,serialterminationsare theonly typepermitted.Table6-19shows thespecificationsfortheseriesterminators.

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PRODUCT□PREVIEW C B A T LPDDRController AM35x AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Table6-19.LPDDR SignalTerminations NO. PARAMETER MIN TYP MAX UNIT NOTES

1 CK Net Class 0 10 Ω See Note(1)

2 ADDR_CTRL Net Class 0 22 Zo Ω See Notes(1),(2),(3)

Data ByteNet Classes3 0 22 Zo Ω See Notes(1),(2),(3) (DQS0-DQS3, DQ0-DQ3) (1) Onlyseriesterminationispermitted,parallelorSST specificallydisallowed. (2) Terminatorvalueslargerthantypicalonlyrecommended toaddressEMI issues. (3) Terminationvalueshouldbe uniformacrossnetclass. 6.4.2.1.8LPDDR CK and ADDR_CTRL Routing Figure6-21 shows thetopologyoftheroutingfortheCK and ADDR_CTRL netclasses.The routeisa balancedT as itisintendedthatthelengthofsegments B and C be equal.Inaddition,thelengthofA shouldbe maximized. Figure6-21.CK and ADDR_CTRL Routing and Topology Table6-20.CK and ADDR_CTRL Routing Specification NO. PARAMETER MIN TYP MAX UNIT NOTES

1 CentertoCenterCK-CK spacing 2w

2 CK A toB/A toC Skew LengthMismatch 25 Mils See Note(1)

3 CK B toC Skew LengthMismatch 25 Mils

CentertoCenterCK toother4 4w See Note(2) LPDDR tracespacing

5 CK/ADDR_CTRL nominaltracelength CACLM-50 CACLM CACLM+50 Mils See Note(3)

6 ADDR_CTRL toCK Skew LengthMismatch 100 Mils

ADDR_CTRL toADDR_CTRL7 100 MilsSkew LengthMismatch CentertoCenterADDR_CTRL toother8 4w See Note(2) LPDDR trace4w spacing CentertoCenterADDR_CTRL toother9 3w See Note(2) ADDR_CTRL 3w tracespacing ADDR_CTRL A toB/A toC Skew Length10 100 Mils See Note(1) Mismatch

11 ADDR_CTRL B toC Skew LengthMismatch 100 Mils

(1) Seriesterminator,ifused,shouldbe locatedclosesttodevice. (2) Centertocenterspacingisallowedtofalltominimum (w)forup to500 milsofroutedlengthtoaccommodate BGA escape and routing congestion. (3) CACLM isthelongestManhattandistanceoftheCK and ADDR_CTRL netclasses. Copyright© 2009–2010,Texas InstrumentsIncorporated TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 133 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW T T AM35x T LPDDRController T AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Figure6-22shows thetopologyand routingfortheDQS and DQ netclasses;theroutesarepointtopoint. Skew matchingacrossbytesisnotneeded norrecommended. Figure6-22.DQS and DQ Routing and Topology Table6-21.DQS and DQ Routing Specification(1) NO. PARAMETER MIN TYP MAX UNIT NOTES

2 DQS E Skew LengthMismatch 25 Mils

CentertoCenterDQS tootherLPDDR3 4w See Note(2) tracespacing

4 DQS/DQ nominaltracelength DQLM -50 DQLM DQLM + 50 Mils See Note(3)

5 DQ toDQS Skew LengthMismatch 100 Mils

6 DQ toDQ Skew LengthMismatch 100 Mils

CentertoCenterDQ tootherLPDDR7 4w See Note(2) tracespacing CentertoCenterDQ tootherDQ trace8 3w See Note(2),(4) spacing

9 DQ E Skew LengthMismatch 100 Mils

(1) Seriesterminator,ifused,shouldbe locatedclosesttoLPDDR. (2) Centertocenterspacingisallowedtofalltominimum (w)forup to500 milsofroutedlengthtoaccommodate BGA escape and routing congestion. (3) Centertocenterspacingisallowedtofalltominimum (w)forup to500 milsofroutedlengthtoaccommodate BGA escape and routing congestion. (4) DQLM isthelongestManhattandistanceoftheDQS and DQ netclasses.

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6.4.2.2 DDR2 Interface

ThissectionprovidesthetimingspecificationfortheDDR2 interfaceas a PCB designand manufacturing specification.The designrulesconstrainPCB tracelength,PCB traceskew, signalintegrity,cross-talk, and signaltiming.These rules,when followed,resultina reliableDDR2 memory system withouttheneed fora complex timingclosureprocess.For more informationregardingguidelinesforusingthisDDR2 specification,UnderstandingTI'sPCB RoutingRule-BasedDDR2 TimingSpecification(SPRAAV0 ). 6.4.2.2.1DDR2 InterfaceSchematic Figure6-23 shows theDDR2 interfaceschematicfora dual-memoryDDR2 system.The single-memory system isshown inFigure6-24.Pinnumbers fortheAM3517/05 can be obtainedfromthepindescription section. 6.4.2.2.2Compatible JEDEC DDR2 Devices Table 6-22 shows the parametersof the JEDEC DDR2 devicesthatare compatiblewiththisinterface. Generally,theDDR2 interfaceiscompatiblewithx16 orx32 DDR2 speed gradeDDR2-333 devices. Table6-22.Compatible JEDEC DDR2 Devices No. Parameter Min Max Unit Notes

1 JEDEC DDR2 DeviceSpeed Grade DDR2-333 MHz See Note (1)

2 JEDEC DDR2 DeviceBitWidth x16 x32 Bits

3 JEDEC DDR2 DeviceCount 1 2 Devices See Note (2)

4 JEDEC DDR2 DeviceBallCount 84 92 Balls See Note (3)

(1) HigherDDR2 speed gradesoperatingatthespecifiedspeeds aresupporteddue toinherentJEDEC DDR2 backwardscompatibility. (2) Devicecountindicatesnumber ofdies.Ifa package contains2 dies,thatisthemaximum number ofdevicesthatcan be connected. (3) 92 balldevicesretainedforlegacysupport.New designswillmigrateto84 ballDDR2 devices.Electrically,the92 and 84 ballDDR2 devicesarethesame. Copyright© 2009–2010,Texas InstrumentsIncorporated TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 135 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com 6.4.2.2.3PCB Stackup The minimum stackuprequiredforroutingtheAM3517/05 isa sixlayerstackas shown inTable 6-23. Additionallayersmay be added tothePCB stackup toaccommodate othercircuitryortoreducethesize ofthePCB footprint. Table6-23.Minimum PCB Stack Up Layer Type Description

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PRODUCT□PREVIEW SPRS550-008 Vio1.8 0.1 0.1 0.10.10.1/c109F (A) AM35x T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T 50 1% T x16 DDR2 SDRC_D0 SDRC_D7 SDRC_DM0 SDRC_DQS0P SDRC_DQS0N SDRC_D8 SDRC_D15 SDRC_DM1 SDRC_DQS1P SDRC_DQS1N SDRC_STRBEN0 SDRC_STRBEN_DLY0 SDRC_D16 SDRC_D23 SDRC_DM2 SDRC_DQS2P SDRC_DQS2N SDRC_D24 SDRC_D31 SDRC_DM3 SDRC_DQS3P SDRC_DQS3N SDRC_STRBEN1 SDRC_STRBEN_DLY1 SDRC_BA0 SDRC_BA1 SDRC_BA2 SDRC_A0 SDRC_A14 SDRC_nCS0 SDRC_nCS1 SDRC_nCAS SDRC_nRAS SDRC_nWE SDRC_nCKE0 SDRC_CLK SDRC_nCLK SDRC_ODT VREFSSTL DDR_PADREF /c109F (A) /c109F (A) /c109F /c109F 1K /c87 1K /c87 DQ0 Length = avg DQS0-1 length+CLK Length = avg DQS2-3 length+CLK DQ7 LDM LDQS LDQS# LQ8 LQ15 UDM UDQS UDQS# DQ0 DQ7 LDM LDQS LDQS# DQ8 DQ15 UDM UDQS UDQS# BA0 BA1 BA2* A14* BA0 BA1 BA2* A14* CS1 CS2* CAS# RAS# WE# CLK CLK# ODT* VREF CS1 CS2* CAS# RAS# WE# CLK CLK# ODT* VREF A. See VREF Routing and Topology figure for information on capacitor placement. AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Completestackup specificationsareprovidedinTable6-24. Figure6-23.DDR2 Dual-Memory High LevelSchematic Copyright© 2009–2010,Texas InstrumentsIncorporated TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 137 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW SDRC_D0 SDRC_D7 SDRC_DM0 SDRC_DQS0P SDRC_D8 SDRC_D15 SDRC_DQS1P SDRC_DQS1N DQ0 DQ7 DM0 DQS0 DQS0# DQ8 DQ15 DM1 DQS1 DQS1# BA0 BA2* A14* CS1 CAS# RAS# WE# CKE CLK CLK# VREF SDRC_BA0 SDRC_BA2 SDRC_A0 SDRC_A14 SDRC_nCS0 SDRC_nCAS SDRC_nRAS SDRC_nWE SDRC_nCKE0 SDRC_CLK SDRC_nCLK ODT* 1K 1%/c87 1K 1%/c87 Vio1.8

0.1 F/c109

0.1 F/c1090.1 F/c109 (A) (A) (A) AM35x DDR2 T T T T T T T T T T T T T T T SDRC_DQS0N T T T T SDRC_DM1 SDRC_D16 SDRC_D23 SDRC_DM2 SDRC_DQS2P DQ16 DQ23 DM2 DQS2 DQS2# T SDRC_DQS2N T T SDRC_D24 SDRC_D31 SDRC_DM3 SDRC_DQS3P DQ24 DQ31 DM3 DQS3 DQS3# T SDRC_DQS3N T TSDRC_BA1 BA1 T SDRC_nCS1 CS2* SDRC_ODT T VREFSSTL SDRC_STRBEN0 SDRC_STRBEN_DLY0 T T T T T T T SDRC_STRBEN1 SDRC_STRBEN_DLY1 T T Length = avg D0-D15 length+CLK Length = avg D16-D31 length+CLK SPRS550-009 DDR_PADREF 50 1% A. See VREF Routing and Topology figure for information on capacitor placement. AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Figure6-24.DDR2 Single-Memory High LevelSchematic

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PRODUCT□PREVIEW X Y OFFSET Recommended DDR2 Device Orientation Y Y OFFSET DDR2 Device DDR2 Controller AM3517/05 AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Table6-24.PCB Stack Up Specifications No. Parameter Min Typ Max Unit Notes

3 FullgroundlayersunderDDR2 routingRegion 2

4 Number ofgroundplanecutsallowedwithinDDR routingregion 0

5 Number ofgroundreferenceplanesrequiredforeach DDR2 routinglayer 1

6 Number oflayersbetween DDR2 routinglayerand groundplane 0

9 PCB BGA escape viapad size 20 Mils

10 PCB BGA escape viaholesize 10 Mils

11 AM3517/05 BGA pad size 12 See Note (1)

12 DDR2 DeviceBGA pad size See Note (2)

14 Impedance Control Z-5 Z Z+5 Ω See Note (3)

(1) The recommended pad sizeis0.3mm perIPC-7351specification. (2) PleaserefertoIPC standardIPC-7351ormanufacturer's recommendationsforcorrectBGA pad size. (3) Z isthenominalsingledended impedance selectedforthePCB specifiedby item12. 6.4.2.2.4Placement Figure6-24 shows the requiredplacementforthe DDR2 devices.The dimensionsforFigure6-25 are definedinTable6-25.The placementdoes notrestrictthesideofthePCB thatthedevicesaremounted on. The ultimatepurpose of the placementisto limitthe maximum tracelengthsand allowforproper routingspace. For single-memoryDDR2 systems, the second DDR2 device is omittedfrom the placement. Figure6-25.DDR2 Device Placement Copyright© 2009–2010,Texas InstrumentsIncorporated TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 139 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW DDR2 Controller DDR2 Device Region should encompass all DDR2 circuitry and varies depending on placement. Non-DDR2 signals should not be routed on the DDR signal layers within the DDR2 keep out region. Non-DDR2 signals may be routed in the region provided they are routed on layers separated from DDR2 signal layers by a ground layer. No breaks should be allowed in the reference ground layers in this region. In addition, the 1.8 V power plane should cover the entire keep out region. AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Table6-25.Placement Specifications No. Parameter Min Max Unit Notes

1 X 1750 Mils See Notes (1),(2)

2 Y 1280 Mils See Notes (1),(2)

3 Y Offset 650 Mils See Notes (1).(2), (3)

4 DDR2 KeepoutRegion See Note (4)

5 Clearancefromnon-DDR2 signaltoDDR2 KeepoutRegion 4 w See Note (5)

(1) See Figure6-23fordimensiondefinitions. (2) Measurements fromcenterofAM3517/05 devicetocenterofDDR2 device. (3) Forsinglememory systemsitisrecommended thatY Offsetbe as smallas possible. (4) DDR2 Keepoutregiontoencompass entireDDR2 routingarea (5) Non-DDR2 signalsallowedwithinDDR2 keepoutregionprovidedtheyareseparatedfromDDR2 routinglayersby a groundplane. 6.4.2.2.5DDR2 Keep Out Region The regionofthePCB used fortheDDR2 circuitrymust be isolatedfrom othersignals.The DDR2 keep outregionisdefinedforthispurposeand isshown inFigure6-26.The sizeofthisregionvarieswiththe placement and DDR routing.Additionalclearancesrequiredforthe keep out regionare shown in Table6-25. Figure6-26.DDR2 Keepout Region

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PRODUCT□PREVIEW AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 6.4.2.2.6Bulk Bypass Capacitors Bulk bypass capacitorsare requiredformoderate speed bypassingof the DDR2 and othercircuitry. Table6-26containstheminimum numbers and capacitancerequiredforthebulkbypass capacitors.Note thatthistableonlycoversthe bypass needs of the AM3517/05 and DDR2 interfaces.Additionalbulk bypasscapacitancemay be needed forothercircuitry. Table6-26.Bulk Bypass Capacitors No. Parameter Min Max Unit Notes

1 VDDS BulkBypass CapacitorCount 3 Devices See Note

(1)

2 VDDS BulkBypass TotalCapacitance 30 uF

3 DDR#1 BulkBypass CapacitorCount 1 Devices See Note

(1)

4 DDR#1 BulkBypass TotalCapacitance 22 uF

5 DDR#2 BulkBypass CapacitorCount 1 Devices See Notes

(1),(2)

6 DDR#2 BulkBypass TotalCapacitance 22 uF See Note

(2) (1) These devicesshouldbe placednearthedevicetheyarebypassing,butpreferenceshouldbe giventotheplacementofthehigh-speed (HS)bypasscaps. (2) Onlyused on dual-memorysystems Copyright© 2009–2010,Texas InstrumentsIncorporated TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 141 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com 6.4.2.2.7High-Speed Bypass Capacitors High-speed(HS) bypass capacitorsare criticalforproperDDR2 interfaceoperation.Itis particularly importanttominimizetheparasiticseriesinductanceoftheHS bypass cap,AM3517/05 DDR2 power,and AM3517/05 DDR2 groundconnections.Table6-27containsthespecificationfortheHS bypass capacitors as wellas forthepower connectionson thePCB. 6.4.2.2.8Net Classes Table6-28liststheclocknetclassesfortheDDR2 interface.Table6-29liststhesignalnetclasses,and associatedclocknetclasses,forthesignalsintheDDR2 interface.These netclassesare used forthe terminationand routingrulesthatfollow. Table6-27.High-Speed Bypass Capacitors No. Parameter Min Max Unit Notes

1 HS Bypass CapacitorPackage Size 0402 10 Mils See Note (1)

2 DistancefromHS bypasscapacitortodevicebeingbypassed 250 Mils

3 Number ofconnectionviasforeach HS bypasscapacitor 2 Vias See Note (2)

4 Tracelengthfrombypasscapacitorcontacttoconnectionvia 1 30 Mils

5 Number ofconnectionviasforeach DDR2 devicepower orgroundballs 1 Vias

6 TracelengthfromDDR2 devicepower balltoconnectionvia 35 Mils

7 VDDS HS Bypass CapacitorCount 20 Devices See Note (3)

8 VDDS HS Bypass CapacitorTotalCapacitance 1.2 mF

9 DDR#1 HS Bypass CapacitorCount 8 Devices See Note (3)

10 DDR#1 HS Bypass CapacitorTotalCapacitance 0.4 mF

11 DDR#2 HS Bypass CapacitorCount 8 Devices See Notes

(3),(4) 12 DDR#2 HS Bypass CapacitorTotalCapacitance 0.4 mF See Note (4) (1) LxW, 10 milunits,i.e.,a 0402 isa 40x20 milsurfacemount capacitor (2) An additionalHS bypasscapacitorcan sharetheconnectionviasonlyifitismounted on theoppositesideoftheboard. (3) These devicesshouldbe placedas closeas possibletothedevicebeingbypassed. (4) Onlyused on dual-memorysystems

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PRODUCT□PREVIEW AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Table6-28.Clock Net Class Definitions Clock Net Class AM3517/05 Device Pin Names CK sdrc_clk/sdrc_nclk DQS0 sdrc_dqs0p/sdrc_dqs0n DQS1 sdrc_dqs1p/sdrc_dqs1n DQS2 sdrc_dqs2p/sdrc_dqs2n DQS3 sdrc_dqs3p/sdrc_dqs3n Table6-29.SignalNet Class Definitions AssociatedClock Net Clock Net Class Class AM3517/05 Device Pin Names ADDR_CTRL CK sdrc_ba[2:0],sdrc_ncs1,sdrc_a[14:0],sdrc_ncs0,sdrc_ncas,sdrc_nras, sdrc_nwe,sdrc_cke0 DQ0 DQS0 sdrc_d[7:0],sdrc_dm0 DQ1 DQS1 sdrc_d[15:8],sdrc_dm1 DQ2 DQS2 sdrc_d[23:16],sdrc_dm2 DQ3 DQS3 sdrc_d[31:24],sdrc_dm3 SDRC_STRBEN0 CK,DQS0,DQS1 sdrc_strben0,sdrc_strben_dly0 SDRC_STRBEN1 CK,DQS2,DQS3 sdrc_strben1,sdrc_strben_dly1 6.4.2.2.9DDR2 SignalTermination No terminationsof any kindare requiredinorderto meet signalintegrityand overshootrequirements. Serialterminatorsare permitted,ifdesired,toreduceEMI risk;however,serialterminationsare theonly typepermitted.Table6-30shows thespecificationsfortheseriesterminators. Table6-30.DDR2 SignalTerminations No. Parameter Min Typ Max Unit Notes

1 CLK Net Class 0 10 Ω See Note (1)

2 ADDR_CTRL Net Class 0 22 Zo Ω See Notes (1),

(2),(3)

3 Data ByteNet Classes(DQS0-DQS1, D0-D31) 0 22 Zo Ω See Notes (1),

(2),(3)

4 SDRC_STRBENx Net Class(SDRC_STRBENx) 0 10 Zo Ω See Notes (1),

(2),(3) (1) Onlyseriesterminationispermitted,parallelorSST specificallydisallowed. (2) Terminatorvalueslargerthantypicalonlyrecommended toaddressEMI issues. (3) Terminationvalueshouldbe uniformacrossnetclass. Copyright© 2009–2010,Texas InstrumentsIncorporated TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 143 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW AM3517/05 Device DDR2 Device VREF Nominal Minimum Trace Width is 20 Mils VREF Bypass Capacitor Neck down to minimum in BGA escape regions is acceptable. Narrowing to accomodate via congestion for short distances is also acceptable. Best performance is obtained if the width of VREF is maximized. C B A T DDR2 Controller AM3517/05 AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com 6.4.2.2.10VREF Routing VREF isused as a referenceby the inputbuffersof the DDR2 memories as wellas the AM3517/05 . VREF isintendedtobe halfoftheDDR2 power supplyvoltageand shouldbe createdusinga resistive divideras shown inFigure6-23. Other methods of creatingVREF are not recommended. Figure6-27 shows thelayoutguidelinesforVREF. Figure6-27.VREF Routing and Topology 6.4.2.2.11DDR2 CLK and ADDR_CTRL Routing Figure6-28 shows thetopologyoftheroutingfortheCLK and ADDR_CTRL netclasses.The routeisa balancedT as itisintendedthatthelengthofsegments B and C be equal.Inaddition,thelengthofA shouldbe maximized. Figure6-28.CLKand ADDR_CTRL Routing and Topology

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PRODUCT□PREVIEW T T AM3517/05 T DDR2 Controller T AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Table6-31.CLK and ADDR_CTRL Routing Specification(1) No Parameter Min Typ Max Unit Notes

1 CentertocenterDQS-DQSN spacing 2w

2 CK differentialpairSkew LengthMismatch 25 Mils See Note (1)

3 CLKB toCLKC Skew LengthMismatch 25 Mils

4 CentertocenterCLK tootherDDR2 tracespacing 4w See Note (2)

5 CK/ADDR_CTRL nominaltracelength CACLM-50 CACLM CACLM+50 Mils See Note (3)

6 ADDR_CTRL toCLK Skew LengthMismatch 100 Mils

7 ADDR_CTRL toADDR_CTRL Skew LengthMismatch 100 Mils

8 CentertocenterADDR_CTRL tootherDDR2 trace 4w See Note (2)

9 CentertocenterADDR_CTRL tootherADDR_CTRL 3w See Note (2)

10 ADDR_CTRL A toB,ADDR_CTRL A toC, Skew Length 100 Mils See Note (1)

(1) Seriesterminator,ifused,shouldbe locatedclosesttoAM3517/05 . (2) Centertocenterspacingisallowedtofalltominimum (w)forup to500 milsofroutedlengthtoaccommodate BGA escape and routing congestion. (3) CACLM isthelongestManhattandistanceoftheCLK and ADDR_CTRL netclasses. Figure6-29shows thetopologyand routingfortheDQS and Dx netclasses;theroutesarepointtopoint. Skew matchingacrossbytesisnotneeded norrecommended. Figure6-29.DQS and Dx Routing and Topology Copyright© 2009–2010,Texas InstrumentsIncorporated TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 145 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW T T FL FH DDR2 Controller AM3517/05 AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Table6-32.DQS and Dx Routing Specification(1)(2) No. Parameter Min Typ Max Unit Notes

2 DQS E differentialpairSkew LengthMismatch 25 Mils

3 CentertocenterDQS tootherDDR2 tracespacing 4w See Note (3)

4 DQS/Dx nominaltracelength DQLM-50 DQLM DQLM+ Mils See Notes (2),

50 (4)

5 Dx toDQS Skew LengthMismatch 100 Mils See Note (4)

6 Dx toDx Skew LengthMismatch 100 Mils See Note (4)

7 CentertocenterDx tootherDDR2 tracespacing 4w See Notes (3),

(5)

8 CentertoCenterDx tootherDx tracespacing 3w See Notes (6),

(3) (1) "Dx"indicatesa dataline.E indicateslengthofDQS differentialpairorDx signal. (2) Seriesterminator,ifused,shouldbe locatedclosesttoDDR. (3) Centertocenterspacingisallowedtofalltominimum (w)forup to500 milsofroutedlengthtoaccommodate BGA escape and routing congestion. (4) Thereisno need and itisnotrecommended toskew match acrossdatabytes,i.e.,fromDQS0 and databyte0 toDQS1 and databyte (5) Dx's fromotherDQS domains areconsideredotherDDR2 trace. (6) DQLM isthelongestManhattandistanceofeach oftheDQS and Dx netclasses. Figure6-30 shows the routingforthe SDRC_STRBENx net classes.Table 6-33 containsthe routing specification.SDRC_STRBENx netclassesshouldbe shieldedfromorroutedon differentlayersthanthe DQx netclasses. Figure6-30.SDRC_STRBENx Routing

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PRODUCT□PREVIEW AM35x DDR2 vo DDR2 on One Chip Select sdrc_cs0 CS# CS# ODT ODT sdrc_odt DDR2 AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Table6-33.SDRC_STRBENx Routing Specification(1)(2) No. Parameter Min Typ Max Unit Notes

1 SDRC_STRBEN0 LengthF CKB0B1 See Note (3)

SDRC_STRBEN1 LengthF CKB0B2 See Note (4)

3 CentertocenterSDRC_STRBENx toany othertracespacing 4w

4 DQS/Dx nominaltracelength DQLM-50 DQLM DQLM+50 Mils

5 SDRC_STRBENx Skew 100 Mils See Note (5)

(1) STRBENx terminationresistorsshouldbe placedclosetoAM35x STRBENx signal(notclosetoSTRBEN_DLYx signal). (2) Ensuresignalvelocitiesacrossdifferentlayersaretakenintoaccountwhen calculatingSTRBENx length.Forexample,ifDQS0 and DSQ1 are1incheach,and DQS0 ison a layerthatis10% faster,use 1.1inchas thelengthforDQS0. (3) CKB0B1 isthesum ofthelengthoftheCLK (theportionthatgoes tothememory associatedwithDQS0 and DQS1) plustheaverage lengthoftheDQS0 and DQS1 differentialpairs. (4) CKB0B2 isthesum ofthelengthoftheCLK (theportionthatgoes tothememory associatedwithDQS2 and DQS3) plustheaverage lengthoftheDQS2 and DQS3 differentialpairs. (5) Skew fromCKB0B1 orCKB0B2. 6.4.2.2.12On Die Termination(ODT) ODT shouldonlybe used with1 chipselectas shown inFigure6-31. Ifusingsdrc_cs0and sdrc_cs1, sdrc_odtshouldnotbe used.ODT signalsshouldbe tiedoffatthememory. Figure6-31.ODT Connection Using One Chip select(sdrc_cs0) Copyright© 2009–2010,Texas InstrumentsIncorporated TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 147 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

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6.5 Video Interfaces

6.5.1 Video ProcessingSubsystem (VPSS)

The VideoProcessingSub-System (VPSS) providesa VideoProcessingFrontEnd (VPFE) inputinterface forexternalimagingperipherals(i.e.,image sensors,videodecoders,etc.).

6.5.1.1 Video ProcessingFrontEnd (VPFE)

The VideoProcessingFront-End(VPFE) controllerreceivesinputvideo/imagedatafromexternalcapture devicesand storesittoexternalmemory whichistransferredintotheexternalmemory viaa builtinDMA engine.An internalbufferblockprovidesa high bandwidthpath between the VPSS module and the externalmemory. The Cortex-A8willprocesstheimage databased on applicationrequirements.

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PRODUCT□PREVIEW VF1 VDIN_CLK (Falling Edge) VF2 VF7 VF7 VF10 VF8, VF9, VF11VF3, VF4, VF6 VF5 VDIN_CLK (Rising Edge) VDIN_D[xx] VDIN_HD, VDIN_VD, VDIN_FIELD VDIN_WEN SPRS550-001 AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 6.5.1.1.1Video ProcessingFrontEnd (VPFE) Timing The followingtablesassume testingoverrecommended operatingconditions. Table6-34.VPFE Timing Requirements 1.8-V,3.3-V NO. PARAMETER MIN MAX UNIT VF1 tc(VDIN_CLK) Cycletime,pixelclockinput,VDIN_CLK 13.33 100 ns VF2 tsu(VDIN_D-VDIN_CLK) Setuptime,VDIN_D toVDIN_CLK risingedge 3.5 ns VF3 tsu(VDIN_HD-VDIN_CLK) Setuptime,VDIN_HD toVDIN_CLK risingedge 3.5 ns VF4 tsu(VDIN_VD-VDIN_CLK) Setuptime,VDIN_VD toVDIN_CLK risingedge 3.5 ns VF5 tsu(VDIN_WEN-VDIN_CLK) Setuptime,VDIN_WEN toVDIN_CLK risingedge 3.5 ns VF6 tsu(C_FLD-VDIN_CLK) Setuptime,VDIN_FIELD toVDIN_CLK risingedge 3.5 ns VF7 th(VDIN_CLK-VDIN_D) Holdtime,VDIN_D validafterVDIN_CLK risingedge 2.5 ns VF8 th(VDIN-HD-VDIN_CLK) Holdtime,VDIN_HD toVDIN_CLK risingedge 2.5 ns VF9 th(VDIN_VD-VDIN_CLK) Holdtime,VDIN_VD toVDIN_CLK risingedge 2.5 ns VF10 th(VDIN_WEN-VDIN_CLK) Holdtime,VDIN_WEN toVDIN_CLK risingedge 2.5 ns VF11 th(C_FLD-VDIN_CLK) Holdtime,VDIN_FIELD toVDIN_CLK risingedge 2.5 ns Table6-35.VPFE Output SwitchingCharacteristics 1.8-V,3.3-V NO. PARAMETER MIN MAX UNIT VF12 td(VDIN_HD-VDIN_CLK) Outputdelaytime,VDIN_HD toCLK risingedge 10 ns VF13 td(VDIN_VD-VDIN_CLK) Outputdelaytime,VDIN_VD toCLK risingedge 10 ns VF14 td(VDIN_WEN-VDIN_CLK) Outputdelaytime,VDIN_WEN toCLK risingedge 10 ns VF15 toh(VDIN_HD-VDIN_CLK) Outputholdtime,VDIN_HD toCLK risingedge 0.5 ns VF16 toh(VDIN_VD-VDIN_CLK) Outputholdtime,VDIN_VD toCLK risingedge 0.5 ns VF17 toh(C_FLD-VDIN_CLK) Outputholdtime,VDIN_FLD toCLK risingedge 0.5 ns Figure6-32.VPFE0 InputTimings Copyright© 2009–2010,Texas InstrumentsIncorporated TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 149 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW VDIN_CLK (Falling Edge) VF12, VF13, VF14 VDIN_CLK (Rising Edge) VDIN_HD, VDIN_VD, VDIN_FIELD VF15, VF16, VF17 VF12, VF13, VF14 VF15, VF16, VF17 SPRS550-002 VDIN_D[xx] VDIN_HD (Falling Edge) VDIN_HD (Rising Edge) VF19 VF20 VF18 SPRS550-003 AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Figure6-33.VPFE Output Timings Figure6-34.VPFE InputTimings With VDIN0_HD as PixelClock

6.5.2 DisplaySubsystem (DSS)

The displaysubsystem (DSS) providesthe logicto displaythe videoframe from external(SDRAM) or internal(SRAM) memory on an LCD panelora TV set.The DSS integratesa displaycontroller.Itcan be used intwo configurations:

• LCD displaysupportin: – Bypass mode (RFBImodule bypassed) – RFBI mode (throughRFBI module)
• TV displaysupport(notdiscussedinthisdocument because ofitsanalogIO signals) The two displaysupportscan be activeatthesame time.

6.5.2.1 LCD DisplaySupport inBypass Mode

Two typesofLCD panelaresupported:

• Thinfilmtransistor(TFT)oractivematrixtechnology
• Supertwistednematic(STN) orpassivematrixtechnology Bothconfigurationsarediscussedinthefollowingparagraphs. 6.5.2.1.1LCD DisplayinTFT Mode Table6-36assumes testingovertherecommended operatingconditions(seeFigure6-35). Table6-36.LCD DisplayInterfaceSwitchingCharacteristicsinTFT Mode (1) NO. PARAMETER 1.8V,3.3V UNIT MIN MAX DL0 td(PCLKA-HSYNCT) Delaytime,dss_pclkactiveedge todss_hsynctransition -4.215 4.215 ns DL1 td(PCLKA-VSYNCT) Delaytime,dss_pclkactiveedge todss_vsynctransition -4.215 4.215 ns DL2 td(PCLKA-ACBIASA) Delaytime,dss_pclkactiveedge todss_acbiasactivelevel -4.215 4.215 ns DL3 td(PCLKA-DATAV) Delaytime,dss_pclkactiveedge todss_databus valid -4.215 4.215 ns (1) The capacitiveloadisequivalentto25 pF.

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PRODUCT□PREVIEW dss_pclk dss_vsync dss_hsync dss_acbias dss_data[23:0] DL4 DL5 DL3 DL0 DL2 DL1 030-061 AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Table6-36.LCD DisplayInterfaceSwitchingCharacteristicsinTFT Mode (1) (continued) NO. PARAMETER 1.8V,3.3V UNIT MIN MAX DL4 tc(PCLK) Cycletime(2),dss_pclk 13.468 ns DL5 tw(PCLK) Pulseduration,dss_pclkloworhigh 6.06 7.46 ns cload Load capacitance 25 pF (2) The pixelclockfrequencyissoftwareprogrammableviathepixelclockdividerconfigurationfrom1 to255 divisionrangeinthe DISPC_DIVISOR register. Figure6-35.LCD DisplayinTFT Mode (1)(2)(3)(4) (1) The pixeldatabus depends on theuse of8-,9-,12-,16-,18-,or24-bitperpixeldataoutputpins. (2) The pixelclockfrequencyisprogrammable. (3) Alltimingsnotillustratedinthewaveform areprogrammableby software,controlsignalpolarity,and drivenedge ofdss_pclk. (4) Formore information,see theAM35x TechnicalReferenceManual (TRM) [literaturenumber SPRUGR0 ]. 6.5.2.1.2LCD DisplayinSTN Mode Table6-37assumes testingovertherecommended operatingconditions(seeFigure6-36). Table6-37.LCD DisplayInterfaceSwitchingCharacteristicsinSTN Mode (1)(2)(3) NO. PARAMETER 1.8V,3.3V UNIT MIN MAX DL3 td(PCLKA-DATAV) Delaytime,dss_pclkactiveedge todss_databus valid -4.21 6.9 ns DL4 tc(PCLK) Cycletime(4),dss_pclk 22.73 ns DL5 tw(PCLK) Pulseduration,dss_pclkloworhigh 10.23 12.5 ns cload Load capacitance 40 pF (1) The DSS inSTN mode isused with4 or8 pinsonly;unused pixeldatabitsalwaysremainlow. (2) The capacitiveloadisequivalentto40 pF. (3) Formore information,see theAM35x TechnicalReferenceManual (TRM) [literaturenumber SPRUGR0 ]. (4) The pixelclockfrequencyissoftwareprogrammableviathepixelclockdividerconfigurationfrom1 to255 divisionrangeinthe DISPC_DIVISOR register. Copyright© 2009–2010,Texas InstrumentsIncorporated TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 151 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW dss_pclk dss_vsync dss_hsync dss_acbias dss_data[23:0] DL4 DL5 DL3 030-062 AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Figure6-36.LCD DisplayinSTN Mode (1)(2)(3)(4)(5) (1) The pixeldatabus depends on theuse 4-,8-,12-,16-,18-,or24-bitperpixeldataoutputpins. (2) Alltimingsnotillustratedinthewaveform areprogrammableby software,controlsignalpolarity,and drivenedge ofdss_pclk. (3) dss_vsyncwidthmust be programmed tobe as smallas possible. (4) The pixelclockfrequencyisprogrammable. (5) Formore information,see theAM35x TechnicalReferenceManual (TRM) [literaturenumber SPRUGR0 ].

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PRODUCT□PREVIEW AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010

6.6 SerialCommunications Interfaces

6.6.1 MultichannelBufferedSerialPort(McBSP) Timing

There are fiveMcBSP modules calledMcBSP1 throughMcBSP5. McBSP providesa full-duplex,direct serialinterfacebetween theAM3517/05 deviceand otherdevicesina system such as otherapplication devicesorcodecs.Itcan accommodate a wide rangeofperipheralsand clockedframe-orientedprotocols (I2S,PCM, and TDM) due toitshighlevelofversatility. The McBSP1-5 modules may supporttwo typesofdatatransferatthesystemlevel:

• The full-cyclemode, forwhichone clockperiodisused totransferthedata,generatedon one edge and capturedon thesame edge (oneclockperiodlater).
• The half-cyclemode, forwhichone halfclockperiodisused totransferthedata,generatedon one edge and capturedon theoppositeedge (onehalfclockperiodlater).Note thata new datais generatedonlyeveryclockperiod,whichsecurestherequiredholdtime. The interfaceclock(CLKX/CLKR) activationedge (data/framesync captureand generation)has to be configuredaccordinglywiththe externalperipheral(activationedge capability)and the type of data transferrequiredatthesystemlevel. The AM3517/05 McBSP1-5 timingcharacteristicsaredescribedforbothrisingand fallingactivationedges. McBSP1 supports:
• 6-pinmode: dx and dras datapins;clkx,clkr,fsx,and fsras controlpins.
• 4-pinmode: dx and dras datapins;clkxand fsxpinsas controlpins.The clkxand fsxpinsare internallyloopedback viasoftwareconfiguration,respectively,totheclkrand fsrinternalsignalsfor datareceive. McBSP2, 3,4,and 5 supportonlythe4-pinmode. The followingsectionsdescribethe timingcharacteristicsforapplicationsin normal mode (thatis, AM3517/05 McBSPx connectedtoone peripheral)and TDM applicationsinmultipointmode.

6.6.1.1 McBSP inNormal Mode

The followingtablesassume=testingovertherecommended operatingconditions. Table6-38.McBSP Timing Conditions TIMING CONDITION PARAMETER 1.8V,3.3V UNIT InputConditions VALUE tR Inputsignalrisetime 2 ns tF Inputsignalfalltime 2 ns Output Conditions C LOAD Outputload 10 pF capacitance Table6-39.McBSP1,2,4,5Output Clock Pulse Duration PARAMETER VDDSHV = 1.8V,3.3V UNIT MIN MAX tC(CLK) CycleTime, 20.83 ns mcbsp1_clkr/mcbspx_clkx (1) tW(CLKH) Typicalpulseduration, 0.5*P(2) 0.5*P(2) ns mcbsp1_clkr/ mcbspx_clkxhigh(1) (1) Inmcbspx,x identifiestheMcBSP number;1,2,4,or5. (2) P = mcbsp1_clkr/mcbspx_clkxclockperiod. Copyright© 2009–2010,Texas InstrumentsIncorporated TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 153 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Table6-39.McBSP1,2,4,5Output Clock Pulse Duration(continued) PARAMETER VDDSHV = 1.8V,3.3V UNIT tW(CLKL) Typicalpulseduration, 0.5*P(2) 0.5*P(2) ns mcbsp1_clkr/ mcbspx_clkxlow(1) tdc(CLK) Dutycycleerror, -0.75 0.75 ns mcbsp1_clkr/ mcbspx_clkx(1) Table6-40.McBSP3 Output Clock Pulse Duration PARAMETER VDDSHV = 1.8V,3.3V UNIT MIN MAX tC(CLK) Cycletime,mcbsp3_clkx 31.25 ns tW(CLKH) Typicalpulseduration, 0.5*P(1) 0.5*P(1) ns mcbsp3_clkxhigh tW(CLKL) Typicalpulseduration, 0.5*P(1) 0.5*P(1) ns mcbsp3_clkxlow tdc(CLK) Dutycycleerror, -0.75 0.75 ns mcbsp3_clkx (1) P = mcbsp3_clkxclockperiod 6.6.1.1.1McBSP1 The followingtablesshow thetimingrequirementsand switchingcharacteristicsforMcBSP1. Table6-41.McBSP1 Timing Requirements -RisingEdge and Receive Mode No. PARAMETER VDDSHV=3.3V VDDSHV=1.8V UNIT MIN MAX MIN MAX B3 tsu(DRV- Setuptime, HalfCycle 5.0 5.0 ns CLKAE) mcbsp1_dr Master validbefore HalfCycle 5.2 5.2 nsmcbsp1_clkr/ Slavemcbsp1_clkx activeedge FullCycle 4.0 4.0 ns Master FullCycle 4.2 4.2 ns Slave B4 th(CLKAE- Holdtime, HalfCycle 5.8 5.8 ns DRV) mcbsp1_dr Master validafter HalfCycle 5.2 5.2 nsmcbsp1_clkr/ Slavemcbsp1_clkx activeedge FullCycle 1.5 1.5 ns Master FullCycle 0.9 0.9 ns Slave B5 tsu(FSV- Setuptime, HalfCycle 5.2 5.2 ns CLKAE) mcbsp1_fsr/ Slave mcbsp1_fsx FullCycle 4.2 4.2 nsvalidbefore Slavemcbsp1_clkr/ mcbsp1_clkx activeedge B6 th(CLKAE-FSV) Holdtime, HalfCycle 0.5 0.5 ns mcbsp1_fsr/ Slave mcbsp1_fsx FullCycle 1.0 1.0 nsvalidafter Slavemcbsp1_clkr/ mcbsp1_clkx activeedge

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PRODUCT□PREVIEW AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Table6-42.McBSP1 SwitchingCharacteristics-RisingEdge and Receive Mode No. PARAMETER VDDSHV=3.3V VDDSHV=1.8V UNIT MIN MAX MIN MAX B2 td(CLKAE-FSV) Delaytime, 0.2 14.8 0.2 14.8 ns mcbsp1_clkr activeedge to mcbsp1_fsr/ mcbsp1_fsx valid Table6-43.McBSP1 Timing Requirements -RisingEdge and TransmitMode No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT MIN MAX MIN MAX B5 tsu(FSXV- Setuptime, FullCycle 5.2 4.7 ns CLKXAE) mcbsp1_fsx Slave validbefore HalfCycle 4.2 3.7 nsmcbsp1_clkx Slaveactiveedge B6 th(CLKXAE- Holdtime, FullCycle 5.2 4.7 ns FSXV) mcbsp1_fsx Slave validafter HalfCycle 1.0 0.5 nsmcbsp1_clkx Slaveactiveedge Table6-44.McBSP1 SwitchingCharacteristics-RisingEdge and TransmitMode No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT MIN MAX MIN MAX B2 td(CLKXAE- Delaytime, 0.2 14.8 0.7 14.8 ns FSXV) mcbsp1_clkx activeedge to mcbsp1_fsx valid B8 td(CLKXAE- Delaytime, Master 0.6 14.8 0.6 14.8 ns DXV) mcbsp1_clkx Slave 0.6 14.8 0.6 14.8 nsactiveedge to mcbsp1_dx valid Table6-45.McBSP1 Timing Requirements -FallingEdge and Receive Mode No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT MIN MAX MIN MAX B3 tsu(DRV- Setuptime, HalfCycle 5.0 5.0 ns CLKAE) mcbsp1_dr Master validbefore HalfCycle 5.2 5.2 nsmcbsp1_clkr/ Slavemcbsp1_clkx activeedge FullCycle 4.0 4.0 ns Master FullCycle 4.2 4.2 ns Slave B4 th(CLKAE- Holdtime, HalfCycle 5.8 5.8 ns DRV) mcbsp1_dr Master validafter HalfCycle 5.2 5.2 nsmcbsp1_clkr/ Slavemcbsp1_clkx activeedge FullCycle 1.5 1.5 ns Master FullCycle 0.9 0.9 ns Slave Copyright© 2009–2010,Texas InstrumentsIncorporated TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 155 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Table6-45.McBSP1 Timing Requirements -FallingEdge and Receive Mode (continued) No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT B5 tsu(FSV- Setuptime, HalfCycle 5.2 5.2 ns CLKAE) mcbsp1_fsr/ Slave mcbsp1_fsx FullCycle 4.2 4.2 nsvalidbefore Slavemcbsp1_clkr/ mcbsp1_clkx activeedge B6 th(CLKAE-FSV) Holdtime, HalfCycle 0.5 0.5 ns mcbsp1_fsr/ Slave mcbsp1_fsx FullCycle 1.0 1.0 nsvalidafter Slavemcbsp1_clkr/ mcbsp1_clkx activeedge Table6-46.McBSP1 SwitchingCharacteristics-FallingEdge and Receive Mode No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT MIN MAX MIN MAX B2 td(CLKAE-FSV) Delaytime,mcbsp1_clkr/ 0.2 14.8 0.7 14.8 ns mcbsp1_clkxactiveedge to mcbsp1_fsr/mcbsp1_fsxvalid Table6-47.McBSP1 Timing Requirements -FallingEdge and TransmitMode No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT MIN MAX MIN MAX B5 tsu(FSXV- Setuptime, HalfCycle 5.2 5.2 ns CLKXAE) mcbsp1_fsx Slave validbefore FullCycle 4.2 4.2 nsmcbsp1_clkx Slaveactiveedge B6 th(CLKXAE- Holdtime, HalfCycle 5.2 5.2 ns FSXV) mcbsp1_fsx Slave validafter FullCycle 1.0 1.0 nsmcbsp1_clkx Slaveactiveedge Table6-48.McBSP1 SwitchingCharacteristics-FallingEdge and TransmitMode No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT MIN MAX MIN MAX B2 td(CLKXAE- Delaytime, 0.2 14.8 0.2 14.8 ns FSXV) mcbsp1_clkx activeedge to mcbsp1_fsx valid B8 td(CLKXAE- Delaytime, Master 0.6 14.8 0.6 14.8 ns DXV) mcbsp1_clkx Slave 0.6 14.8 0.6 14.8 nsactiveedge to mcbsp1_dx valid

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PRODUCT□PREVIEW AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 6.6.1.1.2McBSP2 The followingtablesshow thetimingrequirementsand switchingcharacteristicsforMcBSP2. Table6-49.McBSP2 Timing Requirements -RisingEdge and Receive Mode No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT MIN MAX MIN MAX B3 tsu(DRV- Setuptime, HalfCycle 5.0 5.0 ns CLKXAE) mcbsp2_dr Master validbefore HalfCycle 5.2 5.2 nsmcbsp2_clkx Slaveactiveedge FullCycle 4.2 4.2 ns Master FullCycle 4.2 4.2 ns Slave B4 th(CLKXAE- Holdtime, HalfCycle 5.8 5.8 ns DRV) mcbsp2_dr Master validafter HalfCycle 5.2 5.2 nsmcbsp2_clkx Slaveactiveedge FullCycle 1.5 1.5 ns Master FullCycle 0.9 0.9 ns Slave B5 tsu(FSV- Setuptime, HalfCycle 5.2 5.2 ns CLKXAE) mcbsp2_fsx Slave validbefore FullCycle 4.2 4.2 nsmcbsp2_clkx Slaveactiveedge B6 th(CLKXAE- Holdtime, HalfCycle 5.2 5.2 ns FSV) mcbsp2_fsx Slave validafter FullCycle 1.0 1.0 nsmcbsp2_clkx Slaveactiveedge Table6-50.McBSP2 SwitchingCharacteristics-RisingEdge and Receive Mode No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT MIN MAX MIN MAX B2 td(CLKXAE- Delaytime, 0.2 14.8 0.2 14.8 ns FSXV) mcbsp2_clkx activeedge to mcbsp2_fsx valid Table6-51.McBSP2 Timing Requirements -RisingEdge and TransmitMode No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT MIN MAX MIN MAX B5 tsu(FSXV- Setuptime, HalfCycle 5.2 4.7 ns CLKXAE) mcbsp2_fsx Slave validbefore FullCycle 4.2 3.7 nsmcbsp2_clkx Slaveactiveedge B6 th(CLKXAE- Holdtime, HalfCycle 5.2 4.7 ns FSXV) mcbsp2_fsx Slave validafter FullCycle 1.0 0.5 nsmcbsp2_clkx Slaveactiveedge Copyright© 2009–2010,Texas InstrumentsIncorporated TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 157 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Table6-52.McBSP2 SwitchingCharacteristics-RisingEdge and TransmitMode No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT MIN MAX MIN MAX B2 td(CLKXAE- Delaytime, 0.2 14.8 0.2 14.8 ns FSXV) mcbsp2_clkx activeedge to mcbsp2_fsx valid B8 td(CLKXAE- Delaytime, Master 0.6 14.8 0.6 14.8 ns DXV) mcbsp2_clkx Slave 0.6 14.8 0.6 14.8 nsactiveedge to mcbsp2_dx valid Table6-53.McBSP2 Timing Requirements -FallingEdge and Receive Mode No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT MIN MAX MIN MAX B3 tsu(DRV- Setuptime, HalfCycle 5.0 5.0 ns CLKXAE) mcbsp2_dr Master validbefore HalfCycle 5.2 5.2 nsmcbsp2_clkx Slaveactiveedge FullCycle 4.2 4.2 ns Master FullCycle 4.2 4.2 ns Slave B4 th(CLKXAE- Holdtime, HalfCycle 5.8 5.8 ns DRV) mcbsp2_dr Master validafter HalfCycle 5.2 5.2 nsmcbsp2_clkx Slaveactiveedge FullCycle 1.5 1.5 ns Master FullCycle 0.9 0.9 ns Slave B5 tsu(FSXV- Setuptime, HalfCycle 5.2 5.2 ns CLKXAE) mcbsp2_fsx Slave validbefore FullCycle 4.2 4.2 nsmcbsp2_clkx Slaveactiveedge B6 th(CLKXAE- Holdtime, HalfCycle 5.2 5.2 ns FSXV) mcbsp2_fsx Slave validafter FullCycle 1.0 1.0 nsmcbsp2_clkx Slaveactiveedge Table6-54.McBSP2 SwitchingCharacteristics-FallingEdge and Receive Mode No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT MIN MAX MIN MAX B2 td(CLKXAE- Delaytime,mcbsp2_clkxactive 0.2 14.8 0.2 14.8 ns FSXV) edge tomcbsp2_fsxvalid Table6-55.McBSP2 Timing Requirements -FallingEdge and TransmitMode No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT MIN MAX MIN MAX B5 tsu(FSXV- Setuptime, HalfCycle 5.2 5.2 ns CLKXAE) mcbsp2_fsx Slave validbefore FullCycle 4.2 4.2 nsmcbsp2_clkx Slaveactiveedge B6 th(CLKXAE- Holdtime, HalfCycle 5.2 5.2 ns FSXV) mcbsp2_fsx Slave validafter FullCycle 1.0 1.0 nsmcbsp2_clkx Slaveactiveedge

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PRODUCT□PREVIEW AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Table6-56.McBSP2 SwitchingCharacteristics-FallingEdge and TransmitMode No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT MIN MAX MIN MAX B2 td(CLKXAE- Delaytime,mcbsp2_clkxactive 0.2 14.8 0.2 14.8 ns FSXV) edge tomcbsp2_fsxvalid B8 td(CLKXAE- Delaytime, Master 0.6 14.8 0.6 14.8 ns DXV) mcbsp2_clkx Slave 0.6 14.8 0.6 14.8 nsactiveedge to mcbsp2_dx valid 6.6.1.1.3McBSP3 The followingtablesshow thetimingconditionsand switchingcharacteristicsforMcBSP3 multiplexedon McBSP3 pins. Note:AlltimingsapplyonlytoSet#1-multiplexingon mcbsp3 pins. Table6-57.McBSP3 (Set#1)Timing Requirements -RisingEdge and Receive Mode No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT MIN MAX MIN MAX B3 tsu(DRV- Setuptime, HalfCycle 7.5 7.5 ns CLKXAE) mcbsp3_dr Master validbefore HalfCycle 7.7 7.7 nsmcbsp3_clkx Slaveactiveedge FullCycle 5.6 5.6 ns Master FullCycle 5.8 5.8 ns Slave B4 th(CLKXAE- Holdtime, HalfCycle 8.3 8.3 ns DRV) mcbsp3_dr Master validafter HalfCycle 7.7 7.7 nsmcbsp3_clkx Slaveactiveedge FullCycle 1.5 1.5 ns Master FullCycle 0.9 0.9 ns Slave B5 tsu(FSV- Setuptime, HalfCycle 7.7 7.7 ns CLKXAE) mcbsp3_fsx Slave validbefore FullCycle 5.8 5.8 nsmcbsp3_clkx Slaveactiveedge B6 th(CLKXAE- Holdtime, HalfCycle 7.7 7.7 ns FSV) mcbsp3_fsx Slave validafter FullCycle 1.0 1.0 nsmcbsp3_clkx Slaveactiveedge Table6-58.McBSP3 (Set#1)SwitchingCharacteristics-RisingEdge and Receive Mode No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT MIN MAX MIN MAX B2 td(CLKXAE- Delaytime,mcbsp3_clkxactive 0.2 22.2 0.2 22.2 ns FSXV) edge tomcbsp3_fsxvalid Copyright© 2009–2010,Texas InstrumentsIncorporated TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 159 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Table6-59.McBSP3 (Set#1)Timing Requirements -RisingEdge and TransmitMode No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT MIN MAX MIN MAX B5 tsu(FSXV- Setuptime, HalfCycle 7.7 7.7 ns CLKXAE) mcbsp3_fsx Slave validbefore FullCycle 5.8 5.8 nsmcbsp3_clkx Slaveactiveedge B6 th(CLKXAE- Holdtime, HalfCycle 7.7 7.7 ns FSXV) mcbsp3_fsx Slave validafter FullCycle 1 1 nsmcbsp3_clkx Slaveactiveedge Table6-60.McBSP3 (Set#1)SwitchingCharacteristics-RisingEdge and TransmitMode No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT MIN MAX MIN MAX B2 td(CLKXAE- Delaytime,mcbsp3_clkxactive 0.2 22.2 0.2 22.2 ns FSXV) edge tomcbsp3_fsxvalid B8 td(CLKXAE- Delaytime, Master 0.6 22.2 0.6 22.2 ns DXV) mcbsp3_clkx Slave 0.6 22.2 0.6 22.2 nsactiveedge to mcbsp3_dx valid Table6-61.McBSP3 (Set#1)Timing Requirements -FallingEdge and Receive Mode No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT MIN MAX MIN MAX tsu(DRV- Setuptime, HalfCycle 7.5 7.5 ns CLKXAE) mcbsp3_dr Master validbefore HalfCycle 7.7 7.7 nsmcbsp3_clkx Slaveactiveedge FullCycle 5.6 5.6 ns Master FullCycle 5.8 5.8 ns Slave th(CLKXAE- Holdtime, HalfCycle 8.3 8.3 ns DRV) mcbsp3_dr Master validafter HalfCycle 7.7 7.7 nsmcbsp3_clkx Slaveactiveedge FullCycle 1.5 1.5 ns Master FullCycle 0.9 0.9 ns Slave B5 tsu(FXSV- Setuptime, HalfCycle 7.7 7.7 ns CLKXAE) mcbsp3_fsx Slave validbefore FullCycle 5.8 5.8 nsmcbsp3_clkx Slaveactiveedge B6 th(CLKXAE- Holdtime, HalfCycle 7.7 7.7 ns FSXV) mcbsp3_fsx Slave validafter FullCycle 1.0 1.0 nsmcbsp3_clkx Slaveactiveedge Table6-62.McBSP3 (Set#1)SwitchingCharacteristics-FallingEdge and Receive Mode No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT MIN MAX MIN MAX B2 td(CLKXAE- Delaytime,mcbsp3_clkxactive 0.2 22.2 0.2 22.2 ns FSXV) edge tomcbsp3_fsxvalid

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PRODUCT□PREVIEW AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Table6-63.McBSP3 (Set#1)Timing Requirements -FallingEdge and TransmitMode No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT MIN MAX MIN MAX B5 tsu(FSXV- Setuptime, HalfCycle 5.2 5.2 ns CLKXAE) mcbsp3_fsx Slave validbefore FullCycle 4.2 4.2 nsmcbsp3_clkx Slaveactiveedge B6 th(CLKXAE- Holdtime, HalfCycle 5.2 5.2 ns FSXV) mcbsp3_fsx Slave validafter FullCycle 1.0 1.0 nsmcbsp3_clkx Slaveactiveedge Table6-64.McBSP3 (Set#1)SwitchingCharacteristics-FallingEdge and TransmitMode No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT MIN MAX MIN MAX B2 td(CLKXAE- Delaytime,mcbsp3_clkxactive 0.2 22.2 0.2 22.2 ns FSXV) edge tomcbsp3_fsxvalid B8 td(CLKXAE- Delaytime, Master 0.6 22.2 0.6 22.2 ns DXV) mcbsp3_clkx Slave 0.6 22.2 0.6 22.2 nsactiveedge to mcbsp3_dx valid The followingtablesshow thetimingconditionsand switchingcharacteristicsforMcBSP3 multiplexedon UART2 orMcBSP1 pins. Note:These timingsonlyapplytoSet #2 (multiplexingmode on uart2pins)and Set #3 (multiplexingon mcbsp1 pins). Table6-65.McBSP3 (Sets#2 and #3)Timing Requirements -RisingEdge and Receive Mode No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT MIN MAX MIN MAX B3 tsu(DRV- Setuptime, HalfCycle 5.0 5.0 ns CLKXAE) mcbsp3_dr Master validbefore HalfCycle 5.2 5.2 nsmcbsp3_clkx Slaveactiveedge FullCycle 4.2 4.2 ns Master FullCycle 4.2 4.2 ns Slave B4 th(CLKXAE- Holdtime, HalfCycle 5.8 5.8 ns DRV) mcbsp3_dr Master validafter HalfCycle 5.2 5.2 nsmcbsp3_clkx Slaveactiveedge FullCycle 1.5 1.5 ns Master FullCycle 0.9 0.9 ns Slave B5 tsu(FSV- Setuptime, HalfCycle 5.2 5.2 ns CLKXAE) mcbsp3_fsx Slave validbefore FullCycle 4.2 4.2 nsmcbsp3_clkx Slaveactiveedge B6 th(CLKXAE- Holdtime, HalfCycle 5.2 5.2 ns FSV) mcbsp3_fsx Slave validafter FullCycle 1.0 1.0 nsmcbsp3_clkx Slaveactiveedge Copyright© 2009–2010,Texas InstrumentsIncorporated TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 161 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Table6-66.McBSP3 (Sets#2 and #3)SwitchingCharacteristics-RisingEdge and Receive Mode No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT MIN MAX MIN MAX B2 td(CLKXAE- Delaytime, 0.2 14.8 0.2 14.8 ns FSXV) mcbsp3_clkx activeedge to mcbsp3_fsx valid Table6-67.McBSP3 (Sets#2 and #3)Timing Requirements -RisingEdge and TransmitMode No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT MIN MAX MIN MAX B5 tsu(FSXV- Setuptime, HalfCycle 5.2 5.2 ns CLKXAE) mcbsp3_fsx Slave validbefore FullCycle 4.2 4.2 nsmcbsp3_clkx Slaveactiveedge B6 th(CLKXAE- Holdtime, HalfCycle 5.2 5.2 ns FSXV) mcbsp3_fsx Slave validafter FullCycle 1.0 1.0 nsmcbsp3_clkx Slaveactiveedge Table6-68.McBSP3 (Sets#2 and #3)SwitchingCharacteristics-RisingEdge and TransmitMode No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT MIN MAX MIN MAX B2 td(CLKXAE- Delaytime,mcbsp3_clkxactive 0.2 14.8 0.2 14.8 ns FSXV) edge tomcbsp3_fsxvalid B8 td(CLKXAE- Delaytime, Master 0.6 14.8 0.6 14.8 ns DXV) mcbsp3_clkx Slave 0.6 14.8 0.6 14.8 nsactiveedge to mcbsp3_dx valid Table6-69.McBSP3 (Sets#2 and #3)Timing Requirements -FallingEdge and Receive Mode No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT MIN MAX MIN MAX B3 tsu(DRV- Setuptime, HalfCycle 5.0 5.0 ns CLKXAE) mcbsp3_dr Master validbefore HalfCycle 5.2 5.2 nsmcbsp3_clkx Slaveactiveedge FullCycle 4.2 4.2 ns Master FullCycle 4.2 4.2 ns Slave B4 th(CLKXAE- Holdtime, HalfCycle 5.8 5.8 ns DRV) mcbsp3_dr Master validafter HalfCycle 5.2 5.2 nsmcbsp3_clkx Slaveactiveedge FullCycle 1.5 1.5 ns Master FullCycle 0.9 0.9 ns Slave B5 tsu(FXSV- Setuptime, HalfCycle 5.2 5.2 ns CLKXAE) mcbsp3_fsx Slave validbefore FullCycle 4.2 4.2 nsmcbsp3_clkx Slaveactiveedge B6 th(CLKXAE- Holdtime, HalfCycle 5.2 5.2 ns FSXV) mcbsp3_fsx Slave validafter FullCycle 1.0 1.0 nsmcbsp3_clkx Slaveactiveedge

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PRODUCT□PREVIEW AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Table6-70.McBSP3 (Sets#2 and #3)SwitchingCharacteristics-FallingEdge and Receive Mode No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT MIN MAX MIN MAX B2 td(CLKXAE- Delaytime,mcbsp3_clkxactive 0.2 14.8 0.2 14.8 ns FSXV) edge tomcbsp3_fsxvalid Table6-71.McBSP3 (Sets#2 and #3)Timing Requirements -FallingEdge and TransmitMode No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT MIN MAX MIN MAX B5 tsu(FSXV- Setuptime, HalfCycle 5.2 5.2 ns CLKXAE) mcbsp3_fsx Slave validbefore FullCycle 4.2 4.2 nsmcbsp3_clkx Slaveactiveedge B6 th(CLKXAE- Holdtime, HalfCycle 5.2 5.2 ns FSXV) mcbsp3_fsx Slave validafter FullCycle 1.0 1.0 nsmcbsp3_clkx Slaveactiveedge Table6-72.McBSP3 (Sets#2 and #3)SwitchingCharacteristics-FallingEdge and TransmitMode No. PARAMETER VDDSHV = 3.3V VDDSHV = 1 .8V UNIT MIN MAX MIN MAX B2 td(CLKXAE- Delaytime,mcbsp3_clkxactive 0.2 14.8 0.2 14.8 ns FSXV) edge tomcbsp3_fsxvalid B8 td(CLKXAE- Delaytime, Master 0.6 14.8 0.6 14.8 ns DXV) mcbsp3_clkx activeedge to mcbsp3_dx valid Slave 0.6 14.8 0.6 14.8 ns 6.6.1.1.4McBSP4 The followingtablesshow thetimingrequirementsand switchingcharacteristicsforMcBSP4. Table6-73.McBSP4 Timing Requirements -RisingEdge and Receive Mode No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT MIN MAX MIN MAX B3 tsu(DRV- Setuptime, HalfCycle 7.5 7.5 ns CLKXAE) mcbsp4_dr Master validbefore HalfCycle 7.7 7.7 nsmcbsp4_clkx Slaveactiveedge FullCycle 3.2 3.2 ns Master FullCycle 4.2 4.2 ns Slave B4 th(CLKXAE- Holdtime, HalfCycle 7.7 7.7 ns DRV) mcbsp4_dr Master validafter HalfCycle 5.2 5.2 nsmcbsp4_clkx Slaveactiveedge FullCycle 1.5 1.5 ns Master FullCycle 0.9 0.9 ns Slave B5 tsu(FSV- Setuptime, HalfCycle 7.7 7.7 ns CLKXAE) mcbsp4_fsx Slave validbefore FullCycle 4.2 4.2 nsmcbsp4_clkx Slaveactiveedge Copyright© 2009–2010,Texas InstrumentsIncorporated TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 163 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Table6-73.McBSP4 Timing Requirements -RisingEdge and Receive Mode (continued) No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT B6 th(CLKXAE- Holdtime, HalfCycle 5.2 5.2 ns FSV) mcbsp4_fsx Slave validafter FullCycle 1.0 1.0 nsmcbsp4_clkx Slaveactiveedge Table6-74.McBSP4 SwitchingCharacteristics-RisingEdge and Receive Mode No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT MIN MAX MIN MAX B2 td(CLKXAE- Delaytime, 0.2 16.6 0.2 16.6 ns FSXV) mcbsp4_clkx activeedge to mcbsp4_fsx valid Table6-75.McBSP4 Timing Requirements -RisingEdge and TransmitMode No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT MIN MAX MIN MAX B5 tsu(FSXV- Setuptime, HalfCycle 7.7 7.7 ns CLKXAE) mcbsp4_fsx Slave validbefore FullCycle 3.7 3.7 nsmcbsp4_clkx Slaveactiveedge B6 th(CLKXAE- Holdtime, HalfCycle 1.0 1.0 ns FSXV) mcbsp4_fsx Slave validafter FullCycle 1.0 1.0 nsmcbsp4_clkx Slaveactiveedge Table6-76.McBSP4 SwitchingCharacteristics-RisingEdge and TransmitMode No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT MIN MAX MIN MAX B2 td(CLKXAE- Delaytime, 0.2 16.6 0.2 16.6 ns FSXV) mcbsp4_clkx activeedge to mcbsp4_fsx valid B8 td(CLKXAE- Delaytime, Master 0.6 16.6 0.6 16.6 ns DXV) mcbsp4_clkx Slave 0.6 17.3 0.6 17.3 nsactiveedge to mcbsp4_dx valid Table6-77.McBSP4 Timing Requirements -FallingEdge and Receive Mode No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT MIN MAX MIN MAX B3 tsu(DRV- Setuptime, HalfCycle 7.5 7.5 ns CLKXAE) mcbsp4_dr Master validbefore HalfCycle 7.7 7.7 nsmcbsp4_clkx Slaveactiveedge FullCycle 5.6 5.6 ns Master FullCycle 5.8 5.8 ns Slave

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PRODUCT□PREVIEW AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Table6-77.McBSP4 Timing Requirements -FallingEdge and Receive Mode (continued) No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT B4 th(CLKXAE- Holdtime, HalfCycle 7.7 7.7 ns DRV) mcbsp4_dr Master validafter HalfCycle 5.2 5.2 nsmcbsp4_clkx Slaveactiveedge FullCycle 1.5 1.5 ns Master FullCycle 0.9 0.9 ns Slave B5 tsu(FXSV- Setuptime, HalfCycle 7.7 7.7 ns CLKXAE) mcbsp4_fsx Slave validbefore FullCycle 5.8 5.8 nsmcbsp4_clkx Slaveactiveedge B6 th(CLKXAE- Holdtime, HalfCycle 5.2 5.2 ns FSXV) mcbsp4_fsx Slave validafter mcbsp4_clkx activeedge FullCycle 1.0 1.0 ns Slave Table6-78.McBSP4 SwitchingCharacteristics-FallingEdge and Receive Mode No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT MIN MAX MIN MAX B2 td(CLKXAE- Delaytime,mcbsp4_clkxactive 0.2 16.6 0.2 16.6 ns FSXV) edge tomcbsp4_fsxvalid Table6-79.McBSP4 Timing Requirements -FallingEdge and TransmitMode No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT MIN MAX MIN MAX B5 tsu(FSXV- Setuptime, HalfCycle 7.7 7.7 ns CLKXAE) mcbsp4_fsx Slave validbefore FullCycle 3.7 3.7 nsmcbsp4_clkx Slaveactiveedge B6 th(CLKXAE- Holdtime, HalfCycle 5.2 5.2 ns FSXV) mcbsp4_fsx Slave validafter FullCycle 1.0 1.0 nsmcbsp4_clkx Slaveactiveedge Table6-80.McBSP4 SwitchingCharacteristics-FallingEdge and TransmitMode No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT MIN MAX MIN MAX B2 td(CLKXAE- Delaytime,mcbsp4_clkxactive 0.2 16.6 0.2 16.6 ns FSXV) edge tomcbsp4_fsxvalid B8 td(CLKXAE- Delaytime, Master 0.6 16.6 0.6 16.6 ns DXV) mcbsp4_clkx activeedge to Slave 0.6 17.3 0.6 17.3 nsmcbsp4_dx valid Copyright© 2009–2010,Texas InstrumentsIncorporated TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 165 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com 6.6.1.1.5McBSP5 The followingtablesshow thetimingconditionsand switchingcharacteristicsforMcBSP5. Table6-81.McBSP5 Timing Requirements -RisingEdge and Receive Mode No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT MIN MAX MIN MAX B3 tsu(DRV- Setuptime, HalfCycle 7.5 7.5 ns CLKXAE) mcbsp5_dr Master validbefore HalfCycle 7.7 7.7 nsmcbsp5_clkx Slaveactiveedge FullCycle 5.6 5.6 ns Master FullCycle 5.8 5.8 ns Slave B4 th(CLKXAE- Holdtime, HalfCycle 7.5 7.5 ns DRV) mcbsp5_dr Master validafter HalfCycle 7.7 7.7 nsmcbsp5_clkx Slaveactiveedge FullCycle 1.5 1.5 ns Master FullCycle 0.9 0.9 ns Slave B5 tsu(FSV- Setuptime, HalfCycle 7.7 7.7 ns CLKXAE) mcbsp5_fsx Slave validbefore FullCycle 5.8 5.8 nsmcbsp5_clkx Slaveactiveedge B6 th(CLKXAE- Holdtime, HalfCycle 7.7 7.7 ns FSV) mcbsp5_fsx Slave validafter FullCycle 1.0 1.0 nsmcbsp5_clkx Slaveactiveedge Table6-82.McBSP5 SwitchingCharacteristics-RisingEdge and Receive Mode No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT MIN MAX MIN MAX B2 td(CLKXAE- Delaytime,mcbsp5_clkxactive 0.2 14.8 0.7 14.8 ns FSXV) edge tomcbsp5_fsxvalid Table6-83.McBSP5 Timing Requirements -RisingEdge and TransmitMode No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT MIN MAX MIN MAX B5 tsu(FSXV- Setuptime, HalfCycle 7.7 7.7 ns CLKXAE) mcbsp5_fsx Slave validbefore FullCycle 5.8 5.8 nsmcbsp5_clkx Slaveactiveedge B6 th(CLKXAE- Holdtime, HalfCycle 7.7 7.7 ns FSXV) mcbsp5_fsx Slave validafter FullCycle 1.0 1.0 nsmcbsp5_clkx Slaveactiveedge Table6-84.McBSP5 SwitchingCharacteristics-RisingEdge and TransmitMode No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT MIN MAX MIN MAX B2 td(CLKXAE- Delaytime, 0.2 14.8 0.2 14.8 ns FSXV) mcbsp5_clkx activeedge to mcbsp5_fsx valid

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PRODUCT□PREVIEW AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Table6-84.McBSP5 SwitchingCharacteristics-RisingEdge and TransmitMode (continued) No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT B8 td(CLKXAE- Delaytime, Master 0.6 14.8 0.6 14.8 ns DXV) mcbsp5_clkx Slave 0.6 14.8 0.6 14.8 nsactiveedge to mcbsp5_dx valid Table6-85.McBSP5 Timing Requirements -FallingEdge and Receive Mode No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT MIN MAX MIN MAX B3 tsu(DRV- Setuptime, HalfCycle 7.5 7.5 ns CLKXAE) mcbsp5_dr Master validbefore HalfCycle 7.7 7.7 nsmcbsp5_clkx Slaveactiveedge FullCycle 5.6 5.6 ns Master FullCycle 5.8 5.8 ns Slave B4 th(CLKXAE- Holdtime, HalfCycle 8.3 8.3 ns DRV) mcbsp5_dr Master validafter HalfCycle 7.7 7.7 nsmcbsp5_clkx Slaveactiveedge FullCycle 1.5 1.5 ns Master FullCycle 0.9 0.9 ns Slave B5 tsu(FXSV- Setuptime, HalfCycle 7.7 7.7 ns CLKXAE) mcbsp5_fsx Slave validbefore FullCycle 5.8 5.8 nsmcbsp5_clkx Slaveactiveedge B6 th(CLKXAE- Holdtime, HalfCycle 7.7 7.7 ns FSXV) mcbsp5_fsx Slave validafter FullCycle 1.0 1.0 nsmcbsp5_clkx Slaveactiveedge Table6-86.McBSP5 SwitchingCharacteristics-FallingEdge and Receive Mode No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT MIN MAX MIN MAX B2 td(CLKXAE- Delaytime,mcbsp5_clkxactive 0.2 22.2 0.2 22.2 ns FSXV) edge tomcbsp5_fsxvalid Table6-87.McBSP5 Timing Requirements -FallingEdge and TransmitMode No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT MIN MAX MIN MAX B5 tsu(FSXV- Setuptime, HalfCycle 7.7 7.7 ns CLKXAE) mcbsp5_fsx Slave validbefore FullCycle 5.8 5.8 nsmcbsp5_clkx Slaveactiveedge B6 th(CLKXAE- Holdtime, HalfCycle 7.7 7.7 ns FSXV) mcbsp5_fsx Slave validafter FullCycle 1.0 1.0 nsmcbsp5_clkx Slaveactiveedge Copyright© 2009–2010,Texas InstrumentsIncorporated TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 167 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW mcbspx_clkr mcbspx_fsr mcbspx_dr D7 D6 D5 B2 B2 B3 B4 030-068 AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Table6-88.McBSP5 SwitchingCharacteristics-FallingEdge and TransmitMode No. PARAMETER VDDSHV = 3.3V VDDSHV = 1.8V UNIT MIN MAX MIN MAX B2 td(CLKXAE- Delaytime, 0.2 22.2 0.2 22.2 ns FSXV) mcbsp5_clkx activeedge to mcbsp5_fsx valid B8 td(CLKXAE- Delaytime, Master 0.6 22.2 0.6 22.2 ns DXV) mcbsp5_clkx Slave 0.6 22.2 0.6 22.2 nsactiveedge to mcbsp5_dx valid 6.6.1.1.6McBSP inTDM Mode The followingtablesassume=testingovertherecommended operatingconditions. Table6-89.McBSP Timing Conditions– TDM inMultipointMode PARAMETER DESCRIPTION VDDSHV = 1.8Vor 3.3V UNIT MIN MAX tr Inputsignalrisetime 1 8.5 ns tf Inputsignalfalltime 1 8.5 ns Cload Outputloadcapacitance 40 pf Table6-90.McBSP Timing Requirements — TDM inMultipointMode INDEX PARAMETER DESCRIPTION VDDSHV = 1.8Vor 3.3V UNIT MIN MAX tw(CLKH) CycleTime,mcbspx_clkx 162.8 ns tw(CLKH) TypicalPulseduration,mcbspx_clkxhigh 81.4 ns tw(CLKL) TypicalPulseduration,mcbspx_clkxlow 81.4 ns tdc(CLK) Dutycycleerror,mcbspx_clkx -8.14 8.14 ns B3 tsu(DRV-CLKAE) Setuptime,mcbspx_dr validbefore 9 ns mcbspx_clkxactiveedge B4 th(CLKAE-DRV) Holdtime,mcbspx_dr validaftermcbspx_clkx 2.4 ns activeedge B5 tsu(FSV-CLKAE) Setuptime,mcbspx_fsxvalidbefore 9 ns mcbspx_clkxactiveedge B6 th(CLKAE-FSV) Holdtime,mcbspx_fsxvalidaftermcbspx_clkx 2.4 ns activeedge Table6-91.McBSP SwitchingCharacteristics— TDM inMultipointMode INDEX PARAMETER DESCRIPTION VDDSHV = 1.8Vor 3.3V UNIT MIN MAX B8 td(CLKXAE-DXV) Delaytime,mcbspx_clkxactiveedge to 0.6 16.8 ns mcbspx_dx valid 6.6.1.1.7McBSP Timing Diagrams Figure6-37.McBSP RisingEdge Receive Timing inMaster Mode

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PRODUCT□PREVIEW mcbspx_clkr mcbspx_fsr mcbspx_dr D7 D6 D5 B3 B4 B5 B6 030-069 mcbspx_clkx mcbspx_fsx mcbspx_dx D7 D6 D5 B2 B2 030-070 mcbspx_clkx mcbspx_fsx mcbspx_dx D7 D6 D5 B5 B6 030-071 mcbspx_clkr mcbspx_fsr mcbspx_dr D7 D6 D5 B2 B2 B3 B4 030-072 mcbspx_clkr mcbspx_fsr mcbspx_dr D7 D6 D5 B3 B4 B5 B6 030-073 mcbspx_clkx mcbspx_fsx mcbspx_dx D7 D6 D5 B2 B2 030-074 AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Figure6-38.McBSP RisingEdge Receive Timing inSlaveMode Figure6-39.McBSP RisingEdge TransmitTiming inMaster Mode Figure6-40.McBSP RisingEdge TransmitTiming inSlaveMode Figure6-41.McBSP FallingEdge Receive Timing inMaster Mode Figure6-42.McBSP FallingEdge Receive Timing inSlaveMode Figure6-43.McBSP FallingEdge TransmitTiming inMaster Mode Copyright© 2009–2010,Texas InstrumentsIncorporated TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 169 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW mcbspx_clkx mcbspx_fsx mcbspx_dx D7 D6 D5 B5 B6 030-075 AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Figure6-44.McBSP FallingEdge TransmitTiming inSlaveMode

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6.6.2 MultichannelSerialPortInterface(McSPI)Timing

The multichannelSPI isa master/slavesynchronousserialbus.The McSPI1 module supportsup tofour peripheralsand theothers(McSPI2,McSPI3, and McSPI4) supportup totwo peripherals.The following timingsare applicabletothedifferentconfigurationsofMcSPI inmaster/slavemode forany McSPI and any channel(n).

6.6.2.1 McSPI inSlaveMode

The followingtablesassume testingovertherecommended operatingconditions. Table6-92.McSPI InterfaceTiming Requirements – SlaveMode NO. PARAMETER 1.8V 3.3V UNIT MIN MAX MIN MAX SS0 tc(CLK) Cycletime,mcspix_clk 41.67 41.67 ns SS1 tw(CLK) Pulseduration,mcspix_clkhighorlow 18.75 22.92 11.25 ns SS2 tsu(SIMOV-CLKAE) Setuptime,mcspix_simovalidbeforemcspix_clk 4.2 4 ns activeedge SS3 th(SIMOV-CLKAE) Holdtime,mcspix_simovalidaftermcspix_clkactive 4.6 3 ns edge SS4 tsu(CS0V-CLKFE) Setuptime,mcspix_cs0validbeforemcspix_clkfirst 13.8 7 ns edge SS5 th(CS0I-CLKLE) Holdtime,mcspix_cs0invalidaftermcspix_clklast 13.8 9.17 ns edge Table6-93.McSPI InterfaceSwitchingCharacteristics(1)(2)(3)(4) NO. PARAMETER 1.8V 3.3V UNIT MIN MAX MIN MAX SS6 td(CLKAE-SOMIV) Delaytime,mcspix_clkactiveedge tomcspix_somi 1.8 15.9 2 16.5 ns shifted SS7 td(CS0AE-SOMIV) Delaytime,mcspix_cs0activeedge to Modes 0 and 2 16.38 15.9 ns mcspix_somishifted (1) The capacitiveloadisequivalentto20 pF. (2) Inmcspix,x isequalto1,2,3,or4. (3) The polarityofmcspix_clkand theactiveedge (risingorfalling)on whichmcspix_simoisdrivenand mcspix_somiislatchedisall softwareconfigurable. (4) Thistimingappliestoallconfigurationsregardlessofmcspix_clkpolarityand whichclockedges areused todriveoutputdataand captureinputdata. Copyright© 2009–2010,Texas InstrumentsIncorporated TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 171 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW mcspix_cs0(EPOL=1) mcspix_clk(POL=0) mcspix_clk(POL=1) mcspix_simo mcspix_somi mcspix_cs0(EPOL=1) mcspix_clk(POL=0) mcspix_clk(POL=1) mcspix_simo mcspix_somi Bit□n-1 Bit□n-2 Bit□n-3 Bit□n-4 Bit□0 Bit□n-1 Bit□n-2 Bit□n-3 Bit□n-4 Bit□0 Bit□n-1 Bit□n-2 Bit□n-3 Bit□1 Bit□0 Bit□n-1 Bit□n-2 Bit□n-3 Bit□1 Bit□0 SS4 SS5 SS6 SS3 SS1 SS0 SS2 SS1 SS0 SS4 SS5 SS3 SS1 SS0 SS1 SS0 SS2 SS6 SS7 Mode□0□&□2 Mode□1□&□3 030-076 AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Figure6-45.McSPI InterfaceTransmitand Receive inSlaveMode (1)(2) (1) The activeclockedge (risingorfalling)on whichmcspi_somiisdrivenand mcspi_simodataislatchedissoftwareconfigurablewiththe bitMSPI_CHCONFx[0] = PHA and thebitMSPI_CHCONFx[1] = POL. (2) The polarityofmcspix_csiissoftwareconfigurablewiththebitMSPI_CHCONFx[6] = EPOL Inmcspix,x isequalto1,2,3,or4.

6.6.2.2 McSPI inMaster Mode

The followingtablesassume testingovertherecommended operatingconditions. Table6-94.McSPI1, 2,and 4 InterfaceTiming Requirements – Master Mode (1) NO. PARAMETER 1.8V 3.3V UNIT MIN MAX MIN MAX SM2 tsu(SOMIV-CLKAE) Setuptime,mcspix_somivalidbeforemcspix_clk 2.56 4 ns activeedge SM3 th(SOMIV-CLKAE) Holdtime,mcspix_somivalidaftermcspix_clkactive 2.93 4 ns edge (1) Inmcspix,x isequalto1,2,3,or4.Inmcspix_csn,n isequalto0,1,2,or3 forx equalto1,n isequalto0 or1 forx equalto2 and 3. n isequalto0 forx equalto4.

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PRODUCT□PREVIEW AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Table6-95.McSPI1, 2,and 4 InterfaceSwitchingCharacteristics– Master Mode (1)(2)(3) NO. PARAMETER 1.8V 3.3V UNIT MIN MAX MIN MAX SM0 tc(CLK) Cycletime,mcspix_clk 20.83 20.83 ns tj(CLK) Cyclejitter(4),mcspix_clk -200 200 -200 200 ps SM1 tw(CLK) Pulseduration,mcspix_clkhighorlow 0.45P(5) 0.55P(5) 0.45P(5) 0.55P(5) ns SM4 td(CLKAE-SIMOV) Delaytime,mcspix_clkactiveedge to -2.1 5 -3 6 ns mcspix_simoshifted SM5 td(CSnA-CLKFE) Delaytime,mcspix_csiactiveto Modes 1 A (6)-3.2 A (6)-3.0 6 ns mcspix_clkfirstedge and 3 Modes 0 B (7)-3.2 B (7)-3.0 6 ns and 2 SM6 td(CLKLE-CSnI) Delaytime,mcspix_clklastedge to Modes 1 B (7)-3.2 B (7)-3.0 ns mcspix_csiinactive and 3 Modes 0 A (6)-3.2 A (6)-3.0 ns and 2 SM7 td(CSnAE-SIMOV) Delaytime,mcspix_csiactiveedge Modes 0 5 5 ns tomcspix_simoshifted and 2 (1) Timingsaregivenfora maximum loadcapacitanceof20 pF forspix_csnsignals,30 pF forspix_clkand spix_simosignalswithx = 1 or 2,and 20 pF forspi4_clkand spi4_simosignals. (2) Inmcspix,x isequalto1,2,3,or4.Inmcspix_csn,n isequalto0,1,2,or3 forx equalto1,n isequalto0 or1 forx equalto2 and 3. n isequalto0 forx equalto4. (3) The polarityofmcspix_clkand theactiveedge (risingorfalling)on whichmcspix_simoisdrivenand mcspix_somiislatchedisall softwareconfigurable. (4) Maximum cyclejittersupportedby mcspix_clkinputclock. (5) P = mcspix_clkclockperiod (6) Case P = 20.8ns,A = (TCS+0.5)*P(TCS isa bitfieldofMSPI_CHCONFx[26:25] register).Case P > 20.8ns,A = TCS*P (TCS isa bitfieldofMSPI_CHCONFx[26:25] register).Formore information,see theDeviceMultichannelSerialPortInterface(McSPI)Reference Guide [literaturenumber SPRUFV6 ]. (7) B = TCS*P (TCS isa bitfieldofMSPI_CHCONFx[26:25] register).Formore information,see theDeviceMultichannelSerialPort Interface(McSPI)ReferenceGuide [literaturenumber SPRUFV6 ]. The followingtablesassume testingovertherecommended operatingconditions. Table6-96.McSPI 3 InterfaceTiming Requirements – Master Mode (1)(2) NO. PARAMETER 1.8V 3.3V UNIT MIN MAX MIN MAX SM2 tsu(SOMIV-CLKAE) Setuptime,mcspi3_somivalidbefore 2.5 4 ns mcspi3_clkactiveedge SM3 th(SOMIV-CLKAE) Holdtime,mcspi3_somivalidaftermcspi3_clk 2.89 4 ns activeedge (1) The inputtimingrequirementsaregivenby consideringa risetimeand a falltimeof4 ns. (2) Inmcspi3_csn,n isequalto0 or1.The polarityofmcspi3_clkand theactiveedge (risingorfalling)on whichmcspi3_simoisdrivenand mcspi3_somiislatchedisallsoftwareconfigurable. Copyright© 2009–2010,Texas InstrumentsIncorporated TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 173 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Table6-97.McSPI3 InterfaceSwitchingCharacteristics– Master Mode (1)(2)(3) NO. PARAMETER 1.8V 3.3V UNIT MIN MAX MIN MAX SM0 tc(CLK) Cycletime,mcspix_clk 41.67 41.67 ns tj(CLK) Cyclejitter(4) -200 200 -200 200 ps SM1 tw(CLK) Pulseduration,mcspix_clkhighorlow 0.45P(5) 0.55P(5) 0.45P(5) 0.55P(5) ns SM4 td(CLKAE-SIMOV) Delaytime,mcspix_clkactiveedge to -2.1 11.3 -3 ns mcspix_simoshifted SM5 td(CSnA-CLKFE) Delaytime,mcspix_csiactive Modes 1 A (6)-4.4 A (6)-3.0 6 ns tomcspix_clkfirstedge and 3 Modes 0 B (7)-4.4 B (7)-3.0 6 ns and 2 SM6 td(CLKLE-CSnI) Delaytime,mcspix_clklast Modes 1 B (7)-4.4 B (7)-3.0 ns edge tomcspix_csiinactive and 3 Modes 0 A (6)-4.4 A (6)-3.0 ns and 2 SM7 td(CSnAE-SIMOV) Delaytime,mcspix_csiactive Modes 0 11.3 5 ns edge tomcspix_simoshifted and 2 (1) The capacitiveloadisequivalentto20 pF. (2) Inmcspi3_csn,n isequalto0 or1.The polarityofmcspi3_clkand theactiveedge (risingorfalling)on whichmcspi3_simoisdrivenand mcspi3_somiislatchedisallsoftwareconfigurable. (3) ThistimingappliestoallconfigurationsregardlessofMcSPI3_CLK polarityand whichclockedges areused todriveoutputdataand captureinputdata. (4) Maximum cyclejittersupportedby mcspix_clkinputclock. (5) P = mcspix_clkclockperiod. (6) Case P = 20.8ns,A = (TCS + 0.5)*P(TCS isa bitfieldofMSPI_CHCONFx[26:25] register).Case P > 20.8ns,A = TCS*P (TCS isa bit fieldofMSPI_CHCONFx[26:25] register).Formore information,see theDeviceMultichannelSerialPortInterface(McSPI)Reference Guide [literaturenumber SPRUFV6 ]. (7) B = TCS*P (TCS isa bitfieldofMSPI_CHCONFx[26:25] register).Formore information,see theDeviceMultichannelSerialPort Interface(McSPI)ReferenceGuide [literaturenumber SPRUFV6 ].

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PRODUCT□PREVIEW mcspix_csn(EPOL=1) mcspix_clk(POL=0) mcspix_clk(POL=1) mcspix_simo mcspix_somi mcspix_csn(EPOL=1) mcspix_clk(POL=0) mcspix_clk(POL=1) mcspix_simo mcspix_somi Bit□n-1 Bit□n-2 Bit□n-3 Bit□n-4 Bit□0 Bit□n-1 Bit□n-2 Bit□n-3 Bit□n-4 Bit□0 Bit□n-1 Bit□n-2 Bit□n-3 Bit□1 Bit□0 Bit□n-1 Bit□n-2 Bit□n-3 Bit□1 Bit□0 SM5 SM6 SM4 SM3 SM1 SM0 SM2 SM1 SM0 SM5 SM6 SM3 SM1 SM0 SM1 SM0 SM2 SM4 SM7 Mode□0□&□2 Mode□1□&□3 030-077 AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Figure6-46.McSPI InterfaceTransmitand Receive inMaster Mode (1)(2)(3) (1) The activeclockedge (risingorfalling)on whichmcspix_simoisdrivenand mcspi_somidataislatchedissoftwareconfigurablewiththe bitMSPI_CHCONFx[0] = PHA and thebitMSPI_CHCONFx[1] = POL. (2) The polarityofmcspix_csiissoftwareconfigurablewiththebitMSPI_CHCONFx[6] = EPOL. (3) Inmcspix,x isequalto1.Inmcspix_csn,n isequalto0,1,2,or3. Copyright© 2009–2010,Texas InstrumentsIncorporated TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 175 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com

6.6.3 MultiportFull-SpeedUniversalSerialBus (USB) Interface

The AM3517/05 processorprovidesthreeUSB portsworkinginfull-and low-speeddatatransactions(up to12Mbit/s). Connectedtoeithera seriallinkcontrollerora serialPHY (PHY interfacemodes) itsupports:

• 6-pin(Tx:Dat/Se0orTx:Dp/Dm) unidirectionalmode
• 4-pinbidirectionalmode
• 3-pinbidirectionalmode

6.6.3.1 MultiportFull-SpeedUniversalSerialBus (USB) – UnidirectionalStandard 6-pinMode

The followingtablesassume testingovertherecommended operatingconditions. Table6-98.Low-/Full-SpeedUSB Timing ConditionsUnidirectionalStandard 6-pinMode TIMING CONDITION PARAMETER 1.8V,3.3V UNIT InputConditions tR Inputsignalrisetime 2.0 ns tF Inputsignalfalltime 2.0 ns Output Conditions C LOAD Outputloadcapacitance 15.0 pF Table6-99.Low-/Full-SpeedUSB Timing Requirements UnidirectionalStandard 6-pinMode NO. PARAMETER 1.8V,3.3V UNIT MIN MAX FSU1 td(Vp,Vm) Time duration,mmx_rxdp and mmx_rxdm lowtogetherduringtransition 14.0 ns FSU2 td(Vp,Vm) Time duration,mmx_rxdp and mmx_rxdm hightogetherduringtransition 8.0 ns FSU3 td(RCVU0) Time duration,mmx_rrxcv undefineduringa singleend 0 (mmx_rxdp and 14.0 ns mmx_rxdm lowtogether) FSU4 td(RCVU1) Time duration,mmx_rxrcv undefineduringa singleend 1 (mmx_rxdp and 8.0 ns mmx_rxdm hightogether) Table6-100.Low-/Full-SpeedUSB SwitchingCharacteristicsUnidirectionalStandard 6-pinMode NO. PARAMETER 1.8V,3.3V UNIT MIN MAX FSU5 td(TXENL-DATV) Delaytime,mmx_txen_n lowtommx_txdat valid 81.8 84.8 ns FSU6 td(TXENL-SE0V) Delaytime,mmx_txen_n lowtommx_txse0 valid 81.8 84.8 ns FSU7 ts(DAT-SE0) Skew between mmx_txdat and mmx_txse0 transition 1.5 ns FSU8 td(DATI-TXENH) Delaytime,mmx_txdat invalidtommx_txen_n high 81.8 ns FSU9 td(SE0I-TXENH) Delaytime,mmx_txse0 invalidtommx_txen_n high 81.8 ns tR(do) Risetime,mmx_txen_n 4.0 ns tF(do) Falltime,mmx_txen_n 4.0 ns tR(do) Risetime,mmx_txdat 4.0 ns tF(do) Falltime,mmx_txdat 4.0 ns tR(do) Risetime,mmx_txse0 4.0 ns tF(do) Falltime,mmx_txse0 4.0 ns

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PRODUCT□PREVIEW mmx_txen_n mmx_txdat mmx_txse0 mmx_rxdp mmx_rxdm mmx_rxrcv FSU5 FSU6 FSU7 FSU1 FSU1 FSU2 FSU2 FSU3 FSU4 FSU8 FSU9 Transmit Receive 030-080 AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Inmmx, x isequalto0,1,or2. Figure6-47.Low-/Full-SpeedUSB UnidirectionalStandard 6-pinMode

6.6.3.2 MultiportFull-SpeedUniversalSerialBus (USB) – BidirectionalStandard 4-pinMode

The followingtablesassume testingovertherecommended operatingconditions. Table6-101.Low-/Full-SpeedUSB Timing ConditionsBidirectionalStandard 4-pinMode TIMING CONDITION PARAMETER 1.8V,3.3V UNIT InputConditions tR Inputsignalrisetime 2.0 ns tF Inputsignalfalltime 2.0 ns Output Conditions C LOAD Outputloadcapacitance 15.0 pF Table6-102.Low-/Full-SpeedUSB Timing Requirements BidirectionalStandard 4-pinMode NO. PARAMETER 1.8V,3.3V UNIT MIN MAX FSU10 td(DAT,SE0) Time duration,mmx_txdat and mmx_txse0 lowtogetherduring 14.0 ns transition FSU11 td(DAT,SE0) Time duration,mmx_txdat and mmx_txse0 hightogetherduring 8.0 ns transition FSU12 td(RCVU0) Time duration,mmx_rrxcv undefineduringa singleend 0 14.0 ns (mmx_txdatand mmx_txse0 lowtogether) FSU13 td(RCVU1) Time duration,mmx_rxrcv undefineduringa singleend 1 8.0 ns (mmx_txdatand mmx_txse0 hightogether) Table6-103.Low-/Full-SpeedUSB SwitchingCharacteristicsBidirectionalStandard 4-pinMode NO. PARAMETER 1.8V,3.3V UNIT MIN MAX FSU14 td(TXENL-DATV) Delaytime,mmx_txen_n lowtommx_txdat valid 81.8 84.8 ns FSU15 td(TXENL-SE0V) Delaytime,mmx_txen_n lowtommx_txse0 valid 81.8 84.8 ns FSU16 ts(DAT-SE0) Skew between mmx_txdat and mmx_txse0 transition 1.5 ns FSU17 td(DATV-TXENH) Delaytime,mmx_txdat invalidbeforemmx_txen_n high 81.8 ns FSU18 td(SE0V-TXENH) Delaytime,mmx_txse0 invalidbeforemmx_txen_n high 81.8 ns tR(txen) Risetime,mmx_txen_n 4.0 ns Copyright© 2009–2010,Texas InstrumentsIncorporated TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 177 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW mmx_txen_n mmx_txdat mmx_txse0 mmx_rxrcv FSU16 FSU14 FSU15 FSU10 FSU10 FSU1 1 FSU1 1 FSU12 FSU13 FSU17 FSU18 Transmit Receive 030-081 AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Table6-103.Low-/Full-SpeedUSB SwitchingCharacteristicsBidirectionalStandard 4-pin Mode (continued) NO. PARAMETER 1.8V,3.3V UNIT MIN MAX tF(txen) Falltime,mmx_txen_n 4.0 ns tR(dat) Risetime,mmx_txdat 4.0 ns tF(dat) Falltime,mmx_txdat 4.0 ns tR(se0) Risetime,mmx_txse0 4.0 ns tF(se0) Falltime,mmx_txse0 4.0 ns Inmmx, x isequalto0,1,or2. Figure6-48.Low-/Full-SpeedUSB BidirectionalStandard 4-pinMode

6.6.3.3 MultiportFull-SpeedUniversalSerialBus (USB) – BidirectionalStandard 3-pinMode

The followingtablesassume testingovertherecommended operatingconditions. Table6-104.Low-/Full-SpeedUSB Timing ConditionsBidirectionalStandard 3-pinMode TIMING CONDITION PARAMETER 1.8V,3.3V UNIT InputConditions tR Inputsignalrisetime 2.0 ns tF Inputsignalfalltime 2.0 ns Output Conditions C LOAD Outputloadcapacitance 15.0 pF Table6-105.Low-/Full-SpeedUSB Timing Requirements BidirectionalStandard 3-pinMode NO. PARAMETER 1.8V,3.3V UNIT MIN MAX FSU19 td(DAT,SE0) Time duration,mmx_txdat and mmx_txse0 lowtogetherduring 14.0 ns transition FSU20 td(DAT,SE0) Time duration,mmx_tsdat and mmx_txse0 hightogetherduring 8.0 ns transition Table6-106.Low-/Full-SpeedUSB SwitchingCharacteristicsBidirectionalStandard 3-pinMode NO. PARAMETER 1.8V,3.3V UNIT MIN MAX FSU21 td(TXENL-DATV) Delaytime,mmx_txen_n lowtommx_txdat valid 81.8 84.8 ns FSU22 td(TXENL-SE0V) Delaytime,mmx_txen_n lowtommx_txse0 valid 81.8 84.8 ns FSU23 ts(DAT-SE0) Skew between mmx_txdat and mmx_txse0 transition 1.5 ns

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PRODUCT□PREVIEW mmx_txen_n mmx_txdat mmx_txse0 FSU23 FSU21 FSU22 FSU19 FSU19 FSU20 FSU20 FSU24 FSU25 Transmit Receive 030-082 AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Table6-106.Low-/Full-SpeedUSB SwitchingCharacteristicsBidirectionalStandard 3-pin Mode (continued) NO. PARAMETER 1.8V,3.3V UNIT MIN MAX FSU24 td(DATI-TXENH) Delaytime,mmx_txdat invalidtommx_txen_n high 81.8 ns FSU25 td(SE0I-TXENH) Delaytime,mmx_txse0 invalidtommx_txen_n high 81.8 ns tR(do) Risetime,mmx_txen_n 4.0 ns tF(do) Falltime,mmx_txen_n 4.0 ns tR(do) Risetime,mmx_txdat 4.0 ns tF(do) Falltime,mmx_txdat 4.0 ns tR(do) Risetime,mmx_txse0 4.0 ns tF(do) Falltime,mmx_txse0 4.0 ns Inmmx, x isequalto0,1,or2. Figure6-49.Low-/Full-SpeedUSB BidirectionalStandard 3-pinMode

6.6.4 MultiportHigh-Speed UniversalSerialBus (USB) Timing

In additionto the full-speedUSB controller,a high-speed(HS) USB controlleris instantiatedinside AM3517/05 .Itallowshigh-speedtransactions(upto480 Mbit/s)on theUSB ports1 and 2.

• Port1 and port2: – 12-bitmastermode (SDR)

6.6.4.1 High-Speed UniversalSerialBus (USB) on Ports1 and 2 12-bitMaster Mode

The followingtablesassume testingovertherecommended operatingconditions. Table6-107.High-Speed USB Timing Conditions12-bitMaster Mode TIMING CONDITION PARAMETER 1.8V,3.3V UNIT InputConditions tR Inputsignalrisetime 2 ns tF Inputsignalfalltime 2 ns Output Conditions C LOAD Outputloadcapacitance 3 pF Table6-108.High-Speed USB Timing Requirements 12-bitMaster Mode (1) NO. PARAMETER 1.8V,3.3V UNIT MIN MAX HSU3 ts(DIRV-CLKH) Setuptime,hsusbx_dirvalidbeforehsusbx_clkrisingedge 7.5 ns ts(NXTV-CLKH) Setuptime,hsusbx_nxtvalidbeforehsusbx_clkrisingedge 7.5 ns HSU4 th(CLKH-DIRIV) Holdtime,hsusbx_dirvalidafterhsusbx_clkrisingedge 0.2 ns (1) Inhsusbx,x isequalto1 or2. Copyright© 2009–2010,Texas InstrumentsIncorporated TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 179 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW hsusbx_clk hsusbx_stp hsusbx_dir_&_nxt hsusbx_data[7:0] Data_OUT Data_IN HSU1 HSU0 HSU1 HSU4 HSU2 HSU2 HSU6 HSU3 HSU5 030-087 AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Table6-108.High-Speed USB Timing Requirements 12-bitMaster Mode (1) (continued) NO. PARAMETER 1.8V,3.3V UNIT MIN MAX th(CLKH-NXT/IV) Holdtime,hsusbx_nxtvalidafterhsusbx_clkrisingedge 0.2 ns HSU5 ts(DATAV-CLKH) Setuptime,hsusbx_data[0:7]validbeforehsusbx_clkrisingedge 7.5 ns HSU6 th(CLKH-DATIV) Holdtime,hsusbx_data[0:7]validafterhsusbx_clkrisingedge 0.2 ns Table6-109.High-Speed USB SwitchingCharacteristics12-bitMaster Mode (1) N O. PARAMETER 1.8V,3.3V UNIT MIN MAX HSU0 fp(CLK) hsusbx_clkclockfrequency 60 MHz tj(CLK) Jitterstandarddeviation(2),hsusbx_clk 200 ps HSU1 td(CLKH-STPV) Delaytime,hsusbx_clkhightooutputhsusbx_stpvalid 13 ns td(CLKH-STPIV) Delaytime,hsusbx_clkhightooutputhsusbx_stpinvalid 2 ns HSU2 td(CLKH-DV) Delaytime,hsusbx_clkhightooutputhsusbx_data[0:7]valid 13 ns td(CLKH-DIV) Delaytime,hsusbx_clkhightooutputhsusbx_data[0:7]invalid 2 ns tR(do) Risetime,outputsignals 2 ns tF(do) Falltime,outputsignals 2 ns (1) Inhsusbx,x isequalto1 or2. (2) The jitterprobabilitydensitycan be approximatedby a Gaussianfunction. Inhsusbx,x isequalto1 or2. Figure6-50.High-Speed USB 12-bitMaster Mode

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PRODUCT□PREVIEW AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 6.6.5 USB0 OTG (USB2.0 OTG) The AM3517/05 USB2.0 peripheralsupportsthefollowingfeatures:

• USB 2.0peripheralatspeeds highspeed (HS:480 Mb/s)and fullspeed (FS:12 Mb/s)
• USB 2.0hostatspeeds HS, FS, and lowspeed (LS:1.5Mb/s)
• Alltransfermodes (control,bulk,interrupt,and isochronous)
• 16 Transmit(TX)and 16 Receive(RX)endpointsinadditiontoendpoint0
• FIFO RAM – 32K endpoint – Programmable size
• IntegratedUSB 2.0HighSpeed PHY
• Connectstoa standardCharge Pump forVBUS 5 V generation
• RNDIS mode foracceleratingRNDIS typeprotocolsusingshortpacketterminationoverUSB

6.6.5.1 USB OTG ElectricalParameters

The USB OTG electricalparametersmeet orexceed thosespecifiedinthefollowingdocuments whichcan be obtainedfromtheUSB ImplementersForum:

• UniversalSerialBus Specification,Revision2.0,April27,2000
• On-The-Go SupplementtotheUSB 2.0Specification,Revision1.3,December 5,2006
• EngineeringChange Notice“Pull-up/pull-downresistors”, UniversalSerialBus SpecificationRevision 2.0 For additionalinformationrelatedto USB OTG electricalparameters,please see the respective documents on theUSB ImplementersForum web site(http://www.usb.org). Copyright© 2009–2010,Texas InstrumentsIncorporated TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 181 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW HECCx_RX HECCx_TX AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com

6.6.6 High-End ControllerArea Network Controller(HECC) Timing

The AM3517/05 devicehas a High-End ControllerArea Network Controller(HECC). The HECC uses establishedprotocoltocommunicate seriallywithothercontrollersinharshenvironments.The HECC is fullycompliantwiththeControllerArea Network(CAN) protocol,version2.0B. Key featuresoftheHECC includethefollowing:

• CAN, version2.0Bcompliant
• 32 RX/TX message objects
• 32 receiveidentifiermasks
• Programmable wake-up on bus activity
• Programmable interruptscheme
• Automaticreplytoa remoterequest
• Automaticre-transmissionincase oferrororlossofarbitration
• Protectionagainstreceptionofa new message
• 32-bittimestamp
• Localnetworktimecounter
• Programmable priorityregisterforeach message
• Programmable transmissionand receptiontime-out
• HECC/SCC mode ofoperation
• Standard-ExtendedIdentifier
• Self-testmode

6.6.6.1 HECC Timing Requirements

Table6-110.Timing Requirements forHECC Receive (seeFigure6-51) 1.8V,3.3V NO. UNIT MIN MAX 1 f(baud) Maximum programmablebaud rate 1 Mbps 2 tw(HECC_RX) Pulseduration,receivedatabit H-1(1) H+3 (1) ns (1) These valuesarerelativetoH (whereH = 1/(baudrate).

6.6.6.2 HECC SwitchingCharacteristics

Table6-111.SwitchingCharacteristicsOver Recommended OperatingConditionsforHECC Transmit (seeFigure6-51) 1.8V,3.3V NO. PARAMETER UNIT MIN MAX 3 f(baud) Maximum programmablebaud rate 1 Mbps 4 tw(HECC_TX) Pulseduration,transmitdatabit H-1(1) H+3 (1) ns (1) These valuesarerelativetoH (whereH = 1/(baudrate). Figure6-51.HECC Transmit/ReceiveTiming

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6.6.7 EthernetMedia Access Controller(EMAC)

The EthernetMedia Access Controller(EMAC) providesan efficientinterfacebetween AM3517/05 and the network.The EMAC supportsboth10Base-T and 100Base-TX,or10 Mbits/second(Mbps)and 100 Mbps ineitherhalf-orfull-duplexmode, withhardwareflowcontroland qualityofservice(QOS) support. The EMAC controlstheflowofpacketdatafrom theAM3517/05 devicetothePHY. The MDIO module controlsPHY configurationand statusmonitoring. BoththeEMAC and theMDIO modules interfacetotheAM3517/05 devicethrougha custom interfacethat allowsefficientdatatransmissionand reception.Thiscustom interfaceisreferredtoas theEMAC control module,and isconsideredintegralto the EMAC/MDIO peripheral.The controlmodule isalsoused to multiplexand controlinterrupts.

6.6.7.1 EMAC ElectricalData/Timing

Table6-112.RMII InputTiming Requirements 1.8V,3.3V NO. PARAMETER MIN TYP MAX UNIT fc(REFCLK) Frequency,REF_CLK 50 MHz ft(REFCLK) Frequencystability,REF_CLK +/-50 ppm 1 tc(REFCLK) CycleTime,REF_CLK 20 ns 2 tw(REFCLKH) PulseWidth,REF_CLK High 7 13 ns 3 tw(REFCLKL) PulseWidth,REF_CLK Low 7 13 ns 6 tsu(RXD-REFCLK) InputSetupTime,RXD ValidbeforeREF_CLK 4 ns High 7 th(REFCLK-RXD) InputHoldTime,RXD ValidafterREF_CLK High 2 ns 8 tsu(CRSDV-REFCLK) InputSetupTime,CRSDV Validbefore 4 ns REF_CLK High 9 th(REFCLK-CRSDV) InputHoldTime,CRSDV ValidafterREF_CLK 2 ns High 10 tsu(RXER-REFCLK) InputSetupTime,RXER ValidbeforeREF_CLK 4 ns High 11 th(REFCLKR-RXER) InputHoldTime,RXER ValidafterREF_CLK 2 ns High Table6-113.RMII Output SwitchingCharacteristics 1.8V,3.3V NO. PARAMETER MIN TYP MAX UNIT 4 td(REFCLK-TXD) OutputDelayTime,REF_CLK HightoTXD Valid 2.5 13 ns 5 td(REFCLK-TXEN) OutputDelayTime,REF_CLK HightoTXEN 2.5 13 ns Valid Copyright© 2009–2010,Texas InstrumentsIncorporated TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 183 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW SPRS550-004 2 3 REF_CLK TXEN TXD[1:0] RXD[1:0] CRS_DV RXER_IN AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Figure6-52.RMII Timing Diagram

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PRODUCT□PREVIEW MD_CLK MDIO_D (input) MD_CLK MDIO_D (output) AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010

6.6.8 Management Data Input/Output(MDIO)

The Management Data Input/Output(MDIO) module continuouslypollsall32 MDIO addressesinorderto enumerateallPHY devicesinthesystem. The Management Data Input/Output(MDIO) module implementsthe802.3serialmanagement interfaceto interrogateand controlEthernetPHY(s) usinga shared two-wirebus. Host softwareuses the MDIO module to configurethe auto-negotiationparametersof each PHY attachedto the EMAC, retrievethe negotiationresults,and configurerequiredparametersinthe EMAC module forcorrectoperation.The module is designed to allow almost transparentoperationof the MDIO interface,with very little maintenancefromthecoreprocessor.Onlyone PHY may be connectedatany giventime.

6.6.8.1 Management Data Input/Output(MDIO) ElectricalData/Timing

Table6-114.Timing Requirements forMDIO Input(seeFigure6-53and Figure6-54) No. PARAMETER UNITMIN MAX 1 tc(MD_CLK) Cycletime,MD_CLK 400 ns 4 tsu(MDIO-MDCLKH) Setuptime,MDIO datainputvalidbeforeMD_CLK high 20 ns 5 th(MDCLKH-MDIO) Holdtime,MDIO datainputvalidafterMDCLK high 10 ns Figure6-53.MDIO InputTiming Table6-115.SwitchingCharacteristicsOver Recommended OperatingConditionsforMDIO Output (seeFigure6-54) No. PARAMETER UNITMIN MAX 7 td(MDCLKL-MDIO) Delaytime,MDCLK lowtoMDIO dataoutputvalid 0 100 ns Figure6-54.MDIO Output Timing

6.6.9 UniversalAsynchronous Receiver/Transmitter(UART)

The AM3517/05 has fourUARTs (onewithInfraredData Association[IrDA]and Consumer Infrared[CIR] modes). Copyright© 2009–2010,Texas InstrumentsIncorporated TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 185 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW Start Bit Data□Bits UART_TXDn UART_RXDn Data□Bits Bit Start AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Table6-116.Timing Requirements forUARTx Receive(1) 1.8V,3.3V NO. UNIT MIN MAX 4 tw(URXDB) Pulseduration,receivedatabit(RXDn) .96U 1.05U ns 5 tw(URXSB) Pulseduration,receivestartbit .96U 1.05U ns (1) U = UART baud time= 1/programmedbaud rate. Table6-117.SwitchingCharacteristicsOver Recommended OperatingConditionsforUARTx Transmit(1) 1.8V,3.3V NO. PARAMETER UNIT MIN MAX UART0 Maximum programmablebaud ratef(baud_15) 5 1 f(baud) UART0 Maximum programmablebaud ratef(baud_30) 0.23 mbps UART0 Maximum programmablebaud ratef(baud_100) 0.115 2 tw(UTXDB) Pulseduration,transmitdatabit,15/30/100pF U -2 U + 2 ns 3 tw(UTXSB) Pulseduration,transmitstartbit,15/30/100pF U -2 U + 2 ns (1) U = UART baud time= 1/programmedbaud rate. Figure6-55.UART Transmit/ReceiveTiming

6.6.9.1 UART IrDA Interface

The IrDAmodule can operateinthreedifferentmodes:

• Slow infrared(SIR)(≤115.2Kbits/s)
• Medium infrared(MIR)(0.576Mbits/sand 1.152Mbits/s)
• Fastinfrared(FIR)(4Mbits/s)

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PRODUCT□PREVIEW 030-1 18 Pulse□duration 90% 50% 10% tf 90% 50% 10% tr AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Figure6-56.UART IrDA Pulse Parameters 6.6.9.1.1IrDA— Receive Mode Table6-118.UART IrDA— SignalingRate and Pulse Duration— Receive Mode ELECTRICAL PULSE DURATION SIGNALING RATE UNIT MIN NOMINAL MAX SIR 2.4Kbit/s 1.41 78.1 88.55 ms 9.6Kbit/s 1.41 19.5 22.13 ms 19.2Kbit/s 1.41 9.75 11.07 ms 38.4Kbit/s 1.41 4.87 5.96 ms 57.6Kbit/s 1.41 3.25 4.34 ms 115.2Kbit/s 1.41 1.62 2.23 ms MIR 0.576Mbit/s 297.2 416 518.8 ns 1.152Mbit/s 149.6 208 258.4 ns FIR 4.0Mbit/s(Singlepulse) 67 125 164 ns 4.0Mbit/s(Doublepulse) 190 250 289 ns Table6-119.UART IrDA— Rise and FallTime— Receive Mode PARAMETER MAX UNIT tR Risingtime, 200 ns uart3_rx_irrx tF Fallingtime, 200 ns uart3_rx_irrx 6.6.9.1.2IrDA— TransmitMode Copyright© 2009–2010,Texas InstrumentsIncorporated TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 187 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW HDQ tB tBR 030-095 AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Table6-120.UART IrDA— SignalingRate and Pulse Duration— TransmitMode SIGNALING RATE ELECTRICAL PULSE DURATION UNIT MIN NOMINAL MAX SIR 2.4Kbit/s 78.1 78.1 78.1 ms 9.6Kbit/s 19.5 19.5 19.5 ms 19.2Kbit/s 9.75 9.75 9.75 ms 38.4Kbit/s 4.87 4.87 4.87 ms 57.6Kbit/s 3.25 3.25 3.25 ms 115.2Kbit/s 1.62 1.62 1.62 ms MIR 0.576Mbit/s 414 416 419 ns 1.152Mbit/s 206 208 211 ns FIR 4.0Mbit/s(Singlepulse) 123 125 128 ns 4.0Mbit/s(Doublepulse) 248 250 253 ns

6.6.10 HDQ /1-WireInterfaces

Thismodule isintendedtowork withboththeHDQ and the1-Wireprotocols.The protocolsuse a single wiretocommunicate between themasterand theslave.The protocolsemploy an asynchronousreturnto 1 mechanism where,afterany command, thelineispulledhigh. 6.6.10.1HDQ Protocol Table 6-121 and Table 6-122 assume testingover the recommended operatingconditions(see Figure6-57throughFigure6-60). Table6-121.HDQ Timing Requirements PARAMETER DESCRIPTION MIN MAX UNIT tCYCD Bitwindow 253 s tHW1 Reads 1 68 tHW0 Reads 0 180 tRSPS Command tohostrespondtime(1) (1) Definedby software. Table6-122.HDQ SwitchingCharacteristics PARAMETER DESCRIPTION MIN TYP MAX UNIT tB Breaktiming 193 s tBR Breakrecovery 63 tCYCH Bitwindow 253 tDW1 Sends1 (write) 1.3 tDW0 Sends0 (write) 101 Figure6-57.HDQ Break (Reset)Timing

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PRODUCT□PREVIEW HDQ tHW 1 tHW 0 tCYCH 030-096 HDQ tDW 1 tDW 0 tCYCD 030-097 HDQ Break 0_(LSB ) 1 6 7_(MSB ) tRSPS 0_(LSB ) Command _byte _written Data _byte _received 030-098 1-WIRE tRSTH tPDLtPDHtRTSL 030-099 AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Figure6-58.HDQ Read BitTiming (Data) Figure6-59.HDQ WriteBitTiming (Command/Address or Data) Figure6-60.HDQ Communication Timing 6.6.10.21-WireProtocol Table 6-123 and Table 6-124 assume testingover the recommended operatingconditions(see Figure6-61throughFigure6-63). Table6-123.1-WireTiming Requirements PARAMETER DESCRIPTION MIN MAX UNIT tPDH Presencepulsedelayhigh 68 s tPDL Presencepulsedelaylow 68 tPDH tRDV + tREL Read bit-zerotime 102 Table6-124.1-WireSwitchingCharacteristics PARAMETER DESCRIPTION MIN TYP MAX UNIT tRSTL Resettimelow 484 s tRSTH Resettimehigh 484 tSLOT Writebitcycletime 102 tLOW1 Writebit-onetime 1.3 tLOW0 Writebit-zerotime 101 tREC Recoverytime 134 tLOWR Read bitstrobetime 13 Figure6-61.1-WireBreak (Reset)Timing Copyright© 2009–2010,Texas InstrumentsIncorporated TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 189 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW 1-WIRE tLOWR tRDV_ and_ tREL tSLOT_ and_ tREC 030-100 1-WIRE tLOW1 tLOW0 tSLOT_and _tREC 030-101 AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Figure6-62.1-WireRead BitTiming (Data) Figure6-63.1-WireWriteBitTiming (Command/Address or Data)

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6.6.11 I2C Interface

The multimasterI2C peripheralprovidesan interfacebetween two or more devicesviaan I2C serialbus. The I2C controllersupportsthe multimastermode which allowsmore than one device capable of controllingthe bus to be connectedto it.Each I2C deviceisrecognizedby a uniqueaddressand can operateas eithertransmitteror receiver,accordingto the functionof the device.In additionto beinga transmitterorreceiver,a deviceconnectedtotheI2C bus can alsobe consideredas masterorslavewhen performingdatatransfers.Thisdatatransferiscarriedoutviatwo serialbidirectionalwires:

• An SDA dataline
• An SCL clockline The followingsectionsillustratethedatatransferisinmasteror slaveconfigurationwith7-bitaddressing format.The I2C interfaceiscompliantwithPhilipsI2C specificationversion2.1.Itsupportsstandardmode (upto100K bits/s),fastmode (upto400K bits/s)and high-speedmode (upto3.4Mb/s). 6.6.11.1I2C Standard/Fast-SpeedMode Table6-125.I2C Standard/Fast-SpeedMode Timings 1.8V,3.3-V NO. PARAMETER (1) STANDARD FAST MODE UNIT MODE MIN MAX MIN MAX fSCL ClockFrequency,i2cX_scl 100 400 kHz I1 tw(SCLH) PulseDuration,i2cX_sclhigh 4 0.6 s I2 tw(SCLL) PulseDuration,i2cX_scllow 4.7 1.3 s I3 tsu(SDAV-SCLH) Setuptime,i2cX_sdavalidbeforei2cX_sclactivelevel 250 100(2) ns I4 th(SCLHSDAV) Holdtime,i2cX_sdavalidafteri2cX_sclactivelevel 3.45(3) 0.9(3) s I5 tsu(SDAL-SCLH) Setuptime,i2cX_sclhighafteri2cX_sdalow(fora 4.7 0.6 s START (4)conditionora repeatedSTART condition) I6 th(SCLHSDAH) Holdtime,i2cX_sdalowlevelafteri2cX_sclhighlevel 4 0.6 s (STOP condition) I7 th(SCLHRSTART) Holdtime,i2cX_sdalowlevelafteri2cX_sclhighlevel(for 4 0.6 s a repeatedSTART condition) I8 tw(SDAH) Pulseduration,i2cX_sdahighbetween STOP and START 4.7 1.3 s conditions tR(SCL) Risetime,i2cX_scl 1000 300 ns tF(SCL) Falltime,i2cX_scl 300 300 ns tR(SDA) Risetime,i2cX_sda 1000 300 ns tF(SDA) Falltime,i2cX_sda 300 300 ns CB Capacitiveloadforeach bus line 60 60 pF (1) Ini2cX,X isequalto1,2,or3. (2) A fast-modeI2C-bus devicecan be used ina standard-modeI2C-bus system,buttherequirementtsu(SDAV-SCLH) 250 ns must thenbe met.Thisisautomaticallythecase ifthedevicedoes notstretchthelowperiodofthei2cx_scl.Ifsuch a devicedoes stretchthelow periodofthei2cx_scl,itmust outputthenextdatabittothei2cx_sdalinetr(SDA)max + tsu(SDAV-SCLH) = 1000 + 250 = 1250 ns (according tothestandard-modeI2C-bus specification)beforethei2cx_scllineisreleased. (3) The maximum th(SCLH-SDA) has onlytobe met ifthedevicedoes notstretchthelowperiodofthei2cx_sclsignal. (4) Afterthistime,thefirstclockisgenerated. Copyright© 2009–2010,Texas InstrumentsIncorporated TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 191 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW i2cX_sda i2cX_scl ST ART REPEA T STOPST ART ST ART I3 I4 I6I6 I7 030-093 AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Figure6-64.I2C Standard/FastMode

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PRODUCT□PREVIEW i2cX_sda i2cX_scl STOPST ART REPEA T I1 I2 I3 I4I6I5 I7 030-094 AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 6.6.11.2I2C High-Speed Mode Table6-126.I2C High-Speed Mode Timings(1)(2) 1.8V,3.3V NO. PARAMETER UNIT MIN MAX fSCL Clockfrequency,i2cX_scl 3.4 MHz I1 tw(SCLH) Pulseduration,i2cX_sclhigh 60(3) s I2 tw(SCLL) Pulseduration,i2cX_scllow 160(3) s I3 tsu(SDAV-SCLH) Setuptime,i2cX_sdavalidbeforei2cX_sclactivelevel 10 ns I4 th(SCLHSDAV) Holdtime,i2cX_sdavalidafteri2cX_sclactivelevel 70 s I5 tsu(SDAL-SCLH) Setuptime,i2cX_sclhighafteri2cX_sdalow 160 s (fora START (4)conditionora repeatedSTART condition) I6 th(SCLHSDAH) Holdtime,i2cX_sdalowlevelafteri2cX_sclhighlevel 160 s (STOP condition) I7 th(SCLHRSTART) Holdtime,i2cX_sdalowlevelafteri2cX_sclhighlevel 160 ns (fora repeatedSTART condition) tR(SCL) Risetime,i2cX_scl 10 40 ns tR(SCL) Risetime,i2cX_sclaftera repeatedSTART condition 10 80 ns and aftera bitacknowledge tF(SCL) Falltime,i2cX_scl 10 40 ns tR(SDA) Risetime,i2cX_sda 10 80 ns tF(SDA) Falltime,i2cX_sda 10 80 ns (1) Ini2cX,X isequalto1,2,or3. (2) The deviceprovides(viatheI2C bus)a holdtimeofatleast300 ns forthei2cx_sdasignal(refertothefalland risetimeofi2cx_scl)to bridgetheundefinedregionofthefallingedge ofi2cx_scl. (3) HS-mode masterdevicesgeneratea serialclocksignalwitha hightolowratioof1 to2.tw(SCLL) > 2 tw(SCLH) . (4) Afterthistime,thefirstclockisgenerated. Figure6-65.I2C High-Speed Mode (1)(2)(3) (1) HS-mode masterdevicesgeneratea serialclocksignalwitha high-to-lowratioof1 to2.tw(SCLL) > 2 x tw(SCLH) . (2) Ini2cX,X isequalto1,2,or3. (3) Afterthistime,thefirstclockisgenerated. Table6-127.Correspondence Standard vs.TITiming References TI-AM35x STANDARD-I 2C S/F Mode HS Mode fSCL FSCL FSCLH I1 tw(SCLH) THIGH THIGH I2 tw(SCLL) TLOW TLOW I3 tsu(SDAV-SCLH) TSU;DAT TSU;DAT I4 th(SCLH-SDAV) TSU;DAT TSU;DAT I5 tsu(SDAL-SCLH) TSU;STA TSU;STA I6 th(SCLH-SDAH) THD;STA THD;STA I7 th(SCLH-RSTART) TSU;STO TSU;STO Copyright© 2009–2010,Texas InstrumentsIncorporated TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 193 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Table6-127.Correspondence Standard vs.TITiming References(continued) TI-AM35x STANDARD-I 2C S/F Mode HS Mode I8 tw(SDAH) TBUF

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6.7 Removable Media Interfaces

6.7.1 High-Speed MultimediaMemory Card (MMC) and Secure DigitalIO Card (SDIO)Timing

The MMC/SDIO host controllerprovidesan interfaceto high-speedand standardMMC, SD memory cards,or SDIO cards.The applicationinterfaceisresponsibleformanaging transactionsemantics.The MMC/SDIO host controllerdealswithMMC/SDIO protocolat transmissionlevel,packingdata,adding CRC, start/endbit,and checkingforsyntacticalcorrectness. TherearethreeMMC interfaceson theAM3517/05 :

• MMC/SD/SDIO Interface1 : – 1.8-V/3.3-Vsupport – 8 bits
• MMC/SD/SDIO Interface2 : – 1.8-V/3.3-Vsupport – 8 bits – 4 bitswithexternaltransceiverallowingtosupport1.8-V/3.3-Vperipheralsin1.8-Vmode operation. Transceiverdirectioncontrolsignalsaremultiplexedwiththeupperfourdatabits.
• MMC/SD/SDIO Interface3 : – 1.8-V/3.3-Vsupport – 8 bits

6.7.1.1 MMC/SD/SDIO inSD IdentificationMode

The followingtablesassume testingover the recommended operatingconditionsand electrical characteristicconditions. Table6-128.MMC/SD/SDIO Timing ConditionsSD IdentificationMode TIMING CONDITION PARAMETER 1.8V,3.3V UNIT MIN MAX SD IdentificationMode InputConditions tr Inputsignalrisetime 10 ns tf Inputsignalfalltime 10 ns Output Conditions C LOAD Outputloadcapacitance 30 pF Table6-129.MMC/SD/SDIO Timing Requirements SD IdentificationMode (1)(2)(3)(4) NO. PARAMETER 1.8V,3.3V UNIT MIN MAX SD IdentificationMode MMC/SD/SDIO Interface1 HSSD3/SD3 tsu(CMDV-CLKIH) Setuptime,mmc1_cmd validbeforemmc1_clk rising 1198.4 ns clockedge HSSD4/SD4 tsu(CLKIH-CMDIV) Holdtime,mmc1_cmd validaftermmc1_clk rising 1249.2 ns clockedge MMC/SD/SDIO Interface2 HSSD3/SD3 tsu(CMDV-CLKIH) Setuptime,mmc2_cmd validbeforemmc2_clk rising 1198.4 ns clockedge (1) TimingparametersrefertooutputclockspecifiedinTable6-130. (2) The timingrequirementsareassuredforthecyclejitterand dutycycleerrorconditionsspecifiedinTable6-130. (3) Correspondingfiguresshowingtimingparametersarecommon withotherinterfacemodes. (See SD and HS SD modes). (4) Formore information,see theAM35x TechnicalReferenceManual (TRM) [literaturenumber SPRUGR0 ]. Copyright© 2009–2010,Texas InstrumentsIncorporated TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 195 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Table6-129.MMC/SD/SDIO Timing Requirements SD IdentificationMode (1)(2)(3)(4) (continued) NO. PARAMETER 1.8V,3.3V UNIT MIN MAX HSSD4/SD4 tsu(CLKIH-CMDIV) Holdtime,mmc2_cmd validaftermmc2_clk rising 1249.2 ns clockedge MMC/SD/SDIO Interface3 HSSD3/SD3 tsu(CMDV-CLKIH) Setuptime,mmc3_cmd validbeforemmc3_clk rising 1198.4 ns clockedge HSSD4/SD4 tsu(CLKIH-CMDIV) Holdtime,mmc3_cmd validaftermmc3_clk rising 1249.2 ns clockedge Table6-130.MMC/SD/SDIO SwitchingCharacteristicsSD IdentificationMode (1)(2) NO. PARAMETER 1.8V,3.3V UNIT MIN MAX SD IdentificationMode HSSD1/SD1 tc(clk) Cycletime,outputclkperiod 2500 ns HSSD2/SD2 tW(clkH) Typicalpulseduration,outputclkhigh X (3)*PO (4) ns HSSD2/SD2 tW(clkL) Typicalpulseduration,outputclklow Y (5)*PO (4) ns tdc(clk) Dutycycleerror,outputclk 125 ns tj(clk) Jitterstandarddeviation,outputclk 200 ps MMC/SD/SDIO Interface1 tr(clk) Risetime,outputclk 10 ns tf(clkH) Falltime,outputclk 10 ns tr(clkL) Risetime,outputdata 10 ns tf(clk) Falltime,outputdata 10 ns HSSD5/SD5 td(CLKOH-CMD) Delaytime,mmc1_clk risingclockedge tommc1_cmd 6.3 2492.7 ns transition MMC/SD/SDIO Interface2 tr(clk) Risetime,outputclk 10 ns tf(clkH) Falltime,outputclk 10 ns tr(clkL) Risetime,outputdata 10 ns tf(clk) Falltime,outputdata 10 ns HSSD5/SD5 td(CLKOH-CMD) Delaytime,mmc2_clk risingclockedge tommc2_cmd 6.3 2492.7 ns transition MMC/SD/SDIO Interface3 tr(clk) Risetime,outputclk 10 ns tf(clkH) Falltime,outputclk 10 ns tr(clkL) Risetime,outputdata 10 ns tf(clk) Falltime,outputdata 10 ns HSSD5/SD5 td(CLKOH-CMD) Delaytime,mmc3_clk risingclockedge tommc3_cmd 6.3 2492.7 ns transition (1) Correspondingfiguresshowingtimingparametersarecommon withotherinterfacemodes (seeSD and HS SD modes). (2) The jitterprobabilitydensitycan be approximatedby a Gaussianfunction. (3) The X parameterisdefinedas shown below. (4) PO = outputclkperiodinns. (5) The Y parameterisdefinedas shown below. Table6-131.X Parameter CLKD X 1 orEven 0.5 Odd (trunk[CLKD/2]+1)/CLKD

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PRODUCT□PREVIEW AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Table6-132.Y Parameter CLKD Y 1 orEven 0.5 Odd (trunk[CLKD/2])/CLKD

6.7.1.2 MMC/SD/SDIO inHigh-Speed MMC Mode

The followingtablesassume testingover the recommended operatingconditionsand electrical characteristicconditions. Table6-133.MMC/SD/SDIO Timing ConditionsHigh-Speed MMC Mode TIMING CONDITION PARAMETER 1.8V,3.3V UNIT MIN MAX High-Speed MMC Mode InputConditions tr Inputsignalrisetime 0.19 3 ns tf Inputsignalfalltime 0.19 3 ns Output Conditions C LOAD Outputloadcapacitance 30 pF Table6-134.MMC/SD/SDIO Timing Requirements High-Speed MMC Mode (1)(2)(3)(4) NO. PARAMETER 1.8V,3.3V UNIT MIN MAX High-Speed MMC Mode MMC/SD/SDIO Interface1 MMC3 tsu(CMDV-CLKIH) Setuptime,mmc1_cmd validbeforemmc1_clk risingclock 5.61 ns edge MMC4 th(CLKIH-CMDIV) Holdtime,mmc1_cmd validaftermmc1_clk risingclock 3.43 ns edge MMC7 tsu(DATxV-CLKIH) Setuptime,mmc1_datx validbeforemmc1_clk risingclock 5.61 ns edge MMC8 th(CLKIH-DATxIV) Holdtime,mmc1_datx validaftermmc1_clk risingclock 3.47 ns edge MMC/SD/SDIO Interface2 MMC3 tsu(CMDV-CLKIH) Setuptime,mmc2_cmd validbeforemmc2_clk risingclock 5.61 ns edge MMC4 th(CLKIH-CMDIV) Holdtime,mmc2_cmd validaftermmc2_clk risingclock 2.89 ns edge MMC7 tsu(DATxV-CLKIH) Setuptime,mmc2_datx validbeforemmc2_clk risingclock 5.61 ns edge MMC8 th(CLKIH-DATxIV) Holdtime,mmc2_datx validaftermmc2_clk risingclock 2.9 ns edge MMC/SD/SDIO Interface3 MMC3 tsu(CMDV-CLKIH) Setuptime,mmc3_cmd validbeforemmc3_clk risingclock 5.61 ns edge MMC4 th(CLKIH-CMDIV) Holdtime,mmc3_cmd validaftermmc3_clk risingclock 2.53 ns edge MMC7 tsu(DATxV-CLKIH) Setuptime,mmc3_datx validbeforemmc3_clk risingclock 5.61 ns edge (1) Indatx,x isequalto1,2,3,4,5,6,or7. (2) TimingparametersrefertooutputclockspecifiedinTable6-135. (3) The timingrequirementsareassuredforthecyclejitterand dutycycleerrorconditionsspecifiedinTable6-135. (4) Correspondingfiguresshowingtimingparametersarecommon withStandardMMC mode. Copyright© 2009–2010,Texas InstrumentsIncorporated TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 197 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Table6-134.MMC/SD/SDIO Timing Requirements High-Speed MMC Mode (1)(2)(3)(4) (continued) NO. PARAMETER 1.8V,3.3V UNIT MIN MAX MMC8 th(CLKIH-DATxIV) Holdtime,mmc3_datx validaftermmc3_clk risingclock 2.83 ns edge Table6-135.MMC/SD/SDIO SwitchingCharacteristicsHigh-Speed MMC Mode (1)(2) N O. PARAMETER 1.8V,3.3V UNIT MIN MAX High-Speed MMC Mode MMC1 tc(clk) Cycletime,outputclkperiod 20.83 ns MMC2 tW(clkH) Typicalpulseduration,outputclkhigh X (3)*PO (4) ns MMC2 tW(clkL) Typicalpulseduration,outputclklow Y (5)*PO (4) ns tdc(clk) Dutycycleerror,outputclk 1041.67 ps tj(clk) Jitterstandarddeviation,outputclk 200 ps MMC/SD/SDIO Interface1 tc(clk) Risetime,outputclk 3 ns tW(clkH) Falltime,outputclk 3 ns tW(clkL) Risetime,outputdata 3 ns tdc(clk) Falltime,outputdata 3 ns MMC5 td(CLKOH-CMD) Delaytime,mmc1_clk risingclockedge tommc1_cmd Tc/2-0.35 14.11 ns transition MMC6 td(CLKOH-DATx) Delaytime,mmc1_clk risingclockedge tommc1_datx Tc/2-0.31 16.50 ns transition MMC/SD/SDIO Interface2 tc(clk) Risetime,outputclk 3 ns tW(clkH) Falltime,outputclk 3 ns tW(clkL) Risetime,outputdata 3 ns tdc(clk) Falltime,outputdata 3 ns MMC5 td(CLKOH-CMD) Delaytime,mmc2_clk risingclockedge tommc2_cmd Tc/2-0.27 14.11 ns transition MMC6 td(CLKOH-DATx) Delaytime,mmc2_clk risingclockedge tommc2_datx Tc/2-0.42 16.50 ns transition MMC/SD/SDIO Interface3 tc(clk) Risetime,outputclk 3 ns tW(clkH) Falltime,outputclk 3 ns tW(clkL) Risetime,outputdata 3 ns tdc(clk) Falltime,outputdata 3 ns MMC5 td(CLKOH-CMD) Delaytime,mmc3_clk risingclockedge tommc3_cmd Tc/2-0.07 14.11 ns transition MMC6 td(CLKOH-DATx) Delaytime,mmc3_clk risingclockedge tommc3_datx Tc/2-0.293 16.50 ns transition (1) Indatx,x isequalto1,2,3,4,5,6,or7. (2) The jitterprobabilitydensitycan be approximatedby a Gaussianfunction. (3) The X parameterisdefinedas shown below. (4) PO = outputclkperiodinns. (5) The Y parameterisdefinedas shown below. Table6-136.X Parameter CLKD X 1 orEven 0.5 Odd (trunk[CLKD/2]+1)/CLKD

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PRODUCT□PREVIEW AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Table6-137.Y Parameter CLKD Y 1 orEven 0.5 Odd (trunk[CLKD/2])/CLKD FordetailsaboutclockdivisionfactorCLKD, see theAM35x TechnicalReferenceManual.

6.7.1.3 MMC/SD/SDIO inStandard MMC Mode and MMC IdentificationMode

The followingtablesassume testingover the recommended operatingconditionsand electrical characteristicconditions. Table6-138.MMC/SD/SDIO Timing ConditionsStandard MMC Mode and MMC IdentificationMode TIMING CONDITION PARAMETER 1.8-V/3.3-V UNIT MIN MAX Standard MMC Mode and MMC IdentificationMode InputConditions tr Inputsignalrisetime 0.19 10 ns tf Inputsignalfalltime 0.19 10 ns Output Conditions C LOAD Outputloadcapacitance 30 pF Copyright© 2009–2010,Texas InstrumentsIncorporated TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 199 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Table6-139.MMC/SD/SDIO Timing Requirements Standard MMC Mode and MMC IdentificationMode (1)(2) (3) NO. PARAMETER 1.8V/3.3V UNIT MIN MAX Standard MMC Mode and MMC IdentificationMode MMC/SD/SDIO Interface1 MMC3 tsu(CMDV-CLKIH) Setuptime,mmc1_cmd validbeforemmc1_clk rising 13.58 ns clockedge MMC4 th(CLKIH-CMDIV) Holdtime,mmc1_cmd validaftermmc1_clk risingclock 8.9 ns edge MMC7 tsu(DATxV-CLKIH) Setuptime,mmc1_datx validbeforemmc1_clk rising 13.58 ns clockedge MMC8 th(CLKIH-DATxIV) Holdtime,mmc1_datx validaftermmc1_clk risingclock 8.9 ns edge MMC/SD/SDIO Interface2 MMC3 tsu(CMDV-CLKIH) Setuptime,mmc2_cmd validbeforemmc2_clk rising 13.58 ns clockedge MMC4 th(CLKIH-CMDIV) Holdtime,mmc2_cmd validaftermmc2_clk risingclock 8.9 ns edge MMC7 tsu(DATxV-CLKIH) Setuptime,mmc2_datx validbeforemmc2_clk rising 13.58 ns clockedge MMC8 th(CLKIH-DATxIV) Holdtime,mmc2_datx validaftermmc2_clk risingclock 8.9 ns edge MMC/SD/SDIO Interface3 MMC3 tsu(CMDV-CLKIH) Setuptime,mmc3_cmd validbeforemmc3_clk rising 13.58 ns clockedge MMC4 th(CLKIH-CMDIV) Holdtime,mmc3_cmd validaftermmc3_clk risingclock 8.9 ns edge MMC7 tsu(DATxV-CLKIH) Setuptime,mmc3_datx validbeforemmc3_clk rising 13.58 ns clockedge MMC8 th(CLKIH-DATxIV) Holdtime,mmc3_datx validaftermmc3_clk risingclock 8.9 ns edge (1) TimingparametersarereferredtooutputclockspecifiedinTable6-140. (2) The timingrequirementsareassuredforthecyclejitterand dutycycleerrorconditionsspecifiedinTable6-140. (3) Indatx,x isequalto1,2,3,4,5,6,or7. Table6-140.MMC/SD/SDIO SwitchingCharacteristicsStandard MMC Mode and MMC Identification Mode (1)(2) NO. PARAMETER 1.8V,3.3V UNIT MIN MAX MMC IdentificationMode MMC1 tc(clk) Cycletime 2500 ns MMC2 tW(clkH) Typicalpulseduration,outputclkhigh X (3)*PO (4) ns MMC2 tW(clkL) Typicalpulseduration,outputclklow Y (5)*PO (4) ns tdc(clk) Dutycycleerror,outputclk 2604.17 ns tj(clk) Jitterstandarddeviation 200 ps Standard MMC Mode MMC1 tc(clk) Cycletime 2500 ns MMC2 tW(clkH) Typicalpulseduration,outputclkhigh X (3)*PO (4) ns MMC2 tW(clkL) Typicalpulseduration,outputclklow Y (5)*PO (4) ns (1) Indatx,x isequalto1,2,3,4,5,6,or7. (2) The jitterprobabilitydensitycan be approximatedby a Gaussianfunction. (3) The X parameterisdefinedas shown below. (4) PO = outputclkperiodinns. (5) The Y parameterisdefinedas shown below.

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PRODUCT□PREVIEW AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Table6-140.MMC/SD/SDIO SwitchingCharacteristicsStandard MMC Mode and MMC IdentificationMode (1)(2) (continued) NO. PARAMETER 1.8V,3.3V UNIT MIN MAX tdc(clk) Dutycycleerror,outputclk 2604.17 ps tj(clk) Jitterstandarddeviation 200 ps MMC/SD/SDIO Interface1 tr(clk) Risetime,outputclk 10 ns tf(clkH) Falltime,outputclk 10 ns tr(clkL) Risetime,outputdata 10 ns tf(clk) Falltime,outputdata 10 ns MMC5 td(CLKOH-CMD) Delaytime,mmc1_clk risingclockedge tommc1_cmd 4.3 47.78 ns transition MMC6 td(CLKOH-DATx) Delaytime,mmc1_clk risingclockedge tommc1_datx 4.3 47.78 ns transition MMC/SD/SDIO Interface2 tr(clk) Risetime,outputclk 10 ns tf(clkH) Falltime,outputclk 10 ns tr(clkL) Risetime,outputdata 10 ns tf(clk) Falltime,outputdata 10 ns MMC5 td(CLKOH-CMD) Delaytime,mmc2_clk risingclockedge tommc2_cmd 4.3 47.78 ns transition MMC6 td(CLKOH-DATx) Delaytime,mmc2_clk risingclockedge tommc2_datx 4.3 47.78 ns transition MMC/SD/SDIO Interface3 tr(clk) Risetime,outputclk 10 ns tf(clkH) Falltime,outputclk 10 ns tr(clkL) Risetime,outputdata 10 ns tf(clk) Falltime,outputdata 10 ns MMC5 td(CLKOH-CMD) Delaytime,mmc3_clk risingclockedge tommc3_cmd 4.3 47.78 ns transition MMC6 td(CLKOH-DATx) Delaytime,mmc3_clk risingclockedge tommc3_datx 4.3 47.78 ns transition Table6-141.X Parameter CLKD X 1 orEven 0.5 Odd (trunk[CLKD/2]+1)/CLKD Table6-142.Y Parameter CLKD Y 1 orEven 0.5 Odd (trunk[CLKD/2])/CLKD Copyright© 2009–2010,Texas InstrumentsIncorporated TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 201 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW mmcx_clk mmcx_cmd mmcx_dat[3:0] MMC3 MMC7 MMC4 MMC8 MMC1 MMC2 030-104 mmcx_clk mmcx_cmd mmcx_dat[3:0] MMC5 MMC5 MMC6 MMC6 MMC1 MMC2 030-105 AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com FordetailsaboutclockdivisionfactorCLKD, see theAM35x TechnicalReferenceManual. Inmmcx, x isequalto1,2,or3. Figure6-66.MMC/SD/SDIO High-Speed and Standard MMC Modes Data/Command Receive Inmmcx, x isequalto1,2,or3. Figure6-67.MMC/SD/SDIO High-Speed and Standard MMC Modes Data/Command Transmit

6.7.1.4 MMC/SD/SDIO inHigh-Speed SD Mode

The followingtablesassume testingover the recommended operatingconditionsand electrical characteristicconditions. Table6-143.MMC/SD/SDIO Timing ConditionsHigh-Speed SD Mode TIMING CONDITION PARAMETER 1.8V,3.3V UNIT MIN MAX High-Speed SD Mode InputConditions tR Inputsignalrisetime 0.19 3 ns tF Inputsignalfalltime 0.19 3 ns Output Conditions C LOAD Outputloadcapacitance 30 pF Table6-144.MMC/SD/SDIO Timing Requirements High-Speed SD Mode (1)(2)(3) NO. PARAMETER 1.8V,3.3V UNIT MIN MAX High-Speed SD Mode MMC/SD/SDIO Interface1 HSSD3 tsu(CMDV-CLKIH) Setuptime,mmc1_cmd validbeforemmc1_clk rising 5.61 ns clockedge HSSD4 th(CLKIH-CMDIV) Holdtime,mmc1_cmd validaftermmc1_clk rising 2.28 ns clockedge (1) Indatx,x isequalto1,2,3,4,5,6,or7. (2) The timingrequirementsareassuredforthecyclejitterand dutycycleerrorconditionsspecifiedinTable6-145. (3) TimingParametersrefertooutputclockspecifiedinTable6-145.

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PRODUCT□PREVIEW AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Table6-144.MMC/SD/SDIO Timing Requirements High-Speed SD Mode (1)(2)(3) (continued) NO. PARAMETER 1.8V,3.3V UNIT MIN MAX HSSD7 tsu(DATxV-CLKIH) Setuptime,mmc1_datx validbeforemmc1_clk rising 5.61 ns clockedge HSSD8 th(CLKIH-DATxIV) Holdtime,mmc1_datx validaftermmc1_clk rising 2.28 ns clockedge MMC/SD/SDIO Interface2 HSSD3 tsu(CMDV-CLKIH) Setuptime,mmc2_cmd validbeforemmc2_clk rising 5.61 ns clockedge HSSD4 th(CLKIH-CMDIV) Holdtime,mmc2_cmd validaftermmc2_clk rising 2.28 ns clockedge HSSD7 tsu(DATxV-CLKIH) Setuptime,mmc2_datx validbeforemmc2_clk rising 5.61 ns clockedge HSSD8 th(CLKIH-DATxIV) Holdtime,mmc2_datx validaftermmc2_clk rising 2.28 ns clockedge MMC/SD/SDIO Interface3 HSSD3 tsu(CMDV-CLKIH) Setuptime,mmc3_cmd validbeforemmc3_clk rising 5.61 ns clockedge HSSD4 th(CLKIH-CMDIV) Holdtime,mmc3_cmd validaftermmc3_clk rising 2.28 ns clockedge HSSD7 tsu(DATxV-CLKIH) Setuptime,mmc3_datx validbeforemmc3_clk rising 5.61 ns clockedge HSSD8 th(CLKIH-DATxIV) Holdtime,mmc3_datx validaftermmc3_clk rising 2.28 ns clockedge Table6-145.MMC/SD/SDIO SwitchingCharacteristicsHigh-Speed SD Mode (1)(2) NO. PARAMETER 1.8V,3.3V UNIT MIN MAX High-Speed SD Mode HSSD1 tc(clk) Cycletime 20.83 ns HSSD2 tW(clkH) Typicalpulseduration,outputclkhigh X (3)*PO (4) ns HSSD2 tW(clkL) Typicalpulseduration,outputclklow Y (5)*PO (4) ns tdc(clk) Dutycycleerror,outputclk 1041.67 ps tj(clk) Jitterstandarddeviation 200 ps MMC/SD/SDIO Interface1 tr(clk) Risetime,outputclk 3 ns tf(clkH) Falltime,outputclk 3 ns tr(clkL) Risetime,outputdata 3 ns tf(clk) Falltime,outputdata 3 ns HSSD5 td(CLKOH-CMD) Delaytime,mmc1_clk risingclockedge tommc1_cmd 3.72 14.11 ns transition HSSD6 td(CLKOH-DATx) Delaytime,mmc1_clk risingclockedge tommc1_datx 3.72 14.11 ns transition MMC/SD/SDIO Interface2 tr(clk) Risetime,outputclk 3 ns tf(clkH) Falltime,outputclk 3 ns tr(clkL) Risetime,outputdata 3 ns tf(clk) Falltime,outputdata 3 ns (1) Indatx,x isequalto1,2,3,4,5,6,or7. (2) The jitterprobabilitydensitycan be approximatedby a Gaussianfunction. (3) The X parameterisdefinedas shown inTable6-146. (4) PO = outputclkperiodinns. (5) The Y parameterisdefinedas shown inTable6-147. Copyright© 2009–2010,Texas InstrumentsIncorporated TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 203 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW mmcx_clk mmcx_cmd mmcx_dat[3:0] HSSD3 HSSD7 HSSD4 HSSD8 HSSD1 HSSD2 030-106 mmcx_clk mmcx_cmd mmcx_dat[3:0] HSSD5 HSSD5 HSSD6 HSSD6 HSSD1 HSSD2 030-107 AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Table6-145.MMC/SD/SDIO SwitchingCharacteristicsHigh-Speed SD Mode (1)(2) (continued) NO. PARAMETER 1.8V,3.3V UNIT MIN MAX HSSD5 td(CLKOH-CMD) Delaytime,mmc2_clk risingclockedge tommc2_cmd 3.72 14.11 ns transition HSSD6 td(CLKOH-DATx) Delaytime,mmc2_clk risingclockedge tommc2_datx 3.72 14.11 ns transition MMC/SD/SDIO Interface3 tr(clk) Risetime,outputclk 3 ns tf(clkH) Falltime,outputclk 3 ns tr(clkL) Risetime,outputdata 3 ns tf(clk) Falltime,outputdata 3 ns HSSD5 td(CLKOH-CMD) Delaytime,mmc3_clk risingclockedge tommc3_cmd 3.72 14.11 ns transition HSSD6 td(CLKOH-DATx) Delaytime,mmc3_clk risingclockedge tommc3_datx 3.72 14.11 ns transition Table6-146.X Parameters CLKD X 1 orEven 0.5 Odd (trunk[CLKD/2]+1)/CLKD Table6-147.Y Parameters CLKD Y 1 orEven 0.5 Odd (trunk[CLKD/2])/CLKD FordetailsaboutclockdivisionfactorCLKD, see theAM35x TechnicalReferenceManual. Inmmcx, x isequalto1,2,or3. Figure6-68.MMC/SD/SDIO High-Speed SD Mode Data/Command Receive Inmmcx, x isequalto1,2,or3. Figure6-69.MMC/SD/SDIO High-Speed SD Mode Data/Command Transmit

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PRODUCT□PREVIEW AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010

6.7.1.5 MMC/SD/SDIO inStandard SD Mode

The followingtablesassume testingover the recommended operatingconditionsand electrical characteristicconditions. Table6-148.MMC/SD/SDIO Timing ConditionsStandard SD Mode TIMING CONDITION PARAMETER 1.8V,3.3V UNIT MIN MAX Standard SD Mode InputConditions tR Inputsignalrisetime 0.19 10 ns tF Inputsignalfalltime 0.19 10 ns Output Conditions C LOAD Outputloadcapacitance 30 pF Copyright© 2009–2010,Texas InstrumentsIncorporated TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 205 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Table6-149.MMC/SD/SDIO Timing Requirements Standard SD Mode (1)(2)(3) NO. PARAMETER 1.8V,3.3V UNIT MIN MAX Standard SD Mode MMC/SD/SDIO Interface1 SD3 tsu(CMDV-CLKIH) Setuptime,mmc1_cmd validbeforemmc1_clk risingclock 6.23 ns edge SD4 th(CLKIH-CMDIV) Holdtime,mmc1_cmd validaftermmc1_clk risingclock 19.37 ns edge SD7 tsu(DATxV-CLKIH) Setuptime,mmc1_datx validbeforemmc1_clk risingclock 6.23 ns edge SD8 th(CLKIH-DATxIV) Holdtime,mmc1_datx validaftermmc1_clk risingclock 19.37 ns edge MMC/SD/SDIO Interface2 SD3 tsu(CMDV-CLKIH) Setuptime,mmc2_cmd validbeforemmc2_clk risingclock 6.23 ns edge SD4 th(CLKIH-CMDIV) Holdtime,mmc2_cmd validaftermmc2_clk risingclock 19.37 ns edge SD7 tsu(DATxV-CLKIH) Setuptime,mmc2_datx validbeforemmc2_clk risingclock 6.23 ns edge SD8 th(CLKIH-DATxIV) Holdtime,mmc2_datx validaftermmc2_clk risingclock 19.37 ns edge MMC/SD/SDIO Interface3 SD3 tsu(CMDV-CLKIH) Setuptime,mmc3_cmd validbeforemmc3_clk risingclock 6.23 ns edge SD4 th(CLKIH-CMDIV) Holdtime,mmc3_cmd validaftermmc3_clk risingclock 19.37 ns edge SD7 tsu(DATxV-CLKIH) Setuptime,mmc3_datx validbeforemmc3_clk risingclock 6.23 ns edge SD8 th(CLKIH-DATxIV) Holdtime,mmc3_datx validaftermmc3_clk risingclock 19.37 ns edge (1) TimingparametersrefertooutputclockspecifiedinTable6-150. (2) The timingrequirementsareassuredforthecyclejitterand dutycycleerrorconditionsspecifiedinTable6-150. (3) Indatx,x isequalto1,2,3,4,5,6,or7. Table6-150.MMC/SD/SDIO SwitchingCharacteristicsStandard SD Mode (1)(2) NO. PARAMETER 1.8V,3.3V UNIT MIN MAX Standard SD Mode SD1 tc(clk) Cycletime 41.67 ns SD2 tW(clkH) Typicalpulseduration,outputclkhigh X (3)*PO (4) ns SD2 tW(clkL) Typicalpulseduration,outputclklow Y (5)*PO (4) ns tdc(clk) Dutycycleerror,outputclk 2083.33 ps tj(clk) Jitterstandarddeviation 200 ps MMC/SD/SDIO Interface1 tr(clk) Risetime,outputclk 10 ns tf(clkH) Falltime,outputclk 10 ns tr(clkL) Risetime,outputdata 10 ns tf(clk) Falltime,outputdata 10 ns (1) The jitterprobabilitydensitycan be approximatedby a Gaussianfunction. (2) Indatx,x isequalto1,2,3,4,5,6,or7. (3) The X parameterisdefinedas shown inTable6-151. (4) PO = outputclkperiodinns. (5) The Y parameterisdefinedas shown inTable6-152.

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PRODUCT□PREVIEW mmcx_clk mmcx_cmd mmcx_dat[3:0] SD3 SD7 SD4 SD8 SD1 SD2 030-108 AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Table6-150.MMC/SD/SDIO SwitchingCharacteristicsStandard SD Mode (1)(2) (continued) NO. PARAMETER 1.8V,3.3V UNIT MIN MAX SD5 td(CLKOH-CMD) Delaytime,mmc1_clk risingclockedge tommc1_cmd 6.13 35.53 ns transition SD6 td(CLKOH-DATx) Delaytime,mmc1_clk risingclockedge tommc1_datx 6.13 35.53 ns transition MMC/SD/SDIO Interface2 tr(clk) Risetime,outputclk 10 ns tf(clkH) Falltime,outputclk 10 ns tr(clkL) Risetime,outputdata 10 ns tf(clk) Falltime,outputdata 10 ns SD5 td(CLKOH-CMD) Delaytime,mmc2_clk risingclockedge tommc2_cmd 6.13 35.53 ns transition SD6 td(CLKOH-DATx) Delaytime,mmc2_clk risingclockedge tommc2_datx 6.13 35.53 ns transition MMC/SD/SDIO Interface3 tr(clk) Risetime,outputclk 10 ns tf(clkH) Falltime,outputclk 10 ns tr(clkL) Risetime,outputdata 10 ns tf(clk) Falltime,outputdata 10 ns SD5 td(CLKOH-CMD) Delaytime,mmc3_clk risingclockedge tommc3_cmd 6.13 35.53 ns transition SD6 td(CLKOH-DATx) Delaytime,mmc3_clk risingclockedge tommc3_datx 6.13 35.53 ns transition Table6-151.X Parameter CLKD X 1 orEven 0.5 Odd (trunk[CLKD/2]+1)/CLKD Table6-152.Y Parameter CLKD Y 1 orEven 0.5 Odd (trunk[CLKD/2])/CLKD FordetailsaboutclockdivisionfactorCLKD, see theAM35x TechnicalReferenceManual. Inmmcx, x isequalto1,2,or3. Figure6-70.MMC/SD/SDIO Standard SD Mode Data/Command Receive Copyright© 2009–2010,Texas InstrumentsIncorporated TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 207 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW mmcx_clk mmcx_cmd mmcx_dat[3:0] SD1 SD2 SD5 SD6 SD5 SD6 030-109 AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Inmmcx, x isequalto1,2,or3. Figure6-71.MMC/SD/SDIO Standard SD Mode Data/Command Transmit

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PRODUCT□PREVIEW etk_clk etk_ctl etk_d[15:0] ETM0 ETM2 ETM3 ETM2 ETM1 ETM3 030-1 10 AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010

6.8 TestInterfaces

The emulationand traceinterfacesallowtracingactivitiesofthefollowingCPUs:

• ARM1136JF-STM throughan Embedded TraceMacro-cell(ETM11) dedicatedtoenablereal-time traceoftheARM subsystemoperations. Allprocessorscan be emulatedviaJTAG ports.

6.8.1 Embedded Trace Macro Interface(ETM)

The followingtablesassume testingovertherecommended operatingconditions. Table6-153.Embedded Trace Macro InterfaceSwitchingCharacteristics NO. PARAMETER MIN MAX UNIT f 1/tc(CLK) Frequency,etk_clk 166 MHz ETM0 tc(CLK) Cycletime 6.02 ns ETM1 tW(CLK) Clockpulsewidth,etk_clk 3.01 ns ETM2 td(CLK-CTL) Delaytime,etk_clkclockedge toetk_ctltransition -0.5 0.5 ns ETM3 td(CLK-D) Delaytime,etk_clkclockhightoetk_d[15:0]transition -0.5 0.5 ns Figure6-72.Embedded Trace Macro Interface

6.8.2 JTAG Interfaces

AM3517/05 JTAG TAP controllerhandlesstandardIEEE JTAG interfaces.The followingsectionsdefine thetimingrequirementsforseveraltoolsused totesttheAM3517/05 processorsas:

• Freerunningclocktool,likeXDS560 and XDS510 tools
• Adaptiveclocktool,likeRealViewICE tooland Lauterbachtool

6.8.2.1 JTAG Free Running Clock Mode

The followingtablesassume testingover the recommended operatingconditionsand electrical characteristicconditions. Table6-154.JTAG Timing ConditionsFree Running Clock Mode TIMING CONDITION PARAMETER 1.8V 3.3V MAX MAX UNIT InputConditions tR Inputsignalrisetime 5 3 ns tF Inputsignalfalltime 5 3 ns Output Conditions C LOAD Outputloadcapacitance 30 pF Copyright© 2009–2010,Texas InstrumentsIncorporated TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 209 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Table6-155.JTAG Timing Requirements Free Running Clock Mode (1)(2)(3) 1.8V 3.3VNO. PARAMETER UNIT MIN MAX MIN MAX JT4 tc(tck) Cycletime 20 20 ns JT5 tw(tckL) Typicalpulseduration,jtag_tcklow 10 10 ns JT6 tw(tckH) Typicalpulseduration,jtag_tckhigh 10 10 ns tdc(tck) Dutycycleerror,jtag_tck -1250 1250 -1250 1250 ps tj(tck) Cyclejitter -1250 1250 -1250 1250 ps JT7 tsu(tdiV-rtckH) Setuptime,jtag_tdivalidbeforejtag_rtckhigh 1.8 3.8 ns JT8 th(tdiV-rtckH) Holdtime,jtag_tdivalidafterjtag_rtckhigh 0.7 2.7 ns JT9 tsu(tmsV-rtckH) Setuptime,jtag_tmsvalidbeforejtag_rtckhigh 1.8 3.8 ns JT10 th(tmsV-rtckH) Holdtime,jtag_tmsvalidafterjtag_rtckhigh 0.7 2.7 ns JT12 tsu(emuxV-rtckH) Setuptime,jtag_emux 14.6 14.6 ns JT13 th(emuxV-rtckH) Holdtime,jtag_emux 2 2 ns (1) Maximum cyclejittersupportedby jtag_tckinputclock. (2) x = 0 to1 (3) The timingrequirementsareassuredforthecyclejitterand dutycycleerrorconditionsspecified. Table6-156.JTAG SwitchingCharacteristicsFree Running Clock Mode (1)(2) 1.8V 3.3V NO. PARAMETER MIN MAX MIN MAX UNIT JT1 tc(rtck) Cycletime(1),jtag_rtckperiod 20 20 ns JT2 tw(rtckL) Typicalpulseduration,jtag_rtcklow 10 10 ns JT3 tw(rtckH) Typicalpulseduration,jtag_rtckhigh 10 10 ns tdc(rtck) Dutycycleerror,jtag_rtck -1250 1250 -1250 1250 ps tj(rtck) Jitterstandarddeviation(2),jtag_rtck 33.33 33.33 ps tR(rtck) Risetime,jtag_rtck 4 4 ns tF(rtck) Falltime,jtag_rtck 4 4 ns JT11 td(rtckL-tdoV) Delaytime,jtag_rtcklowtojtag_tdovalid -5.8 5.8 -8 8 ns tR(tdo) Risetime,jtag_tdo 4 4 ns tF(tdo) Falltime,jtag_tdo 4 4 ns JT14 td(rtckH-emuxV) Delaytime,jtag_rtckhighto,jtag_emux 2.7 15.1 2.7 15.1 ns tR(emux) Risetime,jtag_emux 6 6 ns tF(emux) Falltime,jtag_emux 6 6 ns (1) Relatedwiththejtag_rtckmaximum frequency. (2) The jitterprobabilitydensitycan be approximatedby a Gaussianfunction.

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PRODUCT□PREVIEW jtag_tck jtag_rtck jtag_tdi jtag_tms jtag_emux(IN) jtag_tdo jtag_emux(OUT) JT7 JT1 1 JT1 JT2 JT3 JT8 JT10JT9 JT4 JT5 JT6 JT12 JT13 JT14 030-1 13 AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010 Injtag_emux,x isequalto0 to1. Figure6-73.JTAG InterfaceTiming Free Running Clock Mode

6.8.2.2 JTAG AdaptiveClock Mode

The followingtablesassume testingover the recommended operatingconditionsand electrical characteristicconditions. Table6-157.JTAG Timing ConditionsAdaptiveClock Mode TIMING CONDITION PARAMETER 1.8V 3.3V MAX UNIT InputConditions tR Inputsignalrisetime 5 3 ns tF Inputsignalfalltime 5 3 ns Output Conditions C LOAD Outputloadcapacitance 30 pF Table6-158.JTAG Timing Requirements AdaptiveClock Mode (1)(2) 1.8V 3.3V NO. PARAMETER MIN MAX MIN MAX UNIT JA4 tc(tck) Cycletime 20 20 ns JA5 tw(tckL) Typicalpulseduration,jtag_tcklow 10 10 ns JA6 tw(tckH) Typicalpulseduration,jtag_tckhigh 10 10 ns tdc(lclk) Dutycycleerror,jtag_tck -2500 2500 -2500 2500 ps tj(lclk) Cyclejitter -1500 1500 -1500 1500 ps JA7 tsu(tdiV-tckH) Setuptime,jtag_tdivalidbeforejtag_tckhigh 13.8 13.8 ns JA8 th(tdiV-tckH) Holdtime,jtag_tdivalidafterjtag_tckhigh 13.8 13.8 ns JA9 tsu(tmsV-tckH) Setuptime,jtag_tmsvalidbeforejtag_tckhigh 13.8 13.8 ns JA10 th(tmsV-tckH) Holdtime,jtag_tmsvalidafterjtag_tckhigh 13.8 13.8 ns (1) Maximum cyclejittersupportedby jtag_tckinputclock. (2) The timingrequirementsareassuredforthecyclejitterand dutycycleerrorconditionsspecified. Copyright© 2009–2010,Texas InstrumentsIncorporated TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 211 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW jtag_tck jtag_tdi jtag_tms jtag_rtck jtag_tdo JA1 JA2 JA3 JA4 JA5 JA6 JA7 JA8 JA10JA9 JA1 1 030-1 14 AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Table6-159.JTAG SwitchingCharacteristicsAdaptiveClock Mode (1) 1.8V 3.3V NO. PARAMETER MIN MAX MIN MAX UNIT JA1 tc(rtck) Cycletime 20 20 ns JA2 tw(rtckL) Typicalpulseduration,jtag_rtcklow 10 10 ns JA3 tw(rtckH) Typicalpulseduration,jtag_rtckhigh 10 10 ns tdc(rtck) Dutycycleerror,jtag_rtck -2500 2500 -2500 2500 ps tj(rtck) Jitterstandarddeviation 33.33 33.33 ps tR(rtck) Risetime,jtag_rtck 4 4 ns tF(rtck) Falltime,jtag_rtck 4 4 ns JA11 td(rtckL-tdoV) Delaytime,jtag_rtcklowtojtag_tdovalid -14.6 14.6 -14.6 14.6 ns tR(tdo) Risetime,jtag_tdo, 4 4 ns tF(tdo) Falltime,jtag_tdo 4 4 ns (1) The jitterprobabilitydensitycan be approximatedby a Gaussianfunction. Figure6-74.JTAG InterfaceTiming AdaptiveClock Mode

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PRODUCT□PREVIEW AM3517,AM3505 www.ti.com SPRS550A –OCTOBER 2009–REVISED MAY 2010

7 PACKAGE CHARACTERISTICS

7.1 Package Thermal Resistance

Table7-1providesthethermalresistancecharacteristicsfortherecommended package typesused on the AM3517/05 . Table7-1.AM3517/05 Thermal ResistanceCharacteristics(1) PACKAGE POWER (W) R JA (C/W) R JB (C/W) R JC (C/W) BOARD TYPE Figure6-31 ZCN Pkg. 1.6 24.58 10.81 - 2S2P ZER Pkg. 1.6 15.8 6 6 2S2P (1) R JA (Theta-JA)= ThermalResistanceJunction-to-Ambient,C/W R JB (Theta-JB)= ThermalResistanceJunction-to-Board,C/W R JC (Theta-JC)= ThermalResistanceJunction-to-Case,C/W

7.2 Device Support

7.2.1 Device and Development-Support Tool Nomenclature

To designatethestagesintheproductdevelopmentcycle,TI assignsprefixestothepartnumbers ofall AM35x processorsand supporttools.Each devicehas one of threeprefixes:X, P, or null(no prefix). Texas Instrumentsrecommends two ofthreepossibleprefixdesignatorsforitssupporttools:TMDX and TMDS. These prefixesrepresentevolutionarystagesofproductdevelopmentfromengineeringprototypes (TMDX) throughfullyqualifiedproductiondevices/tools(TMDS). Devicedevelopmentevolutionaryflow: X Experimentaldevicethatis not necessarilyrepresentativeof the finaldeviceselectrical specificationsand may notuse productionassemblyflow.(TMX definition) P Prototypedevicethatisnot necessarilythe finalsilicondieand may not necessarilymeet finalelectricalspecifications.(TMP definition) null Productionversionofthesilicondiethatisfullyqualified.(TMS definition) Supporttooldevelopmentevolutionaryflow: TMDX Development supportproductthathas not yet completed Texas Instrumentsinternal qualificationtesting. TMDS Fullyqualifieddevelopmentsupportproduct. TMX and TMP devices and TMDX development-supporttoolsare shipped againstthe following disclaimer: Developmentalproductisintendedforinternalevaluationpurposes. Productiondevicesand TMDS development-supporttoolshave been characterizedfully,and thequality and reliabilityofthedevicehave been demonstratedfully.TIsstandardwarrantyapplies. Predictionsshow thatprototypedevices(X orP),have a greaterfailureratethanthestandardproduction devices.Texas Instrumentsrecommends thatthese devicesnot be used in any productionsystem because theirexpectedend-usefailureratestillisundefined.Only qualifiedproductiondevicesaretobe used. For additionaldescriptionofthedevicenomenclaturemarkings,see theAM35x ProcessorSiliconErrata (literaturenumber SPRZ306 ). Copyright© 2009–2010,Texas InstrumentsIncorporated PACKAGE CHARACTERISTICS 213 SubmitDocumentationFeedback ProductFolderLink(s):AM3517 AM3505

PRODUCT□PREVIEW PREFIX X AM3517 B X = Experimental Device P = Prototype Device blank = Production Device DEVICE PACKAGE TYPE ZCN = 491-pin sPBGA ZER = 484-pin sPBGASILICON REVISION ZCN ( ) blank = commercial temperature A = extended temperature AM3517,AM3505 SPRS550A –OCTOBER 2009–REVISED MAY 2010 www.ti.com Figure7-1.Device Nomenclature

7.2.2 Documentation Support

7.2.2.1 RelatedDocumentation from Texas Instruments

The followingdocuments describetheAM3517/05 ARM Microprocessor.Copies ofthesedocuments are availableon the Internetat www.ti.com. Tip:Enterthe literaturenumber inthe searchbox providedat www.ti.com. The currentdocumentationthatdescribestheAM3517/05 ARM Microprocessor,relatedperipherals,and othertechnicalcollateral,isavailableintheproductfolderat:www.ti.com. SPRUGR0 AM35x ARM MicroprocessorTechnicalReference Manual. Collectionof documents providingdetailedinformationon theSitaraTM architectureincludingpower,reset,and clock control,interrupts,memory map, and switchfabricinterconnect.Detailedinformationon the microprocessorunit(MPU) subsystem as wella functionaldescriptionof the peripherals supportedon AM3517/05 devicesisalsoincluded.

7.2.2.2 RelatedDocumentation from Other Sources

The followingdocuments arerelatedtotheAM3517/05 ARM Microprocessor.Copiesofthesedocuments can be obtaineddirectlyfromtheinternetorfromyourTexas Instrumentsrepresentative. Cortex-A8 Technical Reference Manual. This is the technicalreferencemanual forthe Cortex-A8 processor.A copy ofthisdocument can be obtainedviatheinternetathttp://infocenter.arm.com.Please see the AM3517/05 ARM MicroprocessorSiliconErrata(literaturenumber SPRZ306 ) to determinethe revisionoftheCortex-A8coreused on yourdevice. ARM Core CortexTM -A8 (AT400/AT401) ErrataNotice.Providesa listof advisoriesforthe different revisionsoftheCortex-A8processor.ContactyourTIrepresentativefora copy ofthisdocument.Please see the AM3517/05 ARM MicroprocessorSiliconErrata(literaturenumber SPRZ306 ) to determinethe revisionoftheCortex-A8coreused on yourdevice.

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Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) XAM3517ZCN ACTIVE NFBGA ZCN 491 1 TBD Call TI Call TI (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 6-Apr-2010 Addendum-Page 1

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