AM2841

AM3341 FAIRCHILD | Alldatasheet

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64 x 4 Bits First-In First-Out Memories Complex MOS Integrated Circuits Distinctive Characteristics © Am2841 has 1MHz guaranteed data rate © Am2841A has 1.2MHz guaranteed data rate © “Plug-In” replacement for Fairchild 3341 © 100% reliability assurance testing in compliance with © Asynchronous buffer for up to 64 four-bit words MIL-STD-883 © Easily expandable to larger buffers © Special input circuit provides true TTL compatibility FUNCTIONAL DESCRIPTION The Am3341/Am2841/Am2841A is an asynchronous firstin fist Parallel expansion to wider words only requires that rows of FIFOs out memory stack, organized a 64 four-bit words. The device be placed side By sie, accepts 9 four-bit parallel word Dg—D3 under control of the shift in {S1) input. Data entered into the FIFO immediately ripples Reading and writing operations are completely independent, so the through the device to the outputs Og—G3. Up to 6 words may be device can be used as 0 buffer between two digital machines op- entered before any words are read from the memory. The stored erating asynchronously and at widely differing clock rates, Special words line up at the output end in the order in which they were input circuits are provided on all inputs to pull the input signals up written. A read command on the shift out input (SO) causes the to an MOS Viy when a TTL Vou is reached, providing true TTL fhext to the last word of data to move to the output and all data compatibility without the inconvenience and extra power drain of shifts one place down the stack. Input raady (IR) and output ready external pull-up resistors, A detailed description of the operation is {OR) signals act as memory full and memory empty flags and also fon pages 4 and § of this data sheet. The Am2B41 anc Am2841A are Provide the necessary pulses for interconnecting FIFOs to obtain functionally identical to the Am3341, but are higher pertormance Seeper stacks, Sevices. LOGIC BLOCK DIAGRAM : + 22 =o : — ° = a Pet egies : ORDERING INFORMATION CONNECTION DIAGRAM LOGIC SYMBOL Top View Amagat 12841 Amanat Bananas Pree Tengwarue “Orr “Orca “Ona ioe E} Tyee ‘Renee Number Number Nba Pe. ceseamaney Sf 82 Molded DIP fcr +70 AMINAIPC AMZeATPC AMaBEIAPC fon ro oF 30 Hermeve OF © G'E1 +7FC_AMDBAIDE AMZBAIDE AMZBEIADC os. onf— 4 Hermie IP 88°C 0 s125°C fanzoa10M 2 fin wn a Oe Note ANIME AMBRE AMZBAIA tte ses % OUOUUVDUUDD Yea HO 5 Dy Ds Von Note Ves « Pin 18 ‘Tha dice supplied will contain units which meet both Voc = Fit O°C 10 470°C and ~55°C 10 +125°C tamperature ranges, Note: Pin 1 is marked for orientation, Yop = GND = Ping @ 4077984 0000133 515 a 3\\

MAXIMUM RATING (Above which the useful life may be impaired) | Storage Temperature a _=65°C to +150°C Temperature (Ambient] Under Bias -55°C to +125°C | Vp Supply Voltage _ ee Vgs -7V to Vgs +0.3V | Voc Supply Voltage Vss ~20V to Veg +0.3V OC Input Voltage Vgg —10V to Vgg +0.3V OPERATING RANGE Part No. Amblant Temperature Vs. Yoo Veo ‘AmaaayPC, OC | Am28a1PC, DC orct0 +70°C $5.0 45% GND | -12078% Am2841APC, DC i amgeaiom —j -ss"crorrze'c | vsoes% | ano | -12.0:5% —eerereree ae eee ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (Unless Otherwise Noted) ‘i sti Typ. Parameters Deseription Conditions Min, note 7) Max. Units <— Output HIGH Voltage Ton = 300mA Vss—10 | I Vous Vor | Output LOW Voltage ———S*~*~S:S*S*« LS mA ° rs a. rr : Vn S“WpputHiGH Level ~~ Vgg 4.0 . “Vous i Vie 1 Tapur LOW Level oa Volts jg e On tet ee nr anne - | he | Tnout Leakage Current Vin = 0V 190 ey ' In urrent = Vs ~ eer. tH | IMPUEHIGH Current MINE MSS =1.0V 280 -—---_ .-“A_} i “TT Vgg © MIN. 20 Volts Veur | _Input Pullup Initiation Voltage (Note 2) S87 MIN ! [ss = MAX 22 vous SSS EAR Vear Voltage at Peak input Current (Note 2) Vsg 18 Volts Dtpar [Maximum Inpot Current (Note 2) ° 16 mA | \\ Vee e Tas 0'C 10 +70°C 7 2 ‘a ‘66 6G Ta 55°C 10 #125 C 16 j j Toe Tas 0C10+70°C 30 a8 a f urrent ta eevee Sg po i 00 Ta= 58°C 10 1256 T 60 Notes: 1. Typical limits are at Vgg = SOV, Vag * -12.0V, Ta = 28°C

2 Sue graph of input V | characterianice

SWITCHING CHARACTERISTICS OVER OPERATING RANGE (Uniess Otherwise Noted) Am3341 ‘Am2841 Am2841A4 Frequency _ | uns | Deley, SIHIGH wR Low [90 f 280 [sso [eo || 400 | 00 aso | ns Minimum Time SI and } 7 fOv+ | IR both HIGH 100 80 | [a0 | om i Minimurn Time Stand i | nt {apgi__| Date Alesse Time rs 200 200 | top__| Date Setup Time a OI poy fet — [os tons | Belov, SONIGHro ORLOW | 90 500 {70 [700 450 “| 80 [1200 | "370 [as ton— Delay, SO LOW to OR HIGH ‘50 [70] 200 880] 70 [200 7 450 [| [ter Riepte through Time Firo empty [fo ae fe eT fe Te Te | [ tow | Belov. OR LOW to Oars Gur | so=tow [7s [Te ea [tw | Minimum Reser Putse Wid [aon [foo TT oo Ts 10a | Delay. Date Ouro ORHIGH | sO= HIGH “To | a0 | o | 20 o [20 ns | Gy | lnput Capacitance (Except | 5 1 7 om MA) pF Note: Switching times over the entie temperature range are sueh that two devices at approximately the same ambient temperature can drive each other. MH 8077984 0000134 455 mm 32.

Pull-up Characteristic Input | <___ Current Versus Input Voltage | fas : -—— | 2 gee ee |e | 3° |

2 So 0 2 30 40 50 60

DESCRIPTION OF THE Am3341 FIFO OPERATION The data falling through the register stacks up at the output end. At the output the last control register bit is buffered and brought The Am3341 FIFO consists internally of 64 four-bit data registers ut as Output Ready (OR]_ A HIGH on OR indicates there is a ‘and one 64-bit control register, as shown in the logic block ““1"" in the last contro! register bit and therefore there is valid diagram. A “1” in a bit of the control register indicates that 2 data on the four data outputs Qg—O3. An input signal, shift out tour-bit data word is stored in the corresponding data register, A (SOI, is used to shift the data out of the FIFO. A LOW-to-HIGH "9" in a bit of the control register indicates that the corre transition on SO clears the last register bit, causing OR to go sponding data register does not contain valid data, The contro! LOW, indicating thet the data on the outputs may no longer be register directs the movement of data through the data registers. valid. When SO goes LOW, the “0” which is now present at the Waenever the nt® bit of the control register contains a “1” and _last control register bit allows the data in the next to the last the (n+ 1th bit contains a “0”, then a strobe is generated causing register to move into the last register position and on to the the (n+1)th data register to read the contents of the nth data outputs. The "0" in the control register then “bubbles” back register, simultaneously setting the (n+1)th control register toward the input as the data shifts toward the output bit and clearing the nt control register bit, so that the control —_f the memory is emptied by reading out all the data, then when flag moves with the data. In this fashion data in the data register the last word is being read out and SO goes HIGH, OR will go moves down the stack of data registers toward the output as long LOW as before, but when SO next goes LOW, there is no data as there are “empty” locations ahead of it, The fall through oper to move into the last location, so OR remains LOW until more gtion stops when the data reaches a register n with a “"I”" in the gata arrives at the output. Similarly, when the memory is full {n#1)th control register bit, or the end of the register. data written into the first location will not shift into the second Data is initially loaded from the four data inputs Do~D3 by when foes LOW. and IR will remain LOW instead of returning applying 2 LOW-to-HIGH transition on the shift in (SI) input. A "1" is placed in the first control register bit simultaneously. The pairs of input and output control signals are designed so that The first control register bit is returned, buffered, to the input ‘the SO input of one FIFO can be driven by the IR output of ready {IR} outout, and this pin goes LOW indicating that data has another, and the OR output of the first FIFO ean drive the SI been entered into the first data register and the input is now input of the second, allowing simple expansion of the FIFO to “busy”, unable to accept more data. When SI next goes LOW, any depth. Wider buffers are formed by allowing paraliel rows of the fallithrough process begins (assuming that at least the second ‘FIFOs to operate together, as shown in the application on the location is empty). The data in the first register is copied into last page. the second, and the first control register bit is cleared, This An over-riding master reset (MR) is used to reset all contro! causes IR to go HIGH, indicating the inputs are available for register bits and remove the data from the output (i.e. reset the another data word. outputs to all LOW), @ 6077984 0000135 34] 2,

Stoo CEPEETET) INITIAL CONDITION Word “"C" written in same manner, and so on. When buffer is fll, FIFO empty, SI LOW IR HIGH, word “A” on inputs. all control bits ae I's and IR stays LOW. 2 * 8 Saray CERPEPET ce ee FIRST READ OPERATION Write input into first stage by raising SI. (4 = delay) IR goes LOW ‘SO goes HIGH, indicating “Ready to Read’. OR then goes LOW indiceting data has been entered ingieating “Data Read". 3 % = 9 Tes] we a BNA TAA CrEREEETE) GrTTrrrry Release dats into FIFO by lowering Si. After delay, data moves to When SO goes LOW, the “0” in the last contro! bit bubbles toward second location, and 1R goet HIGH indicating input available for | the memory input. OR goes HIGH a: the new word arrives at the new data word. ‘output. 1F goes HIGH when "0" reaches input 4 % SE EERE EE 10 SC Car oy GEeTeTeETeTT] EEETTErT jae ——a} . — Data spontaneously riople through repisters to end of FIFO, causing word “8 out, word “C*" moves to output, end so on OR to go HIGH. The time required for dats to fall completely Reed word “8 out, word “Cm 10 output, and so on. through the FIFO is the "Ripplesthrough Time” 5 " =.) ] =) 5)> ee an a — EEEEEETT CEPEEEET a oo Read word “H". OR stays LOW because FIFO is empty. Word ‘Word “8” written into FIFO “HI remains in output until new word falls through. © DI CICy w]e | EePEEEETT) St goes LOW allowing word “B" to ell through M@™@ 5077984 000013b 225 34

seston 8 10) a | “ | “Ot aaa wsv we ee i a wax i ine! 00-44 = o oe NVVVVVVA/VA on FVVVVVVVV V4 i Hote axtacur i WOK i USER NOTES 1. When the memory is empty the last word read will remain on. the outputs until the master reset is strobed or a new data word falls through to the output. However. OR will remain LOW, indicating data at the output is not valid 2. When the output data changes as a result of a pulse on SO, the OR signal always goes LOW before there is any change in ‘output data and always stays LOW until after the new data has appeared on the outputs, so anytime OR is HIGH, there is good, stable data on the outputs. 3. If SO is held HIGH while the memory is empty and a word is written into the input, then that word will fall through the memory to the output. OR will go HIGH for one internal cycle (at least tog+) and then will go back LOW again. The stored word will remain on the outputs. If more words are written into the FIFO, they will line up behind the first word and will not appear on the outputs until SO has been brought Low.

4 When the master reset is brought LOW, the control register

and the outputs are cleared. IR goes HIGH and OR goes LOW. If SI is HIGH when the master reset goes HIGH then the data on the inputs will be written into the memory and IR will return to the LOW state until SI is brought LOW. If SI is LOW when the master reset is ended, then IR will go HIGH, but the data on the inputs will not enter the memory until Si goes HIGH. Mm 46077984 0000137 164 mm —

o Be os os = oe te | - _ al oe Bs re Fo aos Fd ef Fo a The composite input ready indicates both devices are ready to receive data. The shift in pulse must be wide enough for all devices to load data under worst case conditions.

8 X 192 FIFO Buffer Using Am3341/Am2841

16-Pin Side Brazed 16-Pin Molded a POA — a + PIV Se — | | 28-3 ai oa EY —,.* ayy [+e a ar —Z2- Bob ++ 8 Ha Metallization and Pad Layout = 74] 09 + — SSR Sa > 120 a = e120, | 1s TIS 0, 126 x138Mils Yoo ho me 8077984 0000138 OTO a Blo