AM2716B ETC1 | Alldatasheet
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2048 x 8-Bit/4096 x 8-Bit EPROM ADVANCE INFORMATION DISTINCTIVE CHARACTERISTICS Hy © Fast access times —as low as 100 ns © Single +5-V power supply 2 © Low-power dissipation © TTL-compatible inputs and outputs & © Programming voltage — 12.6 V © 10% power-supply tolerance available > GENERAL DESCRIPTION 4 The Am2716B and Am2732B are ultraviolet Erasable To eliminate bus contention on a multiple-bus microproces- | Programmable Read-Only Memories (EPROMs) and are sor system, all AMD EPROMs offer separate output enable organized as 2048 x8 bits, and 4096 x 8 bits, respectively. (OE) and chip enable (CE) controls. All standard EPROM offer access times of 250 ns, . ° nS: All signals are TTL levels, including programming signals. allowing operation with high-speed microprocessors with- Bi iocations may be programmed singly, in blocks, or at ‘out any Wait states. Some of AMD's EPROMs have access 7 nn ming time, AMD's EPROMS times of as fast as 100 ns. tray be, progan * fay be programmed using 1-ms pulses. BLOCK DIAGRAM aga ourpurs — Boao oo ——. Oo te a our ename pitirors : =~ | ee spores | eure H ‘80000281 PRODUCT SELECTOR GUIDE [Fore | amcrieranareas ‘Ordering Part No. +8% Voc | 27168-105 | 27168-155 | 27168-205 | 27168 27168-9305 | 2716B-455 Tolerance | 27328-105 | 27328-155_| 27328.205 | 27328 27328-905 | 27328-455 £10% Vee [27168-100 | 27168-1650 | 27168-200 | 27168-2650 | 27168-300 | 27168-4568" Tolerance | 27328-100 | 27928-150 | 27328.200 | 27328.250 | 27328-300 | 27928-4568" [-tace (ne) [100 [150 200 soto aso [ tetra) [too [150 f'a00 280 00 aso Ltoetney [75 ss 00 sto 50 ‘08160 Ly 70 6+ ‘issue Date: May 1986
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ORDERING INFORMATION (Cont'd.) Standard Products ‘AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: A. Device Number B. Speed Option (if applicable) ©, Package Type D. Temperature Range E, Optional Processing a = L E. OPTIONAL PROCESSING Blank = Standard processing 0. TEMPERATURE RANGE C= Commercial 0 to +70"C) I= Industrial (-40 to +85°C) E = Extended (-55 to +125*O) ©. PACKAGE TYPE D = 24.Pin Coramic DIP (COv024) L = 32-Pin Rectangular Ceramic Leadiess Chip Caner (CLVO32) B. SPEED OPTION ‘See Product Selector Guide ‘A. DEVICE NUMBER/DESCRIPTION ‘Am27168 = 2K x8 EPROM ‘Am27328 = 4K x8 EPROM Valid Combinations 75% Voc Tolerance Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations, to check on newly released valid combinations, and to obtain additional data on AMD's standard military grade products. [_Awa7iep-455_ | 0c, o1, teu ‘AM27928-205 [_amers26-455__ | Dc, Di, [awarsee-r00 | 4G De, DI, DE, BOLL LE [_Awa7s26-450 |
ORDERING INFORMATION
‘AMD products for Aerospace and Defense applications are available in several packages and operating ranges. APL (Approved Products List) products are fully compliant with MIL-STD-883C requirements. CPL (Controlled Products List) products are processed in accordance with MIL-STD-883C, but are inherently non-compliant because of package, solderability, or ‘surface treatment exceptions to those specifications. ‘The order number (Valid Combination) for APL products is formed by a combination of: A. Device Number B, Speed Option (if applicable) C. Device Class D. Package Type E. Lead Finish L_. ‘LEAD FINISH oe PACKAGE TYPE J = 24-Pin Ceramic DIP (COVO24) C, DEVICE CLASS rary a. svez0 opr bet es Baie ees Be eS (A. DEVICE NUMBER/DESCRIPTION peer ‘Am2732B = 4K x8 EPROM Vat Combinations +10% Voc Tolerance Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid [cawertes-250 | combinations or to check for newly released valid combinations. sun [averonsas6 | os
FUNCTIONAL DESCRIPTION To activate this mode, the programming equipment must force 12.0 V 0.5 V on address line Ag. Two identifier bytes Erasing the EPROMs. may then be sequenced from the device outputs by , address line Ag from Vi. to Vix. All other address In order to clear all locations of their programmed contents, toggling itis necessary to expose the EPROMs to ap ultraviolet ight lines must be held at Vi. during Auto Select mode. source. A dosage of 15 W seconds/cm? is required to Byte 0 (Ag = Vi, DQq~- 007) represents the manufacturer completely erase an EPROM. This dosage can be obtained code, and byte 1 (Ag = Viv, DQ - DQ), the device identi- by exposure to an ultraviolet lamp — wavelength of 2537 fier code. These identifier bytes are given in Table 2. All Angstroms (A) —with intensity of 12,000 uW/cm® for identifiers for manufacturer and device codes will possess fifteen to twenty minutes. The EPROM should be about ‘odd parity, with the most significant bit (MSB), OQ, defined directly under and about one inch from the source and all as the parity bit. filters should be removed from the ultraviolet light source Read Mode Prior to erasure, A ‘AMD EPROMS have two control functions, both of which nt t to t the EPR i ht coemtaingwartenn tore mer sk anaes tt be ugeay ised tae San na ee grasure tines wit be much longer than with ultraviolet Satoute, Crip Enabe oes, the, Power contro Fred 537 K, neverthol exposur 1ores- selection. cant Ugh and sunignt a eventually execs the EPROM ‘output control and should be used to gate data to the and exposure to them should be prevented to realize crores aepenaent or device os tine weave that ability. h nt, }ocess Tasesaac aonaen jumamnchen meena, peaerfomte ane a han ae a or substance. outputs tog after the falling edge of OF, assuming that CE has been LOW and addresses have been stable for at least Programming the EPROMs tacc- toe: Upon delivery, or after each erasure, the EPROM has all Standby Mode bits in the "1", or HIGH state. Zeros ("0s") are loaded into ° AMD EPROMSs have a standby mode which reduces the the EPROM through the procedure of programming, active power dissipation up to 80%. The EPROM is placed The programming mode is entered when a voltage greater in the standby mode by applying a TTL HIGH signal to the than 12.0, but less than 13.3 V is appiied to the Vpp pin TE input. When in standby mode, the outputs are in a high- (OE/Vpp for 32k) and TE/PGM is given a TTL-LOW pulse. impedance state, independent of the OE input. 8 lol he ia to be owanmed is applied 8 bits in parallel to Output OR-Tieing i To accomodate multiple memory connections, a two-line The flowchart (Figure 1) in the Programming section ofthis control function is provided to allow for: 1) low-memory document shows the AMD-preferred interactive program- dissipation. tod 2) nee tat otoubiee ming algorithm. Interactive algorithms requires less pro- Canton Wil pot eon? 2) assurance that output-bus con- ‘gramming time than most other algorithms. This does not will not occur. Preciude the use of other algorithms, including the conven- It is recommended that TE be decoded and used as the tional 50-ms pulse, as long as the maximum specifications primary device-selecting function, while OE be made a are not violated. ‘common connection to all devices in the array, and , connected to the Read line from the system control bus, 1h, AMO-pretered algorithm reduces programming time This assures that all deselected memory devices are in by using short (1 ms) program pulses and giving each the P low-power standby mode and that the output pins are address only as many pulses as is necessary in order to only active when data f desired from a pertonler ner reliably program the data. After each pulse is applied to a doves oy given address, data in that address is verified. if the data - does not verify, an additional pulse is applied for a Program Inhibit maximum of 15 pulses. This process is repeated while Sequencing through each address of the EPROM. ‘The Programming of multiple EPROMs in parallel with different interactive section of the algorithm is data is also easily accomplished. Except tor CE/PGM, all programmed and verified at Veg = 6.0 V, t5%, like inputs (including OE and Vpp) of the parallel EPROMs . may be common. For the Am2716B, a LOW-level CE/PGM The overprogram section of the algorithm programs the input inhibits the other EPROMs from being programmed. ‘entire array by cycling through each address and applying For the Am2732B, a HIGH-level CE/PGM input inhibits the an additional 2-ms program pulse. This section is done at other EPROMs from being programmed. Voc = 5.0 V, +5%. Program Verity Atter the final address is completed, the entire EPROM is ¢ . , a. A verity should be performed on the programmed bits to Yerifed to the datasheet specications of Voc = 5.0 V, determine that they were correct pleanmen, Data for all the EPROMs should be verified tog after the Auto Select Mode falling edge of OE, Vp may remain at 12.5 V for the 2716B, The Auto Select mode allows the reading out of a binary during program verify, but for the 27328, OE/Vpp must be a code from an EPROM that will identify its manufacturer and TTL low level. type. This mode is intended for use by programming ‘equipment for the purpose of automatically matching the System Applications device to be programmed with its corresponding program- During the switch between active and standby conditions, ming algorithm. This mode is functional in the 25°C +5°C transient current peaks are produced on the rising and ambient-temperature range required when programming falling edges of Chip Enable, The magnitude of these the EPROMs. transient current peaks is dependent on the output capaci-
transient effects. In addition, to ‘overcome the voltage drop where the power supply is connected to the array. TABLE 1. Am2716B MODE SELECT
ABSOLUTE MAXIMUM RATINGS OPERATING RANGES ‘Ambient Temperature with Power Applied .-65 to +135°C Temperature (To) .eesesssseesesseeesnseeeserssO 10 +70°C ‘Supply Voltage Supply Voltage (VOC) ...-.--esssessesesrseeees (Notes 1 & 2) with respect to Ground i ON AQ cessesssseeresnsteesssseestensereees + 13.50 10 =0.6 V SeerehUTe (Tw eereeeeeeenenrerne ed 1 + 85°C Stresses above those listed under ABSOLUTE MAXIMUM — Extended ware to © Devees 55 to +125°C RATINGS may cause permanont covice falure. Fenctoralty Forgets 1 nnn a0 well oes nite en nee ction ceesesceeenseeerensees (NOUS maximum ratings for extended periods may affect device Military (M) Devices Notes: 1. For -105, -155, ~205, blank, ~305, and -455 versions, Voc = +4.75 to +5.25 V. versions, Voc = +4.50 to +5.50 V. Operating ranges define those limits between which the functionality of the device is guaranteed, DC CHARACTERISTICS over operating range unless otherwise specified (Notes 1, 2, & 4)* Parameter Description Test Conditions [vor [ena ran votage [rower ee PP [Vou | onsur vow votuge dP toueatma i oes Tou LOW ae ee ee [sew tone rt ig 8 00 ae] [to ontattatage onrent | Vout =0 =] F009 Ja] oes Voc Standby Current OE=Vit tor Am2732B Vec Active Current for Am2716B DE = CE = Vi, and Am27328 Vpp Program Current - GLE, [| (Note 5) Vrp= 55 V &'M Devices [me [wemann [messy [See | De f= | Notes: See notes following the Capacitance table on next page. “See the last page of this spec for Group A Subgroup Testing information.
CAPACITANCE (Notes 2 & 3) Parameter Description ‘Test Conditions ‘Typ. [cen wea Caractere pew [ceour [oun capsctancs——itvorwov 8 ee G OE/Vpp Ne Input Capacitance cEroM Vin- OV Cina Input Capacitance Notes: 1. Voc must be applied simultaneously or before Vp, and removed simultaneously or after Voc. 2. Typical values are for nominal supply voltages. 3. This parameter is only sampled and not 100% tested. 4. Caution: The EPROMs must not be removed from or inserted into a socket or board when Vpp or Vcc is applied. 5. Vpp may be connected to Voc directly except during programming. The supply would then be the sum of loc and Ip. 6. Igc1 Max. is 40 mA for -4XX devices. KEY TO SWITCHING WAVEFORMS SWITCHING TEST CIRCUITS wevrom —iwuTsUTRUTS son est mugs cnoen KI Sa Y ORNS Seneine & Sern YZ > oAST THR se Re Sige Te003101 ane “Srestare S000010 SWITCHING TEST WAVEFORMS aay zav Zev >» resromns € oy ony aay wer oureur ‘WF00@500 'AC Testing: Inputs are driven at 2.4 V for a logic "1" and 0.4 V for a logic "0". Input pulse rise and fall times are 5 ns.
SWITCHING CHARACTERISTICS over operating range unless otherwise specified (Notes 1 & 3) (Table 1 of 2) . ‘Address to Output -OE- [+ [vce [esgre owe feevee-w | [we] [wo] [ae | | Chip Enable to Output Delay Output Enable to tor Output Enable HIGH (Note 2) | to Output Float Output Hold from Addresses, CE, or OE, whichever occured first (Table 2 of 2) Parameter Parameter Test Address to Output -OE- [+ [veo [Sermo fervor [fa [ [oe [|= | a Chip Enable to ia Output Delay Output Enable to Output Delay ‘Output Enable HIGH ‘to Output Float ‘Output Hold from Addresses, CE, or DE, whichever occured first Notes: 1. Voc must be applied simultaneously or before Vpp, and removed simultaneously or after Vpp- 2. This parameter is only sampled and not 100% tested. 3. Caution: The EPROMs must not be removed from or inserted into a socket or board when Vp or Voc is applied. 4, Output Load: 1 TTL gate and C, = 100 pF, Input Rise and Fall Times: <20 ns, Input Pulse Levels: 0.45 to 2.4 V, Timing Measurement Reference Level— Inputs: 1 V and 2 V Outputs: 0.8 V and 2 V. *See the last page of this spec for Group A Subgroup Testing information,
2 ———— ) 20 2 ( ADORESSES. soonesses os os ~— | | —— | ‘e—— EEN) | | a | Sito) Fasten __ \\ outrur wrozt98t Notes: 1. OE may be delayed up to tacc- tog after the falling edge of OE without impact on tacc. 2. tog is specified from OE or CE, whichever occurs first. 610
Switching Programming Characteristics. Figure 1. interactive Programming Flow Chart
TABLE 4. IDENTIFIER BYTES
- All other Address Lines = CE = OE = Vit
‘Notes: See notes following the Interactive Programming Algorithm Switching Programming Characteristics table.
Description
a Ca | [capes Sep ting TY 2 [cas ata Soup Time [aan trae Hl Teme [os me os tine [oso tor one Eaia to Oconto Oowy —T s a a [ce oNes ec Soup ting CT es [oa Tew PM int Program Pose wim Ts 80s ms [ore] Freee ro wen lef 9 fs fe [ces CE Sty time eT [is | a A PO 2. Voc must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. 3. When programming the EPROMS, a 0.1-uF capacitor is required across Vp and ground to Suppress spurious voltage transients which may damage the device. 4. Programming characteristics are guidelines which must be followed. They are not 100% tested to worst-case limits, 612
INTERACTIVE PROGRAMMING ALGORITHM WAVEFORMS AM2716B (Notes 1 and 3) ‘ progam agama vommy KO = | it? | 38: » Fe a eek vert Pt] WF000583 m2732B (Notes 1 and 2) ve rooms : engonats __y TD “ae i we ‘oe tow ‘ow ‘oF | ——y | ive | | Me i ail ("7 ‘we we Yee vee Wroo1a91 Notes: 1. The input timing reference level is 0.8 V for Vi. and 2 V for Vin. 2. tog and tpr are characteristics of the device, but must be accommodated by the programmer. 3. tog and tpFp are characteristics of the device, but must be accommodated by the programmer. 619
Symbol | Subgroups* [va | | vm | | os re re [eck [323] a ce a [cor | | [ee | [ere | *For DC Programming Characteristics, only Subgroup 1 applies. SWITCHING CHARACTERISTICS Parameter ‘Symbol Subgroups a [oer MILITARY BURN-IN Military burn-in is in accordance with the current revision of MiL-STD-883, Test Method 1015, Conditions A through E. Test conditions are selected at AMD's option. 6-14