Microcontroller

AM2434BSEFHIALXR

Texas Instruments

AM243x Sitara™ Microcontrollers REVISED JUNE 2026

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AM243x Sitara™ Microcontrollers

1 Features

Processor cores:

Up to 2× Dual-core Arm Cortex®-R5F MCU subsystems operating at up to 800MHz, highly- integrated for real-time processing – Dual-core Arm Cortex®-R5F clusters support dual-core and single-core operation – 32KB I-cache and 32KB D-cache per R5F core with SECDED ECC on all memories – Single-core: 128KB TCM per cluster (128KB TCM per R5F core) – Dual-core: 128KB TCM per cluster (64KB TCM per R5F core)
1× Single-core Arm Cortex®-M4F MCU at up to 400MHz – 256KB SRAM with SECDED ECC Memory subsystem:
Up to 2MB of On-chip RAM (OCSRAM) with SECDED ECC: – Can be divided into smaller banks in increments of 256KB for as many as 8 separate memory banks – Each memory bank can be allocated to a single core to facilitate software task partitioning
DDR Subsystem (DDRSS) – Supports LPDDR4, DDR4 memory types – 16-bit data bus with inline ECC – Supports speeds up to 1600 MT/s System on Chip (SoC) services:
Device Management Security Controller (DMSC-L) – Centralized SoC system controller – Manages system services including initial boot, security, and clock/reset/power management – Communication with various processing units over message manager – Simplified interface for optimizing unused peripherals – On-Chip Debug functionality through JTAG and Trace interfaces)
Data Movement Subsystem (DMSS) – Block Copy DMA (BCDMA) – Packet DMA (PKTDMA) – Secure Proxy (SEC_PROXY) – Ring Accelerator (RINGACC)
Time Sync Subsystem – Central Platform Time Sync (CPTS) module – Timer Manager (TIMERMANAGER) with 1024 timers – Time Sync and Compare event interrupt routers Industrial subsystem:
2× Gigabit Industrial Communication Subsystems (PRU_ICSSG) – Optional support for Profinet IRT, Profinet RT, EtherNet/IP, EtherCAT, Time-Sensitive Networking (TSN), and other Networking Protocols – Backwards compatibility with 10/100Mb PRU- ICSS – Each PRU_ICSSG contains:
3× PRU RISC Cores per Slice (2× Slice per PRU_ICSSG) – PRU General Use core (PRU) – PRU Real-Time Unit core (PRU-RTU) – PRU Transmit core (PRU-TX)
Each PRU core supports the following features: – Instruction RAM with ECC – Broadside RAM – Multiplier with optional accumulator (MAC) – CRC16/32 hardware accelerator – Byte swap for Big/Little Endian conversion – SUM32 hardware accelerator for UDP checksum – Task Manager for preemption support
Up to 2× Ethernet ports – RGMII (10/100/1000) – MII (10/100)
Three Data RAMs with ECC
8 banks of 30 × 32-bit register scratchpad memory
Interrupt controller and task manager
2× 64-bit Industrial Ethernet Peripherals (IEPs) for time stamping and other time synchronization functions
18× Sigma-Delta Filter Module (SDFM) interfaces – Short circuit logic – Over-current logic
6× Multi-protocol position encoder interfaces
1× Enhanced Capture Module (ECAP)
16550-compatible UART – Dedicated 192MHz clock to support 12Mbps PROFIBUS Security:
Secure boot supported – Hardware-enforced Root-of-Trust (RoT) – Support to switch RoT via backup key AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

– Support for takeover protection, IP protection, and anti-roll back protection

Security co-processor (DMSC-L) for key and security management, with dedicated device level interconnect for security – Secure watchdog/timer/IPC – Extensive firewall support for isolation
Cryptographic acceleration supported – Session-aware cryptographic engine with ability to auto-switch key-material based on incoming data stream
Supports cryptographic cores – AES – 128-/192-/256-Bit key sizes – SHA2 – 224-/256-/384-/512-Bit key sizes – DRBG with true random number generator – PKA (Public Key Accelerator) to Assist in RSA/ECC processing for secure boot
Debugging security – Secure software controlled debug access – Security aware debugging General connectivity peripherals:
6× Inter-Integrated Circuit (I2C) ports
9× Universal Asynchronous Receive/Transmit (UART) modules
1× 12-bit Analog-to-Digital Converters (ADC) – Configurable sample rate up to 4MSPS – 8× multiplexed analog inputs
7× Multichannel Serial Peripheral Interfaces (SPI) controllers
3× General-Purpose I/O (GPIO) modules Industrial and control interfaces:
9× Enhanced Pulse-Width Modulator (EPWM) modules
3× Enhanced Capture (ECAP) modules
3× Enhanced Quadrature Encoder Pulse (EQEP) modules
2× Modular Controller Area Network (MCAN) modules with full CAN-FD support
2× Fast Serial Interface Transmitter (FSITX) cores
6× Fast Serial Interface Receiver (FSIRX) cores High-speed interfaces:
1× Integrated Ethernet switch supporting: (CPSW) – Up to 2 external Ethernet ports
RGMII (10/100/1000)
RMII (10/100) – IEEE 1588 (2008 Annex D, Annex E, Annex F) with 802.1AS PTP – Clause 45 MDIO PHY management – Energy efficient Ethernet (802.3az)
1× PCI-Express® Gen2 controller (PCIE) – Supports Gen2 Single Lane operation
1× USB 3.1 Dual-Role Device (DRD) Subsystem (USBSS) – Port configurable as USB Host, USB Device, or USB Dual-Role device – USB Device: High-speed (480Mbps) and Full- speed (12Mbps) – USB Host: SuperSpeed Gen1 (5Gbps), High- speed (480Mbps), Full-speed (12Mbps), and Low-speed (1.5Mbps) – Integrated USB VBUS detection
1× Serializer/Deserializer (SERDES) – One SERDES PHY lane to support either PCI-Express® Gen2 or USB SuperSpeed Gen1 Media and data storage:
2× Multimedia Card/Secure Digital (MMCSD) interfaces – One 8-bit for eMMC (MMCSD0) – One 4-bit for MMCSD/SDIO (MMCSD1) – Integrated analog switch for voltage switching from 3.3V to 1.8V for high-speed cards
1× General-Purpose Memory Controller (GPMC) – 16-bit parallel bus with 133MHz clock or – 32-bit parallel bus with 100MHz clock – Error Location Module (ELM) support
1× Flash Subsystem (FSS) for external memory configurable as either: – 1× Octal SPI (OSPI) flash interface – or 1× Quad SPI (QSPI) flash interface Power management:
Simplified power sequencing requirements
Dual-voltage I/O Support (3.3V / 1.8V)
Integrated SDIO LDO for handling automatic voltage transition for SD interface
Integrated voltage supervisor for monitoring over- voltage and under-voltage conditions
Integrated power supply glitch detector for detecting fast supply transients AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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Functional safety:

Functional Safety-Compliant – Developed for functional safety applications – Documentation available to aid IEC 61508 functional safety system design – Systematic capability up to SIL 3 – Hardware integrity up to SIL 2 – Safety-related certification
IEC 61508 certification by TUV SUD – ECC or parity on calculation-critical memories – Built-In Self-Test (BIST) for CPU and on-chip RAM – Error Signaling Module (ESM) with dedicated error pin – ECC and parity on select internal bus interconnects – Run-time safety diagnostics, including:
Voltage, Temperature, and Clock Monitoring
Windowed Watchdog Timers
CRC Engine for memory integrity checks – MCU domain with dedicated memory, interfaces, and M4FSS capable of isolation from the larger SoC with Freedom From Interference (FFI) features:
Separate interconnect
Firewalls and timeout gaskets
Controlled reset isolation
Dedicated MCU PLL and MMR control
Separate I/O voltage supply rail SoC architecture:
Supports boot from OSPI/QSPI Flash, SPI Flash, parallel NOR Flash, parallel NAND Flash, UART, I2C, MMCSD, eMMC, USB, PCIe, and Ethernet interfaces.
16-nm FinFET technology Package options:
ALV: 17.2mm × 17.2mm, 0.8mm pitch (441-pin) [Lidded] Flip-Chip Ball Grid Array (FCBGA)
ANI: 17.2mm × 17.2mm, 0.8mm pitch (441-pin) [Lidded] Flip-Chip Ball Grid Array (FCBGA)
ALX: 11.0mm × 11.0mm, 0.5mm pitch (293-pin) [Overmolded] Flip-Chip Chip Scale Package (FCCSP)

2 Applications

Programmable Logic Controller (PLC)
Motor drives
Remote I/O
Factory automation robots
Industrial & collaborative robots
Condition-monitoring gateway
Communication module
Field transmitter
Test & measurement
Industrial mobile robots
Home automation robots
General-purpose controller www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: AM2434 AM2432 AM2431

3 Description

AM243x is an extension of Sitara’s industrial-grade portfolio into high-performance microcontrollers. The AM243x device is built for industrial applications, such as motor drives and remote I/O modules, which require a combination of real-time communications and processing. The AM243x family provides scalable performance with up to four Cortex-R5F MCUs, one Cortex-M4F, and two instances of Sitara’s gigabit TSN-enabled PRU_ICSSG. The AM243x SoC architecture was designed to provide best-in-class real-time performance through the high- performance Arm Cortex-R5F cores, Tightly-Coupled Memory (TCM) banks, configurable SRAM partitioning, and dedicated low-latency paths to and from peripherals for rapid data movement in and out of the SoC. This deterministic architecture allows for AM243x to handle the tight control loops found in servo drives while the peripherals like FSI, GPMC, ECAPs, PWMs, and encoder interfaces help enable a number of different architectures found in these systems. The SoC provides flexible industrial communications capability including full protocol stacks for EtherCAT target, PROFINET device, EtherNet/IP adapter, and IO-Link Controller. The PRU_ICSSG further provides capability for gigabit and TSN based protocols. In addition, the PRU_ICSSG enables additional interfaces including a UART interface, sigma delta decimation filters, and absolute encoder interfaces. Functional safety features can be enabled through the integrated Cortex-M4F along with dedicated peripherals which can all be isolated from the rest of the SoC. AM243x also supports secure boot.

Package Information

PART NUMBER PACKAGE(1) PACKAGE SIZE(2) AM2434 ALV/ANI (FCBGA, 441) 17.2mm × 17.2mm ALX (FCCSP, 293) 11.0mm × 11.0mm AM2432 ALV/ANI (FCBGA, 441) 17.2mm × 17.2mm ALX (FCCSP, 293) 11.0mm × 11.0mm AM2431 ALV (FCBGA, 441) 17.2mm × 17.2mm ALX (FCCSP, 293) 11.0mm × 11.0mm (1) For more information, see Mechanical, Packaging, and Orderable Information. (2) The package size (length × width) is a nominal value and includes pins, where applicable. AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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3.1 Functional Block Diagram

Figure 3-1 is the functional block diagram for the device. Note Refer to the AM243x SW Build Sheet to understand which device features are currently supported by TI Software Development Kits (SDKs). Industrial Connectivity System Memory Security A 243xM AM243x_FBD

2 MB SRAM with ECC DDR4/LPDDR4 with inline ECC 2x MMCSD

12x GP Timers 4x WWDT Sync Manager 3x EQEP 3x ECAP 9x EPWM 4x I2C GPIO 5x MCSPI 1x ADC 7x UART PCIe 1x Single lane Gen 2 GPMC / ELM 2x FSITX 6x FSIRX OSPI or QSPI 2x CAN-FD 1x USB 3.1 DRD 3-port Gb Ethernet General Connectivity 2x I2C GPIO 2x MCSPI 2x UART Isolated Connectivity (A) (for use with Cortex-M4F) 128KB TCM Arm Cortex -R5F 128KB TCM Arm Cortex -R5F Arm Cortex -R5F Arm Cortex -R5F Arm Cortex -M4F 256KB SRAM Real-time cores Isolated core (A) (C) (B) (C) PRU-ICSSG 2x RGMII/MII 18x

24 PWMs

40 Real-Time GPIOs

A. Isolation of peripherals and M4F core is an optional feature. MCU domain resources are shared across the SoC when in non-isolated configuration. B. One port is connected internally and not routed to any external pins. C. USB3.1 and PCIe share a common SERDES PHY lane. USB will be limited to non-SuperSpeed modes when using the SERDES PHY for PCIe. Figure 3-1. Functional Block Diagram www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: AM2434 AM2432 AM2431

6.8 VPP Specifications for One-Time Programmable

8.2 Peripheral- and Interface-Specific Design

11 Mechanical, Packaging, and Orderable

AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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4 Device Comparison

Table 4-1 shows a comparison between devices options, and highlights the key differences. Note Availability of features listed in this table are a function of shared IO pins, where IO signals associated with many of the features are multiplexed to a limited number of pins. The SysConfig-PinMux tool should be used to assign signal functions to pins. This will provide a better understanding of limitations associated with pin multiplexing. Note To understand what device features are currently supported by TI Software Development Kits (SDKs), see the AM243x SW Build Sheet. Note Features availability may vary by package within an orderable part number. Table 4-1. Device Comparison FEATURES(1) REFERENCE NAME AM2434 (ALV/ANI) AM2432 (ALV/ANI) AM2431 (ALV) AM2434 (ALX) AM2432 (ALX) AM2431 (ALX) MAIN_CTRL_MMR_CFG0_JTAG_USER_ID31:13 Register bit values by device "Features" code (See Nomenclature Description table for more information on device features) C: – 0x19023 0x19003 – 0x19023 0x19003 D: 0x19064 0x19024 0x19004 0x19064 0x19024 0x19004 E: 0x19065 0x19025 – 0x19065 0x19025 – F: 0x19066 0x19026 – 0x19066 0x19026 – PROCESSORS AND ACCELERATORS Speed Grades (See Table 6-1) S S S S S, K S,K Arm Cortex-R5F R5FSS 2 × Dual Core R5F0_0 R5F0_1 R5F1_0 R5F1_1 2 × Single Core R5F0_0 R5F1_0 1 × Single Core R5F0_0 2 × Dual Core R5F0_0 R5F0_1 R5F1_0 R5F1_1 2 × Single Core R5F0_0 R5F1_0 1 × Single Core R5F0_0 Arm Cortex-M4F M4FSS 1 × Single Core Functional Safety Optional(3) Device Management Security Controller DMSC-L Yes Crypto Accelerators Security Yes PROGRAM AND DATA STORAGE Shared On-Chip Memory (OCSRAM) in MAIN Domain OCSRAM 2MB 2MB R5F Tightly Coupled Memory (TCM)(4) TCM 4 × 64KB 2 × 128KB 1 × 128KB 4 × 64KB 2 × 128KB 1 × 128KB Shared On-Chip Memory (OCSRAM) in MCU Domain MCU_MSRAM 1 × 256KB DDR4/LPDDR4 DDR Subsystem DDRSS Up to 2GB (16-bit data) with inline ECC - General-Purpose Memory Controller GPMC Up to 128MB with ECC - PERIPHERALS Modular Controller Area Network Interface MCAN 2 Full CAN-FD Support(5) MCAN Optional General-Purpose I/O GPIO Up to 198 Up to 148 www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: AM2434 AM2432 AM2431

Table 4-1. Device Comparison (continued) FEATURES(1) REFERENCE NAME AM2434 (ALV/ANI) AM2432 (ALV/ANI) AM2431 (ALV) AM2434 (ALX) AM2432 (ALX) AM2431 (ALX) Inter-Integrated Circuit Interface I2C 6 (2 in MCU Domain) 3 (MAIN Domain Only) Analog-to-Digital Converter ADC 1 (12-bit resolution) 1 (10-bit resolution) Multichannel Serial Peripheral Interface MCSPI 7 (2 in MCU Domain) 4 (MAIN Domain Only) MultiMedia Card/ Secure Digital Interface MMCSD0 eMMC (8-bits) - MMCSD1 SD/SDIO (4-bits) SD/SDIO (4-bits) Fast Serial Interface FSI_TX 2 1 FSI_RX 6 4 Flash Subsystem (FSS) OSPI0 Yes(6) QSPI-Mode Only PCI Express Port with Integrated PHY PCIE Single Lane - Programmable Real-Time Unit Subsystem (7) (PRU Cores, eGPIO, UART, ECAP. EPWM) PRU_ICSSG 2 Industrial Communication Subsystem Support(8) (RGMII/MII and additional Networking Interfaces) PRU_ICSSG Optional Gigabit Ethernet Interface CPSW Yes (2 External Ports) General-Purpose Timers TIMER 16 (4 in MCU Domain) Enhanced Pulse-Width Modulation Module EPWM 9 7(9) Enhanced Capture Module ECAP 3 Enhanced Quadrature Encoder Pulse Module EQEP 3 Universal Asynchronous Receiver/ Transmitter UART 9 (2 in MCU Domain) 8 (1 in MCU Domain) Universal Serial Bus (USB3.1 Gen1) SuperSpeed Dual-Role-Device (DRD) Port with SS PHY USB Yes(10) No USB SuperSpeed Support (USB2 Only) (1) Features noted as “not supported” or "-", must not be used. Their functionality is not supported by TI for this family of devices. These features are subject to removal without notice on future device revisions. Any information regarding the unsupported features has been retained in the documentation solely for the purpose of clarifying signal names or for consistency with previous feature descriptions. (2) For more details about the MAIN_CTRL_MMR_CFG0_JTAG_USER_ID register and DEVICE_ID bit field, see the device's associated Technical Reference Manual. (3) Functional Safety is available when selecting an orderable part number that includes a feature code of F. Refer to Nomenclature Description table for the definition of feature codes. (4) The R5F cores share Tightly-Coupled Memory within a cluster and can be allocated per system requirements. (5) Full CAN-FD Support is available when selecting an orderable part number that includes a feature code of E or F. Refer to Nomenclature Description table for the definition of feature codes. (6) One flash interface configured as OSPI0 or QSPI0. (7) Programmable Real-Time Unit Subsystem support (Including Ethernet networking (MII/RGMII, MDIO), Sigma-Delta (SD) decimation, and three channel peripheral interface (EnDat 2.2 and BiSS)) is available when selecting an orderable part number that includes a feature code of C. Refer to Nomenclature Description table for the definition of feature codes. (8) Industrial Communication Subsystem feature support is available when selecting an orderable part number that includes a feature code of D, E, or F. Refer to Nomenclature Description table for the definition of feature codes. (9) Only the PWM_A output signal is available for the EHRPWM5 instance of the ALX package type. (10) Please refer to device Software Build sheet for details regarding USB driver support. AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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4.1 Related Products

Sitara™ Microcontrollers Our best-in-class Arm®-based 32-bit microcontrollers (MCUs) offer you a scalable portfolio of high-performance and power-efficient devices to help meet your system needs. Bring capabilities such as functional safety, power efficiency, real-time control, advanced networking, analytics and security to your designs. Sitara™ Processors Broad family of scalable processors based on Arm ® Cortex®-A cores with flexible accelerators, peripherals, connectivity and unified software support – perfect for sensors to servers. Sitara ™ processors have the features and reliability needed for use in industrial and automotive applications. Sitara™ Microcontroller - Applications Sitara™ microcontrollers provides a scalable portfolio for a wide range of applications from HMIs and gateways to more complex equipment such as drives and substation automation equipment. Sitara also offers multi-protocol support for industrial communication protocols such as EtherCAT®, Ethernet/IP, and Profinet. Sitara™ Microcontroller - Evaluation Modules TI provides Evaluation Modules (EVM) to help kick-start product development. See the AM243x Evaluation Module ( TMDSAM243) and AM243x LaunchPad ( LP- AM243x) tool folders for more information. Companion Products for AM243x Review products that are frequently purchased or used in conjunction with this product to complete your design. Additional products to complete your design:

Ethernet PHYs
Power supply solutions
Power management
Clocks and timing
Power switches
CAN transceivers
ESD Protection Please reference the AM243x EVM schematic for details of how these devices are implemented in a system design, and bill of materials for specific part number recommendations. www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: AM2434 AM2432 AM2431

5 Terminal Configuration and Functions

5.1 Pin Diagram

The terms "ball", "pin", and "terminal" are used interchangeably throughout the document. An attempt is made to use "ball" only when referring to the physical package. The diagrams in this section are used in conjunction with the other Terminal Configuration and Functions tables to locate signal names and ball grid numbers. The HTML version of this document provides additional information when hovering your cursor over a ball.

5.1.1 AM243x ALV/ANI Pin Diagram

Figure 5-1 shows the ball locations for the lidded 441-ball flip chip ball grid array (FCBGA) package. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 A B C D E F G H J K L M N P R T U V W Y AA Not to scale VSS DDR0_DQ1 DDR0_DQ0 DDR0_DQ3 VSS VSS MCU_SPI1 _CS0 MCU_UART0 _TXD MCU_UART0 _RXD MCU_I2C0 _SDA MCU_I2C1 _SCL TDO SPI0_D0 SPI0_D1 SPI1_D1 UART0 _RTSn MCAN0_TX I2C0_SCL EXT _REFCLK1 MCU _SAFETY _ERRORn VSS DDR0_DQS0 _n DDR0_DM0 DDR0_DQ4 DDR0_DQ7 DDR0_DQ2 MCU_SPI0 _D1 MCU_SPI1 _CS1 MCU_UART1 _CTSn MCU_UART1 _RTSn MCU_I2C1 _SDA TCK MCU _RESETz MCU_RESETS TATz SPI1_CS0 SPI1_D0 UART0 _CTSn MCAN0_RX I2C0_SDA I2C1_SDA MCU_OSC0 _XO MCU_PORz DDR0_DQS0 DDR0_DQ6 VSS DDR0_DQ5 DDR0_A1 MCU_SPI0 _CS1 MCU_SPI1 _D0 MCU_SPI1 _D1 MCU_UART1 _RXD VSS TDI TMS SPI0_CS1 SPI1_CLK VSS UART0_TXD MCAN1_TX I2C1_SCL EXTINTn MMC1_SDWP MCU_OSC0 _XI VSS DDR0_A0 DDR0_A4 DDR0_A3 DDR0 _RESET0_n MCU_SPI0 _CS0 MCU_SPI1 _CLK MCU_UART0 _CTSn MCU_UART1 _TXD EMU0 TRSTn SPI0_CS0 SPI0_CLK SPI1_CS1 UART0_RXD UART1 _CTSn MCAN1_RX ECAP0_IN _APWM_OUT MMC1_SDCD ADC0_AIN3 RSVD1 DDR0_CK0 _n DDR0_A2 DDR0_CS0 DDR0_CS1 _n DDR0_ODT0 MCU_SPI0 _CLK MCU_SPI0 _D0 MCU_UART0 _RTSn MCU_I2C0 _SCL EMU1 VSS VMON_1P8 _SOC VSS UART1_TXD UART1_RXD UART1 _RTSn PORz_OUT RESET _REQz USB0 _DRVVBUS ADC0_AIN7 ADC0_AIN2 DDR0_CK0 DDR0_A5 DDR0_CKE1 DDR0_CKE0 DDR0_ODT1 DDR0_RAS _n VDDS_DDR VSS VDDSHV _MCU VSS VDDSHV0 RSVD8 VMON_3P3 _MCU VMON_3P3 _SOC VSS RESETSTA Tz RSVD3 MMC0 _CALPAD ADC0_AIN6 ADC0_AIN1 ADC0_AIN5 VSS DDR0_BG0 VSS DDR0_BA0 DDR0_BA1 VDDS_DDR VSS VDDSHV _MCU VSS VDDSHV _MCU VDDA _TEMP0 VDDSHV0 RSVD2 VDDSHV0 VPP VSS MMC0_DAT7 MMC0_CLK MMC0_DS ADC0_AIN0 ADC0_AIN4 DDR0 _ALERT_n DDR0_ACT _n DDR0_BG1 DDR0_WE_n DDR0_CAL0 VSS VDDS_DDR VSS VDDA_PLL1 CAP_VDDS _MCU VSS CAP_VDDS0 VDDS_OSC VDD_DLL _MMC0 VDDA_3P3 _SDIO RSVD0 MMC0_DAT4 MMC0_DAT6 MMC0_DAT5 VSS VSS DDR0_A11 DDR0_A6 DDR0_A8 DDR0_A9 DDR0_CAS _n VDDS_DDR VSS VDDS_DDR _C VSS VDD_CORE VDDA_PLL2 VDD_CORE VDDA_ADC VSS ADC0_REFP ADC0_REFN MMC0_DAT3 MMC0_DAT2 MMC1_CMD MMC0_DAT1 MMC0_CMD RSVD7 RSVD6 DDR0_A10 DDR0_A13 DDR0_PAR VSS VDDS_DDR VSS VDD_CORE VMON_VSYS VDD_CORE VDDA_MCU VDD_MMC0 VDDS_MMC0 CAP _VDDSHV _MMC1 VMON_1P8 _MCU OSPI0 _CSn2 MMC1_DAT3 MMC1_DAT2 MMC0_DAT0 MMC1_DAT0 VSS DDR0_DQ10 VSS DDR0_DQ9 DDR0_A7 VDDS_DDR VSS VDD_CORE VSS VDDR_CORE VDDA _TEMP1 VDD_CORE CAP_VDDS5 VDDSHV5 VDDSHV5 VSS OSPI0 _CSn3 OSPI0 _CSn1 OSPI0 _CSn0 MMC1_CLK MMC1_DAT1 DDR0_DQS1 _n DDR0_DM1 DDR0_DQ11 DDR0_DQ14 DDR0_A12 VSS VDDSHV1 VSS VDD_CORE VSS VDD_CORE VSS VDDR_CORE VDDSHV4 VDDSHV4 CAP_VDDS4 OSPI0_D7 OSPI0_D1 OSPI0_D0 OSPI0_D2 OSPI0_D3 DDR0_DQS1 DDR0_DQ15 DDR0_DQ13 DDR0_DQ12 DDR0_DQ8 VDDSHV1 VSS VDD_CORE VSS VDD_CORE VSS VDDA_PLL0 VSS CAP_VDDS3 VSS GPMC0_WPn GPMC0_DIR OSPI0_D6 OSPI0_DQS OSPI0_CLK OSPI0 _LBCLKO VSS PRG0 _MDIO0 _MDIO PRG0 _MDIO0 _MDC PRG0_PRU1 _GPO5 PRG0_PRU1 _GPO18 VSS VDDSHV1 VSS VDD_CORE VSS VDDA_0P85 _SERDES0 VDDA_0P85 _SERDES0 VDDA_0P85 _SERDES0 VDDSHV3 VDDSHV3 GPMC0 _ADVn_ALE GPMC0 _BE0n_CLE VSS GPMC0 _CSn2 OSPI0_D5 OSPI0_D4 PRG0_PRU1 _GPO8 PRG0_PRU1 _GPO19 PRG0_PRU0 _GPO5 PRG0_PRU0 _GPO1 PRG0_PRU1 _GPO6 PRG0_PRU0 _GPO13 VSS VDDSHV2 VSS VDDSHV2 CAP_VDDS2 VSS VDDA_3P3 _USB0 VDDA_1P8 _SERDES0 VDDA_1P8 _USB0 GPMC0 _AD10 GPMC0_CLK GPMC0_OEn _REn GPMC0 _CSn0 GPMC0 _CSn1 GPMC0 _CSn3 PRG0_PRU0 _GPO7 PRG0_PRU0 _GPO8 PRG0_PRU0 _GPO6 PRG0_PRU1 _GPO3 PRG0_PRU0 _GPO15 PRG0_PRU1 _GPO13 CAP_VDDS1 VSS VDDSHV2 VSS VSS VDDA_0P85 _USB0 SERDES0 _REXT USB0_VBUS VSS VSS GPMC0_AD9 GPMC0_AD2 GPMC0 _BE1n GPMC0_AD0 GPMC0_WEn PRG0_PRU0 _GPO17 PRG0_PRU0 _GPO2 VSS PRG0_PRU0 _GPO16 PRG0_PRU1 _GPO15 PRG0_PRU1 _GPO14 PRG1_PRU0 _GPO17 PRG1_PRU0 _GPO1 PRG1_PRU0 _GPO12 PRG1_PRU1 _GPO13 PRG1_PRU1 _GPO6 PRG1_PRU1 _GPO8 PRG1_PRU0 _GPO7 PRG1_PRU0 _GPO10 PRG1_PRU0 _GPO9 USB0_ID USB0 _RCALIB GPMC0_AD4 GPMC0_AD5 GPMC0_AD3 GPMC0_AD1 PRG0_PRU0 _GPO18 PRG0_PRU0 _GPO3 PRG0_PRU1 _GPO2 PRG0_PRU0 _GPO14 PRG0_PRU1 _GPO17 PRG0_PRU1 _GPO10 PRG1_PRU0 _GPO18 PRG1_PRU0 _GPO3 PRG1_PRU0 _GPO16 PRG1_PRU1 _GPO12 PRG1_PRU1 _GPO1 PRG1_PRU1 _GPO19 PRG1_PRU0 _GPO5 PRG1_PRU1 _GPO9 PRG1_PRU1 _GPO7 RSVD5 VSS GPMC0 _AD13 GPMC0_AD8 GPMC0_AD6 GPMC0_AD7 PRG0_PRU0 _GPO19 PRG0_PRU1 _GPO1 PRG0_PRU1 _GPO4 PRG0_PRU1 _GPO11 PRG0_PRU1 _GPO7 PRG0_PRU0 _GPO9 PRG1_PRU0 _GPO19 PRG1_PRU0 _GPO2 PRG1_PRU0 _GPO13 VSS PRG1_PRU1 _GPO0 PRG1_PRU1 _GPO4 PRG1_PRU0 _GPO8 PRG1_PRU1 _GPO10 RSVD4 SERDES0 _REFCLK0N SERDES0 _REFCLK0P VSS GPMC0 _WAIT0 GPMC0 _AD11 GPMC0 _AD12 PRG0_PRU0 _GPO0 PRG0_PRU1 _GPO0 PRG0_PRU0 _GPO11 PRG0_PRU1 _GPO12 PRG0_PRU1 _GPO9 PRG1 _MDIO0 _MDC PRG1_PRU0 _GPO0 PRG1_PRU0 _GPO4 PRG1_PRU0 _GPO15 PRG1_PRU1 _GPO16 PRG1_PRU1 _GPO15 PRG1_PRU1 _GPO3 PRG1_PRU1 _GPO18 VSS SERDES0 _RX0_N SERDES0 _RX0_P VSS GPMC0 _WAIT1 VSS GPMC0 _AD15 GPMC0 _AD14 VSS PRG0_PRU0 _GPO4 PRG0_PRU0 _GPO12 PRG0_PRU1 _GPO16 PRG0_PRU0 _GPO10 PRG1 _MDIO0 _MDIO PRG1_PRU0 _GPO6 PRG1_PRU0 _GPO11 PRG1_PRU0 _GPO14 PRG1_PRU1 _GPO11 PRG1_PRU1 _GPO14 PRG1_PRU1 _GPO2 PRG1_PRU1 _GPO5 PRG1_PRU1 _GPO17 VSS SERDES0 _TX0_N SERDES0 _TX0_P VSS USB0_DP USB0_DM VSS Figure 5-1. ALV/ANI FCBGA-N441 Pin Diagram (Top View) AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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5.1.2 AM243x ALX Pin Diagram

The Figure 5-2 shows the ball locations for the non-lidded 293-ball flip chip ball grid array (FCBGA) package. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 A B C D E F G H J K L M N P R T U V W Y AA Not to scale VSS VSS TDI MCU _RESETz MCU_RESETS TATz SPI0_D0 UART0 _RTSn UART1 _RTSn UART1_TXD MCAN0_RX MCAN1_RX I2C1_SCL EXT _REFCLK1 VSS VSS VSS MCU_UART0 _TXD EMU1 TMS TDO TRSTn SPI0_CS1 SPI0_CLK UART0 _CTSn UART0_RXD UART0_TXD UART1_RXD MCAN0_TX MCAN1_TX I2C0_SDA I2C0_SCL MMC1_SDCD I2C1_SDA USB0 _DRVVBUS MCU _SAFETY _ERRORn VSS MCU_UART0 _RTSn EMU0 TCK SPI0_D1 UART1 _CTSn VDDSHV0 MMC1_SDWP RESET _REQz MCU_PORz MCU_OSC0 _XO PRG0_PRU1 _GPO18 PRG0 _MDIO0 _MDC MCU_UART0 _CTSn MCU_UART0 _RXD CAP_VDDS _MCU VSS CAP_VDDS0 VDDSHV0 VSS VSS PORz_OUT MCU_OSC0 _XI PRG0_PRU0 _GPO17 PRG0_PRU0 _GPO7 PRG0_PRU1 _GPO5 PRG0 _MDIO0 _MDIO VSS VDDSHV _MCU VDDSHV _MCU VDDSHV _MCU VSS VSS VDDSHV0 VMON_3P3 _MCU,VMON _3P3_SOC VPP RESETSTA Tz ADC0_AIN7 ADC0_AIN5 PRG0_PRU0 _GPO5 PRG0_PRU1 _GPO19 PRG0_PRU1 _GPO8 PRG0_PRU1 _GPO6 VSS VDD_CORE VMON_1P8 _SOC VSS VDDS_OSC ADC0_AIN1 ADC0_AIN3 ADC0_AIN2 PRG0_PRU0 _GPO2 PRG0_PRU0 _GPO19 VDDR_CORE VDDR_CORE VDDA_PLL1 VDD_CORE VDDA _TEMP0 VDDA_PLL2 VMON_VSYS VSS VDDA_ADC ADC0_AIN6 PRG0_PRU0 _GPO3 PRG0_PRU0 _GPO6 PRG0_PRU0 _GPO8 VSS VSS VDD_CORE RSVD0 VDDA_MCU VDD_CORE VSS VDDA_ADC ADC0_AIN4 ADC0_AIN0 PRG0_PRU1 _GPO1 PRG0_PRU0 _GPO0 PRG0_PRU0 _GPO1 VSS VSS VDD_CORE VDDR_CORE VSS VDDR_CORE RSVD1 VSS CAP _VDDSHV _MMC1 MMC1_DAT0 MMC1_DAT1 MMC1_CLK MMC1_CMD PRG0_PRU0 _GPO12 PRG0_PRU0 _GPO4 PRG0_PRU0 _GPO18 VSS VSS VSS VDD_CORE VDD_CORE VDDA_3P3 _SDIO VSS MMC1_DAT3 MMC1_DAT2 PRG0_PRU0 _GPO11 PRG0_PRU1 _GPO3 PRG0_PRU1 _GPO4 PRG0_PRU1 _GPO0 VDDSHV1 VDD_CORE VSS VSS VSS VDD_CORE VDDSHV5 VDDSHV5 OSPI0_D0 OSPI0 _CSn0 OSPI0_D2 PRG0_PRU1 _GPO2 PRG0_PRU1 _GPO15 VDDSHV1 VSS VDD_CORE VDDA _TEMP1 VDD_CORE VSS VSS CAP_VDDS5 OSPI0 _CSn1 OSPI0 _LBCLKO PRG0_PRU0 _GPO13 PRG0_PRU0 _GPO14 PRG0_PRU0 _GPO16 PRG0_PRU0 _GPO15 CAP_VDDS1 VSS VDD_CORE VDD_CORE VSS VDDA_PLL0 VSS VDDSHV4 VDDSHV4 CAP_VDDS4 OSPI0_D3 OSPI0_D1 PRG0_PRU1 _GPO11 PRG0_PRU1 _GPO12 VDDSHV1 VDDSHV1 VSS VDDR_CORE VSS VDDR_CORE VSS VSS OSPI0_DQS OSPI0_CLK GPMC0 _BE1n PRG0_PRU1 _GPO9 PRG0_PRU1 _GPO14 VSS VDD_CORE VDDR_CORE VSS VDD_CORE VDD_CORE CAP_VDDS3 VDDSHV3 GPMC0_AD1 GPMC0_AD0 PRG0_PRU1 _GPO17 PRG1_PRU0 _GPO17 PRG0_PRU1 _GPO16 PRG0_PRU1 _GPO13 PRG0_PRU1 _GPO7 VDDSHV2 VDDSHV2 VSS VDDSHV3 GPMC0_AD6 GPMC0_AD2 GPMC0_AD5 PRG0_PRU0 _GPO10 PRG0_PRU1 _GPO10 PRG1_PRU0 _GPO19 VSS VDDSHV2 VDDSHV2 CAP_VDDS2 VDDSHV2 PRG1_PRU1 _GPO10 PRG1_PRU0 _GPO5 VDDA_1P8 _USB0 VDDA_3P3 _USB0 GPMC0_AD8 GPMC0_AD7 GPMC0_AD9 GPMC0_AD4 PRG1 _MDIO0 _MDIO PRG1_PRU0 _GPO0 PRG1_PRU0 _GPO11 PRG1_PRU0 _GPO13 PRG1_PRU1 _GPO15 PRG1_PRU1 _GPO6 PRG1_PRU1 _GPO3 PRG1_PRU0 _GPO7 VDDA_0P85 _USB0 USB0_VBUS GPMC0 _AD10 GPMC0_AD3 PRG1 _MDIO0 _MDC PRG1_PRU0 _GPO12 PRG1_PRU0 _GPO1 PRG1_PRU0 _GPO16 PRG1_PRU1 _GPO14 PRG1_PRU1 _GPO8 PRG1_PRU0 _GPO10 PRG1_PRU0 _GPO9 USB0 _RCALIB GPMC0 _AD11 VSS PRG1_PRU0 _GPO6 PRG0_PRU0 _GPO9 PRG1_PRU0 _GPO18 PRG1_PRU0 _GPO3 PRG1_PRU1 _GPO11 PRG1_PRU0 _GPO15 PRG1_PRU1 _GPO16 PRG1_PRU1 _GPO13 PRG1_PRU1 _GPO1 PRG1_PRU1 _GPO2 PRG1_PRU1 _GPO4 PRG1_PRU0 _GPO8 PRG1_PRU1 _GPO7 PRG1_PRU1 _GPO18 PRG1_PRU1 _GPO9 USB0_ID GPMC0 _AD14 GPMC0 _AD13 GPMC0 _AD12 VSS VSS VSS PRG1_PRU0 _GPO2 PRG1_PRU0 _GPO4 PRG1_PRU0 _GPO14 PRG1_PRU1 _GPO12 PRG1_PRU1 _GPO0 PRG1_PRU1 _GPO5 PRG1_PRU1 _GPO19 PRG1_PRU1 _GPO17 USB0_DP USB0_DM GPMC0 _AD15 VSS VSS Figure 5-2. ALX FCBGA-N293 Pin Diagram (Top View) www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: AM2434 AM2432 AM2431

5.2 Pin Attributes

The following list describes the contents of each column in the Pin Attributes table: 1. BALL NUMBER: Ball numbers assigned to each terminal of the Ball Grid Array package. 2. BALL NAME: Ball name assigned to each terminal of the Ball Grid Array package (this name is typically taken from the primary MUXMODE 0 signal function). 3. SIGNAL NAME: Signal name(s) of all dedicated and pin multiplexed signal functions associated with a ball. Note Many device pins support multiple signal functions. Some signal functions are selected via a single layer of multiplexers associated with pins. Other signal functions are selected via two or more layers of multiplexers, where one layer is associated with the pins and other layers are associated with peripheral logic functions. The Pin Attributes table, defines the SoC pin multiplexed signal function implemented at the pin and does not define secondary multiplexing of signal functions implemented in device subsystems. Secondary multiplexing of signal functions are not described in this table. For more information on secondary multiplexed signal functions, see the respective peripheral chapter of the device TRM. 4. MUX MODE: The MUXMODE value associated with each pin multiplexed signal function: a. MUXMODE 0 is the primary pin multiplexed signal function. However, the primary pin multiplexed signal function is not necessarily the default pin multiplexed signal function. Note The value found in the MUX MODE AFTER RESET column defines the default pin multiplexed signal function selected when MCU_PORz is deasserted. b. MUXMODE values 1 through 15 are possible for pin multiplexed signal functions. However, not all MUXMODE values have been implemented. The only valid MUXMODE values are those defined as pin multiplexed signal functions within the Pin Attributes table. Only valid values of MUXMODE can be used. c. Bootstrap defines SOC configuration pins, where the logic state applied to each pin is latched on the rising edge of PORz_OUT. These input signal functions are fixed to their respective pins and are not programmable via MUXMODE. d. An empty box means Not Applicable. Note The following configurations of MUXMODE must be avoided for proper device operation.

Configuring multiple pins operating as inputs to the same pin multiplexed signal function is not supported as it can yield unexpected results.
Configuring a pin to an undefined pin multiplexing mode will cause the pin behavior to be undefined. AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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TYPE: Signal type and direction:

I = Input
O = Output
OD = Output, with open-drain output function
IO = Input, Output, or simultaneously Input and Output
IOD = Input, Output, or simultaneously Input and Output, with open-drain output function
IOZ = Input, Output, or simultaneously Input and Output, with three-state output function
OZ = Output with three-state output function
A = Analog
PWR = Power
GND = Ground
CAP = LDO Capacitor 6. DSIS: The deselected input state (DSIS) indicates the state driven to the subsystem input (logic "0", logic "1", or "pad" level) when the pin multiplexed signal function is not selected by MUXMODE.
0: Logic 0 driven to the subsystem input.
1: Logic 1 driven to the subsystem input.
pad: Logic state of the pad is driven to the subsystem input.
An empty box means Not Applicable. 7. BALL STATE DURING RESET RX/TX/PULL: State of the terminal while MCU_PORz is asserted, where RX defines the state of the input buffer, TX defines the state of the output buffer, and PULL defines the state of internal pull resistors:
RX (Input buffer) – Off: The input buffer is disabled. – On: The input buffer is enabled.
TX (Output buffer) – Off: The output buffer is disabled. – Low: The output buffer is enabled and drives VOL. – High: The output buffer is enabled and drives VOH.
PULL (Internal pull resistors) – Off: Internal pull resistors are turned off. – Up: Internal pull-up resistor is turned on. – Down: Internal pull-down resistor is turned on. – NA: Not Applicable.
An empty box means Not Applicable. 8. BALL STATE AFTER RESET RX/TX/PULL: State of the terminal after MCU_PORz is deasserted, where RX defines the state of the input buffer, TX defines the state of the output buffer, and PULL defines the state of internal pull resistors:
RX (Input buffer) – Off: The input buffer is disabled. – On: The input buffer is enabled.
TX (Output buffer) – Off: The output buffer is disabled. – SS: The subsystem selected with MUXMODE determines the output buffer state.
PULL (Internal pull resistors) – Off: Internal pull resistors are turned off. – Up: Internal pull-up resistor is turned on. – Down: Internal pull-down resistor is turned on. – NA: Not Applicable.
An empty box, NA, or "-" means Not Applicable. www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: AM2434 AM2432 AM2431

MUX MODE AFTER RESET: The value found in this column defines the default pin multiplexed signal function after MCU_PORz is deasserted. An empty box means Not Applicable. 10. I/O OPERATING VOLTAGE: This column describes I/O operating voltage options of the respective power supply, when applicable. An empty box means Not Applicable. For more information, see valid operating voltage range(s) defined for each power supply in Recommended Operating Conditions. 11. POWER: The power supply of the associated I/O, when applicable. An empty box means Not Applicable. 12. HYS: Indicates if the input buffer associated with this I/O has hysteresis:

Yes: With hysteresis
No: Without hysteresis
An empty box means Not Applicable. For more information, see the hysteresis values in Electrical Characteristics. 13. PULL UP/DOWN TYPE: Indicates the presence of an internal pull-up or pull-down resistor. Internal resistors can be enabled or disabled via software.
PU: Internal pull-up
PD: Internal pull-down
PU/PD: Internal pull-up and pull-down
An empty box means No internal pull. 14. BUFFER TYPE: This column defines the buffer type associated with a terminal. This information can be used to determine which Electrical Characteristics table is applicable. An empty box means Not Applicable. For electrical characteristics, refer to the appropriate buffer type table in Electrical Characteristics. 15. PADCONFIG Register: Name of the IO pad configuration register associated with Ball. 16. PADCONFIG Address: Physical address of the IO pad configuration register associated with Ball. AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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Table 5-1. Pin Attributes (ALV, ANI, ALX Packages) ALV ANI BALL NUMBER [1] ALX BALL NUMBER [1] BALL NAME [2] PADCONFIG Register [15] PADCONFIG Address [16] SIGNAL NAME [3] MUX MODE [4] TYPE [5] DSIS [6] BALL STATE DURING RESET RX/TX/PULL [7] BALL STATE AFTER RESET RX/TX/PULL [8] MUX MODE AFTER RESET [9] IO OPERATING VOLTAGE [10] POWER [11] HYS [12] BUFFER TYPE [14] Pull UP/DOWN TYPE [13] J16 ADC0_REFN ADC0_REFN A 1.8V VDDA_ADC0 ADC12B J15 ADC0_REFP ADC0_REFP A 1.8V VDDA_ADC0 ADC12B G20 H21 ADC0_AIN0 ADC0_AIN0 A 1.8V VDDA_ADC0 Yes ADC12B F20 F19 ADC0_AIN1 ADC0_AIN1 A 1.8V VDDA_ADC0 Yes ADC12B E21 F21 ADC0_AIN2 ADC0_AIN2 A 1.8V VDDA_ADC0 Yes ADC12B D20 F20 ADC0_AIN3 ADC0_AIN3 A 1.8V VDDA_ADC0 Yes ADC12B G21 H20 ADC0_AIN4 ADC0_AIN4 A 1.8V VDDA_ADC0 Yes ADC12B F21 E21 ADC0_AIN5 ADC0_AIN5 A 1.8V VDDA_ADC0 Yes ADC12B F19 G20 ADC0_AIN6 ADC0_AIN6 A 1.8V VDDA_ADC0 Yes ADC12B E20 E20 ADC0_AIN7 ADC0_AIN7 A 1.8V VDDA_ADC0 Yes ADC12B H12 D12 CAP_VDDS0 CAP_VDDS0 CAP T7 N5 CAP_VDDS1 CAP_VDDS1 CAP R11 U9 CAP_VDDS2 CAP_VDDS2 CAP N14 R16 CAP_VDDS3 CAP_VDDS3 CAP M16 N18 CAP_VDDS4 CAP_VDDS4 CAP L13 M18 CAP_VDDS5 CAP_VDDS5 CAP K15 J17 CAP_VDDSHV_MMC1 CAP_VDDSHV_MMC1 CAP H10 D9 CAP_VDDS_MCU CAP_VDDS_MCU CAP H2 DDR0_ACT_n DDR0_ACT_n O 1.1V / 1.2V VDDS_DDR, VDDS_DDR_C DDR H1 DDR0_ALERT_n DDR0_ALERT_n IO 1.1V / 1.2V VDDS_DDR, VDDS_DDR_C DDR J5 DDR0_CAS_n DDR0_CAS_n O 1.1V / 1.2V VDDS_DDR, VDDS_DDR_C DDR K5 DDR0_PAR DDR0_PAR O 1.1V / 1.2V VDDS_DDR, VDDS_DDR_C DDR F6 DDR0_RAS_n DDR0_RAS_n O 1.1V / 1.2V VDDS_DDR, VDDS_DDR_C DDR H4 DDR0_WE_n DDR0_WE_n O 1.1V / 1.2V VDDS_DDR, VDDS_DDR_C DDR D2 DDR0_A0 DDR0_A0 O 1.1V / 1.2V VDDS_DDR, VDDS_DDR_C DDR C5 DDR0_A1 DDR0_A1 O 1.1V / 1.2V VDDS_DDR, VDDS_DDR_C DDR E2 DDR0_A2 DDR0_A2 O 1.1V / 1.2V VDDS_DDR, VDDS_DDR_C DDR D4 DDR0_A3 DDR0_A3 O 1.1V / 1.2V VDDS_DDR, VDDS_DDR_C DDR D3 DDR0_A4 DDR0_A4 O 1.1V / 1.2V VDDS_DDR, VDDS_DDR_C DDR www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: AM2434 AM2432 AM2431

Table 5-1. Pin Attributes (ALV, ANI, ALX Packages) (continued) ALV ANI BALL NUMBER [1] ALX BALL NUMBER [1] BALL NAME [2] PADCONFIG Register [15] PADCONFIG Address [16] SIGNAL NAME [3] MUX MODE [4] TYPE [5] DSIS [6] BALL STATE DURING RESET RX/TX/PULL [7] BALL STATE AFTER RESET RX/TX/PULL [8] MUX MODE AFTER RESET [9] IO OPERATING VOLTAGE [10] POWER [11] HYS [12] BUFFER TYPE [14] Pull UP/DOWN TYPE [13] F2 DDR0_A5 DDR0_A5 O 1.1V / 1.2V VDDS_DDR, VDDS_DDR_C DDR J2 DDR0_A6 DDR0_A6 O 1.1V / 1.2V VDDS_DDR, VDDS_DDR_C DDR L5 DDR0_A7 DDR0_A7 O 1.1V / 1.2V VDDS_DDR, VDDS_DDR_C DDR J3 DDR0_A8 DDR0_A8 O 1.1V / 1.2V VDDS_DDR, VDDS_DDR_C DDR J4 DDR0_A9 DDR0_A9 O 1.1V / 1.2V VDDS_DDR, VDDS_DDR_C DDR K3 DDR0_A10 DDR0_A10 O 1.1V / 1.2V VDDS_DDR, VDDS_DDR_C DDR J1 DDR0_A11 DDR0_A11 O 1.1V / 1.2V VDDS_DDR, VDDS_DDR_C DDR M5 DDR0_A12 DDR0_A12 O 1.1V / 1.2V VDDS_DDR, VDDS_DDR_C DDR K4 DDR0_A13 DDR0_A13 O 1.1V / 1.2V VDDS_DDR, VDDS_DDR_C DDR G4 DDR0_BA0 DDR0_BA0 O 1.1V / 1.2V VDDS_DDR, VDDS_DDR_C DDR G5 DDR0_BA1 DDR0_BA1 O 1.1V / 1.2V VDDS_DDR, VDDS_DDR_C DDR G2 DDR0_BG0 DDR0_BG0 O 1.1V / 1.2V VDDS_DDR, VDDS_DDR_C DDR H3 DDR0_BG1 DDR0_BG1 O 1.1V / 1.2V VDDS_DDR, VDDS_DDR_C DDR H5 DDR0_CAL0 DDR0_CAL0 A 1.1V / 1.2V VDDS_DDR, VDDS_DDR_C DDR F1 DDR0_CK0 DDR0_CK0 O 1.1V / 1.2V VDDS_DDR, VDDS_DDR_C DDR E1 DDR0_CK0_n DDR0_CK0_n O 1.1V / 1.2V VDDS_DDR, VDDS_DDR_C DDR F4 DDR0_CKE0 DDR0_CKE0 O 1.1V / 1.2V VDDS_DDR, VDDS_DDR_C DDR F3 DDR0_CKE1 DDR0_CKE1 O 1.1V / 1.2V VDDS_DDR, VDDS_DDR_C DDR E3 DDR0_CS0_n DDR0_CS0_n O 1.1V / 1.2V VDDS_DDR, VDDS_DDR_C DDR E4 DDR0_CS1_n DDR0_CS1_n O 1.1V / 1.2V VDDS_DDR, VDDS_DDR_C DDR B2 DDR0_DM0 DDR0_DM0 IO 1.1V / 1.2V VDDS_DDR, VDDS_DDR_C DDR M2 DDR0_DM1 DDR0_DM1 IO 1.1V / 1.2V VDDS_DDR, VDDS_DDR_C DDR AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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Table 5-1. Pin Attributes (ALV, ANI, ALX Packages) (continued) ALV ANI BALL NUMBER [1] ALX BALL NUMBER [1] BALL NAME [2] PADCONFIG Register [15] PADCONFIG Address [16] SIGNAL NAME [3] MUX MODE [4] TYPE [5] DSIS [6] BALL STATE DURING RESET RX/TX/PULL [7] BALL STATE AFTER RESET RX/TX/PULL [8] MUX MODE AFTER RESET [9] IO OPERATING VOLTAGE [10] POWER [11] HYS [12] BUFFER TYPE [14] Pull UP/DOWN TYPE [13] A3 DDR0_DQ0 DDR0_DQ0 IO 1.1V / 1.2V VDDS_DDR, VDDS_DDR_C DDR A2 DDR0_DQ1 DDR0_DQ1 IO 1.1V / 1.2V VDDS_DDR, VDDS_DDR_C DDR B5 DDR0_DQ2 DDR0_DQ2 IO 1.1V / 1.2V VDDS_DDR, VDDS_DDR_C DDR A4 DDR0_DQ3 DDR0_DQ3 IO 1.1V / 1.2V VDDS_DDR, VDDS_DDR_C DDR B3 DDR0_DQ4 DDR0_DQ4 IO 1.1V / 1.2V VDDS_DDR, VDDS_DDR_C DDR C4 DDR0_DQ5 DDR0_DQ5 IO 1.1V / 1.2V VDDS_DDR, VDDS_DDR_C DDR C2 DDR0_DQ6 DDR0_DQ6 IO 1.1V / 1.2V VDDS_DDR, VDDS_DDR_C DDR B4 DDR0_DQ7 DDR0_DQ7 IO 1.1V / 1.2V VDDS_DDR, VDDS_DDR_C DDR N5 DDR0_DQ8 DDR0_DQ8 IO 1.1V / 1.2V VDDS_DDR, VDDS_DDR_C DDR L4 DDR0_DQ9 DDR0_DQ9 IO 1.1V / 1.2V VDDS_DDR, VDDS_DDR_C DDR L2 DDR0_DQ10 DDR0_DQ10 IO 1.1V / 1.2V VDDS_DDR, VDDS_DDR_C DDR M3 DDR0_DQ11 DDR0_DQ11 IO 1.1V / 1.2V VDDS_DDR, VDDS_DDR_C DDR N4 DDR0_DQ12 DDR0_DQ12 IO 1.1V / 1.2V VDDS_DDR, VDDS_DDR_C DDR N3 DDR0_DQ13 DDR0_DQ13 IO 1.1V / 1.2V VDDS_DDR, VDDS_DDR_C DDR M4 DDR0_DQ14 DDR0_DQ14 IO 1.1V / 1.2V VDDS_DDR, VDDS_DDR_C DDR N2 DDR0_DQ15 DDR0_DQ15 IO 1.1V / 1.2V VDDS_DDR, VDDS_DDR_C DDR C1 DDR0_DQS0 DDR0_DQS0 IO 1.1V / 1.2V VDDS_DDR, VDDS_DDR_C DDR B1 DDR0_DQS0_n DDR0_DQS0_n IO 1.1V / 1.2V VDDS_DDR, VDDS_DDR_C DDR N1 DDR0_DQS1 DDR0_DQS1 IO 1.1V / 1.2V VDDS_DDR, VDDS_DDR_C DDR M1 DDR0_DQS1_n DDR0_DQS1_n IO 1.1V / 1.2V VDDS_DDR, VDDS_DDR_C DDR E5 DDR0_ODT0 DDR0_ODT0 O 1.1V / 1.2V VDDS_DDR, VDDS_DDR_C DDR F5 DDR0_ODT1 DDR0_ODT1 O 1.1V / 1.2V VDDS_DDR, VDDS_DDR_C DDR www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: AM2434 AM2432 AM2431

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Table 5-1. Pin Attributes (ALV, ANI, ALX Packages) (continued) ALV ANI BALL NUMBER [1] ALX BALL NUMBER [1] BALL NAME [2] PADCONFIG Register [15] PADCONFIG Address [16] SIGNAL NAME [3] MUX MODE [4] TYPE [5] DSIS [6] BALL STATE DURING RESET RX/TX/PULL [7] BALL STATE AFTER RESET RX/TX/PULL [8] MUX MODE AFTER RESET [9] IO OPERATING VOLTAGE [10] POWER [11] HYS [12] BUFFER TYPE [14] Pull UP/DOWN TYPE [13] R17 GPMC0_CLK PADCONFIG: PADCONFIG31 0x000F407C GPMC0_CLK 0 O 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV3 Yes LVCMOS PU/PD FSI_RX4_CLK 1 I 0 UART4_RTSn 2 O EHRPWM3_SYNCO 3 O GPMC0_FCLK_MUX 4 O TRC_DATA14 6 O GPIO0_31 7 IO pad PRG0_PWM3_TZ_OUT 9 O N17 GPMC0_DIR PADCONFIG: PADCONFIG41 0x000F40A4 GPMC0_DIR 0 O Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV3 Yes LVCMOS PU/PD EQEP0_B 3 I 0 GPIO0_40 7 IO pad EHRPWM6_B 8 IO 0 PRG1_PWM2_B0 9 IO 1 R18 GPMC0_OEn_REn PADCONFIG: PADCONFIG34 0x000F4088 GPMC0_OEn_REn 0 O Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV3 Yes LVCMOS PU/PD FSI_RX5_D0 1 I 0 UART5_TXD 2 O EHRPWM4_A 3 IO 0 TRC_DATA16 6 O GPIO0_33 7 IO pad PRG0_PWM3_A1 9 IO 0 T21 GPMC0_WEn PADCONFIG: PADCONFIG35 0x000F408C GPMC0_WEn 0 O Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV3 Yes LVCMOS PU/PD FSI_RX5_D1 1 I 0 UART5_RTSn 2 O EHRPWM4_B 3 IO 0 TRC_DATA17 6 O GPIO0_34 7 IO pad PRG0_PWM3_B1 9 IO 1 N16 GPMC0_WPn PADCONFIG: PADCONFIG40 0x000F40A0 GPMC0_WPn 0 O Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV3 Yes LVCMOS PU/PD FSI_TX1_CLK 1 O EQEP0_A 3 I 0 GPMC0_A22 4 OZ TRC_DATA22 6 O GPIO0_39 7 IO pad EHRPWM6_A 8 IO 0 PRG1_PWM2_A0 9 IO 0 www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: AM2434 AM2432 AM2431

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Table 5-1. Pin Attributes (ALV, ANI, ALX Packages) (continued) ALV ANI BALL NUMBER [1] ALX BALL NUMBER [1] BALL NAME [2] PADCONFIG Register [15] PADCONFIG Address [16] SIGNAL NAME [3] MUX MODE [4] TYPE [5] DSIS [6] BALL STATE DURING RESET RX/TX/PULL [7] BALL STATE AFTER RESET RX/TX/PULL [8] MUX MODE AFTER RESET [9] IO OPERATING VOLTAGE [10] POWER [11] HYS [12] BUFFER TYPE [14] Pull UP/DOWN TYPE [13] R21 GPMC0_CSn3 PADCONFIG: PADCONFIG45 0x000F40B4 GPMC0_CSn3 0 O Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV3 Yes LVCMOS PU/PD I2C2_SDA 1 IOD 1 TIMER_IO9 2 IO 0 EQEP1_I 3 IO 0 GPMC0_A20 4 OZ EHRPWM_TZn_IN5 5 I 0 GPIO0_44 7 IO pad W19 GPMC0_WAIT0 PADCONFIG: PADCONFIG38 0x000F4098 GPMC0_WAIT0 0 I 1 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV3 Yes LVCMOS PU/PD EHRPWM5_B 3 IO 0 TRC_DATA20 6 O GPIO0_37 7 IO pad PRG0_PWM3_B2 9 IO 1 Y18 GPMC0_WAIT1 PADCONFIG: PADCONFIG39 0x000F409C GPMC0_WAIT1 0 I 1 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV3 Yes LVCMOS PU/PD FSI_TX1_D1 1 O EHRPWM_TZn_IN5 3 I 0 GPMC0_A21 4 OZ EHRPWM7_B 5 IO 0 TRC_DATA21 6 O GPIO0_38 7 IO pad PRG1_PWM2_B1 9 IO 1 A18 B16 I2C0_SCL PADCONFIG: PADCONFIG152 0x000F4260 I2C0_SCL 0 IOD 1 Off / Off / NA On / SS / NA 7 1.8V / 3.3V VDDSHV0 Yes I2C OD FS GPIO1_64 7 IOD pad B18 B15 I2C0_SDA PADCONFIG: PADCONFIG153 0x000F4264 I2C0_SDA 0 IOD 1 Off / Off / NA On / SS / NA 7 1.8V / 3.3V VDDSHV0 Yes I2C OD FS GPIO1_65 7 IOD pad C18 A17 I2C1_SCL PADCONFIG: PADCONFIG154 0x000F4268 I2C1_SCL 0 IOD 1 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV0 Yes LVCMOS PU/PD CPTS0_HW1TSPUSH 1 I 0 TIMER_IO0 2 IO 0 SPI2_CS1 3 IO 1 GPIO1_66 7 IO pad B19 B18 I2C1_SDA PADCONFIG: PADCONFIG155 0x000F426C I2C1_SDA 0 IOD 1 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV0 Yes LVCMOS PU/PD CPTS0_HW2TSPUSH 1 I 0 TIMER_IO1 2 IO 0 SPI2_CS2 3 IO 1 GPIO1_67 7 IO pad www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: AM2434 AM2432 AM2431

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Table 5-1. Pin Attributes (ALV, ANI, ALX Packages) (continued) ALV ANI BALL NUMBER [1] ALX BALL NUMBER [1] BALL NAME [2] PADCONFIG Register [15] PADCONFIG Address [16] SIGNAL NAME [3] MUX MODE [4] TYPE [5] DSIS [6] BALL STATE DURING RESET RX/TX/PULL [7] BALL STATE AFTER RESET RX/TX/PULL [8] MUX MODE AFTER RESET [9] IO OPERATING VOLTAGE [10] POWER [11] HYS [12] BUFFER TYPE [14] Pull UP/DOWN TYPE [13] C17 B14 MCAN1_TX PADCONFIG: PADCONFIG150 0x000F4258 MCAN1_TX 0 O Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV0 Yes LVCMOS PU/PD I2C3_SCL 1 IOD 1 ECAP1_IN_APWM_OUT 2 IO 0 SYSCLKOUT0 3 O TIMER_IO4 4 IO 0 UART5_RXD 5 I 1 EHRPWM_SOCA 6 O GPIO1_62 7 IO pad EQEP2_A 8 I 0 UART0_DCDn 9 I 1 E9 MCU_I2C0_SCL PADCONFIG: MCU_PADCONFIG18 0x04084048 MCU_I2C0_SCL 0 IOD 1 Off / Off / NA On / SS / NA 7 1.8V / 3.3V VDDSHV_MCU Yes I2C OD FS MCU_GPIO0_18 7 IOD pad A10 MCU_I2C0_SDA PADCONFIG: MCU_PADCONFIG19 0x0408404C MCU_I2C0_SDA 0 IOD 1 Off / Off / NA On / SS / NA 7 1.8V / 3.3V VDDSHV_MCU Yes I2C OD FS MCU_GPIO0_19 7 IOD pad A11 MCU_I2C1_SCL PADCONFIG: MCU_PADCONFIG20 0x04084050 MCU_I2C1_SCL 0 IOD 1 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV_MCU Yes LVCMOS PU/PD MCU_GPIO0_20 7 IO pad B10 MCU_I2C1_SDA PADCONFIG: MCU_PADCONFIG21 0x04084054 MCU_I2C1_SDA 0 IOD 1 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV_MCU Yes LVCMOS PU/PD MCU_GPIO0_21 7 IO pad C21 D20 MCU_OSC0_XI MCU_OSC0_XI I 1.8V VDDS_OSC Yes HFOSC B20 C21 MCU_OSC0_XO MCU_OSC0_XO O 1.8V VDDS_OSC Yes HFOSC B21 C20 MCU_PORz PADCONFIG: MCU_PADCONFIG23 0x0408405C MCU_PORz 0 I 0 1.8V VDDS_OSC Yes FS RESET B13 A6 MCU_RESETSTATz PADCONFIG: MCU_PADCONFIG24 0x04084060 MCU_RESETSTATz 0 O Off / Low / Off Off / SS / Off 0 1.8V / 3.3V VDDSHV_MCU Yes LVCMOS PU/PD MCU_GPIO0_22 7 IO pad B12 A5 MCU_RESETz PADCONFIG: MCU_PADCONFIG22 0x04084058 MCU_RESETz 0 I On / Off / Up On / Off / Up 0 1.8V / 3.3V VDDSHV_MCU Yes LVCMOS PU/PD www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: AM2434 AM2432 AM2431

Table 5-1. Pin Attributes (ALV, ANI, ALX Packages) (continued) ALV ANI BALL NUMBER [1] ALX BALL NUMBER [1] BALL NAME [2] PADCONFIG Register [15] PADCONFIG Address [16] SIGNAL NAME [3] MUX MODE [4] TYPE [5] DSIS [6] BALL STATE DURING RESET RX/TX/PULL [7] BALL STATE AFTER RESET RX/TX/PULL [8] MUX MODE AFTER RESET [9] IO OPERATING VOLTAGE [10] POWER [11] HYS [12] BUFFER TYPE [14] Pull UP/DOWN TYPE [13] A20 B20 MCU_SAFETY_ERRORn PADCONFIG: MCU_PADCONFIG25 0x04084064 MCU_SAFETY_ERRORn 0 IO Off / Off / Down On / SS / Down 0 1.8V VDDS_OSC Yes LVCMOS PU/PD E6 MCU_SPI0_CLK PADCONFIG: MCU_PADCONFIG2 0x04084008 MCU_SPI0_CLK 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV_MCU Yes LVCMOS PU/PD MCU_GPIO0_11 7 IO pad D7 MCU_SPI1_CLK PADCONFIG: MCU_PADCONFIG7 0x0408401C MCU_SPI1_CLK 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV_MCU Yes LVCMOS PU/PD MCU_GPIO0_7 7 IO pad D6 MCU_SPI0_CS0 PADCONFIG: MCU_PADCONFIG0 0x04084000 MCU_SPI0_CS0 0 IO 1 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV_MCU Yes LVCMOS PU/PD MCU_GPIO0_13 7 IO pad C6 MCU_SPI0_CS1 PADCONFIG: MCU_PADCONFIG1 0x04084004 MCU_SPI0_CS1 0 IO 1 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV_MCU Yes LVCMOS PU/PD MCU_OBSCLK0 1 O MCU_SYSCLKOUT0 2 O MCU_GPIO0_12 7 IO pad E7 MCU_SPI0_D0 PADCONFIG: MCU_PADCONFIG3 0x0408400C MCU_SPI0_D0 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV_MCU Yes LVCMOS PU/PD MCU_GPIO0_10 7 IO pad B6 MCU_SPI0_D1 PADCONFIG: MCU_PADCONFIG4 0x04084010 MCU_SPI0_D1 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV_MCU Yes LVCMOS PU/PD MCU_GPIO0_4 7 IO pad A7 MCU_SPI1_CS0 PADCONFIG: MCU_PADCONFIG5 0x04084014 MCU_SPI1_CS0 0 IO 1 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV_MCU Yes LVCMOS PU/PD MCU_GPIO0_5 7 IO pad B7 MCU_SPI1_CS1 PADCONFIG: MCU_PADCONFIG6 0x04084018 MCU_SPI1_CS1 0 IO 1 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV_MCU Yes LVCMOS PU/PD MCU_EXT_REFCLK0 1 I 0 MCU_GPIO0_6 7 IO pad C7 MCU_SPI1_D0 PADCONFIG: MCU_PADCONFIG8 0x04084020 MCU_SPI1_D0 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV_MCU Yes LVCMOS PU/PD MCU_GPIO0_8 7 IO pad C8 MCU_SPI1_D1 PADCONFIG: MCU_PADCONFIG9 0x04084024 MCU_SPI1_D1 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV_MCU Yes LVCMOS PU/PD MCU_GPIO0_9 7 IO pad AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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Table 5-1. Pin Attributes (ALV, ANI, ALX Packages) (continued) ALV ANI BALL NUMBER [1] ALX BALL NUMBER [1] BALL NAME [2] PADCONFIG Register [15] PADCONFIG Address [16] SIGNAL NAME [3] MUX MODE [4] TYPE [5] DSIS [6] BALL STATE DURING RESET RX/TX/PULL [7] BALL STATE AFTER RESET RX/TX/PULL [8] MUX MODE AFTER RESET [9] IO OPERATING VOLTAGE [10] POWER [11] HYS [12] BUFFER TYPE [14] Pull UP/DOWN TYPE [13] D8 D4 MCU_UART0_CTSn PADCONFIG: MCU_PADCONFIG12 0x04084030 MCU_UART0_CTSn 0 I 1 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV_MCU Yes LVCMOS PU/PD MCU_TIMER_IO0 1 IO 0 MCU_SPI0_CS2 2 IO 1 MCU_GPIO0_1 7 IO pad E8 C2 MCU_UART0_RTSn PADCONFIG: MCU_PADCONFIG13 0x04084034 MCU_UART0_RTSn 0 O Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV_MCU Yes LVCMOS PU/PD MCU_TIMER_IO1 1 IO 0 MCU_SPI1_CS2 2 IO 1 MCU_GPIO0_0 7 IO pad A9 D6 MCU_UART0_RXD PADCONFIG: MCU_PADCONFIG10 0x04084028 MCU_UART0_RXD 0 I 1 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV_MCU Yes LVCMOS PU/PD MCU_GPIO0_3 7 IO pad A8 B2 MCU_UART0_TXD PADCONFIG: MCU_PADCONFIG11 0x0408402C MCU_UART0_TXD 0 O Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV_MCU Yes LVCMOS PU/PD MCU_GPIO0_2 7 IO pad B8 MCU_UART1_CTSn PADCONFIG: MCU_PADCONFIG16 0x04084040 MCU_UART1_CTSn 0 I 1 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV_MCU Yes LVCMOS PU/PD MCU_TIMER_IO2 1 IO 0 MCU_SPI0_CS3 2 IO 1 MCU_GPIO0_16 7 IO pad B9 MCU_UART1_RTSn PADCONFIG: MCU_PADCONFIG17 0x04084044 MCU_UART1_RTSn 0 O Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV_MCU Yes LVCMOS PU/PD MCU_TIMER_IO3 1 IO 0 MCU_SPI1_CS3 2 IO 1 MCU_GPIO0_17 7 IO pad C9 MCU_UART1_RXD PADCONFIG: MCU_PADCONFIG14 0x04084038 MCU_UART1_RXD 0 I 1 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV_MCU Yes LVCMOS PU/PD MCU_GPIO0_14 7 IO pad D9 MCU_UART1_TXD PADCONFIG: MCU_PADCONFIG15 0x0408403C MCU_UART1_TXD 0 O Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV_MCU Yes LVCMOS PU/PD MCU_GPIO0_15 7 IO pad F18 MMC0_CALPAD MMC0_CALPAD A 1.8V VDDS_MMC0 eMMCPHY G18 MMC0_CLK MMC0_CLK IO On / Low / Off On / SS / Off 1.8V VDDS_MMC0 eMMCPHY PU/PD J21 MMC0_CMD MMC0_CMD IO On / High / Up On / SS / Up 1.8V VDDS_MMC0 eMMCPHY PU/PD G19 MMC0_DS MMC0_DS IO On / Off / Down On / Off / Down 1.8V VDDS_MMC0 eMMCPHY PU/PD www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: AM2434 AM2432 AM2431

Table 5-1. Pin Attributes (ALV, ANI, ALX Packages) (continued) ALV ANI BALL NUMBER [1] ALX BALL NUMBER [1] BALL NAME [2] PADCONFIG Register [15] PADCONFIG Address [16] SIGNAL NAME [3] MUX MODE [4] TYPE [5] DSIS [6] BALL STATE DURING RESET RX/TX/PULL [7] BALL STATE AFTER RESET RX/TX/PULL [8] MUX MODE AFTER RESET [9] IO OPERATING VOLTAGE [10] POWER [11] HYS [12] BUFFER TYPE [14] Pull UP/DOWN TYPE [13] L20 J20 MMC1_CLK PADCONFIG: PADCONFIG163 0x000F428C MMC1_CLK 0 IO Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV5 Yes SDIO PU/PD UART2_CTSn 1 I 1 TIMER_IO4 2 IO 0 UART4_RXD 3 I 1 GPIO1_75 7 IO pad J19 J21 MMC1_CMD PADCONFIG: PADCONFIG165 0x000F4294 MMC1_CMD 0 IO 1 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV5 Yes SDIO PU/PD UART2_RTSn 1 O TIMER_IO5 2 IO 0 UART4_TXD 3 O GPIO1_76 7 IO pad D19 B17 MMC1_SDCD PADCONFIG: PADCONFIG166 0x000F4298 MMC1_SDCD 0 I 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV0 Yes LVCMOS PU/PD UART3_CTSn 1 I 1 TIMER_IO6 2 IO 0 UART5_RXD 3 I 1 GPIO1_77 7 IO pad C20 C16 MMC1_SDWP PADCONFIG: PADCONFIG167 0x000F429C MMC1_SDWP 0 I 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV0 Yes LVCMOS PU/PD UART3_RTSn 1 O TIMER_IO7 2 IO 0 UART5_TXD 3 O GPIO1_78 7 IO pad K20 MMC0_DAT0 MMC0_DAT0 IO On / Off / Up On / SS / Up 1.8V VDDS_MMC0 eMMCPHY PU/PD J20 MMC0_DAT1 MMC0_DAT1 IO On / Off / Up On / SS / Up 1.8V VDDS_MMC0 eMMCPHY PU/PD J18 MMC0_DAT2 MMC0_DAT2 IO On / Off / Up On / SS / Up 1.8V VDDS_MMC0 eMMCPHY PU/PD J17 MMC0_DAT3 MMC0_DAT3 IO On / Off / Up On / SS / Up 1.8V VDDS_MMC0 eMMCPHY PU/PD H17 MMC0_DAT4 MMC0_DAT4 IO On / Off / Up On / SS / Up 1.8V VDDS_MMC0 eMMCPHY PU/PD H19 MMC0_DAT5 MMC0_DAT5 IO On / Off / Up On / SS / Up 1.8V VDDS_MMC0 eMMCPHY PU/PD H18 MMC0_DAT6 MMC0_DAT6 IO On / Off / Up On / SS / Up 1.8V VDDS_MMC0 eMMCPHY PU/PD G17 MMC0_DAT7 MMC0_DAT7 IO On / Off / Up On / SS / Up 1.8V VDDS_MMC0 eMMCPHY PU/PD K21 J18 MMC1_DAT0 PADCONFIG: PADCONFIG162 0x000F4288 MMC1_DAT0 0 IO 1 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV5 Yes SDIO PU/PD CP_GEMAC_CPTS0_HW2TSPUSH 1 I 0 TIMER_IO3 2 IO 0 UART3_TXD 3 O GPIO1_74 7 IO pad AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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Table 5-1. Pin Attributes (ALV, ANI, ALX Packages) (continued) ALV ANI BALL NUMBER [1] ALX BALL NUMBER [1] BALL NAME [2] PADCONFIG Register [15] PADCONFIG Address [16] SIGNAL NAME [3] MUX MODE [4] TYPE [5] DSIS [6] BALL STATE DURING RESET RX/TX/PULL [7] BALL STATE AFTER RESET RX/TX/PULL [8] MUX MODE AFTER RESET [9] IO OPERATING VOLTAGE [10] POWER [11] HYS [12] BUFFER TYPE [14] Pull UP/DOWN TYPE [13] L21 J19 MMC1_DAT1 PADCONFIG: PADCONFIG161 0x000F4284 MMC1_DAT1 0 IO 1 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV5 Yes SDIO PU/PD CP_GEMAC_CPTS0_HW1TSPUSH 1 I 0 TIMER_IO2 2 IO 0 UART3_RXD 3 I 1 GPIO1_73 7 IO pad K19 K20 MMC1_DAT2 PADCONFIG: PADCONFIG160 0x000F4280 MMC1_DAT2 0 IO 1 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV5 Yes SDIO PU/PD CP_GEMAC_CPTS0_TS_SYNC 1 O TIMER_IO1 2 IO 0 UART2_TXD 3 O GPIO1_72 7 IO pad K18 K18 MMC1_DAT3 PADCONFIG: PADCONFIG159 0x000F427C MMC1_DAT3 0 IO 1 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV5 Yes SDIO PU/PD CP_GEMAC_CPTS0_TS_COMP 1 O TIMER_IO0 2 IO 0 UART2_RXD 3 I 1 GPIO1_71 7 IO pad N20 P20 OSPI0_CLK PADCONFIG: PADCONFIG0 0x000F4000 OSPI0_CLK 0 O Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV4 Yes LVCMOS PU/PD GPIO0_0 7 IO pad N19 P17 OSPI0_DQS PADCONFIG: PADCONFIG2 0x000F4008 OSPI0_DQS 0 I 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV4 Yes LVCMOS PU/PD GPIO0_2 7 IO pad N21 M21 OSPI0_LBCLKO PADCONFIG: PADCONFIG1 0x000F4004 OSPI0_LBCLKO 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV4 Yes LVCMOS PU/PD GPIO0_1 7 IO pad L19 L20 OSPI0_CSn0 PADCONFIG: PADCONFIG11 0x000F402C OSPI0_CSn0 0 O Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV4 Yes LVCMOS PU/PD GPIO0_11 7 IO pad L18 M20 OSPI0_CSn1 PADCONFIG: PADCONFIG12 0x000F4030 OSPI0_CSn1 0 O Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV4 Yes LVCMOS PU/PD GPIO0_12 7 IO pad K17 OSPI0_CSn2 PADCONFIG: PADCONFIG13 0x000F4034 OSPI0_CSn2 0 O Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV4 Yes LVCMOS PU/PD OSPI0_RESET_OUT1 2 O GPIO0_13 7 IO pad www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: AM2434 AM2432 AM2431

Table 5-1. Pin Attributes (ALV, ANI, ALX Packages) (continued) ALV ANI BALL NUMBER [1] ALX BALL NUMBER [1] BALL NAME [2] PADCONFIG Register [15] PADCONFIG Address [16] SIGNAL NAME [3] MUX MODE [4] TYPE [5] DSIS [6] BALL STATE DURING RESET RX/TX/PULL [7] BALL STATE AFTER RESET RX/TX/PULL [8] MUX MODE AFTER RESET [9] IO OPERATING VOLTAGE [10] POWER [11] HYS [12] BUFFER TYPE [14] Pull UP/DOWN TYPE [13] L17 OSPI0_CSn3 PADCONFIG: PADCONFIG14 0x000F4038 OSPI0_CSn3 0 O Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV4 Yes LVCMOS PU/PD OSPI0_RESET_OUT0 1 O OSPI0_ECC_FAIL 2 I 1 GPIO0_14 7 IO pad M19 L19 OSPI0_D0 PADCONFIG: PADCONFIG3 0x000F400C OSPI0_D0 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV4 Yes LVCMOS PU/PD GPIO0_3 7 IO pad M18 N20 OSPI0_D1 PADCONFIG: PADCONFIG4 0x000F4010 OSPI0_D1 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV4 Yes LVCMOS PU/PD GPIO0_4 7 IO pad M20 L21 OSPI0_D2 PADCONFIG: PADCONFIG5 0x000F4014 OSPI0_D2 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV4 Yes LVCMOS PU/PD GPIO0_5 7 IO pad M21 N19 OSPI0_D3 PADCONFIG: PADCONFIG6 0x000F4018 OSPI0_D3 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV4 Yes LVCMOS PU/PD GPIO0_6 7 IO pad P21 OSPI0_D4 PADCONFIG: PADCONFIG7 0x000F401C OSPI0_D4 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV4 Yes LVCMOS PU/PD GPIO0_7 7 IO pad P20 OSPI0_D5 PADCONFIG: PADCONFIG8 0x000F4020 OSPI0_D5 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV4 Yes LVCMOS PU/PD GPIO0_8 7 IO pad N18 OSPI0_D6 PADCONFIG: PADCONFIG9 0x000F4024 OSPI0_D6 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV4 Yes LVCMOS PU/PD GPIO0_9 7 IO pad M17 OSPI0_D7 PADCONFIG: PADCONFIG10 0x000F4028 OSPI0_D7 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV4 Yes LVCMOS PU/PD GPIO0_10 7 IO pad E17 D18 PORz_OUT PADCONFIG: PADCONFIG171 0x000F42AC PORz_OUT 0 O Off / Low / Off Off / SS / Off 0 1.8V / 3.3V VDDSHV0 Yes LVCMOS PU/PD P3 D2 PRG0_MDIO0_MDC PADCONFIG: PADCONFIG129 0x000F4204 PRG0_MDIO0_MDC 0 O Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV1 Yes LVCMOS PU/PD GPIO1_41 7 IO pad GPMC0_A13 9 OZ AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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Table 5-1. Pin Attributes (ALV, ANI, ALX Packages) (continued) ALV ANI BALL NUMBER [1] ALX BALL NUMBER [1] BALL NAME [2] PADCONFIG Register [15] PADCONFIG Address [16] SIGNAL NAME [3] MUX MODE [4] TYPE [5] DSIS [6] BALL STATE DURING RESET RX/TX/PULL [7] BALL STATE AFTER RESET RX/TX/PULL [8] MUX MODE AFTER RESET [9] IO OPERATING VOLTAGE [10] POWER [11] HYS [12] BUFFER TYPE [14] Pull UP/DOWN TYPE [13] P2 E4 PRG0_MDIO0_MDIO PADCONFIG: PADCONFIG128 0x000F4200 PRG0_MDIO0_MDIO 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV1 Yes LVCMOS PU/PD GPIO1_40 7 IO pad GPMC0_A12 9 OZ Y1 J3 PRG0_PRU0_GPO0 PADCONFIG: PADCONFIG88 0x000F4160 PRG0_PRU0_GPO0 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV1 Yes LVCMOS PU/PD PRG0_PRU0_GPI0 1 I 0 PRG0_RGMII1_RD0 2 I 0 PRG0_PWM3_A0 3 IO 0 GPIO1_0 7 IO pad UART2_CTSn 10 I 1 R4 J4 PRG0_PRU0_GPO1 PADCONFIG: PADCONFIG89 0x000F4164 PRG0_PRU0_GPO1 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV1 Yes LVCMOS PU/PD PRG0_PRU0_GPI1 1 I 0 PRG0_RGMII1_RD1 2 I 0 PRG0_PWM3_B0 3 IO 1 GPIO1_1 7 IO pad UART2_TXD 10 O U2 G1 PRG0_PRU0_GPO2 PADCONFIG: PADCONFIG90 0x000F4168 PRG0_PRU0_GPO2 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV1 Yes LVCMOS PU/PD PRG0_PRU0_GPI2 1 I 0 PRG0_RGMII1_RD2 2 I 0 PRG0_PWM2_A0 3 IO 0 GPIO1_2 7 IO pad GPMC0_A0 9 OZ UART2_RTSn 10 O V2 H1 PRG0_PRU0_GPO3 PADCONFIG: PADCONFIG91 0x000F416C PRG0_PRU0_GPO3 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV1 Yes LVCMOS PU/PD PRG0_PRU0_GPI3 1 I 0 PRG0_RGMII1_RD3 2 I 0 PRG0_PWM3_A2 3 IO 0 GPIO1_3 7 IO pad UART3_CTSn 10 I 1 AA2 K2 PRG0_PRU0_GPO4 PADCONFIG: PADCONFIG92 0x000F4170 PRG0_PRU0_GPO4 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV1 Yes LVCMOS PU/PD PRG0_PRU0_GPI4 1 I 0 PRG0_RGMII1_RX_CTL 2 I 0 PRG0_PWM2_B0 3 IO 1 GPIO1_4 7 IO pad GPMC0_A1 9 OZ UART3_TXD 10 O www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 33 Product Folder Links: AM2434 AM2432 AM2431

Table 5-1. Pin Attributes (ALV, ANI, ALX Packages) (continued) ALV ANI BALL NUMBER [1] ALX BALL NUMBER [1] BALL NAME [2] PADCONFIG Register [15] PADCONFIG Address [16] SIGNAL NAME [3] MUX MODE [4] TYPE [5] DSIS [6] BALL STATE DURING RESET RX/TX/PULL [7] BALL STATE AFTER RESET RX/TX/PULL [8] MUX MODE AFTER RESET [9] IO OPERATING VOLTAGE [10] POWER [11] HYS [12] BUFFER TYPE [14] Pull UP/DOWN TYPE [13] R3 F2 PRG0_PRU0_GPO5 PADCONFIG: PADCONFIG93 0x000F4174 PRG0_PRU0_GPO5 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV1 Yes LVCMOS PU/PD PRG0_PRU0_GPI5 1 I 0 PRG0_PWM3_B2 3 IO 1 GPIO1_5 7 IO pad UART3_RTSn 10 O T3 H2 PRG0_PRU0_GPO6 PADCONFIG: PADCONFIG94 0x000F4178 PRG0_PRU0_GPO6 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV1 Yes LVCMOS PU/PD PRG0_PRU0_GPI6 1 I 0 PRG0_RGMII1_RXC 2 I 0 PRG0_PWM3_A1 3 IO 0 GPIO1_6 7 IO pad UART4_CTSn 10 I 1 T1 E2 PRG0_PRU0_GPO7 PADCONFIG: PADCONFIG95 0x000F417C PRG0_PRU0_GPO7 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV1 Yes LVCMOS PU/PD PRG0_PRU0_GPI7 1 I 0 PRG0_IEP0_EDC_LATCH_IN1 2 I 0 PRG0_PWM3_B1 3 IO 1 CPTS0_HW2TSPUSH 4 I 0 CP_GEMAC_CPTS0_HW2TSPUSH 5 I 0 TIMER_IO6 6 IO 0 GPIO1_7 7 IO pad UART4_TXD 10 O T2 H5 PRG0_PRU0_GPO8 PADCONFIG: PADCONFIG96 0x000F4180 PRG0_PRU0_GPO8 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV1 Yes LVCMOS PU/PD PRG0_PRU0_GPI8 1 I 0 PRG0_PWM2_A1 3 IO 0 GPIO1_8 7 IO pad GPMC0_A2 9 OZ UART4_RTSn 10 O W6 Y3 PRG0_PRU0_GPO9 PADCONFIG: PADCONFIG97 0x000F4184 PRG0_PRU0_GPO9 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV1 Yes LVCMOS PU/PD PRG0_PRU0_GPI9 1 I 0 PRG0_UART0_CTSn 2 I 1 PRG0_PWM3_TZ_IN 3 I 0 RGMII1_RX_CTL 4 I 0 RMII1_RX_ER 5 I 0 PRG0_IEP0_EDIO_DATA_IN_OUT28 6 IO 0 GPIO1_9 7 IO pad UART2_RXD 10 I 1 AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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Table 5-1. Pin Attributes (ALV, ANI, ALX Packages) (continued) ALV ANI BALL NUMBER [1] ALX BALL NUMBER [1] BALL NAME [2] PADCONFIG Register [15] PADCONFIG Address [16] SIGNAL NAME [3] MUX MODE [4] TYPE [5] DSIS [6] BALL STATE DURING RESET RX/TX/PULL [7] BALL STATE AFTER RESET RX/TX/PULL [8] MUX MODE AFTER RESET [9] IO OPERATING VOLTAGE [10] POWER [11] HYS [12] BUFFER TYPE [14] Pull UP/DOWN TYPE [13] AA5 U1 PRG0_PRU0_GPO10 PADCONFIG: PADCONFIG98 0x000F4188 PRG0_PRU0_GPO10 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV1 Yes LVCMOS PU/PD PRG0_PRU0_GPI10 1 I 0 PRG0_UART0_RTSn 2 O PRG0_PWM2_B1 3 IO 1 RGMII1_RXC 4 I 0 RMII_REF_CLK 5 I 0 PRG0_IEP0_EDIO_DATA_IN_OUT29 6 IO 0 GPIO1_10 7 IO pad UART3_RXD 10 I 1 Y3 L1 PRG0_PRU0_GPO11 PADCONFIG: PADCONFIG99 0x000F418C PRG0_PRU0_GPO11 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV1 Yes LVCMOS PU/PD PRG0_PRU0_GPI11 1 I 0 PRG0_RGMII1_TD0 2 O PRG0_PWM3_TZ_OUT 3 O GPIO1_11 7 IO pad UART4_RXD 10 I 1 AA3 K1 PRG0_PRU0_GPO12 PADCONFIG: PADCONFIG100 0x000F4190 PRG0_PRU0_GPO12 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV1 Yes LVCMOS PU/PD PRG0_PRU0_GPI12 1 I 0 PRG0_RGMII1_TD1 2 O PRG0_PWM0_A0 3 IO 0 GPIO1_12 7 IO pad GPMC0_A14 9 OZ R6 N1 PRG0_PRU0_GPO13 PADCONFIG: PADCONFIG101 0x000F4194 PRG0_PRU0_GPO13 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV1 Yes LVCMOS PU/PD PRG0_PRU0_GPI13 1 I 0 PRG0_RGMII1_TD2 2 O PRG0_PWM0_B0 3 IO 1 SPI3_D0 6 IO 0 GPIO1_13 7 IO pad GPMC0_A15 9 OZ V4 N2 PRG0_PRU0_GPO14 PADCONFIG: PADCONFIG102 0x000F4198 PRG0_PRU0_GPO14 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV1 Yes LVCMOS PU/PD PRG0_PRU0_GPI14 1 I 0 PRG0_RGMII1_TD3 2 O PRG0_PWM0_A1 3 IO 0 SPI3_D1 6 IO 0 GPIO1_14 7 IO pad GPMC0_A3 9 OZ www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 35 Product Folder Links: AM2434 AM2432 AM2431

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Table 5-1. Pin Attributes (ALV, ANI, ALX Packages) (continued) ALV ANI BALL NUMBER [1] ALX BALL NUMBER [1] BALL NAME [2] PADCONFIG Register [15] PADCONFIG Address [16] SIGNAL NAME [3] MUX MODE [4] TYPE [5] DSIS [6] BALL STATE DURING RESET RX/TX/PULL [7] BALL STATE AFTER RESET RX/TX/PULL [8] MUX MODE AFTER RESET [9] IO OPERATING VOLTAGE [10] POWER [11] HYS [12] BUFFER TYPE [14] Pull UP/DOWN TYPE [13] T4 L2 PRG0_PRU1_GPO3 PADCONFIG: PADCONFIG111 0x000F41BC PRG0_PRU1_GPO3 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV1 Yes LVCMOS PU/PD PRG0_PRU1_GPI3 1 I 0 PRG0_RGMII2_RD3 2 I 0 GPIO1_23 7 IO pad EQEP1_A 8 I 0 GPMC0_A18 9 OZ UART6_CTSn 10 I 1 W3 L3 PRG0_PRU1_GPO4 PADCONFIG: PADCONFIG112 0x000F41C0 PRG0_PRU1_GPO4 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV1 Yes LVCMOS PU/PD PRG0_PRU1_GPI4 1 I 0 PRG0_RGMII2_RX_CTL 2 I 0 PRG0_PWM2_B2 3 IO 1 GPIO1_24 7 IO pad EQEP1_B 8 I 0 UART6_TXD 10 O P4 E3 PRG0_PRU1_GPO5 PADCONFIG: PADCONFIG113 0x000F41C4 PRG0_PRU1_GPO5 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV1 Yes LVCMOS PU/PD PRG0_PRU1_GPI5 1 I 0 GPIO1_25 7 IO pad EQEP1_S 8 IO 0 UART6_RTSn 10 O R5 F5 PRG0_PRU1_GPO6 PADCONFIG: PADCONFIG114 0x000F41C8 PRG0_PRU1_GPO6 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV1 Yes LVCMOS PU/PD PRG0_PRU1_GPI6 1 I 0 PRG0_RGMII2_RXC 2 I 0 GPIO1_26 7 IO pad EQEP2_A 8 I 0 GPMC0_A19 9 OZ UART4_CTSn 10 I 1 W5 T5 PRG0_PRU1_GPO7 PADCONFIG: PADCONFIG115 0x000F41CC PRG0_PRU1_GPO7 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV1 Yes LVCMOS PU/PD PRG0_PRU1_GPI7 1 I 0 PRG0_IEP1_EDC_LATCH_IN1 2 I 0 RGMII1_RD0 4 I 0 RMII1_RXD0 5 I 0 GPIO1_27 7 IO pad EQEP2_B 8 I 0 UART4_TXD 10 O AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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Table 5-1. Pin Attributes (ALV, ANI, ALX Packages) (continued) ALV ANI BALL NUMBER [1] ALX BALL NUMBER [1] BALL NAME [2] PADCONFIG Register [15] PADCONFIG Address [16] SIGNAL NAME [3] MUX MODE [4] TYPE [5] DSIS [6] BALL STATE DURING RESET RX/TX/PULL [7] BALL STATE AFTER RESET RX/TX/PULL [8] MUX MODE AFTER RESET [9] IO OPERATING VOLTAGE [10] POWER [11] HYS [12] BUFFER TYPE [14] Pull UP/DOWN TYPE [13] R1 F4 PRG0_PRU1_GPO8 PADCONFIG: PADCONFIG116 0x000F41D0 PRG0_PRU1_GPO8 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV1 Yes LVCMOS PU/PD PRG0_PRU1_GPI8 1 I 0 PRG0_PWM2_TZ_OUT 3 O GPIO1_28 7 IO pad EQEP2_S 8 IO 0 UART4_RTSn 10 O Y5 R2 PRG0_PRU1_GPO9 PADCONFIG: PADCONFIG117 0x000F41D4 PRG0_PRU1_GPO9 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV1 Yes LVCMOS PU/PD PRG0_PRU1_GPI9 1 I 0 PRG0_UART0_RXD 2 I 1 RGMII1_RD1 4 I 0 RMII1_RXD1 5 I 0 PRG0_IEP0_EDIO_DATA_IN_OUT30 6 IO 0 GPIO1_29 7 IO pad EQEP0_I 8 IO 0 UART5_RXD 10 I 1 V6 U2 PRG0_PRU1_GPO10 PADCONFIG: PADCONFIG118 0x000F41D8 PRG0_PRU1_GPO10 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV1 Yes LVCMOS PU/PD PRG0_PRU1_GPI10 1 I 0 PRG0_UART0_TXD 2 O PRG0_PWM2_TZ_IN 3 I 0 RGMII1_RD2 4 I 0 RMII1_TXD0 5 O PRG0_IEP0_EDIO_DATA_IN_OUT31 6 IO 0 GPIO1_30 7 IO pad EQEP1_I 8 IO 0 UART6_RXD 10 I 1 W4 P1 PRG0_PRU1_GPO11 PADCONFIG: PADCONFIG119 0x000F41DC PRG0_PRU1_GPO11 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV1 Yes LVCMOS PU/PD PRG0_PRU1_GPI11 1 I 0 PRG0_RGMII2_TD0 2 O GPIO1_31 7 IO pad EQEP2_I 8 IO 0 UART4_RXD 10 I 1 www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 39 Product Folder Links: AM2434 AM2432 AM2431

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Table 5-1. Pin Attributes (ALV, ANI, ALX Packages) (continued) ALV ANI BALL NUMBER [1] ALX BALL NUMBER [1] BALL NAME [2] PADCONFIG Register [15] PADCONFIG Address [16] SIGNAL NAME [3] MUX MODE [4] TYPE [5] DSIS [6] BALL STATE DURING RESET RX/TX/PULL [7] BALL STATE AFTER RESET RX/TX/PULL [8] MUX MODE AFTER RESET [9] IO OPERATING VOLTAGE [10] POWER [11] HYS [12] BUFFER TYPE [14] Pull UP/DOWN TYPE [13] AA4 T3 PRG0_PRU1_GPO16 PADCONFIG: PADCONFIG124 0x000F41F0 PRG0_PRU1_GPO16 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV1 Yes LVCMOS PU/PD PRG0_PRU1_GPI16 1 I 0 PRG0_RGMII2_TXC 2 IO 0 PRG0_PWM1_A2 3 IO 0 GPIO1_36 7 IO pad GPMC0_A11 9 OZ PRG0_ECAP0_SYNC_OUT 10 O V5 T1 PRG0_PRU1_GPO17 PADCONFIG: PADCONFIG125 0x000F41F4 PRG0_PRU1_GPO17 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV1 Yes LVCMOS PU/PD PRG0_PRU1_GPI17 1 I 0 PRG0_IEP1_EDC_SYNC_OUT1 2 O PRG0_PWM1_B2 3 IO 1 RGMII1_RD3 4 I 0 RMII1_TXD1 5 O GPIO1_37 7 IO pad PRG0_ECAP0_SYNC_OUT 8 O PRG0_ECAP0_SYNC_IN 10 I 0 P5 D1 PRG0_PRU1_GPO18 PADCONFIG: PADCONFIG126 0x000F41F8 PRG0_PRU1_GPO18 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV1 Yes LVCMOS PU/PD PRG0_PRU1_GPI18 1 I 0 PRG0_IEP1_EDC_LATCH_IN0 2 I 0 PRG0_PWM1_TZ_IN 3 I 0 MDIO0_MDIO 4 IO 0 RMII1_TX_EN 5 O EHRPWM7_A 6 IO 0 GPIO1_38 7 IO pad PRG0_ECAP0_SYNC_IN 8 I 0 R2 F3 PRG0_PRU1_GPO19 PADCONFIG: PADCONFIG127 0x000F41FC PRG0_PRU1_GPO19 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV1 Yes LVCMOS PU/PD PRG0_PRU1_GPI19 1 I 0 PRG0_IEP1_EDC_SYNC_OUT0 2 O PRG0_PWM1_TZ_OUT 3 O MDIO0_MDC 4 O RMII1_CRS_DV 5 I 0 EHRPWM7_B 6 IO 0 GPIO1_39 7 IO pad PRG0_ECAP0_IN_APWM_OUT 8 IO 0 www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 41 Product Folder Links: AM2434 AM2432 AM2431

Table 5-1. Pin Attributes (ALV, ANI, ALX Packages) (continued) ALV ANI BALL NUMBER [1] ALX BALL NUMBER [1] BALL NAME [2] PADCONFIG Register [15] PADCONFIG Address [16] SIGNAL NAME [3] MUX MODE [4] TYPE [5] DSIS [6] BALL STATE DURING RESET RX/TX/PULL [7] BALL STATE AFTER RESET RX/TX/PULL [8] MUX MODE AFTER RESET [9] IO OPERATING VOLTAGE [10] POWER [11] HYS [12] BUFFER TYPE [14] Pull UP/DOWN TYPE [13] Y6 W1 PRG1_MDIO0_MDC PADCONFIG: PADCONFIG87 0x000F415C PRG1_MDIO0_MDC 0 O Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV2 Yes LVCMOS PU/PD MDIO0_MDC 4 O GPIO0_86 7 IO pad AA6 V2 PRG1_MDIO0_MDIO PADCONFIG: PADCONFIG86 0x000F4158 PRG1_MDIO0_MDIO 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV2 Yes LVCMOS PU/PD MDIO0_MDIO 4 IO 0 GPIO0_85 7 IO pad Y7 V4 PRG1_PRU0_GPO0 PADCONFIG: PADCONFIG46 0x000F40B8 PRG1_PRU0_GPO0 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV2 Yes LVCMOS PU/PD PRG1_PRU0_GPI0 1 I 0 PRG1_RGMII1_RD0 2 I 0 PRG1_PWM3_A0 3 IO 0 GPIO0_45 7 IO pad GPMC0_AD16 8 IO 0 U8 W5 PRG1_PRU0_GPO1 PADCONFIG: PADCONFIG47 0x000F40BC PRG1_PRU0_GPO1 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV2 Yes LVCMOS PU/PD PRG1_PRU0_GPI1 1 I 0 PRG1_RGMII1_RD1 2 I 0 PRG1_PWM3_B0 3 IO 1 GPIO0_46 7 IO pad GPMC0_AD17 8 IO 0 W8 AA4 PRG1_PRU0_GPO2 PADCONFIG: PADCONFIG48 0x000F40C0 PRG1_PRU0_GPO2 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV2 Yes LVCMOS PU/PD PRG1_PRU0_GPI2 1 I 0 PRG1_RGMII1_RD2 2 I 0 PRG1_PWM2_A0 3 IO 0 GPIO0_47 7 IO pad GPMC0_AD18 8 IO 0 V8 Y5 PRG1_PRU0_GPO3 PADCONFIG: PADCONFIG49 0x000F40C4 PRG1_PRU0_GPO3 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV2 Yes LVCMOS PU/PD PRG1_PRU0_GPI3 1 I 0 PRG1_RGMII1_RD3 2 I 0 PRG1_PWM3_A2 3 IO 0 GPIO0_48 7 IO pad GPMC0_AD19 8 IO 0 Y8 AA5 PRG1_PRU0_GPO4 PADCONFIG: PADCONFIG50 0x000F40C8 PRG1_PRU0_GPO4 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV2 Yes LVCMOS PU/PD PRG1_PRU0_GPI4 1 I 0 PRG1_RGMII1_RX_CTL 2 I 0 PRG1_PWM2_B0 3 IO 1 GPIO0_49 7 IO pad GPMC0_AD20 8 IO 0 AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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Table 5-1. Pin Attributes (ALV, ANI, ALX Packages) (continued) ALV ANI BALL NUMBER [1] ALX BALL NUMBER [1] BALL NAME [2] PADCONFIG Register [15] PADCONFIG Address [16] SIGNAL NAME [3] MUX MODE [4] TYPE [5] DSIS [6] BALL STATE DURING RESET RX/TX/PULL [7] BALL STATE AFTER RESET RX/TX/PULL [8] MUX MODE AFTER RESET [9] IO OPERATING VOLTAGE [10] POWER [11] HYS [12] BUFFER TYPE [14] Pull UP/DOWN TYPE [13] V13 U14 PRG1_PRU0_GPO5 PADCONFIG: PADCONFIG51 0x000F40CC PRG1_PRU0_GPO5 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV2 Yes LVCMOS PU/PD PRG1_PRU0_GPI5 1 I 0 PRG1_PWM3_B2 3 IO 1 RGMII1_RX_CTL 4 I 0 GPIO0_50 7 IO pad GPMC0_AD21 8 IO 0 AA7 Y2 PRG1_PRU0_GPO6 PADCONFIG: PADCONFIG52 0x000F40D0 PRG1_PRU0_GPO6 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV2 Yes LVCMOS PU/PD PRG1_PRU0_GPI6 1 I 0 PRG1_RGMII1_RXC 2 I 0 PRG1_PWM3_A1 3 IO 0 GPIO0_51 7 IO pad GPMC0_AD22 8 IO 0 U13 V13 PRG1_PRU0_GPO7 PADCONFIG: PADCONFIG53 0x000F40D4 PRG1_PRU0_GPO7 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV2 Yes LVCMOS PU/PD PRG1_PRU0_GPI7 1 I 0 PRG1_IEP0_EDC_LATCH_IN1 2 I 0 PRG1_PWM3_B1 3 IO 1 CPTS0_HW2TSPUSH 4 I 0 CLKOUT0 5 O TIMER_IO10 6 IO 0 GPIO0_52 7 IO pad GPMC0_AD23 8 IO 0 W13 Y13 PRG1_PRU0_GPO8 PADCONFIG: PADCONFIG54 0x000F40D8 PRG1_PRU0_GPO8 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV2 Yes LVCMOS PU/PD PRG1_PRU0_GPI8 1 I 0 PRG1_PWM2_A1 3 IO 0 RGMII1_RXC 4 I 0 GPIO0_53 7 IO pad GPMC0_AD24 8 IO 0 U15 W16 PRG1_PRU0_GPO9 PADCONFIG: PADCONFIG55 0x000F40DC PRG1_PRU0_GPO9 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV2 Yes LVCMOS PU/PD PRG1_PRU0_GPI9 1 I 0 PRG1_UART0_CTSn 2 I 1 PRG1_PWM3_TZ_IN 3 I 0 RGMII1_TX_CTL 4 O RMII1_RX_ER 5 I 0 PRG1_IEP0_EDIO_DATA_IN_OUT28 6 IO 0 GPIO0_54 7 IO pad GPMC0_AD25 8 IO 0 www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 43 Product Folder Links: AM2434 AM2432 AM2431

Table 5-1. Pin Attributes (ALV, ANI, ALX Packages) (continued) ALV ANI BALL NUMBER [1] ALX BALL NUMBER [1] BALL NAME [2] PADCONFIG Register [15] PADCONFIG Address [16] SIGNAL NAME [3] MUX MODE [4] TYPE [5] DSIS [6] BALL STATE DURING RESET RX/TX/PULL [7] BALL STATE AFTER RESET RX/TX/PULL [8] MUX MODE AFTER RESET [9] IO OPERATING VOLTAGE [10] POWER [11] HYS [12] BUFFER TYPE [14] Pull UP/DOWN TYPE [13] U14 W13 PRG1_PRU0_GPO10 PADCONFIG: PADCONFIG56 0x000F40E0 PRG1_PRU0_GPO10 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV2 Yes LVCMOS PU/PD PRG1_PRU0_GPI10 1 I 0 PRG1_UART0_RTSn 2 O PRG1_PWM2_B1 3 IO 1 RGMII1_TXC 4 IO 0 RMII_REF_CLK 5 I 0 PRG1_IEP0_EDIO_DATA_IN_OUT29 6 IO 0 GPIO0_55 7 IO pad GPMC0_AD26 8 IO 0 AA8 V5 PRG1_PRU0_GPO11 PADCONFIG: PADCONFIG57 0x000F40E4 PRG1_PRU0_GPO11 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV2 Yes LVCMOS PU/PD PRG1_PRU0_GPI11 1 I 0 PRG1_RGMII1_TD0 2 O PRG1_PWM3_TZ_OUT 3 O GPIO0_56 7 IO pad GPMC0_AD27 8 IO 0 U9 W2 PRG1_PRU0_GPO12 PADCONFIG: PADCONFIG58 0x000F40E8 PRG1_PRU0_GPO12 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV2 Yes LVCMOS PU/PD PRG1_PRU0_GPI12 1 I 0 PRG1_RGMII1_TD1 2 O PRG1_PWM0_A0 3 IO 0 GPIO0_57 7 IO pad GPMC0_AD28 8 IO 0 W9 V6 PRG1_PRU0_GPO13 PADCONFIG: PADCONFIG59 0x000F40EC PRG1_PRU0_GPO13 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV2 Yes LVCMOS PU/PD PRG1_PRU0_GPI13 1 I 0 PRG1_RGMII1_TD2 2 O PRG1_PWM0_B0 3 IO 1 GPIO0_58 7 IO pad GPMC0_AD29 8 IO 0 AA9 AA7 PRG1_PRU0_GPO14 PADCONFIG: PADCONFIG60 0x000F40F0 PRG1_PRU0_GPO14 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV2 Yes LVCMOS PU/PD PRG1_PRU0_GPI14 1 I 0 PRG1_RGMII1_TD3 2 O PRG1_PWM0_A1 3 IO 0 GPIO0_59 7 IO pad GPMC0_AD30 8 IO 0 AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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Table 5-1. Pin Attributes (ALV, ANI, ALX Packages) (continued) ALV ANI BALL NUMBER [1] ALX BALL NUMBER [1] BALL NAME [2] PADCONFIG Register [15] PADCONFIG Address [16] SIGNAL NAME [3] MUX MODE [4] TYPE [5] DSIS [6] BALL STATE DURING RESET RX/TX/PULL [7] BALL STATE AFTER RESET RX/TX/PULL [8] MUX MODE AFTER RESET [9] IO OPERATING VOLTAGE [10] POWER [11] HYS [12] BUFFER TYPE [14] Pull UP/DOWN TYPE [13] Y9 Y7 PRG1_PRU0_GPO15 PADCONFIG: PADCONFIG61 0x000F40F4 PRG1_PRU0_GPO15 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV2 Yes LVCMOS PU/PD PRG1_PRU0_GPI15 1 I 0 PRG1_RGMII1_TX_CTL 2 O PRG1_PWM0_B1 3 IO 1 GPIO0_60 7 IO pad GPMC0_AD31 8 IO 0 V9 W6 PRG1_PRU0_GPO16 PADCONFIG: PADCONFIG62 0x000F40F8 PRG1_PRU0_GPO16 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV2 Yes LVCMOS PU/PD PRG1_PRU0_GPI16 1 I 0 PRG1_RGMII1_TXC 2 IO 0 PRG1_PWM0_A2 3 IO 0 GPIO0_61 7 IO pad GPMC0_BE2n 8 O U7 T2 PRG1_PRU0_GPO17 PADCONFIG: PADCONFIG63 0x000F40FC PRG1_PRU0_GPO17 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV2 Yes LVCMOS PU/PD PRG1_PRU0_GPI17 1 I 0 PRG1_IEP0_EDC_SYNC_OUT1 2 O PRG1_PWM0_B2 3 IO 1 CPTS0_TS_SYNC 4 O TIMER_IO7 6 IO 0 GPIO0_62 7 IO pad GPMC0_A0 8 OZ V7 Y4 PRG1_PRU0_GPO18 PADCONFIG: PADCONFIG64 0x000F4100 PRG1_PRU0_GPO18 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV2 Yes LVCMOS PU/PD PRG1_PRU0_GPI18 1 I 0 PRG1_IEP0_EDC_LATCH_IN0 2 I 0 PRG1_PWM0_TZ_IN 3 I 0 CPTS0_HW1TSPUSH 4 I 0 TIMER_IO8 6 IO 0 GPIO0_63 7 IO pad GPMC0_A1 8 OZ W7 U3 PRG1_PRU0_GPO19 PADCONFIG: PADCONFIG65 0x000F4104 PRG1_PRU0_GPO19 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV2 Yes LVCMOS PU/PD PRG1_PRU0_GPI19 1 I 0 PRG1_IEP0_EDC_SYNC_OUT0 2 O PRG1_PWM0_TZ_OUT 3 O CPTS0_TS_COMP 4 O TIMER_IO9 6 IO 0 GPIO0_64 7 IO pad GPMC0_A2 8 OZ www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 45 Product Folder Links: AM2434 AM2432 AM2431

Table 5-1. Pin Attributes (ALV, ANI, ALX Packages) (continued) ALV ANI BALL NUMBER [1] ALX BALL NUMBER [1] BALL NAME [2] PADCONFIG Register [15] PADCONFIG Address [16] SIGNAL NAME [3] MUX MODE [4] TYPE [5] DSIS [6] BALL STATE DURING RESET RX/TX/PULL [7] BALL STATE AFTER RESET RX/TX/PULL [8] MUX MODE AFTER RESET [9] IO OPERATING VOLTAGE [10] POWER [11] HYS [12] BUFFER TYPE [14] Pull UP/DOWN TYPE [13] W11 AA10 PRG1_PRU1_GPO0 PADCONFIG: PADCONFIG66 0x000F4108 PRG1_PRU1_GPO0 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV2 Yes LVCMOS PU/PD PRG1_PRU1_GPI0 1 I 0 PRG1_RGMII2_RD0 2 I 0 RGMII2_RD0 4 I 0 RMII2_RXD0 5 I 0 GPIO0_65 7 IO pad GPMC0_A3 8 OZ V11 Y10 PRG1_PRU1_GPO1 PADCONFIG: PADCONFIG67 0x000F410C PRG1_PRU1_GPO1 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV2 Yes LVCMOS PU/PD PRG1_PRU1_GPI1 1 I 0 PRG1_RGMII2_RD1 2 I 0 RGMII2_RD1 4 I 0 RMII2_RXD1 5 I 0 GPIO0_66 7 IO pad GPMC0_A4 8 OZ AA12 Y11 PRG1_PRU1_GPO2 PADCONFIG: PADCONFIG68 0x000F4110 PRG1_PRU1_GPO2 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV2 Yes LVCMOS PU/PD PRG1_PRU1_GPI2 1 I 0 PRG1_RGMII2_RD2 2 I 0 PRG1_PWM2_A2 3 IO 0 RGMII2_RD2 4 I 0 GPIO0_67 7 IO pad GPMC0_A5 8 OZ Y12 V12 PRG1_PRU1_GPO3 PADCONFIG: PADCONFIG69 0x000F4114 PRG1_PRU1_GPO3 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV2 Yes LVCMOS PU/PD PRG1_PRU1_GPI3 1 I 0 PRG1_RGMII2_RD3 2 I 0 RGMII2_RD3 4 I 0 GPIO0_68 7 IO pad GPMC0_A6 8 OZ W12 Y12 PRG1_PRU1_GPO4 PADCONFIG: PADCONFIG70 0x000F4118 PRG1_PRU1_GPO4 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV2 Yes LVCMOS PU/PD PRG1_PRU1_GPI4 1 I 0 PRG1_RGMII2_RX_CTL 2 I 0 PRG1_PWM2_B2 3 IO 1 RGMII2_RX_CTL 4 I 0 RMII2_RX_ER 5 I 0 GPIO0_69 7 IO pad GPMC0_A7 8 OZ AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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Table 5-1. Pin Attributes (ALV, ANI, ALX Packages) (continued) ALV ANI BALL NUMBER [1] ALX BALL NUMBER [1] BALL NAME [2] PADCONFIG Register [15] PADCONFIG Address [16] SIGNAL NAME [3] MUX MODE [4] TYPE [5] DSIS [6] BALL STATE DURING RESET RX/TX/PULL [7] BALL STATE AFTER RESET RX/TX/PULL [8] MUX MODE AFTER RESET [9] IO OPERATING VOLTAGE [10] POWER [11] HYS [12] BUFFER TYPE [14] Pull UP/DOWN TYPE [13] AA13 AA11 PRG1_PRU1_GPO5 PADCONFIG: PADCONFIG71 0x000F411C PRG1_PRU1_GPO5 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV2 Yes LVCMOS PU/PD PRG1_PRU1_GPI5 1 I 0 RGMII1_RD0 4 I 0 GPIO0_70 7 IO pad GPMC0_A8 8 OZ U11 V10 PRG1_PRU1_GPO6 PADCONFIG: PADCONFIG72 0x000F4120 PRG1_PRU1_GPO6 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV2 Yes LVCMOS PU/PD PRG1_PRU1_GPI6 1 I 0 PRG1_RGMII2_RXC 2 I 0 RGMII2_RXC 4 I 0 GPIO0_71 7 IO pad GPMC0_A9 8 OZ V15 Y14 PRG1_PRU1_GPO7 PADCONFIG: PADCONFIG73 0x000F4124 PRG1_PRU1_GPO7 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV2 Yes LVCMOS PU/PD PRG1_PRU1_GPI7 1 I 0 PRG1_IEP1_EDC_LATCH_IN1 2 I 0 RGMII1_TD0 4 O RMII1_RXD0 5 I 0 SPI3_CS3 6 IO 1 GPIO0_72 7 IO pad GPMC0_A10 8 OZ U12 W11 PRG1_PRU1_GPO8 PADCONFIG: PADCONFIG74 0x000F4128 PRG1_PRU1_GPO8 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV2 Yes LVCMOS PU/PD PRG1_PRU1_GPI8 1 I 0 PRG1_PWM2_TZ_OUT 3 O RGMII1_RD1 4 I 0 GPIO0_73 7 IO pad GPMC0_A11 8 OZ V14 Y16 PRG1_PRU1_GPO9 PADCONFIG: PADCONFIG75 0x000F412C PRG1_PRU1_GPO9 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV2 Yes LVCMOS PU/PD PRG1_PRU1_GPI9 1 I 0 PRG1_UART0_RXD 2 I 1 RGMII1_TD1 4 O RMII1_RXD1 5 I 0 PRG1_IEP0_EDIO_DATA_IN_OUT30 6 IO 0 GPIO0_74 7 IO pad GPMC0_A12 8 OZ www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 47 Product Folder Links: AM2434 AM2432 AM2431

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Table 5-1. Pin Attributes (ALV, ANI, ALX Packages) (continued) ALV ANI BALL NUMBER [1] ALX BALL NUMBER [1] BALL NAME [2] PADCONFIG Register [15] PADCONFIG Address [16] SIGNAL NAME [3] MUX MODE [4] TYPE [5] DSIS [6] BALL STATE DURING RESET RX/TX/PULL [7] BALL STATE AFTER RESET RX/TX/PULL [8] MUX MODE AFTER RESET [9] IO OPERATING VOLTAGE [10] POWER [11] HYS [12] BUFFER TYPE [14] Pull UP/DOWN TYPE [13] AA11 W9 PRG1_PRU1_GPO14 PADCONFIG: PADCONFIG80 0x000F4140 PRG1_PRU1_GPO14 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV2 Yes LVCMOS PU/PD PRG1_PRU1_GPI14 1 I 0 PRG1_RGMII2_TD3 2 O PRG1_PWM1_A1 3 IO 0 RGMII2_TD3 4 O GPIO0_79 7 IO pad GPMC0_A17 8 OZ Y11 V9 PRG1_PRU1_GPO15 PADCONFIG: PADCONFIG81 0x000F4144 PRG1_PRU1_GPO15 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV2 Yes LVCMOS PU/PD PRG1_PRU1_GPI15 1 I 0 PRG1_RGMII2_TX_CTL 2 O PRG1_PWM1_B1 3 IO 1 RGMII2_TX_CTL 4 O RMII2_TX_EN 5 O GPIO0_80 7 IO pad GPMC0_A18 8 OZ Y10 Y8 PRG1_PRU1_GPO16 PADCONFIG: PADCONFIG82 0x000F4148 PRG1_PRU1_GPO16 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV2 Yes LVCMOS PU/PD PRG1_PRU1_GPI16 1 I 0 PRG1_RGMII2_TXC 2 IO 0 PRG1_PWM1_A2 3 IO 0 RGMII2_TXC 4 IO 0 GPIO0_81 7 IO pad GPMC0_A19 8 OZ AA14 AA14 PRG1_PRU1_GPO17 PADCONFIG: PADCONFIG83 0x000F414C PRG1_PRU1_GPO17 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV2 Yes LVCMOS PU/PD PRG1_PRU1_GPI17 1 I 0 PRG1_IEP1_EDC_SYNC_OUT1 2 O PRG1_PWM1_B2 3 IO 1 RGMII1_TD3 4 O RMII1_TXD1 5 O GPIO0_19 7 IO pad GPMC0_BE3n 8 O PRG1_ECAP0_SYNC_OUT 9 O www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 49 Product Folder Links: AM2434 AM2432 AM2431

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Table 5-1. Pin Attributes (ALV, ANI, ALX Packages) (continued) ALV ANI BALL NUMBER [1] ALX BALL NUMBER [1] BALL NAME [2] PADCONFIG Register [15] PADCONFIG Address [16] SIGNAL NAME [3] MUX MODE [4] TYPE [5] DSIS [6] BALL STATE DURING RESET RX/TX/PULL [7] BALL STATE AFTER RESET RX/TX/PULL [8] MUX MODE AFTER RESET [9] IO OPERATING VOLTAGE [10] POWER [11] HYS [12] BUFFER TYPE [14] Pull UP/DOWN TYPE [13] W16 SERDES0_REFCLK0N SERDES0_REFCLK0N IO 1.8V VDDA_1P8_SERDES SERDES W17 SERDES0_REFCLK0P SERDES0_REFCLK0P IO 1.8V VDDA_1P8_SERDES SERDES Y15 SERDES0_RX0_N SERDES0_RX0_N I 1.8V VDDA_1P8_SERDES SERDES Y16 SERDES0_RX0_P SERDES0_RX0_P I 1.8V VDDA_1P8_SERDES SERDES AA16 SERDES0_TX0_N SERDES0_TX0_N O 1.8V VDDA_1P8_SERDES SERDES AA17 SERDES0_TX0_P SERDES0_TX0_P O 1.8V VDDA_1P8_SERDES SERDES D13 B8 SPI0_CLK PADCONFIG: PADCONFIG132 0x000F4210 SPI0_CLK 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV0 Yes LVCMOS PU/PD GPIO1_44 7 IO pad C14 SPI1_CLK PADCONFIG: PADCONFIG137 0x000F4224 SPI1_CLK 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV0 Yes LVCMOS PU/PD EHRPWM6_SYNCI 3 I 0 GPIO1_49 7 IO pad D12 SPI0_CS0 PADCONFIG: PADCONFIG130 0x000F4208 SPI0_CS0 0 IO 1 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV0 Yes LVCMOS PU/PD GPIO1_42 7 IO pad C13 B7 SPI0_CS1 PADCONFIG: PADCONFIG131 0x000F420C SPI0_CS1 0 IO 1 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV0 Yes LVCMOS PU/PD CPTS0_TS_COMP 1 O I2C2_SCL 2 IOD 1 TIMER_IO10 3 IO 0 PRG0_IEP0_EDIO_OUTVALID 4 O UART6_RXD 5 I 1 ADC_EXT_TRIGGER0 6 I 0 GPIO1_43 7 IO pad A13 A8 SPI0_D0 PADCONFIG: PADCONFIG133 0x000F4214 SPI0_D0 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV0 Yes LVCMOS PU/PD GPIO1_45 7 IO pad A14 C9 SPI0_D1 PADCONFIG: PADCONFIG134 0x000F4218 SPI0_D1 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV0 Yes LVCMOS PU/PD GPIO1_46 7 IO pad www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 51 Product Folder Links: AM2434 AM2432 AM2431

Table 5-1. Pin Attributes (ALV, ANI, ALX Packages) (continued) ALV ANI BALL NUMBER [1] ALX BALL NUMBER [1] BALL NAME [2] PADCONFIG Register [15] PADCONFIG Address [16] SIGNAL NAME [3] MUX MODE [4] TYPE [5] DSIS [6] BALL STATE DURING RESET RX/TX/PULL [7] BALL STATE AFTER RESET RX/TX/PULL [8] MUX MODE AFTER RESET [9] IO OPERATING VOLTAGE [10] POWER [11] HYS [12] BUFFER TYPE [14] Pull UP/DOWN TYPE [13] B14 SPI1_CS0 PADCONFIG: PADCONFIG135 0x000F421C SPI1_CS0 0 IO 1 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV0 Yes LVCMOS PU/PD EHRPWM6_A 3 IO 0 GPIO1_47 7 IO pad D14 SPI1_CS1 PADCONFIG: PADCONFIG136 0x000F4220 SPI1_CS1 0 IO 1 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV0 Yes LVCMOS PU/PD CPTS0_TS_SYNC 1 O I2C2_SDA 2 IOD 1 PRG1_IEP0_EDIO_OUTVALID 4 O UART6_TXD 5 O ADC_EXT_TRIGGER1 6 I 0 GPIO1_48 7 IO pad TIMER_IO11 8 IO 0 B15 SPI1_D0 PADCONFIG: PADCONFIG138 0x000F4228 SPI1_D0 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV0 Yes LVCMOS PU/PD EHRPWM6_SYNCO 3 O GPIO1_50 7 IO pad A15 SPI1_D1 PADCONFIG: PADCONFIG139 0x000F422C SPI1_D1 0 IO 0 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV0 Yes LVCMOS PU/PD EHRPWM6_B 3 IO 0 GPIO1_51 7 IO pad B11 C6 TCK PADCONFIG: MCU_PADCONFIG26 0x04084068 TCK 0 I On / Off / Up On / Off / Up 0 1.8V / 3.3V VDDSHV_MCU Yes LVCMOS PU/PD C11 A3 TDI PADCONFIG: MCU_PADCONFIG28 0x04084070 TDI 0 I On / Off / Up On / Off / Up 0 1.8V / 3.3V VDDSHV_MCU Yes LVCMOS PU/PD A12 B5 TDO PADCONFIG: MCU_PADCONFIG29 0x04084074 TDO 0 OZ Off / Off / Up Off / SS / Up 0 1.8V / 3.3V VDDSHV_MCU Yes LVCMOS PU/PD C12 B4 TMS PADCONFIG: MCU_PADCONFIG30 0x04084078 TMS 0 I On / Off / Up On / Off / Up 0 1.8V / 3.3V VDDSHV_MCU Yes LVCMOS PU/PD D11 B6 TRSTn PADCONFIG: MCU_PADCONFIG27 0x0408406C TRSTn 0 I On / Off / Down On / Off / Down 0 1.8V / 3.3V VDDSHV_MCU Yes LVCMOS PU/PD AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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Table 5-1. Pin Attributes (ALV, ANI, ALX Packages) (continued) ALV ANI BALL NUMBER [1] ALX BALL NUMBER [1] BALL NAME [2] PADCONFIG Register [15] PADCONFIG Address [16] SIGNAL NAME [3] MUX MODE [4] TYPE [5] DSIS [6] BALL STATE DURING RESET RX/TX/PULL [7] BALL STATE AFTER RESET RX/TX/PULL [8] MUX MODE AFTER RESET [9] IO OPERATING VOLTAGE [10] POWER [11] HYS [12] BUFFER TYPE [14] Pull UP/DOWN TYPE [13] B16 B9 UART0_CTSn PADCONFIG: PADCONFIG142 0x000F4238 UART0_CTSn 0 I 1 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV0 Yes LVCMOS PU/PD SPI0_CS2 1 IO 1 ADC_EXT_TRIGGER0 2 I 0 UART2_RXD 3 I 1 TIMER_IO6 4 IO 0 SPI4_CLK 6 IO 0 GPIO1_54 7 IO pad EQEP0_S 8 IO 0 CP_GEMAC_CPTS0_TS_SYNC 9 O A16 A9 UART0_RTSn PADCONFIG: PADCONFIG143 0x000F423C UART0_RTSn 0 O Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV0 Yes LVCMOS PU/PD SPI0_CS3 1 IO 1 UART2_TXD 3 O TIMER_IO7 4 IO 0 SPI4_D0 6 IO 0 GPIO1_55 7 IO pad EQEP0_I 8 IO 0 D15 B10 UART0_RXD PADCONFIG: PADCONFIG140 0x000F4230 UART0_RXD 0 I 1 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV0 Yes LVCMOS PU/PD SPI2_D0 2 IO 0 GPIO1_52 7 IO pad EQEP0_A 8 I 0 C16 B11 UART0_TXD PADCONFIG: PADCONFIG141 0x000F4234 UART0_TXD 0 O Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV0 Yes LVCMOS PU/PD SPI2_D1 2 IO 0 GPIO1_53 7 IO pad EQEP0_B 8 I 0 D16 C11 UART1_CTSn PADCONFIG: PADCONFIG146 0x000F4248 UART1_CTSn 0 I 1 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV0 Yes LVCMOS PU/PD SPI1_CS2 1 IO 1 ADC_EXT_TRIGGER1 2 I 0 PCIE0_CLKREQn 3 IO 0 UART3_RXD 4 I 1 CP_GEMAC_CPTS0_TS_SYNC 5 O SPI4_D1 6 IO 0 GPIO1_58 7 IO pad EQEP1_S 8 IO 0 www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 53 Product Folder Links: AM2434 AM2432 AM2431

Table 5-1. Pin Attributes (ALV, ANI, ALX Packages) (continued) ALV ANI BALL NUMBER [1] ALX BALL NUMBER [1] BALL NAME [2] PADCONFIG Register [15] PADCONFIG Address [16] SIGNAL NAME [3] MUX MODE [4] TYPE [5] DSIS [6] BALL STATE DURING RESET RX/TX/PULL [7] BALL STATE AFTER RESET RX/TX/PULL [8] MUX MODE AFTER RESET [9] IO OPERATING VOLTAGE [10] POWER [11] HYS [12] BUFFER TYPE [14] Pull UP/DOWN TYPE [13] E16 A11 UART1_RTSn PADCONFIG: PADCONFIG147 0x000F424C UART1_RTSn 0 O Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV0 Yes LVCMOS PU/PD SPI1_CS3 1 IO 1 UART3_TXD 4 O CP_GEMAC_CPTS0_HW2TSPUSH 5 I 0 SPI4_CS0 6 IO 1 GPIO1_59 7 IO pad EQEP1_I 8 IO 0 E15 B12 UART1_RXD PADCONFIG: PADCONFIG144 0x000F4240 UART1_RXD 0 I 1 Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV0 Yes LVCMOS PU/PD SPI2_CS0 2 IO 1 CP_GEMAC_CPTS0_TS_COMP 5 O GPIO1_56 7 IO pad EQEP1_A 8 I 0 E14 A12 UART1_TXD PADCONFIG: PADCONFIG145 0x000F4244 UART1_TXD 0 O Off / Off / Off Off / Off / Off 7 1.8V / 3.3V VDDSHV0 Yes LVCMOS PU/PD SPI2_CLK 2 IO 0 CP_GEMAC_CPTS0_HW1TSPUSH 5 I 0 GPIO1_57 7 IO pad EQEP1_B 8 I 0 AA20 AA17 USB0_DM USB0_DM IO 1.8V / 3.3V VDDA_3P3_USB0, VDDA_1P8_USB0 USB2PHY AA19 AA16 USB0_DP USB0_DP IO 1.8V / 3.3V VDDA_3P3_USB0, VDDA_1P8_USB0 USB2PHY E19 B19 USB0_DRVVBUS PADCONFIG: PADCONFIG170 0x000F42A8 USB0_DRVVBUS 0 O Off / Off / Down Off / Off / Down 7 1.8V / 3.3V VDDSHV0 Yes LVCMOS PU/PD GPIO1_79 7 IO pad U16 Y17 USB0_ID USB0_ID A 1.8V / 3.3V VDDA_3P3_USB0, VDDA_1P8_USB0 USB2PHY U17 W17 USB0_RCALIB USB0_RCALIB A 1.8V / 3.3V VDDA_3P3_USB0, VDDA_1P8_USB0 USB2PHY T14 V18 USB0_VBUS USB0_VBUS A 1.8V / 3.3V VDDA_3P3_USB0, VDDA_1P8_USB0 USB2PHY P12, P13 VDDA_0P85_SERDES0 VDDA_0P85_SERDES0 PWR P11 VDDA_0P85_SERDES0_C VDDA_0P85_SERDES0_C PWR T12 V16 VDDA_0P85_USB0 VDDA_0P85_USB0 PWR R14 VDDA_1P8_SERDES0 VDDA_1P8_SERDES0 PWR R15 U15 VDDA_1P8_USB0 VDDA_1P8_USB0 PWR H15 K15 VDDA_3P3_SDIO VDDA_3P3_SDIO PWR R13 U16 VDDA_3P3_USB0 VDDA_3P3_USB0 PWR J13 G17, H17 VDDA_ADC VDDA_ADC PWR AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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5.3 Signal Descriptions

Many signals are available on multiple pins, according to the software configuration of the pin multiplexing options. The following list describes the column headers: 1. SIGNAL NAME: The name of the signal passing through the pin. Note Signal names and descriptions provided in each Signal Descriptions table, represent the pin multiplexed signal function implemented at the pin and selected via PADCONFIG registers. Some device subsystems provide an additional layer of multiplexing for signal functions that are not described in these tables. For more information on secondary multiplexed signal functions, see the respective peripheral chapter of the device TRM. 2. SIGNAL TYPE: Signal direction and type:

I = Input
O = Output
OD = Output, with open-drain output function
IO = Input, Output, or simultaneously Input and Output
IOD = Input, Output, or simultaneously Input and Output, with open-drain output function
IOZ = Input, Output, or simultaneously Input and Output, with three-state output function
OZ = Output with three-state output function
A = Analog
PWR = Power
GND = Ground
CAP = LDO Capacitor 3. DESCRIPTION: Description of the signal 4. BALL: Ball number associated with signal For more information on the I/O cell configurations, see the Pad Configuration Registers section within the Device Configuration chapter of the device TRM. www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 57 Product Folder Links: AM2434 AM2432 AM2431

5.3.1 AM243x_ALX Package - Unsupported Interfaces and Signals

The following peripherals and signals are not supported by the ALX packaged devices. In some cases, the entire peripheral is not supported due to critical signals not being available on the ALX packaged devices. Table 5-2. AM243x_ALX Package - Unsupported Peripheral Interfaces and Signals Table MAIN DOMAIN MCU DOMAIN PERIPHERAL INSTANCES (1)

DDRSS0
EPWM4
EPWM6
FSI1 TX
FSI4 RX
FSI5 RX
GPMC0
I2C2
MMC0
SERDES0
MCSPI1
MCU_I2C0
MCU_I2C1
MCU_MCSPI0
MCU_MCSPI1
MCU_UART1 GPIO SIGNALS
GPIO0_[7:10]
GPIO0_[13:14]
GPIO0_[31:35]
GPIO0_[37:44]
GPIO1_42
GPIO1_[47:51]
GPIO1_68
GPIO1_70
MCU_GPIO[4:21] MISCELLANEOUS SIGNALS
CPTS0_RFT_CLK
SYNC0_OUT
ECAP0_IN_APWM_OUT
TRC_DATA[14:23]
EHRPWM_TZn_IN[5:3]
EHRPWM5_B
SPI0_CS0
SPI4_CS3
OSPI0_ECC_FAIL
OSPI0_CSn[2:3]
OSPI0_D[4:7]
OSPI0_RESET_OUT[0:1]
PRG1_IEP0_EDIO_OUTVALID
EXTINTn
MCU_EXT_REFCLK0
MCU_SYSCLKOUT0
VMON_1P8_MCU
MCU_TIMER_IO[2:3] (1) The entire peripheral instance is not supported for the ALX packaged devices. AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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5.3.2 ADC

Table 5-3. ADC0 Signal Descriptions SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] ADC0_REFN (5) (7) A ADC0 Negative Reference J16 ADC0_REFP (5) (6) A ADC0 Positive Reference J15 ADC0_AIN0 (2) (3) (4) A ADC Analog Input 0 / GPIO1_80 (Input Only) G20 H21 ADC0_AIN1 (2) (3) (4) A ADC Analog Input 1 / GPIO1_81 (Input Only) F20 F19 ADC0_AIN2 (2) (3) (4) A ADC Analog Input 2 / GPIO1_82 (Input Only) E21 F21 ADC0_AIN3 (2) (3) (4) A ADC Analog Input 3 / GPIO1_83 (Input Only) D20 F20 ADC0_AIN4 (2) (3) (4) A ADC Analog Input 4 / GPIO1_84 (Input Only) G21 H20 ADC0_AIN5 (2) (3) (4) A ADC Analog Input 5 / GPIO1_85 (Input Only) F21 E21 ADC0_AIN6 (2) (3) (4) A ADC Analog Input 6 / GPIO1_86 (Input Only) F19 G20 ADC0_AIN7 (2) (3) (4) A ADC Analog Input 7 / GPIO1_87 (Input Only) E20 E20 ADC_EXT_TRIGGER0 (1) I ADC Trigger Input B16, C13 B7, B9 ADC_EXT_TRIGGER1 (1) I ADC Trigger Input D14, D16 C11 (1) This ADC Trigger input signal has a debounce function. For more information on I/O Debounce configuration, see the TRM Device Configuration chapter. (2) The General Purpose Input signal associated with this ADC0_AIN input has a debounce function when ADC0 is configured to operate in GPI mode. For more information on configuring ADC0 to operate in GPI mode, see the TRM Analog-to-Digital Converter (ADC) section in the Peripherals chapter. For more information on I/O Debounce configuration, see the TRM Device Configuration chapter. (3) The ADC0_AIN[7:0] inputs only have hysterisis when ADC0 is configured to operate in GPI mode. (4) Any unused ADC0_AIN inputs must be pulled to VSS through a resistor or connected directly to VSS when VDDA_ADC is connected to a power source. (5) The ADC0_REFP and ADC0_REFN reference inputs are analog inputs which must be treated like high transient power supply rails, where ADC0_REFN is expected to be connected directly to the PCB ground plane along with all other VSS pins, and ADC0_REFP is connected to a power source capable of providing at least 4mA of current. ADC0_REFP may be connected to the same power source as VDDA_ADC0 if the voltage tolerance of the supply provides an acceptable accuracy for the ADC reference. A high frequency decoupling capacitor must be connected directly between ADC0_REFP and ADC0_REFN. The high frequency decoupling capacitor should be placed in the ball array on the back side of the PCB and connected directly to the ADC0_REFP and ADC0_REFN pins with vias. ADC0_REFP may be connected to VSS if ADC0 is not used and VDDA_ADC0 has been connected to VSS. The high frequency decoupling capacitor described above will not be required if ADC0 is not used and ADC0_REFP is connected to VSS. See the Pin Connectivity Requirements section for more information on ADC0 connectivity. (6) ADC0_REFP is connected to VDDA_ADC0 inside the ALX packaged devices. (7) ADC0_REFN is connected to VSS inside the ALX packaged devices.

5.3.3 CPSW

Table 5-4. CPSW3G0 RGMII1 Signal Descriptions SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] RGMII1_RXC I RGMII Receive Clock AA5, W13 U1, Y13 RGMII1_RX_CTL I RGMII Receive Control V13, W6 U14, Y3 RGMII1_TXC IO RGMII Transmit Clock U14 W13 RGMII1_TX_CTL O RGMII Transmit Control U15 W16 RGMII1_RD0 I RGMII Receive Data 0 AA13, W5 AA11, T5 RGMII1_RD1 I RGMII Receive Data 1 U12, Y5 R2, W11 RGMII1_RD2 I RGMII Receive Data 2 V6, Y13 U2, Y15 RGMII1_RD3 I RGMII Receive Data 3 V12, V5 AA13, T1 RGMII1_TD0 O RGMII Transmit Data 0 V15 Y14 RGMII1_TD1 O RGMII Transmit Data 1 V14 Y16 RGMII1_TD2 O RGMII Transmit Data 2 W14 U13 RGMII1_TD3 O RGMII Transmit Data 3 AA14 AA14 www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 59 Product Folder Links: AM2434 AM2432 AM2431

Table 5-5. CPSW3G0 RGMII2 Signal Descriptions SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] RGMII2_RXC I RGMII Receive Clock U11 V10 RGMII2_RX_CTL I RGMII Receive Control W12 Y12 RGMII2_TXC IO RGMII Transmit Clock Y10 Y8 RGMII2_TX_CTL O RGMII Transmit Control Y11 V9 RGMII2_RD0 I RGMII Receive Data 0 W11 AA10 RGMII2_RD1 I RGMII Receive Data 1 V11 Y10 RGMII2_RD2 I RGMII Receive Data 2 AA12 Y11 RGMII2_RD3 I RGMII Receive Data 3 Y12 V12 RGMII2_TD0 O RGMII Transmit Data 0 AA10 Y6 RGMII2_TD1 O RGMII Transmit Data 1 V10 AA8 RGMII2_TD2 O RGMII Transmit Data 2 U10 Y9 RGMII2_TD3 O RGMII Transmit Data 3 AA11 W9 Table 5-6. CPSW3G0 RMII1 and RMII2 Signal Descriptions SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] RMII1_CRS_DV I RMII Carrier Sense / Data Valid R2, V12 AA13, F3 RMII1_RX_ER I RMII Receive Data Error U15, W6 W16, Y3 RMII1_TX_EN O RMII Transmit Enable P5, Y13 D1, Y15 RMII2_CRS_DV I RMII Carrier Sense / Data Valid U10 Y9 RMII2_RX_ER I RMII Receive Data Error W12 Y12 RMII2_TX_EN O RMII Transmit Enable Y11 V9 RMII1_RXD0 I RMII Receive Data 0 V15, W5 T5, Y14 RMII1_RXD1 I RMII Receive Data 1 V14, Y5 R2, Y16 RMII1_TXD0 O RMII Transmit Data 0 V6, W14 U13, U2 RMII1_TXD1 O RMII Transmit Data 1 AA14, V5 AA14, T1 RMII2_RXD0 I RMII Receive Data 0 W11 AA10 RMII2_RXD1 I RMII Receive Data 1 V11 Y10 RMII2_TXD0 O RMII Transmit Data 0 AA10 Y6 RMII2_TXD1 O RMII Transmit Data 1 V10 AA8 RMII_REF_CLK (1) I RMII Reference Clock AA5, U14 U1, W13 (1) RMII_REF_CLK is common to both RMII1 and RMII2. Table 5-7. MDIO0 Signal Descriptions SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] MDIO0_MDC O MDIO Clock R2, Y6 F3, W1 MDIO0_MDIO IO MDIO Data AA6, P5 D1, V2 AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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5.3.3.1 CPSW3G IOSETs

Table 5-8 defines valid pin combinations of each CPSW3G MDIO0 IOSET. Table 5-8. CPSW3G MDIO0 IOSETs SIGNALS IOSET1 IOSET2 BALL NAME MUXMODE BALL NAME MUXMODE MDIO0_MDIO PRG0_PRU1_GPO18 4 PRG1_MDIO0_MDIO 4 MDIO0_MDC PRG0_PRU1_GPO19 4 PRG1_MDIO0_MDC 4 Table 5-9 defines valid pin combinations of each CPSW3G RMII1 and RMII2 IOSET. Table 5-9. CPSW3G RMII1 and RMII2 IOSETs SIGNALS IOSET1 IOSET2 BALL NAME MUXMODE BALL NAME MUXMODE RMII_REF_CLK(1) PRG1_PRU0_GPO10 5 PRG0_PRU0_GPO10 5 RMII1_CRS_DV PRG1_PRU1_GPO19 5 PRG0_PRU1_GPO19 5 RMII1_RX_ER PRG1_PRU0_GPO9 5 PRG0_PRU0_GPO9 5 RMII1_RXD0 PRG1_PRU1_GPO7 5 PRG0_PRU1_GPO7 5 RMII1_RXD1 PRG1_PRU1_GPO9 5 PRG0_PRU1_GPO9 5 RMII1_TXD0 PRG1_PRU1_GPO10 5 PRG0_PRU1_GPO10 5 RMII1_TXD1 PRG1_PRU1_GPO17 5 PRG0_PRU1_GPO17 5 RMII1_TX_EN PRG1_PRU1_GPO18 5 PRG0_PRU1_GPO18 5 RMII2_CRS_DV PRG1_PRU1_GPO13 5 PRG1_PRU1_GPO13 5 RMII2_RX_ER PRG1_PRU1_GPO4 5 PRG1_PRU1_GPO4 5 RMII2_RXD0 PRG1_PRU1_GPO0 5 PRG1_PRU1_GPO0 5 RMII2_RXD1 PRG1_PRU1_GPO1 5 PRG1_PRU1_GPO1 5 RMII2_TXD0 PRG1_PRU1_GPO11 5 PRG1_PRU1_GPO11 5 RMII2_TXD1 PRG1_PRU1_GPO12 5 PRG1_PRU1_GPO12 5 RMII2_TX_EN PRG1_PRU1_GPO15 5 PRG1_PRU1_GPO15 5 (1) RMII_REF_CLK is common to both RMII1 and RMII2. For proper operation, all pin multiplexed signal assignments must use the same IOSET. Table 5-10 defines valid pin combinations of each CPSW3G RGMII1 IOSET. Table 5-10. CPSW3G RGMII1 IOSETs SIGNALS IOSET1 IOSET2 BALL NAME MUXMODE BALL NAME MUXMODE RGMII1_TX_CTL PRG1_PRU0_GPO9 4 PRG1_PRU0_GPO9 4 RGMII1_TXC PRG1_PRU0_GPO10 4 PRG1_PRU0_GPO10 4 RGMII1_TD0 PRG1_PRU1_GPO7 4 PRG1_PRU1_GPO7 4 RGMII1_TD1 PRG1_PRU1_GPO9 4 PRG1_PRU1_GPO9 4 RGMII1_TD2 PRG1_PRU1_GPO10 4 PRG1_PRU1_GPO10 4 RGMII1_TD3 PRG1_PRU1_GPO17 4 PRG1_PRU1_GPO17 4 RGMII1_RX_CTL PRG0_PRU0_GPO9 4 PRG1_PRU0_GPO5 4 RGMII1_RXC PRG0_PRU0_GPO10 4 PRG1_PRU0_GPO8 4 RGMII1_RD0 PRG0_PRU1_GPO7 4 PRG1_PRU1_GPO5 4 RGMII1_RD1 PRG0_PRU1_GPO9 4 PRG1_PRU1_GPO8 4 RGMII1_RD2 PRG0_PRU1_GPO10 4 PRG1_PRU1_GPO18 4 RGMII1_RD3 PRG0_PRU1_GPO17 4 PRG1_PRU1_GPO19 4 www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 61 Product Folder Links: AM2434 AM2432 AM2431

5.3.4 CPTS

Table 5-11. CP GEMAC CPTS0 Signal Descriptions SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] CP_GEMAC_CPTS0_RFT_CLK (1) I CPTS Reference Clock Input to CPSW3G0 CPTS D18 CP_GEMAC_CPTS0_TS_COMP O CPTS Time Stamp Counter Compare Output from CPSW3G0 CPTS E15, K18, W1 B12, G2, K18 CP_GEMAC_CPTS0_TS_SYNC O CPTS Time Stamp Counter Bit Output from CPSW3G0 CPTS B16, D16, K19, U1 B9, C11, E1, K20 CP_GEMAC_CPTS0_HW1TSPUSH I CPTS Hardware Time Stamp Push Input to CPSW3G0 CPTS E14, L21, V1 A12, J19, K4 CP_GEMAC_CPTS0_HW2TSPUSH I CPTS Hardware Time Stamp Push Input to CPSW3G0 CPTS E16, K21, T1 A11, E2, J18 (1) The CP_GEMAC_CPTS0_RFT_CLK signal is not supported by the ALX packaged device. See AM243x_ALX Package - Unsupported Interfaces and Signals for additional details. Table 5-12. CPTS0 Signal Descriptions SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] CPTS0_RFT_CLK (2) I CPTS Reference Clock Input D18 CPTS0_TS_COMP O CPTS Time Stamp Counter Compare Output C13, W1, W7 B7, G2, U3 CPTS0_TS_SYNC O CPTS Time Stamp Counter Bit Output D14, U1, U7 E1, T2 CPTS0_HW1TSPUSH I CPTS Hardware Time Stamp Push Input to Time Sync Router C18, V1, V7 A17, K4, Y4 CPTS0_HW2TSPUSH I CPTS Hardware Time Stamp Push Input to Time Sync Router B19, T1, U13 B18, E2, V13 SYNC0_OUT (1) O CPTS Time Stamp Generator Bit 0 Output from Time Sync Router D18 SYNC1_OUT O CPTS Time Stamp Generator Bit 1 Output from Time Sync Router A19 A18 SYNC2_OUT O CPTS Time Stamp Generator Bit 2 Output from Time Sync Router A17 B13 SYNC3_OUT O CPTS Time Stamp Generator Bit 3 Output from Time Sync Router B17 A14 (1) The SYNC0_OUT signal is not supported by the ALX packaged device. See AM243x_ALX Package - Unsupported Interfaces and Signals for additional details. (2) The CPTS0_RFT_CLK signal is not supported by the ALX packaged device. See AM243x_ALX Package - Unsupported Interfaces and Signals for additional details.

5.3.5 DDRSS

Table 5-13. DDRSS0 Signal Descriptions SIGNAL NAME [1] ((2)) SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] DDR0_ACT_n O DDRSS Activation Command H2 DDR0_ALERT_n IO DDRSS Alert H1 DDR0_CAS_n O DDRSS Column Address Strobe J5 DDR0_PAR O DDRSS Command and Address Parity K5 DDR0_RAS_n O DDRSS Row Address Strobe F6 DDR0_WE_n O DDRSS Write Enable H4 DDR0_A0 O DDRSS Address Bus D2 DDR0_A1 O DDRSS Address Bus C5 DDR0_A2 O DDRSS Address Bus E2 DDR0_A3 O DDRSS Address Bus D4 DDR0_A4 O DDRSS Address Bus D3 DDR0_A5 O DDRSS Address Bus F2 DDR0_A6 O DDRSS Address Bus J2 DDR0_A7 O DDRSS Address Bus L5 AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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Table 5-13. DDRSS0 Signal Descriptions (continued) SIGNAL NAME [1] ((2)) SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] DDR0_A8 O DDRSS Address Bus J3 DDR0_A9 O DDRSS Address Bus J4 DDR0_A10 O DDRSS Address Bus K3 DDR0_A11 O DDRSS Address Bus J1 DDR0_A12 O DDRSS Address Bus M5 DDR0_A13 O DDRSS Address Bus K4 DDR0_BA0 O DDRSS Bank Address G4 DDR0_BA1 O DDRSS Bank Address G5 DDR0_BG0 O DDRSS Bank Group G2 DDR0_BG1 O DDRSS Bank Group H3 DDR0_CAL0 (1) A IO Pad Calibration Resistor H5 DDR0_CK0 O DDRSS Clock F1 DDR0_CK0_n O DDRSS Negative Clock E1 DDR0_CKE0 O DDRSS Clock Enable F4 DDR0_CKE1 O DDRSS Clock Enable F3 DDR0_CS0_n O DDRSS Chip Select 0 E3 DDR0_CS1_n O DDRSS Chip Select 1 E4 DDR0_DM0 IO DDRSS Data Mask B2 DDR0_DM1 IO DDRSS Data Mask M2 DDR0_DQ0 IO DDRSS Data A3 DDR0_DQ1 IO DDRSS Data A2 DDR0_DQ2 IO DDRSS Data B5 DDR0_DQ3 IO DDRSS Data A4 DDR0_DQ4 IO DDRSS Data B3 DDR0_DQ5 IO DDRSS Data C4 DDR0_DQ6 IO DDRSS Data C2 DDR0_DQ7 IO DDRSS Data B4 DDR0_DQ8 IO DDRSS Data N5 DDR0_DQ9 IO DDRSS Data L4 DDR0_DQ10 IO DDRSS Data L2 DDR0_DQ11 IO DDRSS Data M3 DDR0_DQ12 IO DDRSS Data N4 DDR0_DQ13 IO DDRSS Data N3 DDR0_DQ14 IO DDRSS Data M4 DDR0_DQ15 IO DDRSS Data N2 DDR0_DQS0 IO DDRSS Data Strobe 0 C1 DDR0_DQS0_n IO DDRSS Complimentary Data Strobe 0 B1 DDR0_DQS1 IO DDRSS Data Strobe 1 N1 DDR0_DQS1_n IO DDRSS Complimentary Data Strobe 1 M1 DDR0_ODT0 O DDRSS On-Die Termination for Chip Select 0 E5 DDR0_ODT1 O DDRSS On-Die Termination for Chip Select 1 F5 DDR0_RESET0_n O DDRSS Reset D5 (1) An external 240Ω ±1% resistor must be connected between this pin and VSS. The maximum power dissipation for the resistor is 5.2mW. No external voltage should be applied to this pin. (2) The DDRSS0 interface is not supported by the ALX packaged devices. See AM243x_ALX Package - Unsupported Interfaces and Signals for additional details. www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 63 Product Folder Links: AM2434 AM2432 AM2431

5.3.6 ECAP

Table 5-14. ECAP0 Signal Descriptions SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] ECAP0_IN_APWM_OUT (1) IO Enhanced Capture (ECAP) Input or Auxiliary PWM (APWM) Output D18 (1) The ECAP0_IN_APWM_OUT signal is not supported by the ALX packaged device. See AM243x_ALX Package - Unsupported Interfaces and Signals for additional details. Table 5-15. ECAP1 Signal Descriptions SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] ECAP1_IN_APWM_OUT IO Enhanced Capture (ECAP) Input or Auxiliary PWM (APWM) Output C17 B14 Table 5-16. ECAP2 Signal Descriptions SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] ECAP2_IN_APWM_OUT IO Enhanced Capture (ECAP) Input or Auxiliary PWM (APWM) Output D17 A15

5.3.7 Emulation and Debug

Table 5-17. Trace Signal Descriptions SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] TRC_CLK O Trace Clock T20 R21 TRC_CTL O Trace Control U21 R20 TRC_DATA0 O Trace Data 0 T18 T19 TRC_DATA1 O Trace Data 1 U20 V21 TRC_DATA2 O Trace Data 2 U18 U21 TRC_DATA3 O Trace Data 3 U19 T20 TRC_DATA4 O Trace Data 4 V20 T18 TRC_DATA5 O Trace Data 5 V21 U19 TRC_DATA6 O Trace Data 6 V19 U18 TRC_DATA7 O Trace Data 7 T17 U20 TRC_DATA8 O Trace Data 8 R16 V20 TRC_DATA9 O Trace Data 9 W20 W20 TRC_DATA10 O Trace Data 10 W21 Y20 TRC_DATA11 O Trace Data 11 V18 Y19 TRC_DATA12 O Trace Data 12 Y21 Y18 TRC_DATA13 O Trace Data 13 Y20 AA19 TRC_DATA14 (1) O Trace Data 14 R17 TRC_DATA15 (1) O Trace Data 15 P16 TRC_DATA16 (1) O Trace Data 16 R18 TRC_DATA17 (1) O Trace Data 17 T21 TRC_DATA18 (1) O Trace Data 18 P17 TRC_DATA19 (1) O Trace Data 19 T19 P21 TRC_DATA20 (1) O Trace Data 20 W19 TRC_DATA21 (1) O Trace Data 21 Y18 TRC_DATA22 (1) O Trace Data 22 N16 AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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Table 5-17. Trace Signal Descriptions (continued) SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] TRC_DATA23 (1) O Trace Data 23 R19 (1) This TRC_DATA signal is not supported by the ALX packaged device. See AM243x_ALX Package - Unsupported Interfaces and Signals for additional details. MCU Domain Instances Table 5-18. JTAG Signal Descriptions SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] EMU0 IO Emulation Control 0 D10 C5 EMU1 IO Emulation Control 1 E10 B3 TCK I JTAG Test Clock Input B11 C6 TDI I JTAG Test Data Input C11 A3 TDO OZ JTAG Test Data Output A12 B5 TMS I JTAG Test Mode Select Input C12 B4 TRSTn I JTAG Reset D11 B6

5.3.8 EPWM

Table 5-19. EPWM Signal Descriptions SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] EHRPWM_SOCA O EPWM Start of Conversion A C17 B14 EHRPWM_SOCB O EPWM Start of Conversion B D17 A15 EHRPWM_TZn_IN0 I EPWM Trip Zone Input 0 (active low) T18 T19 EHRPWM_TZn_IN1 I EPWM Trip Zone Input 1 (active low) V21 U19 EHRPWM_TZn_IN2 I EPWM Trip Zone Input 2 (active low) R16, R20 V20 EHRPWM_TZn_IN3 (1) I EPWM Trip Zone Input 3 (active low) P16 EHRPWM_TZn_IN4 (2) I EPWM Trip Zone Input 4 (active low) P17, P19 EHRPWM_TZn_IN5 (3) I EPWM Trip Zone Input 5 (active low) R21, Y18 (1) The EHRPWM_TZn_IN3 signal is not supported by the ALX packaged device. See AM243x_ALX Package - Unsupported Interfaces and Signals for additional details. (2) The EHRPWM_TZn_IN4 signal is not supported by the ALX packaged device. See AM243x_ALX Package - Unsupported Interfaces and Signals for additional details. (3) The EHRPWM_TZn_IN5 signal is not supported by the ALX packaged device. See AM243x_ALX Package - Unsupported Interfaces and Signals for additional details. Table 5-20. EPWM0 Signal Descriptions SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] EHRPWM0_A IO EPWM Output A U20 V21 EHRPWM0_B IO EPWM Output B U18 U21 EHRPWM0_SYNCI I Sync Input to EPWM module from an external pin T20 R21 EHRPWM0_SYNCO O Sync Output from EPWM module to an external pin U21 R20 Table 5-21. EPWM1 Signal Descriptions SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] EHRPWM1_A IO EPWM Output A U19 T20 EHRPWM1_B IO EPWM Output B V20 T18 www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 65 Product Folder Links: AM2434 AM2432 AM2431

Table 5-22. EPWM2 Signal Descriptions SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] EHRPWM2_A IO EPWM Output A V19 U18 EHRPWM2_B IO EPWM Output B T17 U20 Table 5-23. EPWM3 Signal Descriptions SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] EHRPWM3_A IO EPWM Output A V18 Y19 EHRPWM3_B IO EPWM Output B Y21 Y18 EHRPWM3_SYNCI I Sync Input to EPWM module from an external pin Y20 AA19 EHRPWM3_SYNCO (1) O Sync Output from EPWM module to an external pin R17 (1) The EHRPWM3_SYNCO signal is not supported by the ALX packaged device. See AM243x_ALX Package - Unsupported Interfaces and Signals for additional details. Table 5-24. EPWM4 Signal Descriptions SIGNAL NAME [1] ((1)) SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] EHRPWM4_A IO EPWM Output A R18 EHRPWM4_B IO EPWM Output B T21 (1) The EPWM4 interface is not supported by the ALX packaged devices. See AM243x_ALX Package - Unsupported Interfaces and Signals for additional details. Table 5-25. EPWM5 Signal Descriptions SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] EHRPWM5_A IO EPWM Output A T19 P21 EHRPWM5_B (1) IO EPWM Output B W19 (1) The EHRPWM5_B signal is not supported by the ALX packaged device. See AM243x_ALX Package - Unsupported Interfaces and Signals for additional details. Table 5-26. EPWM6 Signal Descriptions SIGNAL NAME [1] ((1)) SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] EHRPWM6_A IO EPWM Output A B14, N16 EHRPWM6_B IO EPWM Output B A15, N17 EHRPWM6_SYNCI I Sync Input to EPWM module from an external pin C14, R19 EHRPWM6_SYNCO O Sync Output from EPWM module to an external pin B15, R20 (1) The EPWM6 interface is not supported by the ALX packaged devices. See AM243x_ALX Package - Unsupported Interfaces and Signals for additional details. Table 5-27. EPWM7 Signal Descriptions SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] EHRPWM7_A IO EPWM Output A P17, P5, W20 D1, W20 EHRPWM7_B IO EPWM Output B R2, W21, Y18 F3, Y20 Table 5-28. EPWM8 Signal Descriptions SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] EHRPWM8_A IO EPWM Output A V1, V21 K4, U19 EHRPWM8_B IO EPWM Output B R16, W1 G2, V20 AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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5.3.9 EQEP

Table 5-29. EQEP0 Signal Descriptions SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] EQEP0_A (1) I EQEP Quadrature Input A D15, N16, Y2 B10, L5 EQEP0_B (1) I EQEP Quadrature Input B C16, N17, W2 B11, J2 EQEP0_I (1) IO EQEP Index A16, R20, T6, Y5 A9, R2, T4 EQEP0_S (1) IO EQEP Strobe B16, R19, V3 B9, M2 (1) This EQEP input signal has a debounce function. For more information on I/O Debounce configuration, see the TRM Device Configuration chapter. Table 5-30. EQEP1 Signal Descriptions SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] EQEP1_A (1) I EQEP Quadrature Input A E15, T4, W20 B12, L2, W20 EQEP1_B (1) I EQEP Quadrature Input B E14, W21, W3 A12, L3, Y20 EQEP1_I (1) IO EQEP Index E16, R21, U6, V6 A11, R5, U2 EQEP1_S (1) IO EQEP Strobe D16, P19, P4 C11, E3 (1) This EQEP input signal has a debounce function. For more information on I/O Debounce configuration, see the TRM Device Configuration chapter. Table 5-31. EQEP2 Signal Descriptions SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] EQEP2_A (1) I EQEP Quadrature Input A C17, R5 B14, F5 EQEP2_B (1) I EQEP Quadrature Input B D17, W5, Y4 A15, P2, T5 EQEP2_I (1) IO EQEP Index A17, W4 B13, P1 EQEP2_S (1) IO EQEP Strobe B17, R1 A14, F4 (1) This EQEP input signal has a debounce function. For more information on I/O Debounce configuration, see the TRM Device Configuration chapter.

5.3.10 FSI

Table 5-32. FSI0 RX Signal Descriptions SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] FSI_RX0_CLK I FSI Receiver Clock V19 U18 FSI_RX0_D0 I FSI Receiver Data 0 T17 U20 FSI_RX0_D1 I FSI Receiver Data 1 R16 V20 Table 5-33. FSI0 TX Signal Descriptions SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] FSI_TX0_CLK O FSI Transmitter Clock T19 P21 FSI_TX0_D0 O FSI Transmitter Data 0 Y21 Y18 FSI_TX0_D1 O FSI Transmitter Data 1 Y20 AA19 Table 5-34. FSI1 RX Signal Descriptions SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] FSI_RX1_CLK I FSI Receiver Clock W20 W20 www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 67 Product Folder Links: AM2434 AM2432 AM2431

Table 5-34. FSI1 RX Signal Descriptions (continued) SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] FSI_RX1_D0 I FSI Receiver Data 0 W21 Y20 FSI_RX1_D1 I FSI Receiver Data 1 V18 Y19 Table 5-35. FSI1 TX Signal Descriptions SIGNAL NAME [1] ((1)) SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] FSI_TX1_CLK O FSI Transmitter Clock N16 FSI_TX1_D0 O FSI Transmitter Data 0 P17 FSI_TX1_D1 O FSI Transmitter Data 1 Y18 (1) The FSI1 TX interface is not supported by the ALX packaged devices. See AM243x_ALX Package - Unsupported Interfaces and Signals for additional details. Table 5-36. FSI2 RX Signal Descriptions SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] FSI_RX2_CLK I FSI Receiver Clock T20 R21 FSI_RX2_D0 I FSI Receiver Data 0 U21 R20 FSI_RX2_D1 I FSI Receiver Data 1 T18 T19 Table 5-37. FSI3 RX Signal Descriptions SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] FSI_RX3_CLK I FSI Receiver Clock U20 V21 FSI_RX3_D0 I FSI Receiver Data 0 U18 U21 FSI_RX3_D1 I FSI Receiver Data 1 U19 T20 Table 5-38. FSI4 RX Signal Descriptions SIGNAL NAME [1] ((1)) SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] FSI_RX4_CLK I FSI Receiver Clock R17 FSI_RX4_D0 I FSI Receiver Data 0 V20 T18 FSI_RX4_D1 I FSI Receiver Data 1 V21 U19 (1) The FSI4 RX interface is not supported by the ALX packaged devices. See AM243x_ALX Package - Unsupported Interfaces and Signals for additional details. Table 5-39. FSI5 RX Signal Descriptions SIGNAL NAME [1] ((1)) SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] FSI_RX5_CLK I FSI Receiver Clock P16 FSI_RX5_D0 I FSI Receiver Data 0 R18 FSI_RX5_D1 I FSI Receiver Data 1 T21 (1) The FSI5 RX interface is not supported by the ALX packaged devices. See AM243x_ALX Package - Unsupported Interfaces and Signals for additional details.

5.3.11 GPIO

Table 5-40. GPIO0 Signal Descriptions SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] GPIO0_0 IO General Purpose Input/Output N20 P20 AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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Table 5-40. GPIO0 Signal Descriptions (continued) SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] GPIO0_1 IO General Purpose Input/Output N21 M21 GPIO0_2 IO General Purpose Input/Output N19 P17 GPIO0_3 IO General Purpose Input/Output M19 L19 GPIO0_4 IO General Purpose Input/Output M18 N20 GPIO0_5 IO General Purpose Input/Output M20 L21 GPIO0_6 IO General Purpose Input/Output M21 N19 GPIO0_7 (2) IO General Purpose Input/Output P21 GPIO0_8 (2) IO General Purpose Input/Output P20 GPIO0_9 (2) IO General Purpose Input/Output N18 GPIO0_10 (2) IO General Purpose Input/Output M17 GPIO0_11 IO General Purpose Input/Output L19 L20 GPIO0_12 IO General Purpose Input/Output L18 M20 GPIO0_13 (2) IO General Purpose Input/Output K17 GPIO0_14 (2) IO General Purpose Input/Output L17 GPIO0_15 IO General Purpose Input/Output T20 R21 GPIO0_16 IO General Purpose Input/Output U21 R20 GPIO0_17 IO General Purpose Input/Output T18 T19 GPIO0_18 IO General Purpose Input/Output U20 V21 GPIO0_19 IO General Purpose Input/Output AA14 AA14 GPIO0_20 IO General Purpose Input/Output Y13 Y15 GPIO0_21 IO General Purpose Input/Output V20 T18 GPIO0_22 IO General Purpose Input/Output V21 U19 GPIO0_23 IO General Purpose Input/Output V19 U18 GPIO0_24 IO General Purpose Input/Output T17 U20 GPIO0_25 IO General Purpose Input/Output R16 V20 GPIO0_26 IO General Purpose Input/Output W20 W20 GPIO0_27 IO General Purpose Input/Output W21 Y20 GPIO0_28 IO General Purpose Input/Output V18 Y19 GPIO0_29 IO General Purpose Input/Output Y21 Y18 GPIO0_30 IO General Purpose Input/Output Y20 AA19 GPIO0_31 (2) IO General Purpose Input/Output R17 GPIO0_32 (2) IO General Purpose Input/Output P16 GPIO0_33 (2) IO General Purpose Input/Output R18 GPIO0_34 (2) IO General Purpose Input/Output T21 GPIO0_35 (2) IO General Purpose Input/Output P17 GPIO0_36 IO General Purpose Input/Output T19 P21 GPIO0_37 (2) IO General Purpose Input/Output W19 GPIO0_38 (2) IO General Purpose Input/Output Y18 GPIO0_39 (2) IO General Purpose Input/Output N16 GPIO0_40 (2) IO General Purpose Input/Output N17 GPIO0_41 (2) IO General Purpose Input/Output R19 GPIO0_42 (2) IO General Purpose Input/Output R20 GPIO0_43 (1) (2) IO General Purpose Input/Output P19 GPIO0_44 (1) (2) IO General Purpose Input/Output R21 GPIO0_45 IO General Purpose Input/Output Y7 V4 GPIO0_46 IO General Purpose Input/Output U8 W5 GPIO0_47 IO General Purpose Input/Output W8 AA4 GPIO0_48 IO General Purpose Input/Output V8 Y5 GPIO0_49 IO General Purpose Input/Output Y8 AA5 www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 69 Product Folder Links: AM2434 AM2432 AM2431

Table 5-40. GPIO0 Signal Descriptions (continued) SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] GPIO0_50 IO General Purpose Input/Output V13 U14 GPIO0_51 IO General Purpose Input/Output AA7 Y2 GPIO0_52 IO General Purpose Input/Output U13 V13 GPIO0_53 IO General Purpose Input/Output W13 Y13 GPIO0_54 IO General Purpose Input/Output U15 W16 GPIO0_55 IO General Purpose Input/Output U14 W13 GPIO0_56 IO General Purpose Input/Output AA8 V5 GPIO0_57 IO General Purpose Input/Output U9 W2 GPIO0_58 IO General Purpose Input/Output W9 V6 GPIO0_59 IO General Purpose Input/Output AA9 AA7 GPIO0_60 IO General Purpose Input/Output Y9 Y7 GPIO0_61 IO General Purpose Input/Output V9 W6 GPIO0_62 IO General Purpose Input/Output U7 T2 GPIO0_63 IO General Purpose Input/Output V7 Y4 GPIO0_64 IO General Purpose Input/Output W7 U3 GPIO0_65 IO General Purpose Input/Output W11 AA10 GPIO0_66 IO General Purpose Input/Output V11 Y10 GPIO0_67 IO General Purpose Input/Output AA12 Y11 GPIO0_68 IO General Purpose Input/Output Y12 V12 GPIO0_69 IO General Purpose Input/Output W12 Y12 GPIO0_70 IO General Purpose Input/Output AA13 AA11 GPIO0_71 IO General Purpose Input/Output U11 V10 GPIO0_72 IO General Purpose Input/Output V15 Y14 GPIO0_73 IO General Purpose Input/Output U12 W11 GPIO0_74 IO General Purpose Input/Output V14 Y16 GPIO0_75 IO General Purpose Input/Output W14 U13 GPIO0_76 IO General Purpose Input/Output AA10 Y6 GPIO0_77 IO General Purpose Input/Output V10 AA8 GPIO0_78 IO General Purpose Input/Output U10 Y9 GPIO0_79 IO General Purpose Input/Output AA11 W9 GPIO0_80 IO General Purpose Input/Output Y11 V9 GPIO0_81 IO General Purpose Input/Output Y10 Y8 GPIO0_82 IO General Purpose Input/Output U18 U21 GPIO0_83 IO General Purpose Input/Output U19 T20 GPIO0_84 IO General Purpose Input/Output V12 AA13 GPIO0_85 IO General Purpose Input/Output AA6 V2 GPIO0_86 IO General Purpose Input/Output Y6 W1 (1) This GPIO input signal has a debounce function. For more information on I/O Debounce configuration, see the TRM Device Configuration chapter. (2) This GPIO0 signal is not supported by the ALX packaged device. See AM243x_ALX Package - Unsupported Interfaces and Signals for additional details. Table 5-41. GPIO1 Signal Descriptions SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] GPIO1_0 IO General Purpose Input/Output Y1 J3 GPIO1_1 IO General Purpose Input/Output R4 J4 GPIO1_2 IO General Purpose Input/Output U2 G1 GPIO1_3 IO General Purpose Input/Output V2 H1 GPIO1_4 IO General Purpose Input/Output AA2 K2 AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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Table 5-41. GPIO1 Signal Descriptions (continued) SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] GPIO1_5 IO General Purpose Input/Output R3 F2 GPIO1_6 IO General Purpose Input/Output T3 H2 GPIO1_7 IO General Purpose Input/Output T1 E2 GPIO1_8 IO General Purpose Input/Output T2 H5 GPIO1_9 IO General Purpose Input/Output W6 Y3 GPIO1_10 IO General Purpose Input/Output AA5 U1 GPIO1_11 IO General Purpose Input/Output Y3 L1 GPIO1_12 IO General Purpose Input/Output AA3 K1 GPIO1_13 IO General Purpose Input/Output R6 N1 GPIO1_14 IO General Purpose Input/Output V4 N2 GPIO1_15 IO General Purpose Input/Output T5 N4 GPIO1_16 IO General Purpose Input/Output U4 N3 GPIO1_17 IO General Purpose Input/Output U1 E1 GPIO1_18 IO General Purpose Input/Output V1 K4 GPIO1_19 IO General Purpose Input/Output W1 G2 GPIO1_20 IO General Purpose Input/Output Y2 L5 GPIO1_21 IO General Purpose Input/Output W2 J2 GPIO1_22 IO General Purpose Input/Output V3 M2 GPIO1_23 IO General Purpose Input/Output T4 L2 GPIO1_24 IO General Purpose Input/Output W3 L3 GPIO1_25 IO General Purpose Input/Output P4 E3 GPIO1_26 IO General Purpose Input/Output R5 F5 GPIO1_27 IO General Purpose Input/Output W5 T5 GPIO1_28 IO General Purpose Input/Output R1 F4 GPIO1_29 IO General Purpose Input/Output Y5 R2 GPIO1_30 IO General Purpose Input/Output V6 U2 GPIO1_31 IO General Purpose Input/Output W4 P1 GPIO1_32 IO General Purpose Input/Output Y4 P2 GPIO1_33 IO General Purpose Input/Output T6 T4 GPIO1_34 IO General Purpose Input/Output U6 R5 GPIO1_35 IO General Purpose Input/Output U5 M4 GPIO1_36 IO General Purpose Input/Output AA4 T3 GPIO1_37 IO General Purpose Input/Output V5 T1 GPIO1_38 IO General Purpose Input/Output P5 D1 GPIO1_39 IO General Purpose Input/Output R2 F3 GPIO1_40 IO General Purpose Input/Output P2 E4 GPIO1_41 IO General Purpose Input/Output P3 D2 GPIO1_42 (2) IO General Purpose Input/Output D12 GPIO1_43 IO General Purpose Input/Output C13 B7 GPIO1_44 IO General Purpose Input/Output D13 B8 GPIO1_45 IO General Purpose Input/Output A13 A8 GPIO1_46 IO General Purpose Input/Output A14 C9 GPIO1_47 (2) IO General Purpose Input/Output B14 GPIO1_48 (2) IO General Purpose Input/Output D14 GPIO1_49 (2) IO General Purpose Input/Output C14 GPIO1_50 (2) IO General Purpose Input/Output B15 GPIO1_51 (2) IO General Purpose Input/Output A15 GPIO1_52 IO General Purpose Input/Output D15 B10 GPIO1_53 IO General Purpose Input/Output C16 B11 www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 71 Product Folder Links: AM2434 AM2432 AM2431

Table 5-41. GPIO1 Signal Descriptions (continued) SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] GPIO1_54 IO General Purpose Input/Output B16 B9 GPIO1_55 IO General Purpose Input/Output A16 A9 GPIO1_56 IO General Purpose Input/Output E15 B12 GPIO1_57 IO General Purpose Input/Output E14 A12 GPIO1_58 IO General Purpose Input/Output D16 C11 GPIO1_59 IO General Purpose Input/Output E16 A11 GPIO1_60 IO General Purpose Input/Output A17 B13 GPIO1_61 IO General Purpose Input/Output B17 A14 GPIO1_62 IO General Purpose Input/Output C17 B14 GPIO1_63 IO General Purpose Input/Output D17 A15 GPIO1_64 IOD General Purpose Input/Output A18 B16 GPIO1_65 IOD General Purpose Input/Output B18 B15 GPIO1_66 IO General Purpose Input/Output C18 A17 GPIO1_67 IO General Purpose Input/Output B19 B18 GPIO1_68 (1) (2) IO General Purpose Input/Output D18 GPIO1_69 IO General Purpose Input/Output A19 A18 GPIO1_70 (1) (2) IOD General Purpose Input/Output C19 GPIO1_71 (1) IO General Purpose Input/Output K18 K18 GPIO1_72 (1) IO General Purpose Input/Output K19 K20 GPIO1_73 (1) IO General Purpose Input/Output L21 J19 GPIO1_74 (1) IO General Purpose Input/Output K21 J18 GPIO1_75 (1) IO General Purpose Input/Output L20 J20 GPIO1_76 (1) IO General Purpose Input/Output J19 J21 GPIO1_77 (1) IO General Purpose Input/Output D19 B17 GPIO1_78 (1) IO General Purpose Input/Output C20 C16 GPIO1_79 IO General Purpose Input/Output E19 B19 (1) This GPIO input signal has a debounce function. For more information on I/O Debounce configuration, see the TRM Device Configuration chapter. (2) This GPIO1 signal is not supported by the ALX packaged device. See AM243x_ALX Package - Unsupported Interfaces and Signals for additional details. MCU Domain Instances Table 5-42. MCU_GPIO0 Signal Descriptions SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] MCU_GPIO0_0 (1) IO General Purpose Input/Output E8 C2 MCU_GPIO0_1 (1) IO General Purpose Input/Output D8 D4 MCU_GPIO0_2 IO General Purpose Input/Output A8 B2 MCU_GPIO0_3 IO General Purpose Input/Output A9 D6 MCU_GPIO0_4 (2) IO General Purpose Input/Output B6 MCU_GPIO0_5 (1) (2) IO General Purpose Input/Output A7 MCU_GPIO0_6 (1) (2) IO General Purpose Input/Output B7 MCU_GPIO0_7 (2) IO General Purpose Input/Output D7 MCU_GPIO0_8 (2) IO General Purpose Input/Output C7 MCU_GPIO0_9 (2) IO General Purpose Input/Output C8 MCU_GPIO0_10 (2) IO General Purpose Input/Output E7 MCU_GPIO0_11 (2) IO General Purpose Input/Output E6 MCU_GPIO0_12 (1) (2) IO General Purpose Input/Output C6 MCU_GPIO0_13 (1) (2) IO General Purpose Input/Output D6 MCU_GPIO0_14 (2) IO General Purpose Input/Output C9 AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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Table 5-42. MCU_GPIO0 Signal Descriptions (continued) SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] MCU_GPIO0_15 (2) IO General Purpose Input/Output D9 MCU_GPIO0_16 (1) (2) IO General Purpose Input/Output B8 MCU_GPIO0_17 (1) (2) IO General Purpose Input/Output B9 MCU_GPIO0_18 (2) IOD General Purpose Input/Output E9 MCU_GPIO0_19 (2) IOD General Purpose Input/Output A10 MCU_GPIO0_20 (1) (2) IO General Purpose Input/Output A11 MCU_GPIO0_21 (1) (2) IO General Purpose Input/Output B10 MCU_GPIO0_22 IO General Purpose Input/Output B13 A6 (1) This GPIO input signal has a debounce function. For more information on I/O Debounce configuration, see the TRM Device Configuration chapter. (2) This MCU_GPIO0 signal is not supported by the ALX packaged device. See AM243x_ALX Package - Unsupported Interfaces and Signals for additional details.

5.3.12 GPMC

Table 5-43. GPMC0 Signal Descriptions SIGNAL NAME [1] ((2)) SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] GPMC0_ADVn_ALE O GPMC Address Valid (active low) or Address Latch Enable P16 GPMC0_CLK O GPMC Clock R17 GPMC0_DIR O GPMC Data Bus Signal Direction Control N17 GPMC0_FCLK_MUX (1) O GPMC functional clock output selected through mux logic R17 GPMC0_OEn_REn O GPMC Output Enable (active low) or Read Enable (active low) R18 GPMC0_WEn O GPMC Write Enable (active low) T21 GPMC0_WPn O GPMC Flash Write Protect (active low) N16 GPMC0_A0 OZ GPMC Address 0 Output. Only used to effectively address 8-bit data non-multiplexed memories U2, U7 G1, T2 GPMC0_A1 OZ GPMC address 1 Output in A/D non-multiplexed mode and Address 17 in A/D multiplexed mode AA2, V7 K2, Y4 GPMC0_A2 OZ GPMC address 2 Output in A/D non-multiplexed mode and Address 18 in A/D multiplexed mode T2, W7 H5, U3 GPMC0_A3 OZ GPMC address 3 Output in A/D non-multiplexed mode and Address 19 in A/D multiplexed mode V4, W11 AA10, N2 GPMC0_A4 OZ GPMC address 4 Output in A/D non-multiplexed mode and Address 20 in A/D multiplexed mode U4, V11 N3, Y10 GPMC0_A5 OZ GPMC address 5 Output in A/D non-multiplexed mode and Address 21 in A/D multiplexed mode AA12, V1 K4, Y11 GPMC0_A6 OZ GPMC address 6 Output in A/D non-multiplexed mode and Address 22 in A/D multiplexed mode W1, Y12 G2, V12 GPMC0_A7 OZ GPMC address 7 Output in A/D non-multiplexed mode and Address 23 in A/D multiplexed mode W12, Y4 P2, Y12 GPMC0_A8 OZ GPMC address 8 Output in A/D non-multiplexed mode and Address 24 in A/D multiplexed mode AA13, T6 AA11, T4 GPMC0_A9 OZ GPMC address 9 Output in A/D non-multiplexed mode and Address 25 in A/D multiplexed mode U11, U6 R5, V10 GPMC0_A10 OZ GPMC address 10 Output in A/D non-multiplexed mode and Address 26 in A/D multiplexed mode U5, V15 M4, Y14 GPMC0_A11 OZ GPMC address 11 Output in A/D non-multiplexed mode and unused in A/D multiplexed mode AA4, U12 T3, W11 GPMC0_A12 OZ GPMC address 12 Output in A/D non-multiplexed mode and unused in A/D multiplexed mode P2, V14 E4, Y16 GPMC0_A13 OZ GPMC address 13 Output in A/D non-multiplexed mode and unused in A/D multiplexed mode P3, W14 D2, U13 GPMC0_A14 OZ GPMC address 14 Output in A/D non-multiplexed mode and unused in A/D multiplexed mode AA10, AA3 K1, Y6 www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 73 Product Folder Links: AM2434 AM2432 AM2431

Table 5-43. GPMC0 Signal Descriptions (continued) SIGNAL NAME [1] ((2)) SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] GPMC0_A15 OZ GPMC address 15 Output in A/D non-multiplexed mode and unused in A/D multiplexed mode R6, V10 AA8, N1 GPMC0_A16 OZ GPMC address 16 Output in A/D non-multiplexed mode and unused in A/D multiplexed mode T5, U10 N4, Y9 GPMC0_A17 OZ GPMC address 17 Output in A/D non-multiplexed mode and unused in A/D multiplexed mode AA11, U1 E1, W9 GPMC0_A18 OZ GPMC address 18 Output in A/D non-multiplexed mode and unused in A/D multiplexed mode T4, Y11 L2, V9 GPMC0_A19 OZ GPMC address 19 Output in A/D non-multiplexed mode and unused in A/D multiplexed mode R5, Y10 F5, Y8 GPMC0_A20 OZ GPMC address 20 Output in A/D non-multiplexed mode and unused in A/D multiplexed mode R21 GPMC0_A21 OZ GPMC address 21 Output in A/D non-multiplexed mode and unused in A/D multiplexed mode Y18 GPMC0_A22 OZ GPMC address 22 Output in A/D non-multiplexed mode and unused in A/D multiplexed mode N16 GPMC0_AD0 IO GPMC Data 0 Input/Output in A/D non-multiplexed mode and additionally Address 1 Output in A/D multiplexed mode T20 R21 GPMC0_AD1 IO GPMC Data 1 Input/Output in A/D non-multiplexed mode and additionally Address 2 Output in A/D multiplexed mode U21 R20 GPMC0_AD2 IO GPMC Data 2 Input/Output in A/D non-multiplexed mode and additionally Address 3 Output in A/D multiplexed mode T18 T19 GPMC0_AD3 IO GPMC Data 3 Input/Output in A/D non-multiplexed mode and additionally Address 4 Output in A/D multiplexed mode U20 V21 GPMC0_AD4 IO GPMC Data 4 Input/Output in A/D non-multiplexed mode and additionally Address 5 Output in A/D multiplexed mode U18 U21 GPMC0_AD5 IO GPMC Data 5 Input/Output in A/D non-multiplexed mode and additionally Address 6 Output in A/D multiplexed mode U19 T20 GPMC0_AD6 IO GPMC Data 6 Input/Output in A/D non-multiplexed mode and additionally Address 7 Output in A/D multiplexed mode V20 T18 GPMC0_AD7 IO GPMC Data 7 Input/Output in A/D non-multiplexed mode and additionally Address 8 Output in A/D multiplexed mode V21 U19 GPMC0_AD8 IO GPMC Data 8 Input/Output in A/D non-multiplexed mode and additionally Address 9 Output in A/D multiplexed mode V19 U18 GPMC0_AD9 IO GPMC Data 9 Input/Output in A/D non-multiplexed mode and additionally Address 10 Output in A/D multiplexed mode T17 U20 GPMC0_AD10 IO GPMC Data 10 Input/Output in A/D non-multiplexed mode and additionally Address 11 Output in A/D multiplexed mode R16 V20 GPMC0_AD11 IO GPMC Data 11 Input/Output in A/D non-multiplexed mode and additionally Address 12 Output in A/D multiplexed mode W20 W20 GPMC0_AD12 IO GPMC Data 12 Input/Output in A/D non-multiplexed mode and additionally Address 13 Output in A/D multiplexed mode W21 Y20 GPMC0_AD13 IO GPMC Data 13 Input/Output in A/D non-multiplexed mode and additionally Address 14 Output in A/D multiplexed mode V18 Y19 GPMC0_AD14 IO GPMC Data 14 Input/Output in A/D non-multiplexed mode and additionally Address 15 Output in A/D multiplexed mode Y21 Y18 GPMC0_AD15 IO GPMC Data 15 Input/Output in A/D non-multiplexed mode and additionally Address 16 Output in A/D multiplexed mode Y20 AA19 GPMC0_AD16 IO GPMC Data 16 Input/Output in A/D non-multiplexed mode and additionally Address 17 Output in A/D multiplexed mode Y7 V4 GPMC0_AD17 IO GPMC Data 17 Input/Output in A/D non-multiplexed mode and additionally Address 18 Output in A/D multiplexed mode U8 W5 GPMC0_AD18 IO GPMC Data 18 Input/Output in A/D non-multiplexed mode and additionally Address 19 Output in A/D multiplexed mode W8 AA4 GPMC0_AD19 IO GPMC Data 19 Input/Output in A/D non-multiplexed mode and additionally Address 20 Output in A/D multiplexed mode V8 Y5 GPMC0_AD20 IO GPMC Data 20 Input/Output in A/D non-multiplexed mode and additionally Address 21 Output in A/D multiplexed mode Y8 AA5 AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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Table 5-43. GPMC0 Signal Descriptions (continued) SIGNAL NAME [1] ((2)) SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] GPMC0_AD21 IO GPMC Data 21 Input/Output in A/D non-multiplexed mode and additionally Address 22 Output in A/D multiplexed mode V13 U14 GPMC0_AD22 IO GPMC Data 22 Input/Output in A/D non-multiplexed mode and additionally Address 23 Output in A/D multiplexed mode AA7 Y2 GPMC0_AD23 IO GPMC Data 23 Input/Output in A/D non-multiplexed mode and additionally Address 24 Output in A/D multiplexed mode U13 V13 GPMC0_AD24 IO GPMC Data 24 Input/Output in A/D non-multiplexed mode and additionally Address 25 Output in A/D multiplexed mode W13 Y13 GPMC0_AD25 IO GPMC Data 25 Input/Output in A/D non-multiplexed mode and additionally Address 26 Output in A/D multiplexed mode U15 W16 GPMC0_AD26 IO GPMC Data 26 Input/Output in A/D non-multiplexed mode and additionally Address 27 Output in A/D multiplexed mode U14 W13 GPMC0_AD27 IO GPMC Data 27 Input/Output in A/D non-multiplexed mode and additionally Address 28 Output in A/D multiplexed mode AA8 V5 GPMC0_AD28 IO GPMC Data 28 Input/Output in A/D non-multiplexed mode and additionally Address 29 Output in A/D multiplexed mode U9 W2 GPMC0_AD29 IO GPMC Data 29 Input/Output in A/D non-multiplexed mode and additionally Address 30 Output in A/D multiplexed mode W9 V6 GPMC0_AD30 IO GPMC Data 30 Input/Output in A/D non-multiplexed mode and additionally Address 31 Output in A/D multiplexed mode AA9 AA7 GPMC0_AD31 IO GPMC Data 31 Input/Output in A/D non-multiplexed mode and additionally Address 0 Output in A/D multiplexed mode Y9 Y7 GPMC0_BE0n_CLE O GPMC Lower-Byte Enable (active low) or Command Latch Enable P17 GPMC0_BE1n O GPMC Upper-Byte Enable (active low) T19 P21 GPMC0_BE2n O GPMC Upper-Byte Enable (active low) V9 W6 GPMC0_BE3n O GPMC Upper-Byte Enable (active low) AA14 AA14 GPMC0_CSn0 O GPMC Chip Select 0 (active low) R19 GPMC0_CSn1 O GPMC Chip Select 1 (active low) R20 GPMC0_CSn2 O GPMC Chip Select 2 (active low) P19 GPMC0_CSn3 O GPMC Chip Select 3 (active low) R21 GPMC0_WAIT0 I GPMC External Indication of Wait W19 GPMC0_WAIT1 I GPMC External Indication of Wait Y18 (1) The GPMC0_FCLK_MUX signal is not supported by the ALX packaged device. See AM243x_ALX Package - Unsupported Interfaces and Signals for additional details. (2) The GPMC0 interface is not supported by the ALX packaged devices. See AM243x_ALX Package - Unsupported Interfaces and Signals for additional details. www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 75 Product Folder Links: AM2434 AM2432 AM2431

5.3.12.1 GPMC0 IOSETs (ALV/ANI)

Table 5-44 defines valid pin combinations of each ALV/ANI package GPMC0 IOSET. Table 5-44. GPMC0 IOSETs (ALV/ANI) SIGNALS IOSET1 IOSET2 BALL NAME (ALV/ANI) MUXMODE BALL NAME (ALV/ANI) MUXMODE GPMC0_AD0 GPMC0_AD0 0 GPMC0_AD0 0 GPMC0_AD1 GPMC0_AD1 0 GPMC0_AD1 0 GPMC0_AD2 GPMC0_AD2 0 GPMC0_AD2 0 GPMC0_AD3 GPMC0_AD3 0 GPMC0_AD3 0 GPMC0_AD4 GPMC0_AD4 0 GPMC0_AD4 0 GPMC0_AD5 GPMC0_AD5 0 GPMC0_AD5 0 GPMC0_AD6 GPMC0_AD6 0 GPMC0_AD6 0 GPMC0_AD7 GPMC0_AD7 0 GPMC0_AD7 0 GPMC0_AD8 GPMC0_AD8 0 GPMC0_AD8 0 GPMC0_AD9 GPMC0_AD9 0 GPMC0_AD9 0 GPMC0_AD10 GPMC0_AD10 0 GPMC0_AD10 0 GPMC0_AD11 GPMC0_AD11 0 GPMC0_AD11 0 GPMC0_AD12 GPMC0_AD12 0 GPMC0_AD12 0 GPMC0_AD13 GPMC0_AD13 0 GPMC0_AD13 0 GPMC0_AD14 GPMC0_AD14 0 GPMC0_AD14 0 GPMC0_AD15 GPMC0_AD15 0 GPMC0_AD15 0 GPMC0_CLK GPMC0_CLK 0 GPMC0_CLK 0 GPMC0_ADVn_ALE GPMC0_ADVn_ALE 0 GPMC0_ADVn_ALE 0 GPMC0_OEn_REn GPMC0_OEn_REn 0 GPMC0_OEn_REn 0 GPMC0_WEn GPMC0_WEn 0 GPMC0_WEn 0 GPMC0_BE0n_CLE GPMC0_BE0n_CLE 0 GPMC0_BE0n_CLE 0 GPMC0_BE1n GPMC0_BE1n 0 GPMC0_BE1n 0 GPMC0_WAIT0 GPMC0_WAIT0 0 GPMC0_WAIT0 0 GPMC0_WAIT1 GPMC0_WAIT1 0 GPMC0_WAIT1 0 GPMC0_WPn GPMC0_WPn 0 GPMC0_WPn 0 GPMC0_DIR GPMC0_DIR 0 GPMC0_DIR 0 GPMC0_CSn0 GPMC0_CSn0 0 GPMC0_CSn0 0 GPMC0_CSn1 GPMC0_CSn1 0 GPMC0_CSn1 0 GPMC0_CSn2 GPMC0_CSn2 0 GPMC0_CSn2 0 GPMC0_CSn3 GPMC0_CSn3 0 GPMC0_CSn3 0 GPMC0_AD16 PRG1_PRU0_GPO0 8 PRG1_PRU0_GPO0 8 GPMC0_AD17 PRG1_PRU0_GPO1 8 PRG1_PRU0_GPO1 8 GPMC0_AD18 PRG1_PRU0_GPO2 8 PRG1_PRU0_GPO2 8 GPMC0_AD19 PRG1_PRU0_GPO3 8 PRG1_PRU0_GPO3 8 GPMC0_AD20 PRG1_PRU0_GPO4 8 PRG1_PRU0_GPO4 8 GPMC0_AD21 PRG1_PRU0_GPO5 8 PRG1_PRU0_GPO5 8 GPMC0_AD22 PRG1_PRU0_GPO6 8 PRG1_PRU0_GPO6 8 GPMC0_AD23 PRG1_PRU0_GPO7 8 PRG1_PRU0_GPO7 8 GPMC0_AD24 PRG1_PRU0_GPO8 8 PRG1_PRU0_GPO8 8 GPMC0_AD25 PRG1_PRU0_GPO9 8 PRG1_PRU0_GPO9 8 GPMC0_AD26 PRG1_PRU0_GPO10 8 PRG1_PRU0_GPO10 8 AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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Table 5-44. GPMC0 IOSETs (ALV/ANI) (continued) SIGNALS IOSET1 IOSET2 BALL NAME (ALV/ANI) MUXMODE BALL NAME (ALV/ANI) MUXMODE GPMC0_AD27 PRG1_PRU0_GPO11 8 PRG1_PRU0_GPO11 8 GPMC0_AD28 PRG1_PRU0_GPO12 8 PRG1_PRU0_GPO12 8 GPMC0_AD29 PRG1_PRU0_GPO13 8 PRG1_PRU0_GPO13 8 GPMC0_AD30 PRG1_PRU0_GPO14 8 PRG1_PRU0_GPO14 8 GPMC0_AD31 PRG1_PRU0_GPO15 8 PRG1_PRU0_GPO15 8 GPMC0_BE2n PRG1_PRU0_GPO16 8 PRG1_PRU0_GPO16 8 GPMC0_A0 PRG1_PRU0_GPO17 8 PRG0_PRU0_GPO2 9 GPMC0_A1 PRG1_PRU0_GPO18 8 PRG0_PRU0_GPO4 9 GPMC0_A2 PRG1_PRU0_GPO19 8 PRG0_PRU0_GPO8 9 GPMC0_A3 PRG1_PRU1_GPO0 8 PRG0_PRU0_GPO14 9 GPMC0_A4 PRG1_PRU1_GPO1 8 PRG0_PRU0_GPO16 9 GPMC0_A5 PRG1_PRU1_GPO2 8 PRG0_PRU0_GPO18 9 GPMC0_A6 PRG1_PRU1_GPO3 8 PRG0_PRU0_GPO19 9 GPMC0_A7 PRG1_PRU1_GPO4 8 PRG0_PRU1_GPO12 9 GPMC0_A8 PRG1_PRU1_GPO5 8 PRG0_PRU1_GPO13 9 GPMC0_A9 PRG1_PRU1_GPO6 8 PRG0_PRU1_GPO14 9 GPMC0_A10 PRG1_PRU1_GPO7 8 PRG0_PRU1_GPO15 9 GPMC0_A11 PRG1_PRU1_GPO8 8 PRG0_PRU1_GPO16 9 GPMC0_A12 PRG1_PRU1_GPO9 8 PRG0_MDIO0_MDIO 9 GPMC0_A13 PRG1_PRU1_GPO10 8 PRG0_MDIO0_MDC 9 GPMC0_A14 PRG1_PRU1_GPO11 8 PRG0_PRU0_GPO12 9 GPMC0_A15 PRG1_PRU1_GPO12 8 PRG0_PRU0_GPO13 9 GPMC0_A16 PRG1_PRU1_GPO13 8 PRG0_PRU0_GPO15 9 GPMC0_A17 PRG1_PRU1_GPO14 8 PRG0_PRU0_GPO17 9 GPMC0_A18 PRG1_PRU1_GPO15 8 PRG0_PRU1_GPO3 9 GPMC0_A19 PRG1_PRU1_GPO16 8 PRG0_PRU1_GPO6 9 GPMC0_BE3n PRG1_PRU1_GPO17 8 PRG1_PRU1_GPO17 8 GPMC0_A20 GPMC0_CSn3 4 GPMC0_CSn3 4 GPMC0_A21 GPMC0_WAIT1 4 GPMC0_WAIT1 4 GPMC0_A22 GPMC0_WPn 4 GPMC0_WPn 4

5.3.13 I2C

Table 5-45. I2C0 Signal Descriptions SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] I2C0_SCL IOD I2C Clock A18 B16 I2C0_SDA IOD I2C Data B18 B15 Table 5-46. I2C1 Signal Descriptions SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] I2C1_SCL IOD I2C Clock C18 A17 I2C1_SDA IOD I2C Data B19 B18 www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 77 Product Folder Links: AM2434 AM2432 AM2431

Table 5-47. I2C2 Signal Descriptions SIGNAL NAME [1] ((1)) SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] I2C2_SCL IOD I2C Clock C13, P19 B7 I2C2_SDA IOD I2C Data D14, R21 (1) The I2C2 interface is not supported by the ALX packaged devices. See AM243x_ALX Package - Unsupported Interfaces and Signals for additional details. Table 5-48. I2C3 Signal Descriptions SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] I2C3_SCL IOD I2C Clock C17 B14 I2C3_SDA IOD I2C Data D17 A15 MCU Domain Instances Table 5-49. MCU_I2C0 Signal Descriptions SIGNAL NAME [1] ((1)) SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] MCU_I2C0_SCL IOD I2C Clock E9 MCU_I2C0_SDA IOD I2C Data A10 (1) The MCU_I2C0 interface is not supported by the ALX packaged devices. See AM243x_ALX Package - Unsupported Interfaces and Signals for additional details. Table 5-50. MCU_I2C1 Signal Descriptions SIGNAL NAME [1] ((1)) SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] MCU_I2C1_SCL IOD I2C Clock A11 MCU_I2C1_SDA IOD I2C Data B10 (1) The MCU_I2C1 interface is not supported by the ALX packaged devices. See AM243x_ALX Package - Unsupported Interfaces and Signals for additional details.

5.3.14 MCAN

Table 5-51. MCAN0 Signal Descriptions SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] MCAN0_RX I MCAN Receive Data B17 A14 MCAN0_TX O MCAN Transmit Data A17 B13 Table 5-52. MCAN1 Signal Descriptions SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] MCAN1_RX I MCAN Receive Data D17 A15 MCAN1_TX O MCAN Transmit Data C17 B14

5.3.15 SPI (MCSPI)

Table 5-53. MCSPI0 Signal Descriptions SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] SPI0_CLK IO SPI Clock D13 B8 SPI0_CS0 (1) IO SPI Chip Select 0 D12 SPI0_CS1 IO SPI Chip Select 1 C13 B7 AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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Table 5-53. MCSPI0 Signal Descriptions (continued) SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] SPI0_CS2 IO SPI Chip Select 2 B16 B9 SPI0_CS3 IO SPI Chip Select 3 A16 A9 SPI0_D0 IO SPI Data 0 A13 A8 SPI0_D1 IO SPI Data 1 A14 C9 (1) The SPI0_CS0 signal is not supported by the ALX packaged device. See AM243x_ALX Package - Unsupported Interfaces and Signals for additional details. Table 5-54. MCSPI1 Signal Descriptions SIGNAL NAME [1] ((1)) SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] SPI1_CLK IO SPI Clock C14 SPI1_CS0 IO SPI Chip Select 0 B14 SPI1_CS1 IO SPI Chip Select 1 D14 SPI1_CS2 IO SPI Chip Select 2 D16 C11 SPI1_CS3 IO SPI Chip Select 3 E16 A11 SPI1_D0 IO SPI Data 0 B15 SPI1_D1 IO SPI Data 1 A15 (1) The SPI1 interface is not supported by the ALX packaged devices. See AM243x_ALX Package - Unsupported Interfaces and Signals for additional details. Table 5-55. MCSPI2 Signal Descriptions SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] SPI2_CLK IO SPI Clock E14 A12 SPI2_CS0 IO SPI Chip Select 0 E15 B12 SPI2_CS1 IO SPI Chip Select 1 C18 A17 SPI2_CS2 IO SPI Chip Select 2 B19 B18 SPI2_CS3 IO SPI Chip Select 3 A19 A18 SPI2_D0 IO SPI Data 0 D15 B10 SPI2_D1 IO SPI Data 1 C16 B11 Table 5-56. MCSPI3 Signal Descriptions SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] SPI3_CLK IO SPI Clock U4 N3 SPI3_CS0 IO SPI Chip Select 0 U1 E1 SPI3_CS1 IO SPI Chip Select 1 T5 N4 SPI3_CS2 IO SPI Chip Select 2 V12 AA13 SPI3_CS3 IO SPI Chip Select 3 V15 Y14 SPI3_D0 IO SPI Data 0 R6 N1 SPI3_D1 IO SPI Data 1 V4 N2 Table 5-57. MCSPI4 Signal Descriptions SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] SPI4_CLK IO SPI Clock B16 B9 SPI4_CS0 IO SPI Chip Select 0 E16 A11 SPI4_CS1 IO SPI Chip Select 1 A17 B13 SPI4_CS2 IO SPI Chip Select 2 B17 A14 SPI4_CS3 (1) IO SPI Chip Select 3 D18 www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 79 Product Folder Links: AM2434 AM2432 AM2431

Table 5-57. MCSPI4 Signal Descriptions (continued) SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] SPI4_D0 IO SPI Data 0 A16 A9 SPI4_D1 IO SPI Data 1 D16 C11 (1) The SPI4_CS3 signal is not supported by the ALX packaged device. See AM243x_ALX Package - Unsupported Interfaces and Signals for additional details. MCU Domain Instances Table 5-58. MCU_MCSPI0 Signal Descriptions SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] MCU_SPI0_CLK IO SPI Clock E6 MCU_SPI0_CS0 IO SPI Chip Select 0 D6 MCU_SPI0_CS1 IO SPI Chip Select 1 C6 MCU_SPI0_CS2 IO SPI Chip Select 2 D8 D4 MCU_SPI0_CS3 IO SPI Chip Select 3 B8 MCU_SPI0_D0 IO SPI Data 0 E7 MCU_SPI0_D1 IO SPI Data 1 B6 Table 5-59. MCU_MCSPI1 Signal Descriptions SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] MCU_SPI1_CLK IO SPI Clock D7 MCU_SPI1_CS0 IO SPI Chip Select 0 A7 MCU_SPI1_CS1 IO SPI Chip Select 1 B7 MCU_SPI1_CS2 IO SPI Chip Select 2 E8 C2 MCU_SPI1_CS3 IO SPI Chip Select 3 B9 MCU_SPI1_D0 IO SPI Data 0 C7 MCU_SPI1_D1 IO SPI Data 1 C8

5.3.16 MMC

Table 5-60. MMC0 Signal Descriptions SIGNAL NAME [1] ((2)) SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] MMC0_CALPAD (1) A MMC/SD/SDIO Calibration Resistor F18 MMC0_CLK IO MMC/SD/SDIO Clock G18 MMC0_CMD IO MMC/SD/SDIO Command J21 MMC0_DS IO MMC Data Strobe G19 MMC0_DAT0 IO MMC/SD/SDIO Data 0 K20 MMC0_DAT1 IO MMC/SD/SDIO Data 1 J20 MMC0_DAT2 IO MMC/SD/SDIO Data 2 J18 MMC0_DAT3 IO MMC/SD/SDIO Data 3 J17 MMC0_DAT4 IO MMC/SD/SDIO Data 4 H17 MMC0_DAT5 IO MMC/SD/SDIO Data 5 H19 MMC0_DAT6 IO MMC/SD/SDIO Data 6 H18 MMC0_DAT7 IO MMC/SD/SDIO Data 7 G17 (1) An external 10kΩ ±1% resistor must be connected between this pin and VSS. No external voltage should be applied to this pin. (2) The MMC0 interface is not supported by the ALX packaged devices. See AM243x_ALX Package - Unsupported Interfaces and Signals for additional details. AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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Table 5-61. MMC1 Signal Descriptions SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] MMC1_CLK IO MMC/SD/SDIO Clock L20 J20 MMC1_CMD IO MMC/SD/SDIO Command J19 J21 MMC1_SDCD I SD Card Detect D19 B17 MMC1_SDWP I SD Write Protect C20 C16 MMC1_DAT0 IO MMC/SD/SDIO Data 0 K21 J18 MMC1_DAT1 IO MMC/SD/SDIO Data 1 L21 J19 MMC1_DAT2 IO MMC/SD/SDIO Data 2 K19 K20 MMC1_DAT3 IO MMC/SD/SDIO Data 3 K18 K18

5.3.17 OSPI

Table 5-62. OSPI0 Signal Descriptions SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] OSPI0_CLK O OSPI Clock Output N20 P20 OSPI0_DQS I OSPI Data Strobe (DQS) or Loopback Clock Input N19 P17 OSPI0_ECC_FAIL (2) I OSPI ECC Status L17 OSPI0_LBCLKO IO OSPI Loopback Clock Output N21 M21 OSPI0_CSn0 O OSPI Chip Select 0 (active low) L19 L20 OSPI0_CSn1 O OSPI Chip Select 1 (active low) L18 M20 OSPI0_CSn2 (2) O OSPI Chip Select 2 (active low) K17 OSPI0_CSn3 (2) O OSPI Chip Select 3 (active low) L17 OSPI0_D0 IO OSPI Data 0 M19 L19 OSPI0_D1 IO OSPI Data 1 M18 N20 OSPI0_D2 IO OSPI Data 2 M20 L21 OSPI0_D3 IO OSPI Data 3 M21 N19 OSPI0_D4 (1) IO OSPI Data 4 P21 OSPI0_D5 (1) IO OSPI Data 5 P20 OSPI0_D6 (1) IO OSPI Data 6 N18 OSPI0_D7 (1) IO OSPI Data 7 M17 OSPI0_RESET_OUT0 (2) O OSPI Reset Output L17 OSPI0_RESET_OUT1 (2) O OSPI Reset Output K17 (1) This OSPI0 signal is not supported by the ALX packaged device. See AM243x_ALX Package - Unsupported Interfaces and Signals for additional details. The OSPI0 is limited to QSPI (4-bit) functionality for the ALX package. (2) This OSPI0 signal is not supported by the ALX packaged device. See AM243x_ALX Package - Unsupported Interfaces and Signals for additional details.

5.3.18 Power Supply

Table 5-63. Power Supply Signal Descriptions SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] CAP_VDDS0 (1) CAP External capacitor connection for IO group 0 H12 D12 CAP_VDDS1 (1) CAP External capacitor connection for IO group 1 T7 N5 CAP_VDDS2 (1) CAP External capacitor connection for IO group 2 R11 U9 CAP_VDDS3 (1) CAP External capacitor connection for IO group 3 N14 R16 CAP_VDDS4 (1) CAP External capacitor connection for IO group 4 M16 N18 CAP_VDDS5 (1) CAP External capacitor connection for IO group 5 L13 M18 CAP_VDDSHV_MMC1 (2) CAP External capacitor connection for SDIO_LDO K15 J17 CAP_VDDS_MCU (1) CAP External capacitor connection for IO MCU H10 D9 VDDA_0P85_SERDES0 PWR SERDES0 0.85V analog supply P12, P13 www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 81 Product Folder Links: AM2434 AM2432 AM2431

Table 5-63. Power Supply Signal Descriptions (continued) SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] VDDA_0P85_SERDES0_C PWR SERDES0 clock 0.85V analog supply P11 VDDA_0P85_USB0 PWR USB0 0.85V analog supply T12 V16 VDDA_1P8_SERDES0 PWR SERDES0 1.8V analog supply R14 VDDA_1P8_USB0 PWR USB0 1.8V analog supply R15 U15 VDDA_3P3_SDIO PWR SDIO_LDO 3.3V analog supply H15 K15 VDDA_3P3_USB0 PWR USB0 3.3V analog supply R13 U16 VDDA_ADC PWR ADC0 analog supply J13 G17, H17 VDDA_MCU PWR RCOSC, POR, POK, and MCU_PLL0 analog supply K12 H14 VDDA_PLL0 PWR MAIN_PLL0, MAIN_PLL2, and MAIN_PLL14 analog supply N12 N12 VDDA_PLL1 PWR MAIN_PLL8 and MAIN_PLL12 analog supply H9 G9 VDDA_PLL2 PWR MAIN_PLL1 analog supply J11 G12 VDDA_TEMP0 PWR TEMP0 analog supply G11 G11 VDDA_TEMP1 PWR TEMP1 analog supply L11 M11 VDDR_CORE PWR RAM supply L10, M13 G5, G6, J10, J12, P14, P8, R10 VDDSHV0 PWR IO supply for IO group 0 F11, G12, G14 C13, D13, E14 VDDSHV1 PWR IO supply for IO group 1 M7, N6, P7 L6, M6, P5, P6 VDDSHV2 PWR IO supply for IO group 2 R10, R8, T9 T11, T8, U11, U7, VDDSHV3 PWR IO supply for IO group 3 P14, P15 R17, T17 VDDSHV4 PWR IO supply for IO group 4 M14, M15 N16, N17 VDDSHV5 PWR IO supply for IO group 5 L14, L15 L16, L17 VDDSHV_MCU PWR IO supply for IO MCU F9, G10, G8 E7, E8, E9 VDDS_DDR PWR DDR PHY IO supply F7, G6, H7, J6, K7, VDDS_DDR_C PWR DDR clock IO supply J8 VDDS_MMC0 PWR MMC0 PHY IO supply K14 VDDS_OSC PWR MCU_OSC0 supply H13 F18 VDD_CORE PWR Core supply J10, J12, K11, K9, L12, L8, M11, M9, N10, N8, P9 F11, G10, H15, H8, J9, K11, K14, L13, L9, M14, M8, N10, N9, R12, R13, R9 VDD_DLL_MMC0 PWR MMC0 PLL analog supply H14 VDD_MMC0 PWR MMC0 PHY core supply K13 VPP PWR eFuse ROM programming supply G15 E16 VSS GND Ground A1, A21, A5, A6, AA1, AA15, AA18, AA21, C10, C15, C3, D1, E11, E13, F10, F15, F8, G1, G16, G3, G7, G9, H11, H20, H21, H6, H8, J14, J7, J9, K6, K8, L1, L16, L3, L7, L9, M10, M12, M6, M8, N11, N13, N15, N7, N9, P1, P10, P18, P6, P8, R12, R7, R9, T10, T11, T15, T16, T8, U3, V17, W10, W18, Y14, Y17, Y19 A1, A2, A20, A21, AA1, AA2, AA20, AA21, B1, B21, D10, D16, D17, E11, E13, E6, F17, F8, G16, H16, H6, H7, J11, J16, J5, J6, K16, K6, K7, K8, L10, L11, L12, M15, M16, M7, N11, N13, N6, P11, P15, P16, P7, R11, R6, T14, U6, Y1, Y21 (1) This pin must always be connected via a 6.3V or greater, 0.8uF to 1.5μF capacitor to VSS if the respective VDDSHVx pin is ever operated at 3.3V. The capacitor selected must provide a capacitance within the defined range after it has been derated for DC-bias, operating temperature, and aging effects. There are three connection options if the respective VDDSHVx pin is only operated at 1.8V. AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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The pin can be connected to the same decoupling capacitor that is required for 3.3V operation, it can be left unconnected, or it can be connected to the same 1.8V power source as the respective VDDSHVx pin. (2) This pin must always be connected via a 6.3V or greater, 3.3μF ±20% capacitor to VSS when the SDIO_LDO is being used to source VDDSHV5. The capacitor selected must provide a capacitance within the defined range after it has been derated for DC-bias, operating temperature, and aging effects. Otherwise, this pin may be connected directly to VSS when the VDDA_3P3_SDIO pin is also connected directly to VSS.

5.3.19 PRU_ICSSG

Table 5-64. PRU_ICSSG0 Signal Descriptions SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] PRG0_ECAP0_IN_APWM_OUT IO PRU_ICSSG0 Enhanced Capture (ECAP) Input or Auxiliary PWM (APWM) Output R2, U5 F3, M4 PRG0_ECAP0_SYNC_IN I PRU_ICSSG0 ECAP Sync Input P5, V5 D1, T1 PRG0_ECAP0_SYNC_OUT O PRU_ICSSG0 ECAP Sync Output AA4, V5 T1, T3 PRG0_IEP0_EDIO_OUTVALID O PRU_ICSSG0 Industrial Ethernet (IEP0) Digital I/O Outvalid C13 B7 PRG0_IEP0_EDC_LATCH_IN0 I PRU_ICSSG0 Industrial Ethernet (IEP0) Distributed Clock Latch Input 0 V1 K4 PRG0_IEP0_EDC_LATCH_IN1 I PRU_ICSSG0 Industrial Ethernet (IEP0) Distributed Clock Latch Input 1 T1 E2 PRG0_IEP0_EDC_SYNC_OUT0 O PRU_ICSSG0 Industrial Ethernet (IEP0) Distributed Clock Sync Output 0 W1 G2 PRG0_IEP0_EDC_SYNC_OUT1 O PRU_ICSSG0 Industrial Ethernet (IEP0) Distributed Clock Sync Output 1 U1 E1 PRG0_IEP0_EDIO_DATA_IN_OUT28 IO PRU_ICSSG0 Industrial Ethernet Digital I/O Data Input/Output W6 Y3 PRG0_IEP0_EDIO_DATA_IN_OUT29 IO PRU_ICSSG0 Industrial Ethernet Digital I/O Data Input/Output AA5 U1 PRG0_IEP0_EDIO_DATA_IN_OUT30 IO PRU_ICSSG0 Industrial Ethernet (IEP0) Digital I/O Data Input/Output Y5 R2 PRG0_IEP0_EDIO_DATA_IN_OUT31 IO PRU_ICSSG0 Industrial Ethernet Digital I/O Data Input/Output V6 U2 PRG0_IEP1_EDC_LATCH_IN0 I PRU_ICSSG0 Industrial Ethernet (IEP1) Distributed Clock Latch Input 0 P5 D1 PRG0_IEP1_EDC_LATCH_IN1 I PRU_ICSSG0 Industrial Ethernet (IEP1) Distributed Clock Latch Input 1 W5 T5 PRG0_IEP1_EDC_SYNC_OUT0 O PRU_ICSSG0 Industrial Ethernet (IEP1) Distributed Clock Sync Output 0 R2 F3 PRG0_IEP1_EDC_SYNC_OUT1 O PRU_ICSSG0 Industrial Ethernet (IEP1) Distributed Clock Sync Output 1 V5 T1 PRG0_MDIO0_MDC O PRU_ICSSG0 MDIO Clock P3 D2 PRG0_MDIO0_MDIO IO PRU_ICSSG0 MDIO0 Data P2 E4 PRG0_PRU0_GPI0 I PRU_ICSSG0 PRU Data Input Y1 J3 PRG0_PRU0_GPI1 I PRU_ICSSG0 PRU Data Input R4 J4 PRG0_PRU0_GPI2 I PRU_ICSSG0 PRU Data Input U2 G1 PRG0_PRU0_GPI3 I PRU_ICSSG0 PRU Data Input V2 H1 PRG0_PRU0_GPI4 I PRU_ICSSG0 PRU Data Input AA2 K2 PRG0_PRU0_GPI5 I PRU_ICSSG0 PRU Data Input R3 F2 PRG0_PRU0_GPI6 I PRU_ICSSG0 PRU Data Input T3 H2 PRG0_PRU0_GPI7 I PRU_ICSSG0 PRU Data Input T1 E2 PRG0_PRU0_GPI8 I PRU_ICSSG0 PRU Data Input T2 H5 PRG0_PRU0_GPI9 I PRU_ICSSG0 PRU Data Input W6 Y3 PRG0_PRU0_GPI10 I PRU_ICSSG0 PRU Data Input AA5 U1 PRG0_PRU0_GPI11 I PRU_ICSSG0 PRU Data Input Y3 L1 PRG0_PRU0_GPI12 I PRU_ICSSG0 PRU Data Input AA3 K1 PRG0_PRU0_GPI13 I PRU_ICSSG0 PRU Data Input R6 N1 PRG0_PRU0_GPI14 I PRU_ICSSG0 PRU Data Input V4 N2 PRG0_PRU0_GPI15 I PRU_ICSSG0 PRU Data Input T5 N4 PRG0_PRU0_GPI16 I PRU_ICSSG0 PRU Data Input U4 N3 www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 83 Product Folder Links: AM2434 AM2432 AM2431

Table 5-64. PRU_ICSSG0 Signal Descriptions (continued) SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] PRG0_PRU0_GPI17 I PRU_ICSSG0 PRU Data Input U1 E1 PRG0_PRU0_GPI18 I PRU_ICSSG0 PRU Data Input V1 K4 PRG0_PRU0_GPI19 I PRU_ICSSG0 PRU Data Input W1 G2 PRG0_PRU0_GPO0 IO PRU_ICSSG0 PRU Data Output Y1 J3 PRG0_PRU0_GPO1 IO PRU_ICSSG0 PRU Data Output R4 J4 PRG0_PRU0_GPO2 IO PRU_ICSSG0 PRU Data Output U2 G1 PRG0_PRU0_GPO3 IO PRU_ICSSG0 PRU Data Output V2 H1 PRG0_PRU0_GPO4 IO PRU_ICSSG0 PRU Data Output AA2 K2 PRG0_PRU0_GPO5 IO PRU_ICSSG0 PRU Data Output R3 F2 PRG0_PRU0_GPO6 IO PRU_ICSSG0 PRU Data Output T3 H2 PRG0_PRU0_GPO7 IO PRU_ICSSG0 PRU Data Output T1 E2 PRG0_PRU0_GPO8 IO PRU_ICSSG0 PRU Data Output T2 H5 PRG0_PRU0_GPO9 IO PRU_ICSSG0 PRU Data Output W6 Y3 PRG0_PRU0_GPO10 IO PRU_ICSSG0 PRU Data Output AA5 U1 PRG0_PRU0_GPO11 IO PRU_ICSSG0 PRU Data Output Y3 L1 PRG0_PRU0_GPO12 IO PRU_ICSSG0 PRU Data Output AA3 K1 PRG0_PRU0_GPO13 IO PRU_ICSSG0 PRU Data Output R6 N1 PRG0_PRU0_GPO14 IO PRU_ICSSG0 PRU Data Output V4 N2 PRG0_PRU0_GPO15 IO PRU_ICSSG0 PRU Data Output T5 N4 PRG0_PRU0_GPO16 IO PRU_ICSSG0 PRU Data Output U4 N3 PRG0_PRU0_GPO17 IO PRU_ICSSG0 PRU Data Output U1 E1 PRG0_PRU0_GPO18 IO PRU_ICSSG0 PRU Data Output V1 K4 PRG0_PRU0_GPO19 IO PRU_ICSSG0 PRU Data Output W1 G2 PRG0_PRU1_GPI0 I PRU_ICSSG0 PRU Data Input Y2 L5 PRG0_PRU1_GPI1 I PRU_ICSSG0 PRU Data Input W2 J2 PRG0_PRU1_GPI2 I PRU_ICSSG0 PRU Data Input V3 M2 PRG0_PRU1_GPI3 I PRU_ICSSG0 PRU Data Input T4 L2 PRG0_PRU1_GPI4 I PRU_ICSSG0 PRU Data Input W3 L3 PRG0_PRU1_GPI5 I PRU_ICSSG0 PRU Data Input P4 E3 PRG0_PRU1_GPI6 I PRU_ICSSG0 PRU Data Input R5 F5 PRG0_PRU1_GPI7 I PRU_ICSSG0 PRU Data Input W5 T5 PRG0_PRU1_GPI8 I PRU_ICSSG0 PRU Data Input R1 F4 PRG0_PRU1_GPI9 I PRU_ICSSG0 PRU Data Input Y5 R2 PRG0_PRU1_GPI10 I PRU_ICSSG0 PRU Data Input V6 U2 PRG0_PRU1_GPI11 I PRU_ICSSG0 PRU Data Input W4 P1 PRG0_PRU1_GPI12 I PRU_ICSSG0 PRU Data Input Y4 P2 PRG0_PRU1_GPI13 I PRU_ICSSG0 PRU Data Input T6 T4 PRG0_PRU1_GPI14 I PRU_ICSSG0 PRU Data Input U6 R5 PRG0_PRU1_GPI15 I PRU_ICSSG0 PRU Data Input U5 M4 PRG0_PRU1_GPI16 I PRU_ICSSG0 PRU Data Input AA4 T3 PRG0_PRU1_GPI17 I PRU_ICSSG0 PRU Data Input V5 T1 PRG0_PRU1_GPI18 I PRU_ICSSG0 PRU Data Input P5 D1 PRG0_PRU1_GPI19 I PRU_ICSSG0 PRU Data Input R2 F3 PRG0_PRU1_GPO0 IO PRU_ICSSG0 PRU Data Output Y2 L5 PRG0_PRU1_GPO1 IO PRU_ICSSG0 PRU Data Output W2 J2 PRG0_PRU1_GPO2 IO PRU_ICSSG0 PRU Data Output V3 M2 PRG0_PRU1_GPO3 IO PRU_ICSSG0 PRU Data Output T4 L2 PRG0_PRU1_GPO4 IO PRU_ICSSG0 PRU Data Output W3 L3 PRG0_PRU1_GPO5 IO PRU_ICSSG0 PRU Data Output P4 E3 AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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Table 5-64. PRU_ICSSG0 Signal Descriptions (continued) SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] PRG0_PRU1_GPO6 IO PRU_ICSSG0 PRU Data Output R5 F5 PRG0_PRU1_GPO7 IO PRU_ICSSG0 PRU Data Output W5 T5 PRG0_PRU1_GPO8 IO PRU_ICSSG0 PRU Data Output R1 F4 PRG0_PRU1_GPO9 IO PRU_ICSSG0 PRU Data Output Y5 R2 PRG0_PRU1_GPO10 IO PRU_ICSSG0 PRU Data Output V6 U2 PRG0_PRU1_GPO11 IO PRU_ICSSG0 PRU Data Output W4 P1 PRG0_PRU1_GPO12 IO PRU_ICSSG0 PRU Data Output Y4 P2 PRG0_PRU1_GPO13 IO PRU_ICSSG0 PRU Data Output T6 T4 PRG0_PRU1_GPO14 IO PRU_ICSSG0 PRU Data Output U6 R5 PRG0_PRU1_GPO15 IO PRU_ICSSG0 PRU Data Output U5 M4 PRG0_PRU1_GPO16 IO PRU_ICSSG0 PRU Data Output AA4 T3 PRG0_PRU1_GPO17 IO PRU_ICSSG0 PRU Data Output V5 T1 PRG0_PRU1_GPO18 IO PRU_ICSSG0 PRU Data Output P5 D1 PRG0_PRU1_GPO19 IO PRU_ICSSG0 PRU Data Output R2 F3 PRG0_PWM0_TZ_IN I PRU_ICSSG0 PWM Trip Zone Input V1 K4 PRG0_PWM0_TZ_OUT O PRU_ICSSG0 PWM Trip Zone Output W1 G2 PRG0_PWM1_TZ_IN I PRU_ICSSG0 PWM Trip Zone Input P5 D1 PRG0_PWM1_TZ_OUT O PRU_ICSSG0 PWM Trip Zone Output R2 F3 PRG0_PWM2_TZ_IN I PRU_ICSSG0 PWM Trip Zone Input T18, V6 T19, U2 PRG0_PWM2_TZ_OUT O PRU_ICSSG0 PWM Trip Zone Output R1, U21 F4, R20 PRG0_PWM3_TZ_IN I PRU_ICSSG0 PWM Trip Zone Input P16, W6 Y3 PRG0_PWM3_TZ_OUT O PRU_ICSSG0 PWM Trip Zone Output R17, Y3 L1 PRG0_PWM0_A0 IO PRU_ICSSG0 PWM Output A AA3 K1 PRG0_PWM0_A1 IO PRU_ICSSG0 PWM Output A V4 N2 PRG0_PWM0_A2 IO PRU_ICSSG0 PWM Output A U4 N3 PRG0_PWM0_B0 IO PRU_ICSSG0 PWM Output B R6 N1 PRG0_PWM0_B1 IO PRU_ICSSG0 PWM Output B T5 N4 PRG0_PWM0_B2 IO PRU_ICSSG0 PWM Output B2 U1 E1 PRG0_PWM1_A0 IO PRU_ICSSG0 PWM Output A Y4 P2 PRG0_PWM1_A1 IO PRU_ICSSG0 PWM Output A U6 R5 PRG0_PWM1_A2 IO PRU_ICSSG0 PWM Output A AA4 T3 PRG0_PWM1_B0 IO PRU_ICSSG0 PWM Output B T6 T4 PRG0_PWM1_B1 IO PRU_ICSSG0 PWM Output B U5 M4 PRG0_PWM1_B2 IO PRU_ICSSG0 PWM Output B2 V5 T1 PRG0_PWM2_A0 IO PRU_ICSSG0 PWM Output A U2, U20 G1, V21 PRG0_PWM2_A1 IO PRU_ICSSG0 PWM Output A T2, U19 H5, T20 PRG0_PWM2_A2 IO PRU_ICSSG0 PWM Output A V19, V3 M2, U18 PRG0_PWM2_B0 IO PRU_ICSSG0 PWM Output B AA2, U18 K2, U21 PRG0_PWM2_B1 IO PRU_ICSSG0 PWM Output B AA5, V20 T18, U1 PRG0_PWM2_B2 IO PRU_ICSSG0 PWM Output B T17, W3 L3, U20 PRG0_PWM3_A0 IO PRU_ICSSG0 PWM Output A V18, Y1 J3, Y19 PRG0_PWM3_A1 IO PRU_ICSSG0 PWM Output A R18, T3 H2 PRG0_PWM3_A2 IO PRU_ICSSG0 PWM Output A T19, V2 H1, P21 PRG0_PWM3_B0 IO PRU_ICSSG0 PWM Output B R4, Y21 J4, Y18 PRG0_PWM3_B1 IO PRU_ICSSG0 PWM Output B T1, T21 E2 PRG0_PWM3_B2 IO PRU_ICSSG0 PWM Output B R3, W19 F2 PRG0_RGMII1_RXC I PRU_ICSSG0 RGMII Receive Clock T3 H2 PRG0_RGMII1_RX_CTL I PRU_ICSSG0 RGMII Receive Control AA2 K2 PRG0_RGMII1_TXC IO PRU_ICSSG0 RGMII Transmit Clock U4 N3 www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 85 Product Folder Links: AM2434 AM2432 AM2431

Table 5-64. PRU_ICSSG0 Signal Descriptions (continued) SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] PRG0_RGMII1_TX_CTL O PRU_ICSSG0 RGMII Transmit Control T5 N4 PRG0_RGMII2_RXC I PRU_ICSSG0 RGMII Receive Clock R5 F5 PRG0_RGMII2_RX_CTL I PRU_ICSSG0 RGMII Receive Control W3 L3 PRG0_RGMII2_TXC IO PRU_ICSSG0 RGMII Transmit Clock AA4 T3 PRG0_RGMII2_TX_CTL O PRU_ICSSG0 RGMII Transmit Control U5 M4 PRG0_RGMII1_RD0 I PRU_ICSSG0 RGMII Receive Data Y1 J3 PRG0_RGMII1_RD1 I PRU_ICSSG0 RGMII Receive Data R4 J4 PRG0_RGMII1_RD2 I PRU_ICSSG0 RGMII Receive Data U2 G1 PRG0_RGMII1_RD3 I PRU_ICSSG0 RGMII Receive Data V2 H1 PRG0_RGMII1_TD0 O PRU_ICSSG0 RGMII Transmit Data Y3 L1 PRG0_RGMII1_TD1 O PRU_ICSSG0 RGMII Transmit Data AA3 K1 PRG0_RGMII1_TD2 O PRU_ICSSG0 RGMII Transmit Data R6 N1 PRG0_RGMII1_TD3 O PRU_ICSSG0 RGMII Transmit Data V4 N2 PRG0_RGMII2_RD0 I PRU_ICSSG0 RGMII Receive Data Y2 L5 PRG0_RGMII2_RD1 I PRU_ICSSG0 RGMII Receive Data W2 J2 PRG0_RGMII2_RD2 I PRU_ICSSG0 RGMII Receive Data V3 M2 PRG0_RGMII2_RD3 I PRU_ICSSG0 RGMII Receive Data T4 L2 PRG0_RGMII2_TD0 O PRU_ICSSG0 RGMII Transmit Data W4 P1 PRG0_RGMII2_TD1 O PRU_ICSSG0 RGMII Transmit Data Y4 P2 PRG0_RGMII2_TD2 O PRU_ICSSG0 RGMII Transmit Data T6 T4 PRG0_RGMII2_TD3 O PRU_ICSSG0 RGMII Transmit Data U6 R5 PRG0_UART0_CTSn I PRU_ICSSG0 UART Clear to Send (active low) W6 Y3 PRG0_UART0_RTSn O PRU_ICSSG0 UART Request to Send (active low) AA5 U1 PRG0_UART0_RXD I PRU_ICSSG0 UART Receive Data Y5 R2 PRG0_UART0_TXD O PRU_ICSSG0 UART Transmit Data V6 U2 Table 5-65. PRU_ICSSG1 Signal Descriptions SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] PRG1_ECAP0_IN_APWM_OUT IO PRU_ICSSG1 Enhanced Capture (ECAP) Input or Auxiliary PWM (APWM) Output V12 AA13 PRG1_ECAP0_SYNC_IN I PRU_ICSSG1 ECAP Sync Input Y13 Y15 PRG1_ECAP0_SYNC_OUT O PRU_ICSSG1 ECAP Sync Output AA14 AA14 PRG1_IEP0_EDIO_OUTVALID (1) O PRU_ICSSG1 Industrial Ethernet Digital I/O Outvalid D14 PRG1_IEP0_EDC_LATCH_IN0 I PRU_ICSSG1 Industrial Ethernet Distributed Clock Latch Input V7 Y4 PRG1_IEP0_EDC_LATCH_IN1 I PRU_ICSSG1 Industrial Ethernet Distributed Clock Latch Input U13 V13 PRG1_IEP0_EDC_SYNC_OUT0 O PRU_ICSSG1 Industrial Ethernet Distributed Clock Sync Output W7 U3 PRG1_IEP0_EDC_SYNC_OUT1 O PRU_ICSSG1 Industrial Ethernet Distributed Clock Sync Output U7 T2 PRG1_IEP0_EDIO_DATA_IN_OUT28 IO PRU_ICSSG1 Industrial Ethernet Digital I/O Data Input/Output U15 W16 PRG1_IEP0_EDIO_DATA_IN_OUT29 IO PRU_ICSSG1 Industrial Ethernet Digital I/O Data Input/Output U14 W13 PRG1_IEP0_EDIO_DATA_IN_OUT30 IO PRU_ICSSG1 Industrial Ethernet Digital I/O Data Input/Output V14 Y16 PRG1_IEP0_EDIO_DATA_IN_OUT31 IO PRU_ICSSG1 Industrial Ethernet Digital I/O Data Input/Output W14 U13 PRG1_IEP1_EDC_LATCH_IN0 I PRU_ICSSG1 Industrial Ethernet Distributed Clock Latch Input Y13 Y15 PRG1_IEP1_EDC_LATCH_IN1 I PRU_ICSSG1 Industrial Ethernet Distributed Clock Latch Input V15 Y14 PRG1_IEP1_EDC_SYNC_OUT0 O PRU_ICSSG1 Industrial Ethernet Distributed Clock Sync Output V12 AA13 AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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Table 5-65. PRU_ICSSG1 Signal Descriptions (continued) SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] PRG1_IEP1_EDC_SYNC_OUT1 O PRU_ICSSG1 Industrial Ethernet Distributed Clock Sync Output AA14 AA14 PRG1_MDIO0_MDC O PRU_ICSSG1 MDIO Clock Y6 W1 PRG1_MDIO0_MDIO IO PRU_ICSSG1 MDIO Data AA6 V2 PRG1_PRU0_GPI0 I PRU_ICSSG1 PRU Data Input Y7 V4 PRG1_PRU0_GPI1 I PRU_ICSSG1 PRU Data Input U8 W5 PRG1_PRU0_GPI2 I PRU_ICSSG1 PRU Data Input W8 AA4 PRG1_PRU0_GPI3 I PRU_ICSSG1 PRU Data Input V8 Y5 PRG1_PRU0_GPI4 I PRU_ICSSG1 PRU Data Input Y8 AA5 PRG1_PRU0_GPI5 I PRU_ICSSG1 PRU Data Input V13 U14 PRG1_PRU0_GPI6 I PRU_ICSSG1 PRU Data Input AA7 Y2 PRG1_PRU0_GPI7 I PRU_ICSSG1 PRU Data Input U13 V13 PRG1_PRU0_GPI8 I PRU_ICSSG1 PRU Data Input W13 Y13 PRG1_PRU0_GPI9 I PRU_ICSSG1 PRU Data Input U15 W16 PRG1_PRU0_GPI10 I PRU_ICSSG1 PRU Data Input U14 W13 PRG1_PRU0_GPI11 I PRU_ICSSG1 PRU Data Input AA8 V5 PRG1_PRU0_GPI12 I PRU_ICSSG1 PRU Data Input U9 W2 PRG1_PRU0_GPI13 I PRU_ICSSG1 PRU Data Input W9 V6 PRG1_PRU0_GPI14 I PRU_ICSSG1 PRU Data Input AA9 AA7 PRG1_PRU0_GPI15 I PRU_ICSSG1 PRU Data Input Y9 Y7 PRG1_PRU0_GPI16 I PRU_ICSSG1 PRU Data Input V9 W6 PRG1_PRU0_GPI17 I PRU_ICSSG1 PRU Data Input U7 T2 PRG1_PRU0_GPI18 I PRU_ICSSG1 PRU Data Input V7 Y4 PRG1_PRU0_GPI19 I PRU_ICSSG1 PRU Data Input W7 U3 PRG1_PRU0_GPO0 IO PRU_ICSSG1 PRU Data Output Y7 V4 PRG1_PRU0_GPO1 IO PRU_ICSSG1 PRU Data Output U8 W5 PRG1_PRU0_GPO2 IO PRU_ICSSG1 PRU Data Output W8 AA4 PRG1_PRU0_GPO3 IO PRU_ICSSG1 PRU Data Output V8 Y5 PRG1_PRU0_GPO4 IO PRU_ICSSG1 PRU Data Output Y8 AA5 PRG1_PRU0_GPO5 IO PRU_ICSSG1 PRU Data Output V13 U14 PRG1_PRU0_GPO6 IO PRU_ICSSG1 PRU Data Output AA7 Y2 PRG1_PRU0_GPO7 IO PRU_ICSSG1 PRU Data Output U13 V13 PRG1_PRU0_GPO8 IO PRU_ICSSG1 PRU Data Output W13 Y13 PRG1_PRU0_GPO9 IO PRU_ICSSG1 PRU Data Output U15 W16 PRG1_PRU0_GPO10 IO PRU_ICSSG1 PRU Data Output U14 W13 PRG1_PRU0_GPO11 IO PRU_ICSSG1 PRU Data Output AA8 V5 PRG1_PRU0_GPO12 IO PRU_ICSSG1 PRU Data Output U9 W2 PRG1_PRU0_GPO13 IO PRU_ICSSG1 PRU Data Output W9 V6 PRG1_PRU0_GPO14 IO PRU_ICSSG1 PRU Data Output AA9 AA7 PRG1_PRU0_GPO15 IO PRU_ICSSG1 PRU Data Output Y9 Y7 PRG1_PRU0_GPO16 IO PRU_ICSSG1 PRU Data Output V9 W6 PRG1_PRU0_GPO17 IO PRU_ICSSG1 PRU Data Output U7 T2 PRG1_PRU0_GPO18 IO PRU_ICSSG1 PRU Data Output V7 Y4 PRG1_PRU0_GPO19 IO PRU_ICSSG1 PRU Data Output W7 U3 PRG1_PRU1_GPI0 I PRU_ICSSG1 PRU Data Input W11 AA10 PRG1_PRU1_GPI1 I PRU_ICSSG1 PRU Data Input V11 Y10 PRG1_PRU1_GPI2 I PRU_ICSSG1 PRU Data Input AA12 Y11 PRG1_PRU1_GPI3 I PRU_ICSSG1 PRU Data Input Y12 V12 PRG1_PRU1_GPI4 I PRU_ICSSG1 PRU Data Input W12 Y12 www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 87 Product Folder Links: AM2434 AM2432 AM2431

Table 5-65. PRU_ICSSG1 Signal Descriptions (continued) SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] PRG1_PRU1_GPI5 I PRU_ICSSG1 PRU Data Input AA13 AA11 PRG1_PRU1_GPI6 I PRU_ICSSG1 PRU Data Input U11 V10 PRG1_PRU1_GPI7 I PRU_ICSSG1 PRU Data Input V15 Y14 PRG1_PRU1_GPI8 I PRU_ICSSG1 PRU Data Input U12 W11 PRG1_PRU1_GPI9 I PRU_ICSSG1 PRU Data Input V14 Y16 PRG1_PRU1_GPI10 I PRU_ICSSG1 PRU Data Input W14 U13 PRG1_PRU1_GPI11 I PRU_ICSSG1 PRU Data Input AA10 Y6 PRG1_PRU1_GPI12 I PRU_ICSSG1 PRU Data Input V10 AA8 PRG1_PRU1_GPI13 I PRU_ICSSG1 PRU Data Input U10 Y9 PRG1_PRU1_GPI14 I PRU_ICSSG1 PRU Data Input AA11 W9 PRG1_PRU1_GPI15 I PRU_ICSSG1 PRU Data Input Y11 V9 PRG1_PRU1_GPI16 I PRU_ICSSG1 PRU Data Input Y10 Y8 PRG1_PRU1_GPI17 I PRU_ICSSG1 PRU Data Input AA14 AA14 PRG1_PRU1_GPI18 I PRU_ICSSG1 PRU Data Input Y13 Y15 PRG1_PRU1_GPI19 I PRU_ICSSG1 PRU Data Input V12 AA13 PRG1_PRU1_GPO0 IO PRU_ICSSG1 PRU Data Output W11 AA10 PRG1_PRU1_GPO1 IO PRU_ICSSG1 PRU Data Output V11 Y10 PRG1_PRU1_GPO2 IO PRU_ICSSG1 PRU Data Output AA12 Y11 PRG1_PRU1_GPO3 IO PRU_ICSSG1 PRU Data Output Y12 V12 PRG1_PRU1_GPO4 IO PRU_ICSSG1 PRU Data Output W12 Y12 PRG1_PRU1_GPO5 IO PRU_ICSSG1 PRU Data Output AA13 AA11 PRG1_PRU1_GPO6 IO PRU_ICSSG1 PRU Data Output U11 V10 PRG1_PRU1_GPO7 IO PRU_ICSSG1 PRU Data Output V15 Y14 PRG1_PRU1_GPO8 IO PRU_ICSSG1 PRU Data Output U12 W11 PRG1_PRU1_GPO9 IO PRU_ICSSG1 PRU Data Output V14 Y16 PRG1_PRU1_GPO10 IO PRU_ICSSG1 PRU Data Output W14 U13 PRG1_PRU1_GPO11 IO PRU_ICSSG1 PRU Data Output AA10 Y6 PRG1_PRU1_GPO12 IO PRU_ICSSG1 PRU Data Output V10 AA8 PRG1_PRU1_GPO13 IO PRU_ICSSG1 PRU Data Output U10 Y9 PRG1_PRU1_GPO14 IO PRU_ICSSG1 PRU Data Output AA11 W9 PRG1_PRU1_GPO15 IO PRU_ICSSG1 PRU Data Output Y11 V9 PRG1_PRU1_GPO16 IO PRU_ICSSG1 PRU Data Output Y10 Y8 PRG1_PRU1_GPO17 IO PRU_ICSSG1 PRU Data Output AA14 AA14 PRG1_PRU1_GPO18 IO PRU_ICSSG1 PRU Data Output Y13 Y15 PRG1_PRU1_GPO19 IO PRU_ICSSG1 PRU Data Output V12 AA13 PRG1_PWM0_TZ_IN I PRU_ICSSG1 PWM Trip Zone Input V7 Y4 PRG1_PWM0_TZ_OUT O PRU_ICSSG1 PWM Trip Zone Output W7 U3 PRG1_PWM1_TZ_IN I PRU_ICSSG1 PWM Trip Zone Input Y13 Y15 PRG1_PWM1_TZ_OUT O PRU_ICSSG1 PWM Trip Zone Output V12 AA13 PRG1_PWM2_TZ_IN I PRU_ICSSG1 PWM Trip Zone Input P19, W14 U13 PRG1_PWM2_TZ_OUT O PRU_ICSSG1 PWM Trip Zone Output R20, U12 W11 PRG1_PWM3_TZ_IN I PRU_ICSSG1 PWM Trip Zone Input U15 W16 PRG1_PWM3_TZ_OUT O PRU_ICSSG1 PWM Trip Zone Output AA8 V5 PRG1_PWM0_A0 IO PRU_ICSSG1 PWM Output A U9 W2 PRG1_PWM0_A1 IO PRU_ICSSG1 PWM Output A AA9 AA7 PRG1_PWM0_A2 IO PRU_ICSSG1 PWM Output A V9 W6 PRG1_PWM0_B0 IO PRU_ICSSG1 PWM Output B W9 V6 PRG1_PWM0_B1 IO PRU_ICSSG1 PWM Output B Y9 Y7 PRG1_PWM0_B2 IO PRU_ICSSG1 PWM Output B U7 T2 AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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Table 5-65. PRU_ICSSG1 Signal Descriptions (continued) SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] PRG1_PWM1_A0 IO PRU_ICSSG1 PWM Output A V10 AA8 PRG1_PWM1_A1 IO PRU_ICSSG1 PWM Output A AA11 W9 PRG1_PWM1_A2 IO PRU_ICSSG1 PWM Output A Y10 Y8 PRG1_PWM1_B0 IO PRU_ICSSG1 PWM Output B U10 Y9 PRG1_PWM1_B1 IO PRU_ICSSG1 PWM Output B Y11 V9 PRG1_PWM1_B2 IO PRU_ICSSG1 PWM Output B AA14 AA14 PRG1_PWM2_A0 IO PRU_ICSSG1 PWM Output A N16, W8 AA4 PRG1_PWM2_A1 IO PRU_ICSSG1 PWM Output A P17, W13 Y13 PRG1_PWM2_A2 IO PRU_ICSSG1 PWM Output A AA12, V21 U19, Y11 PRG1_PWM2_B0 IO PRU_ICSSG1 PWM Output B N17, Y8 AA5 PRG1_PWM2_B1 IO PRU_ICSSG1 PWM Output B U14, Y18 W13 PRG1_PWM2_B2 IO PRU_ICSSG1 PWM Output B R16, W12 V20, Y12 PRG1_PWM3_A0 IO PRU_ICSSG1 PWM Output A Y7 V4 PRG1_PWM3_A1 IO PRU_ICSSG1 PWM Output A AA7 Y2 PRG1_PWM3_A2 IO PRU_ICSSG1 PWM Output A V8 Y5 PRG1_PWM3_B0 IO PRU_ICSSG1 PWM Output B U8 W5 PRG1_PWM3_B1 IO PRU_ICSSG1 PWM Output B U13 V13 PRG1_PWM3_B2 IO PRU_ICSSG1 PWM Output B V13 U14 PRG1_RGMII1_RXC I PRU_ICSSG1 RGMII Receive Clock AA7 Y2 PRG1_RGMII1_RX_CTL I PRU_ICSSG1 RGMII Receive Control Y8 AA5 PRG1_RGMII1_TXC IO PRU_ICSSG1 RGMII Transmit Clock V9 W6 PRG1_RGMII1_TX_CTL O PRU_ICSSG1 RGMII Transmit Control Y9 Y7 PRG1_RGMII2_RXC I PRU_ICSSG1 RGMII Receive Clock U11 V10 PRG1_RGMII2_RX_CTL I PRU_ICSSG1 RGMII Receive Control W12 Y12 PRG1_RGMII2_TXC IO PRU_ICSSG1 RGMII Transmit Clock Y10 Y8 PRG1_RGMII2_TX_CTL O PRU_ICSSG1 RGMII Transmit Control Y11 V9 PRG1_RGMII1_RD0 I PRU_ICSSG1 RGMII Receive Data Y7 V4 PRG1_RGMII1_RD1 I PRU_ICSSG1 RGMII Receive Data U8 W5 PRG1_RGMII1_RD2 I PRU_ICSSG1 RGMII Receive Data W8 AA4 PRG1_RGMII1_RD3 I PRU_ICSSG1 RGMII Receive Data V8 Y5 PRG1_RGMII1_TD0 O PRU_ICSSG1 RGMII Transmit Data AA8 V5 PRG1_RGMII1_TD1 O PRU_ICSSG1 RGMII Transmit Data U9 W2 PRG1_RGMII1_TD2 O PRU_ICSSG1 RGMII Transmit Data W9 V6 PRG1_RGMII1_TD3 O PRU_ICSSG1 RGMII Transmit Data AA9 AA7 PRG1_RGMII2_RD0 I PRU_ICSSG1 RGMII Receive Data W11 AA10 PRG1_RGMII2_RD1 I PRU_ICSSG1 RGMII Receive Data V11 Y10 PRG1_RGMII2_RD2 I PRU_ICSSG1 RGMII Receive Data AA12 Y11 PRG1_RGMII2_RD3 I PRU_ICSSG1 RGMII Receive Data Y12 V12 PRG1_RGMII2_TD0 O PRU_ICSSG1 RGMII Transmit Data AA10 Y6 PRG1_RGMII2_TD1 O PRU_ICSSG1 RGMII Transmit Data V10 AA8 PRG1_RGMII2_TD2 O PRU_ICSSG1 RGMII Transmit Data U10 Y9 PRG1_RGMII2_TD3 O PRU_ICSSG1 RGMII Transmit Data AA11 W9 PRG1_UART0_CTSn I PRU_ICSSG1 UART Clear to Send (active low) U15 W16 PRG1_UART0_RTSn O PRU_ICSSG1 UART Request to Send (active low) U14 W13 PRG1_UART0_RXD I PRU_ICSSG1 UART Receive Data V14 Y16 PRG1_UART0_TXD O PRU_ICSSG1 UART Transmit Data W14 U13 (1) The PRG1_IEP0_EDIO_OUTVALID signal is not supported by the ALX packaged device. See AM243x_ALX Package - Unsupported Interfaces and Signals for additional details. www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 89 Product Folder Links: AM2434 AM2432 AM2431

5.3.20 Reserved and No Connect

Table 5-66. Reserved Signal Descriptions SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] RSVD0 N/A Reserved, must be left unconnected H16 H11 RSVD1 N/A Reserved, must be left unconnected D21 J13 RSVD2 N/A Reserved, must be left unconnected G13 RSVD3 N/A Reserved, must be left unconnected F17 RSVD4 N/A Reserved, must be left unconnected W15 RSVD5 N/A Reserved, must be left unconnected V16 RSVD6 N/A Reserved, must be left unconnected K2 RSVD7 N/A Reserved, must be left unconnected K1 RSVD8 N/A Reserved, must be left unconnected F12

5.3.21 SERDES

Table 5-67. SERDES0 Signal Descriptions SIGNAL NAME [1] ((3)) ((2)) SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] PCIE0_CLKREQn IO PCIE Clock Request Signal D16 C11 SERDES0_REXT (1) A External SerDes PHY Calibration Resistor T13 SERDES0_REFCLK0N IO SerDes PHY Reference Clock Input/Output (negative) W16 SERDES0_REFCLK0P IO SerDes PHY Reference Clock Input/Output (positive) W17 SERDES0_RX0_N I SerDes PHY Differential Receive Data (negative) Y15 SERDES0_RX0_P I SerDes PHY Differential Receive Data (positive) Y16 SERDES0_TX0_N O SerDes PHY Differential Transmit Data (negative) AA16 SERDES0_TX0_P O SerDes PHY Differential Transmit Data (positive) AA17 (1) An external 3.01kΩ ±1% resistor must be connected between this pin and VSS. No external voltage should be applied to this pin. (2) The functionality of these pins is controlled by the SERDES0_LN0_CTRL_LANE_FUNC_SEL register. (3) The SERDES0 interface is not supported by the ALX packaged devices. See AM243x_ALX Package - Unsupported Interfaces and Signals for additional details.

5.3.22 System and Miscellaneous

5.3.22.1 Boot Mode Configuration

Table 5-68. Sysboot Signal Descriptions SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] BOOTMODE00 I Bootmode pin 0 T20 R21 BOOTMODE01 I Bootmode pin 1 U21 R20 BOOTMODE02 I Bootmode pin 2 T18 T19 BOOTMODE03 I Bootmode pin 3 U20 V21 BOOTMODE04 I Bootmode pin 4 U18 U21 BOOTMODE05 I Bootmode pin 5 U19 T20 BOOTMODE06 I Bootmode pin 6 V20 T18 BOOTMODE07 I Bootmode pin 7 V21 U19 BOOTMODE08 I Bootmode pin 8 V19 U18 BOOTMODE09 I Bootmode pin 9 T17 U20 BOOTMODE10 I Bootmode pin 10 R16 V20 BOOTMODE11 I Bootmode pin 11 W20 W20 BOOTMODE12 I Bootmode pin 12 W21 Y20 BOOTMODE13 I Bootmode pin 13 V18 Y19 AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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Table 5-68. Sysboot Signal Descriptions (continued) SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] BOOTMODE14 I Bootmode pin 14 Y21 Y18 BOOTMODE15 I Bootmode pin 15 Y20 AA19

5.3.22.2 Clocking

Table 5-69. MCU Clock Signal Descriptions SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] MCU_OSC0_XI I High frequency oscillator input C21 D20 MCU_OSC0_XO O High frequency oscillator output B20 C21

5.3.22.3 SYSTEM

Table 5-70. System Signal Descriptions SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] CLKOUT0 O RMII Clock Output (50MHz). This pin is used for clock source to the external PHY and must be routed back to the RMII_REF_CLK pin for proper device operation. A19, U13 A18, V13 EXTINTn (1) I External Interrupt C19 EXT_REFCLK1 I External clock input to Main domain A19 A18 OBSCLK0 O Observation clock output for test and debug purposes only D17 A15 PORz_OUT O MAIN domain POR status output E17 D18 RESETSTATz O MAIN domain warm reset status output F16 E19 RESET_REQz I MAIN domain external warm reset request input E18 C17 SYSCLKOUT0 O SYSCLK0 output from MAIN PLL controller (divided by 6) for test and debug purposes only C17 B14 (1) The EXTINTn signal is not supported by the ALX packaged device. See AM243x_ALX Package - Unsupported Interfaces and Signals for additional details. MCU Domain Instances Table 5-71. MCU System Signal Descriptions SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] MCU_EXT_REFCLK0 (2) I External system clock input B7 MCU_OBSCLK0 O Observation clock output for test and debug purposes only C6, E10 B3 MCU_PORz I MCU and Main domain cold reset B21 C20 MCU_RESETSTATz O MCU domain warm reset status output B13 A6 MCU_RESETz I MCU domain warm reset B12 A5 MCU_SAFETY_ERRORn IO Error signal output from MCU domain ESM A20 B20 MCU_SYSCLKOUT0 (1) O MCU domain system clock output for test and debug purposes only C6 (1) The MCU_SYSCLKOUT0 signal is not supported by the ALX packaged device. See AM243x_ALX Package - Unsupported Interfaces and Signals for additional details. (2) The MCU_EXT_REFCLK0 signal is not supported by the ALX packaged device. See AM243x_ALX Package - Unsupported Interfaces and Signals for additional details. www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 91 Product Folder Links: AM2434 AM2432 AM2431

5.3.22.4 VMON

Table 5-72. VMON Signal Descriptions SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] VMON_1P8_MCU A Voltage monitor input for 1.8V MCU power supply K16 VMON_1P8_SOC A Voltage monitor input for 1.8V SoC power supply E12 F14 VMON_3P3_MCU A Voltage monitor input for 3.3V MCU power supply F13 VMON_3P3_SOC A Voltage monitor input for 3.3V SoC power supply F14 E15 VMON_VSYS A Voltage monitor input, fixed 0.45V (+/-3%) threshold. Use with external precision voltage divider to monitor a higher voltage rail such as the PMIC input supply. K10 G13

5.3.23 TIMER

Table 5-73. TIMER Signal Descriptions SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] TIMER_IO0 IO Timer Inputs and Outputs (not tied to single timer instance) C18, K18 A17, K18 TIMER_IO1 IO Timer Inputs and Outputs (not tied to single timer instance) B19, K19 B18, K20 TIMER_IO2 IO Timer Inputs and Outputs (not tied to single timer instance) A17, L21 B13, J19 TIMER_IO3 IO Timer Inputs and Outputs (not tied to single timer instance) B17, K21 A14, J18 TIMER_IO4 IO Timer Inputs and Outputs (not tied to single timer instance) C17, L20 B14, J20 TIMER_IO5 IO Timer Inputs and Outputs (not tied to single timer instance) D17, J19 A15, J21 TIMER_IO6 IO Timer Inputs and Outputs (not tied to single timer instance) B16, D19, T1 B17, B9, E2 TIMER_IO7 IO Timer Inputs and Outputs (not tied to single timer instance) A16, C20, U7 A9, C16, T2 TIMER_IO8 IO Timer Inputs and Outputs (not tied to single timer instance) P19, V7 Y4 TIMER_IO9 IO Timer Inputs and Outputs (not tied to single timer instance) R21, W7 U3 TIMER_IO10 IO Timer Inputs and Outputs (not tied to single timer instance) C13, U13 B7, V13 TIMER_IO11 IO Timer Inputs and Outputs (not tied to single timer instance) D14, U1 E1 MCU Domain Instances Table 5-74. MCU_TIMER Signal Descriptions SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] MCU_TIMER_IO0 IO Timer Inputs and Outputs (not tied to single timer instance) D8 D4 MCU_TIMER_IO1 IO Timer Inputs and Outputs (not tied to single timer instance) E8 C2 MCU_TIMER_IO2 (1) IO Timer Inputs and Outputs (not tied to single timer instance) B8 MCU_TIMER_IO3 (1) IO Timer Inputs and Outputs (not tied to single timer instance) B9 (1) This MCU_TIMER_IO signal is not supported by the ALX packaged device. See AM243x_ALX Package - Unsupported Interfaces and Signals for additional details.

5.3.24 UART

Table 5-75. UART0 Signal Descriptions SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] UART0_CTSn I UART Clear to Send (active low) B16 B9 UART0_DCDn I UART Data Carrier Detect (active low) C17 B14 UART0_DSRn I UART Data Set Ready (active low) D17 A15 UART0_DTRn O UART Data Terminal Ready (active low) A17 B13 UART0_RIn I UART Ring Indicator B17 A14 UART0_RTSn O UART Request to Send (active low) A16 A9 AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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Table 5-75. UART0 Signal Descriptions (continued) SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] UART0_RXD I UART Receive Data D15 B10 UART0_TXD O UART Transmit Data C16 B11 Table 5-76. UART1 Signal Descriptions SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] UART1_CTSn I UART Clear to Send (active low) D16 C11 UART1_RTSn O UART Request to Send (active low) E16 A11 UART1_RXD I UART Receive Data E15 B12 UART1_TXD O UART Transmit Data E14 A12 Table 5-77. UART2 Signal Descriptions SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] UART2_CTSn I UART Clear to Send (active low) L20, V19, Y1 J20, J3, U18 UART2_RTSn O UART Request to Send (active low) J19, T18, U2 G1, J21, T19 UART2_RXD I UART Receive Data B16, K18, T20, V1, B9, K18, K4, R21, UART2_TXD O UART Transmit Data A16, K19, R4, U21 A9, J4, K20, R20 Table 5-78. UART3 Signal Descriptions SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] UART3_CTSn I UART Clear to Send (active low) D19, T17, V2 B17, H1, U20 UART3_RTSn O UART Request to Send (active low) C20, R3, U19 C16, F2, T20 UART3_RXD I UART Receive Data AA5, D16, L21, U20, W1 C11, G2, J19, U1, V21 UART3_TXD O UART Transmit Data AA2, E16, K21, U18 A11, J18, K2, U21 Table 5-79. UART4 Signal Descriptions SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] UART4_CTSn I UART Clear to Send (active low) R16, R5, T3, V1 F5, H2, K4, V20 UART4_RTSn O UART Request to Send (active low) R1, R17, T2, W1 F4, G2, H5 UART4_RXD I UART Receive Data A17, L20, V20, W4, Y3 B13, J20, L1, P1, T18 UART4_TXD O UART Transmit Data B17, J19, T1, V21, W5, Y4 A14, E2, J21, P2, T5, U19 Table 5-80. UART5 Signal Descriptions SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] UART5_CTSn I UART Clear to Send (active low) W20, Y13, Y2 L5, W20, Y15 UART5_RTSn O UART Request to Send (active low) T21, V12, V3 AA13, M2 UART5_RXD I UART Receive Data C17, D19, P16, T6, Y5 B14, B17, R2, T4 UART5_TXD O UART Transmit Data C20, D17, R18, W2 A15, C16, J2 www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 93 Product Folder Links: AM2434 AM2432 AM2431

Table 5-81. UART6 Signal Descriptions SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] UART6_CTSn I UART Clear to Send (active low) T4, W21 L2, Y20 UART6_RTSn O UART Request to Send (active low) P17, P4 E3 UART6_RXD I UART Receive Data C13, U6, V6, Y21 B7, R5, U2, Y18 UART6_TXD O UART Transmit Data D14, W3, Y20 AA19, L3 MCU Domain Instances Table 5-82. MCU_UART0 Signal Descriptions SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] MCU_UART0_CTSn I UART Clear to Send (active low) D8 D4 MCU_UART0_RTSn O UART Request to Send (active low) E8 C2 MCU_UART0_RXD I UART Receive Data A9 D6 MCU_UART0_TXD O UART Transmit Data A8 B2 Table 5-83. MCU_UART1 Signal Descriptions SIGNAL NAME [1] ((1)) SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] MCU_UART1_CTSn I UART Clear to Send (active low) B8 MCU_UART1_RTSn O UART Request to Send (active low) B9 MCU_UART1_RXD I UART Receive Data C9 MCU_UART1_TXD O UART Transmit Data D9 (1) The MCU_UART1 interface is not supported by the ALX packaged devices. See AM243x_ALX Package - Unsupported Interfaces and Signals for additional details.

5.3.25 USB

Table 5-84. USB0 Signal Descriptions SIGNAL NAME [1] SIGNAL TYPE [2] DESCRIPTION [3] ALV/ANI PIN [4] ALX PIN [4] USB0_DM IO USB 2.0 Differential Data (negative) AA20 AA17 USB0_DP IO USB 2.0 Differential Data (positive) AA19 AA16 USB0_DRVVBUS O USB VBUS control output (active high) E19 B19 USB0_ID A USB 2.0 Dual-Role Device (DRD) role select U16 Y17 USB0_RCALIB (1) A Pin to connect to calibration resistor U17 W17 USB0_VBUS (2) A USB Level-shifted VBUS Input T14 V18 (1) An external 499Ω ±1% resistor must be connected between this pin and VSS. The maximum power dissipation for the resistor is 7.2mW. No external voltage should be applied to this pin. (2) An external resistor divider is required to limit the voltage applied to the device pin. For more information, see Section 8.2.4, USB VBUS Design Guidelines. AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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5.4 Pin Connectivity Requirements

This section describes connectivity requirements for package balls that have specific connectivity requirements and unused package balls. Note All power balls must be supplied with the voltages specified in the Recommended Operating Conditions section, unless otherwise specified. Note For additional clarification, "leave unconnected" or "no connect" (NC) means no signal traces can be connected to these device ball numbers. Table 5-85. Connectivity Requirements (ALV/ANI Package) BALL NUMBER BALL NAME CONNECTION REQUIREMENTS A20 D11 MCU_SAFETY_ERRORn TRSTn Each of these balls must be connected to VSS through separate external pull resistors to ensure the inputs associated with these balls are held to a valid logic low level if a PCB signal trace is connected and not actively driven by an attached device. The internal pull-down can be used to hold a valid logic low level if no PCB signal trace is connected to the ball. D10 E10 B12 E18 B11 C11 C12 EMU0 EMU1 MCU_RESETz RESET_REQz TCK TDI TMS Each of these balls must be connected to the corresponding power supply(1) through separate external pull resistors to ensure the inputs associated with these balls are held to a valid logic high level if a PCB signal trace is connected and not actively driven by an attached device. The internal pull-up can be used to hold a valid logic high level if no PCB signal trace is connected to the ball. A18 B18 A10 I2C0_SCL I2C0_SDA MCU_I2C0_SCL MCU_I2C0_SDA Each of these balls must be connected to the corresponding power supply(1) or VSS through separate external pull resistors to ensure the inputs associated with these balls are held to a valid logic high or low level as appropriate for the selected signal function. T20 U21 T18 U20 U18 U19 V20 V21 V19 T17 R16 W20 W21 V18 Y21 Y20 GPMC0_AD0 GPMC0_AD1 GPMC0_AD2 GPMC0_AD3 GPMC0_AD4 GPMC0_AD5 GPMC0_AD6 GPMC0_AD7 GPMC0_AD8 GPMC0_AD9 GPMC0_AD10 GPMC0_AD11 GPMC0_AD12 GPMC0_AD13 GPMC0_AD14 GPMC0_AD15 Each of these balls must be connected to the corresponding power supply(1) or VSS through separate external pull resistors to ensure the inputs associated with these balls are held to a valid logic high or low level as appropriate to select the desired device boot mode. J13 G20 F20 E21, D20 G21 F21 F19 E20 J15 J16 VDDA_ADC ADC0_AIN0 ADC0_AIN1 ADC0_AIN2 ADC0_AIN3 ADC0_AIN4 ADC0_AIN5 ADC0_AIN6 ADC0_AIN7 ADC0_REFP ADC0_REFN If the entire ADC0 is not used, each of these balls must be connected directly to VSS. www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 95 Product Folder Links: AM2434 AM2432 AM2431

Table 5-85. Connectivity Requirements (ALV/ANI Package) (continued) BALL NUMBER BALL NAME CONNECTION REQUIREMENTS G20 F20 E21 D20 G21 F21 F19 E20 ADC0_AIN0 ADC0_AIN1 ADC0_AIN2 ADC0_AIN3 ADC0_AIN4 ADC0_AIN5 ADC0_AIN6 ADC0_AIN7 Any unused ADC0_AIN[7:0] ball must be pulled to VSS through a resistor or connected directly to VSS when VDDA_ADC is connected to a power source. J6, VDDS_DDR VDDS_DDR VDDS_DDR VDDS_DDR VDDS_DDR VDDS_DDR VDDS_DDR_C If DDRSS0 is not used, each of these balls must be connected directly to VSS. AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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Table 5-85. Connectivity Requirements (ALV/ANI Package) (continued) BALL NUMBER BALL NAME CONNECTION REQUIREMENTS DDR0_ACT_n DDR0_ALERT_n DDR0_CAS_n DDR0_PAR DDR0_RAS_n DDR0_WE_n DDR0_A0 DDR0_A1 DDR0_A2 DDR0_A3 DDR0_A4 DDR0_A5 DDR0_A6 DDR0_A7 DDR0_A8 DDR0_A9 DDR0_A10 DDR0_A11 DDR0_A12 DDR0_A13 DDR0_BA0 DDR0_BA1 DDR0_BG0 DDR0_BG1 DDR0_CAL0 DDR0_CK0 DDR0_CK0_n DDR0_CKE0 DDR0_CKE1 DDR0_CS0_n DDR0_CS1_n DDR0_DM0 DDR0_DM1 DDR0_DQ0 DDR0_DQ1 DDR0_DQ2 DDR0_DQ3 DDR0_DQ4 DDR0_DQ5 DDR0_DQ6 DDR0_DQ7 DDR0_DQ8 DDR0_DQ9 DDR0_DQ10 DDR0_DQ11 DDR0_DQ12 DDR0_DQ13 DDR0_DQ14 DDR0_DQ15 DDR0_DQS0 DDR0_DQS0_n DDR0_DQS1 DDR0_DQS1_n DDR0_ODT0 DDR0_ODT1 DDR0_RESET0_n If DDRSS0 is not used, leave unconnected. Note: The DDR0 pins in this list can only be left unconnected when VDDS_DDR and VDDS_DDR_C are connected to VSS. The DDR0 pins must be connected as defined in the AM64x\\AM243x DDR Board Design and Layout Guidelines, when VDDS_DDR and VDDS_DDR_C are connected to a power source. K13 H14 VDD_MMC0 VDD_DLL_MMC0 If MMC0 is not used, each of these balls must be connected to the same power source as VDD_CORE. K14 VDDS_MMC0 If MMC0 is not used, each of these balls must be connected to any 1.8V power source that does not violate device power supply sequencing requirements. www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 97 Product Folder Links: AM2434 AM2432 AM2431

Table 5-85. Connectivity Requirements (ALV/ANI Package) (continued) BALL NUMBER BALL NAME CONNECTION REQUIREMENTS F18 G18 J21 G19 K20 J20 J18 J17 H17 H19 H18 G17 MMC0_CALPAD MMC0_CLK MMC0_CMD MMC0_DS MMC0_DAT0 MMC0_DAT1 MMC0_DAT2 MMC0_DAT3 MMC0_DAT4 MMC0_DAT5 MMC0_DAT6 MMC0_DAT7 If MMC0 is not used, each of these balls must be left unconnected. H15 K15 VDDA_3P3_SDIO CAP_VDDSHV_MMC1 If SDIO_LDO is not used to power VDDSHV5, each of these balls must be connected directly to VSS. P12 P13 P11 R14 VDDA_0P85_SERDES0 VDDA_0P85_SERDES0 VDDA_0P85_SERDES0_C VDDA_1P8_SERDES0 If SERDES0 is not used and the device boundary scan function is required, each of these balls must be connected to valid power sources. If SERDES0 is not used and the device boundary scan function is not required, each of these balls can alternatively be connected directly to VSS. T13 W16 W17 Y15 Y16 AA16 AA17 SERDES0_REXT SERDES0_REFCLK0N SERDES0_REFCLK0P SERDES0_RX0_N SERDES0_RX0_P SERDES0_TX0_N SERDES0_TX0_P If SERDES0 is not used, leave unconnected. Note: The SERDES0_REXT pin can only be left unconnected when VDDA_0P85_SERDES0, VDDA_0P85_SERDES0_C, and VDDA_1P8_SERDES0 are connected to VSS. The SERDES0_REXT pin must be connected to VSS through the appropriate external resistor when VDDA_0P85_SERDES0, VDDA_0P85_SERDES0_C, and VDDA_1P8_SERDES0 are connected to power sources. T12 R15 R13 VDDA_0P85_USB0 VDDA_1P8_USB0 VDDA_3P3_USB0 If USB0 is not used, each of these balls must be connected directly to VSS. AA20 AA19 U16 U17 T14 USB0_DM USB0_DP USB0_ID USB0_RCALIB USB0_VBUS If USB0 is not used, leave unconnected. Note: The USB0_RCALIB pin can only be left unconnected when VDDA_0P85_USB0, VDDA_1P8_USB0, and VDDA_3P3_USB0 are connected to VSS. The USB0_RCALIB pin must be connected to VSS through the appropriate external resistor when VDDA_0P85_USB0, VDDA_1P8_USB0, and VDDA_3P3_USB0 are connected to power sources. K10 VMON_VSYS If VMON_VSYS is not used, this ball must be connected directly to VSS. E12 VMON_1P8_SOC If VMON_1P8_SOC is not used to monitor the SOC power rail, this ball must remain connected to a 1.8V power rail. K16 F13 F14 VMON_1P8_MCU VMON_3P3_MCU VMON_3P3_SOC If VMON_1P8_MCU, VMON_3P3_MCU, and VMON_3P3_SOC are not used to monitor the MCU and SOC power rails, these balls must remain connected to the respective 1.8V and 3.3V power rails or connected directly to VSS. (1) To determine which power supply is associated with any IO, see the POWER column of the Pin Attributes table. AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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Table 5-86. Connectivity Requirements (ALX Package) BALL NUMBER BALL NAME CONNECTION REQUIREMENTS B20 MCU_SAFETY_ERRORn TRSTn Each of these balls must be connected to VSS through separate external pull resistors to ensure these balls are held to a valid logic low level if a PCB signal trace is connected and not actively driven by an attached device. The internal pull-down can be used to hold a valid logic low level if no PCB signal trace is connected to the ball. C17 EMU0 EMU1 MCU_RESETz RESET_REQz TCK TDI TMS Each of these balls must be connected to the corresponding power supply(1) through separate external pull resistors to ensure these balls are held to a valid logic high level if a PCB signal trace is connected and not actively driven by an attached device. The internal pull-up can be used to hold a valid logic high level if no PCB signal trace is connected to the ball. B16 B15 I2C0_SCL I2C0_SDA Each of these balls must be connected to the corresponding power supply(1) through separate external pull resistors to ensure these balls are held to a valid logic high level. G17 H17 H21 F19 F21, F20 H20 E21 G20 E20 VDDA_ADC VDDA_ADC ADC0_AIN0 ADC0_AIN1 ADC0_AIN2 ADC0_AIN3 ADC0_AIN4 ADC0_AIN5 ADC0_AIN6 ADC0_AIN7 If the entire ADC0 is not used, each of these balls must be connected directly to VSS. H21 F19 F21 F20 H20 E21 G20 E20 ADC0_AIN0 ADC0_AIN1 ADC0_AIN2 ADC0_AIN3 ADC0_AIN4 ADC0_AIN5 ADC0_AIN6 ADC0_AIN7 Any unused ADC0_AIN[7:0] ball must be pulled to VSS through a resistor or connected directly to VSS when VDDA_ADC is connected to a power source. K15 J17 VDDA_3P3_SDIO CAP_VDDSHV_MMC1 If SDIO_LDO is not used to power VDDSHV5, each of these balls must be connected directly to VSS. V16 U15 U16 VDDA_0P85_USB0 VDDA_1P8_USB0 VDDA_3P3_USB0 If USB0 is not used, each of these balls must be connected directly to VSS. AA17 AA16 Y17 W17 V18 USB0_DM USB0_DP USB0_ID USB0_RCALIB USB0_VBUS If USB0 is not used, leave unconnected. Note: The USB0_RCALIB pin can only be left unconnected when VDDA_0P85_USB0, VDDA_1P8_USB0, and VDDA_3P3_USB0 are connected to VSS. The USB0_RCALIB pin must be connected to VSS through the appropriate external resistor when VDDA_0P85_USB0, VDDA_1P8_USB0, and VDDA_3P3_USB0 are connected to a power source. G13 VMON_VSYS If VMON_VSYS is not used, this ball must be connected directly to VSS. F14 VMON_1P8_SOC If VMON_1P8_SOC is not used to monitor the SOC power rail, this ball must remain connected to a 1.8V power rail. E15 VMON_3P3_SOC If VMON_3P3_SOC is not used to monitor the SOC power rail, this ball must remain connected to a 3.3V power rail or connected directly to VSS. (1) To determine which power supply is associated with any IO, see POWER column of the Pin Attributes table. www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 99 Product Folder Links: AM2434 AM2432 AM2431

Internal pull resistors are weak and may not source enough current to maintain a valid logic level for some operating conditions. This can be the case when connected to components with leakage to the opposite logic level, or when external noise sources couple to signal traces attached to balls which are only pulled to a valid logic level by the internal resistor. Therefore, external pull resistors are recommended to hold a valid logic level on balls with external connections. Many of the device IOs are turned off by default and external pull resistors may be required to hold inputs of any attached device in a valid logic state until software initializes the respective IOs. The state of configurable device IOs are defined in the BALL STATE DURING RESET RX/TX/PULL and BALL STATE AFTER RESET RX/TX/PULL columns of the Pin Attributes table. Any IO with its input buffer (RX) turned off is allowed to float without damaging the device. However, any IO with its input buffer (RX) turned on shall never be allowed to float to any potential between V ILSS and V IHSS. The input buffer can enter a high-current state which could damage the IO cell if allowed to float between these levels. AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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6 Specifications

6.1 Absolute Maximum Ratings

over operating junction temperature range (unless otherwise noted)(1) (2) PARAMETER MIN MAX UNIT VDD_CORE Core supply -0.3 1.05 V VDDR_CORE RAM supply -0.3 1.05 V VDD_MMC0 MMC0 PHY core supply -0.3 1.05 V VDD_DLL_MMC0 MMC0 PLL analog supply -0.3 1.05 V VDDA_0P85_SERDES0 SERDES0 0.85V analog supply -0.3 1.05 V VDDA_0P85_SERDES0_C SERDES0 clock 0.85V analog supply -0.3 1.05 V VDDA_0P85_USB0 USB0 0.85V analog supply -0.3 1.05 V VDDS_DDR DDR PHY IO supply -0.3 1.57 V VDDS_DDR_C DDR clock IO supply -0.3 1.57 V VDDS_MMC0 MMC0 PHY IO supply -0.3 1.98 V VDDS_OSC MCU_OSC0 supply -0.3 1.98 V VDDA_MCU RCOSC, POR, POK, and MCU_ PLL0 analog supply -0.3 1.98 V VDDA_ADC0 ADC0 analog supply -0.3 1.98 V VDDA_PLL0 MAIN_PLL0, MAIN_PLL2, and MAIN_PLL14 analog supply -0.3 1.98 V VDDA_PLL1 MAIN_PLL8 and MAIN_PLL12 analog supply -0.3 1.98 V VDDA_PLL2 MAIN_PLL1 analog supply -0.3 1.98 V VDDA_1P8_SERDES0 SERDES0 1.8V analog supply -0.3 1.98 V VDDA_1P8_USB0 USB0 1.8V analog supply -0.3 1.98 V VDDA_TEMP0 TEMP0 analog supply -0.3 1.98 V VDDA_TEMP1 TEMP1 analog supply -0.3 1.98 V VPP eFuse ROM programming supply -0.3 1.98 V VDDSHV_MCU IO supply for IO MCU -0.3 3.63 V VDDSHV0 IO supply for IO group 0 -0.3 3.63 V VDDSHV1 IO supply for IO group 1 -0.3 3.63 V VDDSHV2 IO supply for IO group 2 -0.3 3.63 V VDDSHV3 IO supply for IO group 3 -0.3 3.63 V VDDSHV4 IO supply for IO group 4 -0.3 3.63 V VDDSHV5 IO supply for IO group 5 -0.3 3.63 V VDDA_3P3_USB0 USB0 3.3V analog supply -0.3 3.63 V VDDA_3P3_SDIO SDIO 3.3V analog supply -0.3 3.63 V Steady-state max voltage at all fail-safe IO pins MCU_PORz -0.3 3.63 V MCU_I2C0_SCL, MCU_I2C0_SDA, I2C0_SCL, I2C0_SDA, and EXTINTn When operating at 1.8V -0.3 1.98(3) V MCU_I2C0_SCL, MCU_I2C0_SDA, I2C0_SCL, I2C0_SDA, and EXTINTn When operating at 3.3V -0.3 3.63(3) V VMON_1P8_MCU and VMON_1P8_SOC -0.3 1.98 V VMON_3P3_MCU and VMON_3P3_SOC -0.3 3.63 V VMON_VSYS(4) -0.3 1.98 V www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 101 Product Folder Links: AM2434 AM2432 AM2431

over operating junction temperature range (unless otherwise noted)(1) (2) PARAMETER MIN MAX UNIT Steady-state max voltage at all other IO pins(5) USB0_VBUS(6) -0.3 3.6 V USB0_ID(7) -0.3 3.6 V All other IO pins -0.3 IO supply voltage + 0.3 V Transient overshoot and undershoot at IO pin 20% of IO supply voltage for up to 20% of the signal period (see Figure 6-1, IO Transient Voltage Ranges) 0.2 × VDD(8) V Latch-up performance I-Test(9) -100 +100 mA Over-Voltage (OV) Test(10) 1.5 x VDD(8) V TSTG Storage temperature(11) -55 +150 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside Section 6.4, Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and may affect device reliability, functionality, performance, and shorten the device lifetime. (2) All voltage values are with respect to VSS, unless otherwise noted. (3) The absolute maximum ratings for these fail-safe pins depends on their IO supply operating voltage. Therefore, this value is also defined by the maximum VIH value found in Section 6.7.1, I2C Open-Drain, and Fail-Safe (I2C OD FS) Electrical Characteristics, where the electrical characteristics table has separate parameter values for 1.8V mode and 3.3V mode. (4) The VMON_VSYS pin provides a way to monitor the system power supply. For more information, see Section 8.2.5, System Power Supply Monitor Design Guidelines. (5) This parameter applies to all IO pins which are not fail-safe and the requirement applies to all values of IO supply voltage. For example, if the voltage applied to a specific IO supply is 0 volts the valid input voltage range for any IO powered by that supply will be –0.3 to +0.3 volts. Special attention should be applied anytime peripheral devices are not powered from the same power sources used to power the respective IO supply. It is important the attached peripheral never sources a voltage outside the valid input voltage range, including power supply ramp-up and ramp-down sequences. (6) An external resistor divider is required to limit the voltage applied to this device pin. For more information, see Section 8.2.4, USB VBUS Design Guidelines. (7) The USB0_ID pin is connected to analog circuits in the USB0 PHY. The analog circuits source a known current while measuring voltage, to determine the resistance value (RID), if connected to VSS through a resistor. This pin should be connected to VSS for USB host operation, or left unconnected for USB device operation, and should never be connected to any external voltage source. (8) VDD is the voltage on the corresponding power-supply pin(s) for the IO. (9) For current pulse injection (I-Test):

Pins stressed per JEDEC JESD78 (Class II) and passed with specified I/O pin injection current and clamp voltage of 1.5 times maximum recommended I/O voltage and negative 0.5 times maximum recommended I/O voltage. (10) For over-voltage performance (Over-Voltage (OV) Test):
Supplies stressed per JEDEC JESD78 (Class II) and passed specified voltage injection. (11) For tape and reel the storage temperature range is [–10°C; +50°C] with a maximum relative humidity of 70%. TI recommends returning to ambient room temperature before usage. Fail-safe IO terminals are designed without any dependencies on the respective IO power supply voltage. This allows external voltage sources to be connected to these IO terminals when the respective IO power supplies are turned off. MCU_I2C0_SCL, MCU_I2C0_SDA, I2C0_SCL, I2C0_SDA, EXTINTn, VMON_1P8_MCU, VMON_1P8_SOC, VMON_3P3_MCU, VMON_3P3_SOC, and MCU_PORz are the only fail-safe IO terminals. All other IO terminals are not fail-safe and the voltage applied to them should be limited to the value defined by the Steady-state max voltage at all other IO pins parameter in Section 6.1, Absolute Maximum Ratings. AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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Overshoot = 20% of nominal IO supply voltage Undershoot = 20% of nominal IO supply voltage A. Tovershoot + Tundershoot < 20% of Tperiod Figure 6-1. IO Transient Voltage Range

6.2 ESD Ratings

V(ESD) Electrostatic discharge (ESD) Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000 V Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2) ±250 (1) JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process. www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 103 Product Folder Links: AM2434 AM2432 AM2431

6.3 Power-On Hours (POH)

The estimated POH data for continuous device operation at specific junction temperatures is provided in the table below. Temperature Rating Temperature Range JUNCTION TEMP (T J )(1) ESTIMATED(2) LIFETIME (POH)(3) A -40°C to 105°C 105°C 100000 I -40°C to 125°C 105°C 100000 110°C 64000 115°C 41000 120°C 26500 125°C 17500 (1) Unless specified, all voltage domains and operating conditions are supported in the device at the noted temperatures. (2) This information is provided solely for your convenience and does not extend or modify the warranty provided under TI's standard terms and conditions for TI semiconductor products. (3) POH is a function of voltage, temperature and time. Usage at higher voltages and temperatures results in a reduction in POH. AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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6.4 Recommended Operating Conditions

over operating junction temperature range (unless otherwise noted) SUPPLY NAME DESCRIPTION MIN(1) NOM MAX(1) UNIT VDD_CORE Core supply 0.81 0.85 0.895 V VDDR_CORE RAM supply 0.81 0.85 0.895 V VDD_MMC0(2) MMC0 PHY core supply 0.81 0.85 0.895 V VDD_DLL_MMC0(2) MMC0 PLL analog supply 0.81 0.85 0.895 V VDDA_0P85_SERDES0 SERDES0 0.85V analog supply 0.81 0.85 0.895 V VDDA_0P85_SERDES0_C SERDES0 clock 0.85V analog supply 0.81 0.85 0.895 V VDDA_0P85_USB0 USB0 0.85V analog supply 0.81 0.85 0.895 V VDDS_DDR(3) VDDS_DDR_C(3) DDR PHY IO supply DDR clock IO supply 1.1V Operation 1.06 1.1 1.17 V 1.2V Operation 1.14 1.2 1.26 V VDDS_MMC0 MMC0 PHY IO supply 1.71 1.8 1.89 V VDDS_OSC MCU_OSC0 supply 1.71 1.8 1.89 V VDDA_MCU RCOSC, POR, POK, and MCU_ PLL0 analog supply 1.71 1.8 1.89 V VDDA_ADC0 ADC0 analog supply 1.71 1.8 1.89 V VDDA_PLL0 MAIN_PLL0, MAIN_PLL2, and MAIN_PLL14 analog supply 1.71 1.8 1.89 V VDDA_PLL1 MAIN_PLL8 and MAIN_PLL12 analog supply 1.71 1.8 1.89 V VDDA_PLL2 MAIN_PLL1 analog supply 1.71 1.8 1.89 V VDDA_1P8_SERDES0 SERDES0 1.8V analog supply 1.71 1.8 1.89 V VDDA_1P8_USB0 USB0 1.8V analog supply 1.71 1.8 1.89 V VDDA_TEMP0 TEMP0 analog supply 1.71 1.8 1.89 V VDDA_TEMP1 TEMP1 analog supply 1.71 1.8 1.89 V VPP eFuse ROM programming supply see(4) see(4) see(4) V VMON_1P8_MCU Voltage monitor for 1.8V MCU power supply 1.71 1.8 1.89 V VMON_1P8_SOC Voltage monitor for 1.8V SoC power supply 1.71 1.8 1.89 V VDDA_3P3_USB0 USB0 3.3V analog supply 3.135 3.3 3.465 V VDDA_3P3_SDIO SDIO 3.3V analog supply 3.135 3.3 3.465 V VMON_3P3_MCU Voltage monitor for 3.3V MCU power supply 3.135 3.3 3.465 V VMON_3P3_SOC Voltage monitor for 3.3V SoC power supply 3.135 3.3 3.465 V VMON_VSYS Voltage monitor pin 0 see(5) 1 V USB0_VBUS USB Level-shifted VBUS Input 0 see(6) 3.465 V USB0_ID USB0 analog I/O for RID detection see(7) V VDDSHV_MCU Dual-voltage IO supply 1.8V Operation 1.71 1.8 1.89 V 3.3V Operation 3.135 3.3 3.465 V VDDSHV0 Dual-voltage IO supply 1.8V Operation 1.71 1.8 1.89 V 3.3V Operation 3.135 3.3 3.465 V VDDSHV1 Dual-voltage IO supply 1.8V Operation 1.71 1.8 1.89 V 3.3V Operation 3.135 3.3 3.465 V VDDSHV2 Dual-voltage IO supply 1.8V Operation 1.71 1.8 1.89 V 3.3V Operation 3.135 3.3 3.465 V VDDSHV3 Dual-voltage IO supply 1.8V Operation 1.71 1.8 1.89 V 3.3V Operation 3.135 3.3 3.465 V VDDSHV4 Dual-voltage IO supply 1.8V Operation 1.71 1.8 1.89 V 3.3V Operation 3.135 3.3 3.465 V www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 105 Product Folder Links: AM2434 AM2432 AM2431

over operating junction temperature range (unless otherwise noted) SUPPLY NAME DESCRIPTION MIN(1) NOM MAX(1) UNIT VDDSHV5 Dual-voltage IO supply 1.8V Operation 1.71 1.8 1.89 V 3.3V Operation 3.135 3.3 3.465 V TJ Operating junction temperature range 125°C Industrial –40 125 °CExtended Industrial –40 105 (1) The voltage at the device ball must never drop below the MIN voltage or above the MAX voltage for any amount of time during normal device operation. (2) VDD_MMC0 and VDD_DLL_MMC0 must be connected to the same power source as VDD_CORE. (3) VDDS_DDR and VDDS_DDR_C shall be sourced from the same power source. (4) Refer to the Recommended Operating Conditions for OTP eFuse Programming table for VPP supply voltages based on eFuse usage. (5) The VMON_VSYS pin provides a way to monitor the system power supply. For more information, see System Power Supply Monitor Design Guidelines. (6) An external resistor divider is required to limit the voltage applied to this device pin. For more information, see USB Design Guidelines. (7) The USB0_ID pin is connected to analog circuits in the USB0 PHY. The analog circuits source a known current while measuring voltage, to determine the resistance value (RID), if connected to VSS through a resistor. This pin must be connected to VSS for USB host operation, or left unconnected for USB device operation, and should never be connected to any external voltage source. AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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6.5 Operating Performance Points

This section describes the operating conditions of the device. This section also contains the description of each Operating Performance Point (OPP) for processor clocks and device core clocks. Table 6-1 describes the maximum supported frequency per speed grade for the device. Table 6-1. Speed Grade Maximum Frequency DEVICE(1) MAXIMUM FREQUENCY (MHz) SPEED GRADE R5FSS M4FSS INFRA (CBASS) ICSSG DMSC-L DDR4(2) LPDDR4(2) AM243x...ALV S 800 400 250 333 250 800 (DDR-1600) 800 (LPDDR-1600)AM243x...ANI AM243x...ALV K 400 400 250 333 250 800 (DDR-1600) 800 (LPDDR-1600)AM243x...ANI AM243x...ALX S 800 400 250 333 250 N/A N/A AM243x...ALX K 400 400 250 333 250 N/A N/A (1) N/A in this table stands for Not Applicable. (2) Maximum DDR Frequency will be limited based on the specific memory type (vendor) used in a system and by PCB implementation. Refer to AM64x\\AM243x DDR Board Design and Layout Guidelines for the proper PCB implementation to achieve maximum DDR frequency.

6.6 Power Consumption Summary

For information on the device power consumption, see the AM64x/AM243x Power Estimation Tool application note. www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 107 Product Folder Links: AM2434 AM2432 AM2431

6.7 Electrical Characteristics

The interfaces or signals described in Section 6.7.1 through Section 6.7.11 correspond to the interfaces or signals available in multiplexing mode 0 (Primary Function). All interfaces or signals multiplexed on the balls described in these tables have the same DC electrical characteristics, unless multiplexing involves a PHY and GPIO combination, in which case different DC electrical characteristics are specified for the different multiplexing modes (Functions).

6.7.1 I2C Open-Drain, and Fail-Safe (I2C OD FS) Electrical Characteristics

over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 1.8V MODE VIL Input Low Voltage 0.3 × VDD (1) V VILSS Input Low Voltage Steady State 0.3 × VDD (1) V VIH Input High Voltage 0.7 × VDD (1) 1.98(2) V VIHSS Input High Voltage Steady State 0.7 × VDD (1) V VHYS Input Hysteresis Voltage 0.1 × VDD (1) mV IIN (3) Input Leakage Current. VI = 1.8V 10 µA VI = 0V -10 µA VOL Output Low Voltage 0.2 × VDD (1) V IOL (4) Low Level Output Current VOL(MAX) 10 mA SRI (6) Input Slew Rate 18f(5) or 1.8E+6 V/s 3.3V MODE (7) VIL Input Low Voltage 0.3 × VDD (1) V VILSS Input Low Voltage Steady State 0.25 × VDD (1) V VIH Input High Voltage 0.7 × VDD (1) 3.63(2) V VIHSS Input High Voltage Steady State 0.7 × VDD (1) V VHYS Input Hysteresis Voltage 0.05 × VDD (1) mV IIN (3) Input Leakage Current. VI = 3.3V 10 µA VI = 0V -10 µA VOL Output Low Voltage 0.4 V IOL (4) Low Level Output Current VOL(MAX) 10 mA SRI (6) Input Slew Rate 33f(5) or 3.3E+6 8E+7 V/s (1) VDD stands for corresponding power supply. For more information on the power supply name and the corresponding ball(s), see POWER column of the Pin Attributes table. (2) This value also defines the Absolute Maximum Ratings value the IO. (3) This parameter defines leakage current when the terminal is operating as an input, undriven output, or both input and undriven output. (4) The IOL parameter defines the minimum Low Level Output Current for which the device is able to maintain the specified VOL value. The value defined by this parameter should be considered the maximum current available to a system implementation which needs to maintain the specified VOL value for attached components. (5) f = toggle frequency of the input signal in Hz. (6) This MIN parameter only applies to input signal functions which are not defined in their respective Timing and Switching Characteristics sections. Select the MIN parameter which results in the largest value. (7) I2C Hs-mode is not supported when operating the IO in 3.3V mode. AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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6.7.2 Fail-Safe Reset (FS RESET) Electrical Characteristics

over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIL Input Low Voltage 0.3 × VDDS_OSC V VILSS Input Low Voltage Steady State 0.3 × VDDS_OSC V VIH Input High Voltage 0.7 × VDDS_OSC V VIHSS Input High Voltage Steady State 0.7 × VDDS_OSC V VHYS Input Hysteresis Voltage 200 mV IIN (1) Input Leakage Current. VI = 1.8V 10 µA VI = 0V -10 µA SRI (3) Input Slew Rate 18f(2) or 1.8E+6 V/s (1) This parameter defines leakage current when the terminal is operating as an input. (2) f = toggle frequency of the input signal in Hz. (3) This MIN parameter only applies to input signal functions which are not defined in their respective Timing and Switching Characteristics sections. Select the MIN parameter which results in the largest value.

6.7.3 High-Frequency Oscillator (HFOSC) Electrical Characteristics

over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIL Input Low Voltage 0.35 × VDDS_OSC V VIH Input High Voltage 0.65 × VDDS_OSC V VHYS Input Hysteresis Voltage 49 mV IIN (1) Input Leakage Current. VI = 1.8V 10 µA VI = 0V -10 µA (1) This parameter defines leakage current when the terminal is operating as an input. www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 109 Product Folder Links: AM2434 AM2432 AM2431

6.7.4 eMMCPHY Electrical Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIL Input Low Voltage 0.35 × VDDS_MMC0 V VILSS Input Low Voltage Steady State 0.20 V VIH Input High Voltage 0.65 × VDDS_MMC0 V VIHSS Input High Voltage Steady State 1.4 V IIN (1) Input Leakage Current. VI = 1.8V 10 µA VI = 0V -10 µA RPU Pull-up Resistor 15 20 25 kΩ RPD Pull-down Resistor 15 20 25 kΩ VOL Output Low Voltage IOL = 2mA 0.30 V VOH Output High Voltage IOH = -2mA VDDS_MMC0 - 0.30 V SRI Input Slew Rate 5E+8 V/s (1) This parameter defines leakage current when the terminal is operating as an input, undriven output, or both input and undriven output, without internal pulls enabled. AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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6.7.5 SDIO Electrical Characteristics

over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 1.8V MODE VIL Input Low Voltage 0.58 V VILSS Input Low Voltage Steady State 0.58 V VIH Input High Voltage 1.27 V VIHSS Input High Voltage Steady State 1.7 V VHYS Input Hysteresis Voltage 150 mV IIN (1) Input Leakage Current. VI = 1.8V 10 µA VI = 0V -10 µA RPU Pull-up Resistor 40 50 60 kΩ RPD Pull-down Resistor 40 50 60 kΩ VOL Output Low Voltage 0.45 V VOH Output High Voltage VDD(2) - 0.45 V IOL (3) Low Level Output Current VOL(MAX) 4 mA IOH (3) High Level Output Current VOH(MIN) 4 mA SRI (5) Input Slew Rate 18f(4) or 1.8E+6 V/s 3.3V MODE VIL Input Low Voltage 0.25 × VDD(2) V VILSS Input Low Voltage Steady State 0.15 × VDD(2) V VIH Input High Voltage 0.625 × VDD(2) V VIHSS Input High Voltage Steady State 0.625 × VDD(2) V VHYS Input Hysteresis Voltage 150 mV IIN (1) Input Leakage Current. VI = 3.3V 10 µA VI = 0V -10 µA RPU Pull-up Resistor 40 50 60 kΩ RPD Pull-down Resistor 40 50 60 kΩ VOL Output Low Voltage 0.125 × VDD(2) V VOH Output High Voltage 0.75 × VDD(2) V IOL (3) Low Level Output Current VOL(MAX) 6 mA IOH (3) High Level Output Current VOH(MIN) 10 mA SRI (5) Input Slew Rate 33f(4) or 3.3E+6 V/s (1) This parameter defines leakage current when the terminal is operating as an input, undriven output, or both input and undriven output, without internal pulls enabled. (2) VDD stands for corresponding power supply. For more information on the power supply name and the corresponding ball(s), see POWER column of the Pin Attributes table. (3) The IOL and IOH parameters define the minimum Low Level Output Current and High Level Output Current for which the device is able to maintain the specified VOL and VOH values. Values defined by these parameters should be considered the maximum current available to a system implementation which needs to maintain the specified VOL and VOH values for attached components. (4) f = toggle frequency of the input signal in Hz. (5) This MIN parameter only applies to input signal functions which are not defined in their respective Timing and Switching Characteristics sections. Select the MIN parameter which results in the largest value. www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 111 Product Folder Links: AM2434 AM2432 AM2431

6.7.6 LVCMOS Electrical Characteristics

over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 1.8V MODE VIL Input Low Voltage 0.35 × VDD(1) V VILSS Input Low Voltage Steady State 0.3 × VDD(1) V VIH Input High Voltage 0.65 × VDD(1) V VIHSS Input High Voltage Steady State 0.85 × VDD(1) V VHYS Input Hysteresis Voltage 150 mV IIN (2) Input Leakage Current. VI = 1.8V 10 µA VI = 0V -10 µA RPU Pull-up Resistor 15 22 30 kΩ RPD Pull-down Resistor 15 22 30 kΩ VOL Output Low Voltage 0.45 V VOH Output High Voltage VDD(1) - 0.45 V IOL (3) Low Level Output Current VOL(MAX) 3 mA IOH (3) High Level Output Current VOH(MIN) 3 mA SRI (5) Input Slew Rate 18f(4) or 1.8E+6 V/s 3.3V MODE VIL Input Low Voltage 0.8 V VILSS Input Low Voltage Steady State 0.6 V VIH Input High Voltage 2.0 V VIHSS Input High Voltage Steady State 2.0 V VHYS Input Hysteresis Voltage 150 mV IIN (2) Input Leakage Current. VI = 3.3V 10 µA VI = 0V -10 µA RPU Pull-up Resistor 15 22 30 kΩ RPD Pull-down Resistor 15 22 30 kΩ VOL Output Low Voltage 0.4 V VOH Output High Voltage 2.4 V IOL (3) Low Level Output Current VOL(MAX) 5 mA IOH (3) High Level Output Current VOH(MIN) 9 mA SRI (5) Input Slew Rate 33f(4) or 3.3E+6 V/s (1) VDD stands for corresponding power supply. For more information on the power supply name and the corresponding ball(s), see POWER column of the Pin Attributes table. (2) This parameter defines leakage current when the terminal is operating as an input, undriven output, or both input and undriven output, without internal pulls enabled. (3) The IOL and IOH parameters define the minimum Low Level Output Current and High Level Output Current for which the device is able to maintain the specified VOL and VOH values. Values defined by these parameters should be considered the maximum current available to a system implementation which needs to maintain the specified VOL and VOH values for attached components. (4) f = toggle frequency of the input signal in Hz. (5) This MIN parameter only applies to input signal functions which are not defined in their respective Timing and Switching Characteristics sections. Select the MIN parameter which results in the largest value. AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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6.7.7 ADC12B Electrical Characteristics (ALV/ANI package)

over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Resolution (ALV/ANI package) 12 Bits VADC0_VREFP (1) Positive Reference Voltage, ADC0_VREFP 1.71 1.89 V VADC0_VREFN (1) Negative Reference Voltage, ADC0_VREFN VSS V VADC_AIN[7:0] Analog Input Voltage, ADC_AIN[7:0], Full-scale VSS VDDA_ADC0 V DNL Differential Non-Linearity > -1 +1 LSB INL Integral Non-Linearity -2 +2 LSB LSBGAIN-ERROR Gain Error ±10 LSB LSBOFFSET-ERROR Offset Error ±5 LSB SNR Signal-to-Noise Ratio Input Signal: 200kHz sine wave at -0.5dB Full Scale 70 dB THD Total Harmonic Distortion Input Signal: 200kHz sine wave at -0.5dB Full Scale -75 dB ZADC_AIN[0:7] Analog Input Impedance, ADC0_AIN[7:0] (2) Ω IIN Input Leakage ±10 μA CSMPL Sampling Capacitance 5.5 pF Sampling Dynamics FSMPL_CLK ADC0 SMPL_CLK Frequency 60 MHz tC Conversion Time 13 ADC0 SMPL_CLK Cycles tACQ Acquisition Time 2 257 ADC0 SMPL_CLK Cycles TR Sampling Rate ADC0 SMPL_CLK = 60MHz 4 MSPS General Purpose Input Mode (3) VIL Input Low Voltage 0.35 × VDDA_ADC0 V VILSS Input Low Voltage Steady State 0.35 × VDDA_ADC0 V VIH Input High Voltage 0.65 × VDDA_ADC0 V VIHSS Input High Voltage Steady State 0.65 × VDDA_ADC0 V VHYS Input Hysteresis Voltage 200 mV II (4) Input Leakage Current ADC0_AIN[7:0] = VDDA_ADC0 10 μA ADC0_AIN[7:0] = VSS -10 μA (1) The ADC0_REFP and ADC0_REFN reference inputs are analog inputs which must be treated like high transient power supply rails. ADC0_REFN is expected to be connected directly to the PCB ground plane along with all other VSS pins, and ADC0_REFP is connected to a power source capable of providing at least 4mA of current. ADC0_REFP can be connected to the same power source as VDDA_ADC0 if the voltage tolerance of the supply provides an acceptable accuracy for the ADC reference. A high frequency decoupling capacitor must be connected directly to the ADC0_REFP and ADC0_REFN pins with vias and be placed in the ball array on the back side of the PCB. www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 113 Product Folder Links: AM2434 AM2432 AM2431

(2) The ADC0_AIN pins are connected to an internal sampling capacitor for a user configurable acquisition time and acquisition frequency. The input impedance of the ADC0_AIN pins is a function of the sampling capacitance along with user configurable acquisition time and acquisition frequency. The designer must understand the time required for the source impedance of each ADC0_AIN pin to charge the internal sampling capacitor. The acquisition time must be set long enough for the internal sampling capacitor to settle to greater than 14 bits of accuracy. (3) ADC0 can be configured to operate in General Purpose Input mode, where all ADC0_AIN[7:0] inputs are globally enabled to operate as digital inputs via the ADC0_CTRL register (gpi_mode_en = 1). (4) This parameter defines leakage current when the terminal is operating as a general purpose input. AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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6.7.8 ADC10B Electrical Characteristics (ALX package)

over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Resolution (ALX package) 10 Bits VADC0_VREFP (1) Positive Reference Voltage 1.71 1.89 V VADC0_VREFN (1) Negative Reference Voltage VSS V VADC_AIN[7:0] Analog Input Voltage, ADC_AIN[7:0], Full-scale VSS VDDA_ADC0 V DNL Differential Non-Linearity > -1 +1 LSB INL Integral Non-Linearity -2 +2 LSB LSBGAIN-ERROR Gain Error ±10 LSB LSBOFFSET-ERROR Offset Error ±5 LSB SNR Signal-to-Noise Ratio Input Signal: 200kHz sine wave at -0.5 dB Full Scale 65 dB THD Total Harmonic Distortion Input Signal: 200kHz sine wave at -0.5 dB Full Scale -64 dB ZADC_AIN[0:7] Analog Input Impedance, ADC0_AIN[7:0] (2) Ω IIN Input Leakage ±10 μA CSMPL Sampling Capacitance 5.5 pF Sampling Dynamics FSMPL_CLK ADC0 SMPL_CLK Frequency 60 MHz tC Conversion Time 13 ADC0 SMPL_CLK Cycles tACQ Acquisition Time 2 257 ADC0 SMPL_CLK Cycles TR Sampling Rate ADC0 SMPL_CLK = 60MHz 4 MSPS General Purpose Input Mode (3) VIL Input Low Voltage 0.35 × VDDA_ADC0 V VILSS Input Low Voltage Steady State 0.35 × VDDA_ADC0 V VIH Input High Voltage 0.65 × VDDA_ADC0 V VIHSS Input High Voltage Steady State 0.65 × VDDA_ADC0 V VHYS Input Hysteresis Voltage 200 mV II Input Leakage Current ADC0_AIN[7:0] = VDDA_ADC0 or ADC0_AIN[7:0] = VSS 10 μA (1) ADC0_REFP and ADC0_REFN are directly connected to VDDA_ADC0 and VSS inside the SoC. References to ADC0_REFP and ADC0_REFN in this table must be considered as VDDA_ADC0 or VSS. (2) The ADC0_AIN pins are connected to an internal sampling capacitor for a user configurable acquisition time and acquisition frequency. The input impedance of the ADC0_AIN pins is a function of the sampling capacitance along with user configurable acquisition time and acquisition frequency. The designer must understand the time required for the source impedance of each ADC0_AIN pin to charge the internal sampling capacitor. The acquisition time must be set long enough for the internal sampling capacitor to settle to greater than 14 bits of accuracy. www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 115 Product Folder Links: AM2434 AM2432 AM2431

(3) ADC0 can be configured to operate in General Purpose Input mode, where all ADC0_AIN[7:0] inputs are globally enabled to operate as digital inputs via the ADC0_CTRL register (GPI_MODE_EN = 1).

6.7.9 USB2PHY Electrical Characteristics

USB0 interface is compliant with Universal Serial Bus Revision 2.0 Specification dated April 27, 2000 including ECNs and Errata as applicable.

6.7.10 SerDes PHY Electrical Characteristics

The PCIe interface is compliant with the electrical parameters specified in PCI Express ® Base Specification Revision 4.0, February 19, 2014. Note USB0 instance is compliant with the USB3.1 SuperSpeed Transmitter and Receiver Normative Electrical Parameters as defined in the Universal Serial Bus 3.1 Specification, Revision 1.0 , July 26, 2013.

6.7.11 DDR Electrical Characteristics

The DDR interface is compatible with DDR4 devices that are JESD79-4B standard-compliant, and LPDDR4 devices that are JESD209-4B standard-compliant AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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6.8 VPP Specifications for One-Time Programmable (OTP) eFuses

This section specifies the operating conditions required for programming the OTP eFuses..

6.8.1 Recommended Operating Conditions for OTP eFuse Programming

over operating junction temperature range (unless otherwise noted) PARAMETER DESCRIPTION MIN NOM MAX UNIT VDD_CORE Supply voltage range for the core domain during OTP operation See Recommended Operating Conditions V VPP Supply voltage range for the eFuse ROM domain during normal operation without hardware support to program eFuse ROM NC(1) V Supply voltage range for the eFuse ROM domain during normal operation with hardware support to program eFuse ROM 0 V Supply voltage range for the eFuse ROM domain during OTP programming(2) 1.71 1.8 1.89 V I(VPP) VPP current 400 mA SR(VPP) VPP Power-up Slew Rate 6E+4 V/s TJ Operating junction temperature range while programming eFuse ROM. 0 25 85 °C (1) NC stands for No Connect. (2) Supply voltage range includes DC errors and peak-to-peak noise.

6.8.2 Hardware Requirements

The following hardware requirements must be met when programming keys in the OTP eFuses:

The VPP power supply must be disabled when not programming OTP registers.
The VPP power supply must be ramped up after the proper device power-up sequence (for more details, see Section 6.11.2, Power Supply Sequencing).

6.8.3 Programming Sequence

Programming sequence for OTP eFuses:

Power on the board per the power-up sequencing. No voltage should be applied on the VPP terminal during power up and normal operation.
Load the OTP write software required to program the eFuse (contact your local TI representative for the OTP software package).
Apply the voltage on the VPP terminal according to the specification in Section 6.8.1.
Run the software that programs the OTP registers.
After validating the content of the OTP registers, remove the voltage from the VPP terminal.

6.8.4 Impact to Your Hardware Warranty

You accept that eFusing the TI Devices with security keys permanently alters them. You acknowledge that the eFuse can fail, for example, due to incorrect or aborted program sequence or if you omit a sequence step. Further the TI device may fail to secure boot if the error code correction check fails for the Production Keys or if the image is not signed and optionally encrypted with the current active Production Keys. These types of situations will render the TI device inoperable and TI will be unable to confirm whether the TI devices conformed to their specifications prior to the attempted eFuse. Consequently, TI will have no liability ( warranty or otherwise) for any TI devices that have been incorrectly eFused by customers. www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 117 Product Folder Links: AM2434 AM2432 AM2431

6.9 Thermal Resistance Characteristics

For operation and reliability concerns, the maximum junction temperature of the device must be equal to or less than the TJ value identified in Recommended Operating Conditions. Note The thermal parameters are generated following JEDEC standard JESD51x and are not intended for design parameters. If you need a more accurate thermal representation, download the processor thermal model and import your PCB design into a thermal simulation environment. For details on thermal implementation guidelines, see the Thermal Solution Guidance section.

6.9.1 Thermal Resistance Characteristics

Table 6-2. Thermal Resistance Characteristics TI recommends performing system level thermal simulations with worst case device power consumption. NO. PARAMETER DESCRIPTION ALX Package °C/W(1) (2) ALV Package °C/W(1) (2) ANI Package °C/W(1) (2) AIR FLOW (m/s)(3) T1 RΘJC Junction-to-case 4.8 0.98 3.0 N/A T2 RΘJB Junction-to-board 5.4 3.87 8.2 N/A T3 RΘJA Junction-to-free air 19.8 12.8 18.7 0 RΘJA Junction-to-moving air 14.1 9.2 13.8 1 T5 13 8.2 12.8 2 T6 12.3 7.6 12.3 3 ΨJT Junction-to-package top 0.06 0.53 0.08 0 T8 0.16 0.55 0.14 1 T9 0.21 0.57 0.17 2 T10 0.25 0.58 0.20 3 T11 ΨJB Junction-to-board 5.3 3.74 8.1 0 T12 4.95 3.5 7.6 1 T13 4.88 3.4 7.4 2 T14 4.83 3.3 7.3 3 (1) These values are based on a JEDEC defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a JEDEC defined 1S0P system) and is subject to change based on environment as well as application. For more information, see the EIA/JEDEC standards.

JESD51-2, Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-6, Integrated Circuit Thermal Test Method Environmental Conditions - Forced Convection (Moving Air)
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Packages (2) °C/W = degrees Celsius per watt. (3) m/s = meters per second. AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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6.10 Temperature Sensor Characteristics

This section summarizes the Voltage and Temperature Module (VTM) on die temperature sensor characteristics. For operation and reliability concerns, the maximum junction temperature of the device must be equal to or less than the TJ value identified in Recommended Operating Conditions. Table 6-3. VTM Die Temperature Sensor Characteristics PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Tacc VTM temperature sensor accuracy –40℃ to 125℃ –5 5 ℃ www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 119 Product Folder Links: AM2434 AM2432 AM2431

6.11 Timing and Switching Characteristics

This section describes the device Timing Parameters and Switching Characteristics. Note The default PADCONFIG settings for output slew rate and/or drive strength must be used to ensure compliance with timing specifications, unless specific instructions are provided otherwise. Modifying these settings may affect signal integrity and timing performance. For more information on the supported PADCONFIG options, see the Pad Configuration Registers section of the device TRM.

6.11.1 Timing Parameters and Information

The timing parameter symbols used in Timing and Switching Characteristics sections are created in accordance with JEDEC Standard 100. To shorten the symbols, some pin names and other related terminologies have been abbreviated in Table 6-4: Table 6-4. Timing Parameters Subscripts SYMBOL PARAMETER c Cycle time (period) d Delay time dis Disable time en Enable time h Hold time su Setup time START Start bit t Transition time v Valid time w Pulse duration (width) X Unknown, changing, or don't care level F Fall time H High L Low R Rise time V Valid IV Invalid AE Active Edge FE First Edge LE Last Edge Z High impedance AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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6.11.2 Power Supply Requirements

This section describes the power supply requirements to ensure proper device operation. Note All power balls must be supplied with the voltages specified in the Recommended Operating Conditions section, unless otherwise specified in Signal Descriptions and Pin Connectivity Requirements.

6.11.2.1 Power Supply Slew Rate Requirement

To maintain the safe operating range of the internal ESD protection devices, TI recommends limiting the maximum slew rate of supplies to be less than 18mV/µs. For instance, as shown in Figure 6-2, TI recommends having the supply ramp slew for a 1.8V supply of more than 100µs. Figure 6-2 describes the Power Supply Slew Rate Requirement in the device. t slew rate < 18 mV/ s slew > (supply value) / (18 ) or supply value × 55.6 s/Vμ μ μmV/ s Supply value SPRT740_ELCH_06 Figure 6-2. Power Supply Slew and Slew Rate www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 121 Product Folder Links: AM2434 AM2432 AM2431

6.11.2.2 Power Supply Sequencing

This section describes power sequence requirements using power sequence diagrams and associated notes. Each power sequence diagram demonstrates the sequential order expected for each device power rail. This is done by assigning each device power rail to one or more waveform. A dual-voltage power rail may be associated with more than one waveform and the associated note will describe which waveform is applicable. Each waveform defines a transition region for the associated power rails and shows its sequential relationship to the transition regions of other power rails. The notes associated with the power sequence diagram provides further detail of these requirements. See the Power-up Sequence section for details on power-up requirements, and the Power-down Sequence section for details on power-down requirements. Two types of power supply transition regions are used to simplify the power supply sequencing diagrams. The legends shown in Figure 6-3 and Figure 6-4 along with their descriptions are provided to clarify what each transition regions represents. Figure 6-3 defines a transition region with multiple power rails which may be sourced from multiple power supplies or a single power supply. Transitions shown within the transition region represent a use case where multiple power supplies are used to source power rails associated with this waveform, and these power supplies are allowed to ramp at different times within the region since they do not have any specific sequence requirement relative to each other. Figure 6-3. Multiple Power Supply Transition Legend Figure 6-4 defines a transition region with one or more power rails which must be sourced from a single common power supply. No transitions are shown within the region to represent a single ramp within the transition region. Figure 6-4. Single Common Power Supply Transition Legend AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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6.11.2.2.1 Power-Up Sequencing

Table 6-6 and Figure 6-6 describe the device power-up sequencing. Note All power rails must be turned off and decay below 300mV before initiating a new power-up sequence anytime a power rail drops below the minimum value defined in Recommended Operating Conditions. Table 6-5. Power-Up Sequencing – Supply / Signal Assignments See: Figure 6-6 WAVEFORM SUPPLY / SIGNAL NAME A VSYS(1), VMON_VSYS(2) B VDDSHV_MCU(3), VDDSHV0(3), VDDSHV1(3), VDDSHV2(3), VDDSHV3(3), VDDSHV4(3), VDDA_3P3_USB0, VMON_3P3_SOC(4), VMON_3P3_MCU(4) C VDDSHV_MCU(5), VDDSHV0(5), VDDSHV1(5), VDDSHV2(5), VDDSHV3(5), VDDSHV4(5), VDDA_MCU, VDDS_OSC, VDDA_ADC0, VDDA_PLL0, VDDA_PLL1, VDDA_PLL2, VDDA_1P8_SERDES0, VDDA_1P8_USB0, VMON_1P8_SOC(6), VMON_1P8_MCU(6), VDDA_TEMP0, VDDA_TEMP1, VDDS_MMC0 D VDDA_3P3_SDIO(7) (8), VDDSHV5(7) E VDDS_DDR(9), VDDS_DDR_C(9) G VDD_CORE(10), VDDA_0P85_USB0(10), VDDA_0P85_SERDES0(10), VDDA_0P85_SERDES0_C(10), VDD_MMC0(10), VDDA_DLL_MMC0(10), VDDR_CORE(10) (10) H VPP(11) I MCU_PORz J MCU_OSC0_XI, MCU_OSC0_XO (1) VSYS represents the name of a supply which sources power to the entire system. This supply is expected to be a pre-regulated supply that sources power management devices which source all other supplies. (2) VMON_VSYS input is used to monitor VSYS via an external resistor divider circuit. For more information, see Section 8.2.5, System Power Supply Monitor Design Guidelines. (3) VDDSHV_MCU and VDDSHVx [x=0-4] are dual voltage IO supplies which can be operated at 1.8V or 3.3V depending on the application requirements. When any of the VDDSHV_MCU or VDDSHVx [x=0-4] IO supplies are operating at 3.3V, they shall be ramped up with other 3.3V supplies during the 3.3V ramp period defined by this waveform. (4) The VMON_3P3_MCU and VMON_3P3_SOC inputs are used to monitor supply voltage and shall be connected to the respective 3.3V supply source. (5) VDDSHV_MCU and VDDSHVx [x=0-4] are dual voltage IO supplies which can be operated at 1.8V or 3.3V depending on the application requirements. When any of the VDDSHV_MCU or VDDSHVx [x=0-4] IO supplies are operating at 1.8V, they shall be ramped up with other 1.8V supplies during the 1.8V ramp period defined by this waveform. (6) The VMON_1P8_MCU and VMON_1P8_SOC inputs are used to monitor supply voltage and shall be connected to the respective 1.8V supply source. (7) VDDA_3P3_SDIO was designed to support power-up or power-down without any dependency on other power rails. VDDSHV5 is a dual voltage IO supply that was designed to support power-up, power-down, or dynamic voltage change without any dependency on other power rails. This capability is required to support UHS-I SD Cards. (8) VDDA_3P3_SDIO is the 3.3V power rail for the internal SDIO_LDO. This power rail must be sourced from the same 3.3V power supply that provides power to a UHS-I SD Card connected to MMC1, which allows the MMC1 IOs and the SD Card IOs to power-up and power-down at the same time when the SD Card power supply is powered off to reset the SD Card. For this use case the SDIO_LDO output (CAP_VDDSHV_MMC1) is used to power the VDDSHV5 IO power rail, which will ramp-up and ramp-down along with the VDDA_3P3_SDIO power rail. (9) VDDS_DDR and VDDS_DDR_C are expected to be powered by the same source such that they ramp together. (10) VDD_CORE, VDDA_0P85_USB0, VDDA_0P85_SERDES0, VDDA_0P85_SERDES0_C, VDD_MMC0, VDDA_DLL_MMC0, and VDDR_CORE are expected to be powered by the same 0.85V source such that they ramp together. (11) VPP is the 1.8V eFuse programming supply, which shall be left floating (HiZ) or grounded during power-up/down sequences and during normal device operation. This supply shall only be sourced while programming eFuse. www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 123 Product Folder Links: AM2434 AM2432 AM2431

VMON_VSYS Hi-Z Waveform <A> Waveform <B> Waveform <C> Waveform <D> Waveform <E> Waveform <G> AM243x_ELCH_01 Waveform <H> Waveform <I> Waveform <J> Figure 6-5. Power-Up Sequencing AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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6.11.2.2.2 Power-Down Sequencing

Table 6-6 and Figure 6-6 describe the device power-down sequencing. Note All power rails must be turned off and decay below 300mV before initiating a new power-up sequence anytime a power rail drops below the minimum value defined in Recommended Operating Conditions. Table 6-6. Power-Down Sequencing – Supply / Signal Assignments See: Figure 6-6 WAVEFORM SUPPLY / SIGNAL NAME A VSYS, VMON_VSYS B VDDSHV_MCU(1), VDDSHV0(1), VDDSHV1(1), VDDSHV2(1), VDDSHV3(1), VDDSHV4(1),VDDA_3P3_USB0, VMON_3P3_SOC, VMON_3P3_MCU C VDDSHV_MCU(2), VDDSHV0(2), VDDSHV1(2), VDDSHV2(2), VDDSHV3(2), VDDSHV4(2), VDDA_MCU, VDDS_OSC, VDDA_ADC0, VDDA_PLL0, VDDA_PLL1, VDDA_PLL2, VDDA_1P8_SERDES0, VDDA_1P8_USB0, VMON_1P8_SOC, VMON_1P8_MCU, VDDA_TEMP0, VDDA_TEMP1, VDDS_MMC0 D VDDA_3P3_SDIO(3) (4), VDDSHV5(3) E VDDS_DDR(5), VDDS_DDR_C(5) G VDD_CORE(6), VDDA_0P85_USB0(6), VDDA_0P85_SERDES0(6), VDDA_0P85_SERDES0_C(6), VDD_MMC0(6), VDDA_DLL_MMC0(6), VDDR_CORE(6) H VPP I MCU_PORz J MCU_OSC0_XI, MCU_OSC0_XO (1) VDDSHV_MCU and VDDSHVx [x=0-4] when operating at 3.3V. (2) VDDSHV_MCU and VDDSHVx [x=0-4] when operating at 1.8V. (3) VDDA_3P3_SDIO was designed to support power-up or power-down without any dependency on other power rails. VDDSHV5 is a dual voltage IO supply that was designed to support power-up, power-down, or dynamic voltage change without any dependency on other power rails. This capability is required to support UHS-I SD Cards. (4) VDDA_3P3_SDIO is the 3.3V power rail for the internal SDIO_LDO. This power rail must be sourced from the same 3.3V power supply that provides power to a UHS-I SD Card connected to MMC1, which allows the MMC1 IOs and the SD Card IOs to power-up and power-down at the same time when the SD Card power supply is powered off to reset the SD Card. For this use case the SDIO_LDO output (CAP_VDDSHV_MMC1) is used to power the VDDSHV5 IO power rail, which will ramp-up and ramp-down along with the VDDA_3P3_SDIO power rail. (5) VDDS_DDR and VDDS_DDR_C are expected to be powered by the same source such that they ramp together. (6) VDD_CORE, VDDA_0P85_USB0, VDDA_0P85_SERDES0, VDDA_0P85_SERDES0_C, VDD_MMC0, VDDA_DLL_MMC0, and VDDR_CORE are expected to be powered by the same 0.85V source such that they ramp together. www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 125 Product Folder Links: AM2434 AM2432 AM2431

Waveform <A> Waveform <B> Waveform <C> Waveform <D> Waveform <E> Waveform <G> Waveform <H> Waveform <I> Waveform <J> VSYS VMON_VSYS Horizontal dashed lines represent a use case where the system power remains turned on while the device power management solution is turned off. Hi-Z AM243x_ELCH_02 Figure 6-6. Power-Down Sequencing AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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6.11.3 System Timing

For more details about features and additional description information on the subsystem multiplexing signals, see the corresponding subsections within Signal Descriptions and Detailed Description sections.

6.11.3.1 Reset Timing

Tables and figures provided in this section define timing conditions, timing requirements, and switching characteristics for reset related signals. Table 6-7. Reset Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate VDD(1) = 1.8V 0.0018 V/ns VDD(1) = 3.3V 0.0033 V/ns OUTPUT CONDITIONS CL Output load capacitance 30 pF (1) VDD stands for corresponding power supply. For more information on the power supply name and the corresponding ball(s), see POWER column of the Pin Attributes table. Table 6-8. MCU_PORz Timing Requirements see Figure 6-7 NO. PARAMETER MIN MAX UNIT RST1 th(SUPPLIES_VALID - MCU_PORz) Hold time, MCU_PORz active (low) at Power-up after supplies valid (using external crystal circuit) 9500000 ns RST2 Hold time, MCU_PORz active (low) at Power-up after supplies valid and external clock stable (using external LVCMOS clock source) 1200 ns RST3 tw(MCU_PORzL) Pulse Width, MCU_PORz low after Power-up (without removal of Power or system reference clock MCU_OSC0_XI/XO) 1200 ns Figure 6-7. MCU_PORz Timing Requirements www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 127 Product Folder Links: AM2434 AM2432 AM2431

Table 6-9. MCU_RESETSTATz, and RESETSTATz Switching Characteristics see Figure 6-8 NO. PARAMETER MIN MAX UNIT RST4 td(MCU_PORzL-MCU_RESETSTATzL) Delay time, MCU_PORz active (low) to MCU_RESETSTATz active (low) 0 ns RST5 td(MCU_PORzH-MCU_RESETSTATzH) Delay time, MCU_PORz inactive (high) to MCU_RESETSTATz inactive (high) 6120*S(1) ns RST6 td(MCU_PORzL-RESETSTATzL) Delay time, MCU_PORz active (low) to RESETSTATz active (low) 0 ns RST7 td(MCU_PORzH-RESETSTATzH) Delay time, MCU_PORz inactive (high) to RESETSTATz inactive (high) 9195*S(1) ns RST8 tw(MCU_RESETSTATzL) Pulse Width, MCU_RESETSTATz low (SW_MCU_WARMRST) 966*S(1) ns RST9 tw(RESETSTATzL) Pulse Width, RESETSTATz low (SW_MCU_WARMRST, SW_MAIN_PORz, or SW_MAIN_WARMRST) 4040*S ns (1) S = MCU_OSC0_XI/XO clock period in ns. Figure 6-8. MCU_RESETSTATz, and RESETSTATz Switching Characteristics AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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Table 6-10. MCU_RESETz Timing Requirements see Figure 6-9 NO. PARAMETER MIN MAX UNIT RST10 tw(MCU_RESETzL) (1) Pulse Width, MCU_RESETz active (low) 1200 ns (1) This timing parameter is valid only after all supplies are valid and MCU_PORz has been asserted for the specified time. Table 6-11. MCU_RESETSTATz, and RESETSTATz Switching Characteristics see Figure 6-9 NO. PARAMETER MIN MAX UNIT RST11 td(MCU_RESETzL-MCU_RESETSTATzL) Delay time, MCU_RESETz active (low) to MCU_RESETSTATz active (low) 0 ns RST12 td(MCU_RESETzH-MCU_RESETSTATzH) Delay time, MCU_RESETz inactive (high) to MCU_RESETSTATz inactive (high) 966*S(1) ns RST13 td(MCU_RESETzL-RESETSTATzL) Delay time, MCU_RESETz active (low) to RESETSTATz active (low) 960 ns RST14 td(MCU_RESETzH-RESETSTATzH) Delay time, MCU_RESETz inactive (high) to RESETSTATz inactive (high) 4040*S(1) ns (1) S = MCU_OSC0_XI/XO clock period in ns. Figure 6-9. MCU_RESETz, MCU_RESETSTATz, and RESETSTATz Timing Requirements and Switching Characteristics www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 129 Product Folder Links: AM2434 AM2432 AM2431

Table 6-12. RESET_REQz Timing Requirements see Figure 6-10 NO. PARAMETER MIN MAX UNIT RST15 tw(RESET_REQzL) (1) Pulse Width, RESET_REQz active (low) 1200 ns (1) This timing parameter is valid only after all supplies are valid and MCU_PORz has been asserted for the specified time. Table 6-13. RESETSTATz Switching Characteristics see Figure 6-10 NO. PARAMETER MIN MAX UNIT RST16 td(RESET_REQzL-RESETSTATzL) Delay time, RESET_REQz active (low) to RESETSTATz active (low) 900*T(1) ns RST17 td(RESET_REQzH-RESETSTATzH) Delay time, RESET_REQz inactive (high) to RESETSTATz inactive (high) 4040*S(2) ns (1) T = Reset Isolation Time (Software Dependent) (2) S = MCU_OSC0_XI/XO clock period in ns. Figure 6-10. RESET_REQz and RESETSTATz Timing Requirements and Switching Characteristics Table 6-14. EMUx Timing Requirements see Figure 6-11 NO. PARAMETER MIN MAX UNIT RST18 tsu(EMUx-MCU_PORz) Setup time, EMU[1:0] before MCU_PORz inactive (high) 3*S(1) ns RST19 th(MCU_PORz - EMUx) Hold time, EMU[1:0] after MCU_PORz inactive (high) 10 ns (1) S = MCU_OSC0_XI/XO clock period in ns. Figure 6-11. EMUx Timing Requirements AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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Table 6-15. BOOTMODE Timing Requirements see Figure 6-12 NO. PARAMETER MIN MAX UNIT RST23 tsu(BOOTMODE-PORz_OUT) Setup time, BOOTMODE[15:00] valid before PORz_OUT high (External MCU PORz event or Software SW_MAIN_PORz) 3*S(1) ns RST24 th(PORz_OUT - BOOTMODE) Hold time, BOOTMODE[15:00] valid after PORz_OUT high (External MCU PORz event, or Software SW_MAIN_PORz) 0 ns (1) S = MCU_OSC0_XI/XO clock period in ns. Table 6-16. PORz_OUT Switching Characteristics see Figure 6-12 NO. PARAMETER MIN MAX UNIT RST25 td(MCU_PORzL-PORz_OUT) Delay time, MCU_PORz active (low) to PORz_OUT active (low) 0 ns RST26 td(MCU_PORzH-PORz_OUT) Delay time, MCU_PORz inactive (high) to PORz_OUT inactive (high) 1840 ns RST27 tw(PORz_OUTL) Pulse Width, PORz_OUT low (MCU_PORz or SW_MAIN_PORz) 1200 ns Figure 6-12. BOOTMODE Timing Requirements and PORz_OUT Switching Characteristics www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 131 Product Folder Links: AM2434 AM2432 AM2431

6.11.3.2 Safety Signal Timing

Tables and figures provided in this section define timing conditions and switching characteristics for MCU_SAFETY_ERRORn. Table 6-17. MCU_SAFETY_ERRORn Timing Conditions PARAMETER MIN MAX UNIT OUTPUT CONDITIONS CL Output load capacitance 30 pF Table 6-18. MCU_SAFETY_ERRORn Switching Characteristics see Figure 6-13 NO. PARAMETER MIN MAX UNIT SFTY1 tc(MCU_SAFETY_ERRORn) Cycle time minimum, MCU_SAFETY_ERRORn (PWM mode enabled) (P*H)+(P*L)(1) (3) (4) ns SFTY2 tw(MCU_SAFETY_ERRORn) Pulse width minimum, MCU_SAFETY_ERRORn active (PWM mode disabled)(5) P*R(1) (2) ns SFTY3 td (ERROR_CONDITION- MCU_SAFETY_ERRORnL) Delay time, ERROR CONDITION to MCU_SAFETY_ERRORn active(5) 50*P(1) ns (1) P = ESM functional clock (2) R = Error Pin Counter Pre-Load Register count value (3) H = Error Pin PWM High Pre-Load Register count value (4) L = Error Pin PWM Low Pre-Load Register count value (5) When PWM mode is enabled, MCU_SAFETY_ERRORn stops toggling after SFTY3 and will maintain its value (either high or low) until the error is cleared. When PWM mode is disabled, MCU_SAFETY_ERRORn is active low. Figure 6-13. MCU_SAFETY_ERRORn Timing Requirements and Switching Characteristics AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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6.11.3.3 Clock Timing

Tables and figures provided in this section define timing conditions, timing requirements, and switching characteristics for clock signals. Table 6-19. Clock Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate 0.5 V/ns OUTPUT CONDITIONS CL Output load capacitance 10ns ≤ tc < 20ns 10 pF 20ns ≤ tc 30 pF Table 6-20. Clock Timing Requirements see Figure 6-14 NO. MIN MAX UNIT CLK1 tc(EXT_REFCLK1) Cycle time minimum, EXT_REFCLK1 10 ns CLK2 tw(EXT_REFCLK1H) Pulse Duration, EXT_REFCLK1 high E*0.45(1) E*0.55(1) ns CLK3 tw(EXT_REFCLK1L) Pulse Duration, EXT_REFCLK1 low E*0.45(1) E*0.55(1) ns CLK1 tc(MCU_EXT_REFCLK0) Cycle time minimum, MCU_EXT_REFCLK0 10 ns CLK2 tw(MCU_EXT_REFCLK0H) Pulse Duration, MCU_EXT_REFCLK0 high F*0.45(2) F*0.55(2) ns CLK3 tw(MCU_EXT_REFCLK0L) Pulse Duration, MCU_EXT_REFCLK0 low F*0.45(2) F*0.55(2) ns (1) E = EXT_REFCLK1 cycle time (2) F = MCU_EXT_REFCLK0 cycle time Input Clock CLK1 CLK2 CLK3 Figure 6-14. Clock Timing Requirements www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 133 Product Folder Links: AM2434 AM2432 AM2431

Table 6-21. Clock Switching Characteristics see Figure 6-15 NO. PARAMETER MIN MAX UNIT CLK4 tc(SYSCLKOUT0) Cycle time minimum,SYSCLKOUT0 8 ns CLK5 tw(SYSCLKOUT0H) Pulse Duration, SYSCLKOUT0 high A*0.4(1) A*0.6(1) ns CLK6 tw(SYSCLKOUT0L) Pulse Duration, SYSCLKOUT0 low A*0.4(1) A*0.6(1) ns CLK4 tc(OBSCLK0) Cycle time minimum, OBSCLK0 5 ns CLK5 tw(OBSCLK0H) Pulse Duration, OBSCLK0 high B*0.45(2) B*0.55(2) ns CLK6 tw(OBSCLK0L) Pulse Duration,OBSCLK0 low B*0.45(2) B*0.55(2) ns CLK4 tc(CLKOUT0) Cycle time minimum, CLKOUT0 20 ns CLK5 tw(CLKOUT0H) Pulse Duration, CLKOUT0 high C*0.4(3) C*0.6(3) ns CLK6 tw(CLKOUT0L) Pulse Duration,CLKOUT0 low C*0.4(3) C*0.6(3) ns CLK4 tc(MCU_SYSCLKOUT0) Cycle time minimum, MCU_SYSCLKOUT0 10 ns CLK5 tw(MCU_SYSCLKOUT0H) Pulse Duration, MCU_SYSCLKOUT0 high G*0.4(4) G*0.6(4) ns CLK6 tw(MCU_SYSCLKOUT0L) Pulse Duration,MCU_SYSCLKOUT0 low G*0.4(4) G*0.6(4) ns CLK4 tc(MCU_OBSCLK0) Cycle time minimum, MCU_OBSCLK0 5 ns CLK5 tw(MCU_OBSCLK0H) Pulse Duration, MCU_OBSCLK0 high H*0.45(5) H*0.55(5) ns CLK6 tw(MCU_OBSCLK0L) Pulse Duration,MCU_OBSCLK0 low H*0.45(5) H*0.55(5) ns (1) A = SYSCLKOUT0 cycle time (2) B = OBSCLK0 cycle time (3) C = CLKOUT0 cycle time (4) G = MCU_SYSCLKOUT0 cycle time (5) H = MCU_OBSCLK0 cycle time Output Clock CLK4 CLK5 CLK6 Figure 6-15. Clock Switching Characteristics AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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6.11.4 Clock Specifications

6.11.4.1 Input Clocks / Oscillators

Various external clock inputs/outputs are needed to drive the device. Summary of these input clock signals is as follows:

MCU_OSC0_XI/MCU_OSC0_XO — Еxternal main crystal interface pins connected to the internal high- frequency oscillator (MCU_HFOSC0), which is the default clock source for internal reference clock MCU_HFOSC0_CLKOUT.
General purpose clock inputs – MCU_EXT_REFCLK0 — Optional external system clock input for MCU domain. – EXT_REFCLK1 — Optional external system clock input for MAIN domain. – SERDES0_REFCLK0P/N — Optional SERDES0 reference clock input for PCIe.
External CPTS reference clock inputs – CP_GEMAC_CPTS0_RFT_CLK — CPTS reference clock input. – CPTS_RFT_CLK — CPTS reference clock input. Figure 6-16 shows the external input clock sources and the output clocks to peripherals. DEVICE MCU_SYSCLKOUT0 Main Domain System Clock (MAIN_SYSCLK0) divided-by-4 External main crystal interface pins connected to internal oscillator which provides reference clock to PLLs within MCU domain and MAIN domain. MCU Domain System Clock (MCU_SYSCLK0) divided-by-4 MCU_OSC0_XI MCU_OSC0_XO SYSCLKOUT0 J7ES_CLOCK_01 TCK MCU_EXT_REFCLK0 / EXT_REFCLK1 Optional External System Clock Inputs - (MCU Domain) / (MAIN Domain) JTAG Clock Input CLKOUT CPTS Reference Clock Inputs CP_GEMAC_CPTS0_RFT_CLK / CPTS0_RFT_CLK CP_GEMAC_CPTS0_RFT_CLK / CPTS0_RFT_CLK MCU_PORz MCU_RESETz MCU Warm Reset Input / Device Warm Reset Input BOOTMODE[15:00] MCU Power ON Reset / Device Power ON Reset Boot Mode Configuration / Devices Select DDR0_CK0/DDR0_CK0_n DDR Differential Clock Outputs SERDES0_REFCLK0P/N Optional SERDES0 Reference Clock Input for PCIe MCU_OBSCLK0 / OBSCLK0 Observation Clock Outputs for MCU Domain Clock / MAIN Domain Clocks Reference Clock Output Figure 6-16. Input Clocks Interface For more information about Input clock interfaces, see Clocking section in Device Configuration chapter in the device TRM. www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 135 Product Folder Links: AM2434 AM2432 AM2431

6.11.4.1.1 MCU_OSC0 Internal Oscillator Clock Source

Figure 6-17 shows the recommended crystal circuit. All discrete components used to implement the oscillator circuit must be placed as close as possible to the MCU_OSC0_XI and MCU_OSC0_XO pins. Device MCU_OSC0_XOMCU_OSC0_XI CL1 Crystal CL2 AM65x_MCU_OSC_INT_01 PCB Ground Figure 6-17. MCU_OSC0 Crystal Implementation The crystal must be in the fundamental mode of operation and parallel resonant. Table 6-22 summarizes the required electrical constraints. Table 6-22. MCU_OSC0 Crystal Circuit Requirements PARAMETER MIN TYP MAX UNIT Fxtal Crystal Parallel Resonance Frequency 25 MHz Fxtal Crystal Frequency Stability and Tolerance Ethernet RGMII and RMII not used ±100 ppm Ethernet RGMII and RMII using derived clock ±50 CL1+PCBXI Capacitance of CL1 + CPCBXI 12 24 pF CL2+PCBXO Capacitance of CL2 + CPCBXO 12 24 pF CL Crystal Load Capacitance 6 12 pF Cshunt Crystal Circuit Shunt Capacitance ESRxtal = 30 Ω 25MHz 7 pF ESRxtal = 40 Ω 25MHz 5 pF ESRxtal = 50 Ω 25MHz 5 pF ESRxtal Crystal Effective Series Resistance (1) Ω (1) The maximum ESR of the crystal is a function of the crystal frequency and shunt capacitance. See the Cshunt parameter. AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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When selecting a crystal, the system design must consider temperature and aging characteristics of the crystal based on worst case environment and expected life expectancy of the system. Table 6-23 details the switching characteristics of the oscillator. Table 6-23. MCU_OSC0 Switching Characteristics - Crystal Mode PARAMETER PACKAGE MIN TYP MAX UNIT CXI XI Capacitance ALV 1.44 pF CXO XO Capacitance 1.52 pF CXIXO XI to XO Mutual Capacitance 0.01 pF CXI XI Capacitance ANI 1.435 pF CXO XO Capacitance 1.472 pF CXIXO XI to XO Mutual Capacitance 0.01 pF CXI XI Capacitance ALX 0.812 pF CXO XO Capacitance 0.821 pF CXIXO XI to XO Mutual Capacitance 0.01 pF ts Start-up Time 4 ms VDDS_OSC MCU_OSC0_XO tsX Time Voltage VSS VDDS_OSC (min.) VDD_CORE (min.) VSS VDD_CORE AM65x_MCU_OSC_STARTUP_02 Figure 6-18. MCU_OSC0 Start-up Time The crystal circuit must be designed such that it applies the appropriate capacitive load to the crystal, as defined by the crystal manufacturer. The capacitive load, C L, of this circuit is a combination of discrete capacitors CL1, C L2, and several parasitic contributions. PCB signal traces which connect crystal circuit components to MCU_OSC0_XI and MCU_OSC0_XO have parasitic capacitance to ground, C PCBXI and C PCBXO, where the PCB designer should be able to extract parasitic capacitance for each signal trace. The MCU_OSC0 circuits and device package have combined parasitic capacitance to ground, C PCBXI and CPCBXO, where these parasitic capacitance values are defined in Table 6-23. www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 137 Product Folder Links: AM2434 AM2432 AM2431

AM65x_MCU_OSC_CC_05 CPCBXI CPCBXO CL1 CL2 PCB Signal Traces Crystal Circuit Components MCU_OSC0_XO MCU_OSC0_XI CXI CXO Device Figure 6-19. Load Capacitance Load capacitors, C L1 and C L2 in Figure 6-17, should be chosen such that the below equation is satisfied. C L in the equation is the load specified by the crystal manufacturer. CL = [(CL1 + CPCBXI + CXI) × (CL2 + CPCBXO + CXO)] / [(CL1 + CPCBXI + CXI) + (CL2 + CPCBXO + CXO)] To determine the value of C L1 and C L2, multiply the capacitive load value C L by 2. Using this result, subtract the combined values of C PCBXI + C XI to determine the value of C L1 and the combined values of C PCBXO + C XO to determine the value of C L2. For example, if C L = 10pF, CPCBXI = 2.9pF, CXI = 0.5pF, CPCBXO = 3.7pF, CXO = 0.5pF, the value of C L1 = [(2C L) - (C PCBXI + C XI)] = [(2 × 10pF) - 2.9pF - 0.5pF)] = 16.6pF and C L2 = [(2C L) - (CPCBXO + CXO)] = [(2 × 10pF) - 3.7pF - 0.5pF)] = 15.8pF The crystal circuit must also be designed such that it does not exceed the maximum shunt capacitance for MCU_OSC0 operating conditions defined in Table 6-22. Shunt capacitance, C shunt, of the crystal circuit is a combination of crystal shunt capacitance and parasitic contributions. PCB signal traces which connect crystal circuit components to MCU_OSC0 have mutual parasitic capacitance to each other, C PCBXIXO, where the PCB designer should be able to extract mutual parasitic capacitance between these signal traces. The device package also has mutual parasitic capacitance, C XIXO, where this mutual parasitic capacitance value is defined in Table 6-23. PCB routing should be designed to minimize mutual capacitance between XI and XO signal traces. This is typically done by keeping signal traces short and not routing them in close proximity. Mutual capacitance can also be minimized by placing a ground trace between these signals when the layout requires them to be routed in close proximity. It is important to minimize the mutual capacitance on the PCB to provide as much margin as possible when selecting a crystal. AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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AM65x_MCU_OSC_SC_06 Device MCU_OSC0_XO MCU_OSC0_XI CPCBXIXO PCB Signal Traces Crystal Circuit Components CXIXOCO Figure 6-20. Shunt Capacitance A crystal should be chosen such that the below equation is satisfied. C O in the equation is the maximum shunt capacitance specified by the crystal manufacturer. Cshunt ≥ CO + CPCBXIXO + CXIXO For example, the equation would be satisfied when the crystal being used is 25MHz with an ESR = 30 Ω, CPCBXIXO = 0.04pF, CXIXO = 0.01pF, and shunt capacitance of the crystal is less than or equal to 6.95pF. www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 139 Product Folder Links: AM2434 AM2432 AM2431

6.11.4.1.2 MCU_OSC0 LVCMOS Digital Clock Source

Figure 6-21 shows the recommended oscillator connections when MCU_OSC0_XI is connected to a 1.8V LVCMOS square-wave digital clock source. Note 1. A DC steady-state condition is not allowed on MCU_OSC0_XI when the oscillator is powered up. This is not allowed because MCU_OSC0_XI is internally AC coupled to a comparator that can enter an unknown state when DC is applied to the input. Therefore, application software must power down MCU_OSC0 any time MCU_OSC0_XI is not toggling between logic states. 2. The PCB trace length connecting the LVCMOS clock source to MCU_OSC0_XI should be minimized. This reduces capacitive loading and decreases probability of external noise sources coupling into the clock signal. Reduced capacitive loading improves rise/fall times of the clock signal which reduces the probability of jitter being introduced in the system. 3. The LVCMOS clock signal sourcing the MCU_OSC0_XI input must have monotonic transitions. The clock source should be connected to MCU_OSC0_XI with a point-to-point connection, via a series termination resistor placed near the clock source. The series termination resistor value should match the clock source output impedance to the transmission line impedance. For example, the series termination resistor value needs to be 20 ohms if the clock source has an output impedance of 30 ohms and the PCB signal trace has a characteristic impedance of 50 ohms. This allows the reflection that returns from the far end of the un-terminated transmission line to be completely absorbed such that is does not introduce any non-monotonic events on the signal. Device MCU_OSC0_XOMCU_OSC0_XI PCB Ground Figure 6-21. 1.8V LVCMOS-Compatible Clock Input AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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Table 6-24. MCU_OSC0 LVCMOS Digital Clock Source Requirements PARAMETER MIN TYP MAX UNIT Fxtal Frequency 25 MHz Frequency Stability and Tolerance Ethernet RGMII and RMII not used ±100 ppm Ethernet RGMII and RMII using derived clock ±50 DC Duty Cycle 45 55 % tR/F Rise/Fall Time (10%-90% rise, 90%-10% fall) 4(1) ns JPeriod(RMS) Period Jitter, RMS (100k samples) 20 ps JPeriod(PK-PK) Period Jitter, Peak to Peak (100k samples) 300 ps JPhase(RMS) Phase Jitter, RMS (BW 100Hz to 1MHz) 10(2) ps PN Phase Noise(3) 100Hz –92.3 dBc/Hz 1kHz –112.3 10kHz –132.3 100kHz –142.3 1MHz –152.3 (1) Most LVCMOS oscillator datasheets define their maximum Output Rise/Fall times with a capacitive load much larger than the actual load that will be applied by the combined PCB trace capacitance and MCU_OSC0_XI input capacitance. It should not be difficult to find a LVCMOS oscillator that meets this requirement. However, the system designer must confirm the LVCMOS oscillator selected will provide the appropriate rise/fall time to MCU_OSC0_XI input. (2) Most LVCMOS oscillator datasheets define their max RMS Phase Jitter using a larger bandwidth integration range than required by this device. To get a more appropriate value, it may be necessary to contact the LVCMOS oscillator manufacture and ask them to provide a maximum RMS Phase Jitter using the same bandwidth integration range that has been defined for this parameter. (3) The Phase Noise parameter is only applicable when the SerDes PHY is used for USB SuperSpeed, or PCIe operating without a common external clock source. www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 141 Product Folder Links: AM2434 AM2432 AM2431

6.11.4.2 Output Clocks

The device provides several system clock outputs. Summary of these output clocks are as follows:

MCU_SYSCLKOUT0 – MCU_SYSCLKOUT0 is the MCU domain system clock (MCU_SYSCK0) divided-by-4. This clock output is provided for test and debug purposes only.
MCU_OBSCLK0 – Observation clock output for test and debug purposes only.
SYSCLKOUT0 – SYSCLKOUT0 is the MAIN domain system clock (MAIN_SYSCLK0) divided-by-4. This clock output is provided for test and debug purposes only.
CLKOUT0 – CLKOUT0 is the Ethernet subsystem clock (MAIN_PLL0_HSDIV4_CLKOUT) divided-by-5 or divided- by-10. This clock output was provided to source to the external PHY. When configured to operate as the RMII Clock source (50MHz) the signal must also be routed back to the RMII_REF_CLK pin for proper device operation.
OBSCLK0 – Observation clock output for test and debug purposes only.
GPMC_FCLK_MUX – GPMC_FCLK_MUX is the GPMC0 functional clock (GPMC_FCLK). This clock is provided as an alternative GPMC interface clock when attached devices require a continuous running clock. For more information, see Clock Outputs section in Clocking chapter and GPMC Clock Configuration section in Peripherals chapter in the device TRM.

6.11.4.3 PLLs

Power is supplied to the Phase-Locked Loop circuits (PLLs) by internal regulators that derive their power from off-chip power-sources. There is one PLL in the MCU domain:

MCU_PLL0 (MCU PLL) There are six PLLs in the MAIN domain:
MAIN_PLL0 (MAIN PLL)
MAIN_PLL1 (PER0 PLL)
MAIN_PLL2 (PER1 PLL)
MAIN_PLL8 (ARM0 PLL)
MAIN_PLL12 (DDR PLL)
MAIN_PLL14 (R5F PLL) Note For more information, see:
Device Configuration / Clocking / PLLs section in the device TRM.
Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem - Gigabit (PRU_ICSSG) section in the device TRM. Note The input reference clock (MCU_OSC0_XI / MCU_OSC0_XO) is specified and the lock time is ensured by the PLL controller, as documented in the Device Configuration chapter in the device TRM. AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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6.11.4.4 Recommended System Precautions for Clock and Control Signal Transitions

All clock and strobe signals must transition between V IH and V IL (or between V IL and V IH) in a monotonic manner. Monotonic transitions are more likely to occur with fast signal transitions. It is easy for noise to create non- monotonic events on a signal with slow transitions. Therefore, avoid slow signal transitions on all clock and control signals since they are more likely to generate glitches inside the device. www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 143 Product Folder Links: AM2434 AM2432 AM2431

6.11.5 Peripherals

6.11.5.1 CPSW3G

For more details about features and additional description information on the device Gigabit Ethernet MAC, see the corresponding subsections within Signal Descriptions and Detailed Description sections. Note CPSW3G MDIO0, CPSW3G RMII1, CPSW3G RMII2, and CPSW3G RGMII1 have one or more signals which can be multiplexed to more than one pin. Timing requirements and switching characteristics defined in this section are only valid for specific pin combinations known as IOSETs. Valid pin combinations or IOSETs for these interfaces can be found in the tables of the CPSW3G IOSETs section.

6.11.5.1.1 CPSW3G MDIO Timing

Table 6-25 , Table 6-26 , Table 6-27 , and Figure 6-22 present timing conditions, timing requirements, and switching characteristics for CPSW3G MDIO. Table 6-25. CPSW3G MDIO Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate 0.9 3.6 V/ns OUTPUT CONDITIONS CL Output load capacitance 10 470 pF PCB CONNECTIVITY REQUIREMENTS td(Trace Delay) Propagation delay of each trace 0 5 ns td(Trace Mismatch Delay) Propagation delay mismatch across all traces 1 ns Table 6-26. CPSW3G MDIO Timing Requirements see Figure 6-22 NO. PARAMETER MIN MAX UNIT MDIO1 tsu(MDIO_MDC) Setup time, MDIO[x]_MDIO valid before MDIO[x]_MDC high 45 ns MDIO2 th(MDC_MDIO) Hold time, MDIO[x]_MDIO valid after MDIO[x]_MDC high 0 ns Table 6-27. CPWS3G MDIO Switching Characteristics see Figure 6-22 NO. PARAMETER MIN MAX UNIT MDIO3 tc(MDC) Cycle time, MDIO[x]_MDC 400 ns MDIO4 tw(MDCH) Pulse Duration, MDIO[x]_MDC high 160 ns MDIO5 tw(MDCL) Pulse Duration, MDIO[x]_MDC low 160 ns MDIO7 td(MDC_MDIO) Delay time, MDIO[x]_MDC low to MDIO[x]_MDIO valid -10 10 ns AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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MDIO[x]_MDC MDIO[x]_MDIO (input) MDIO[x]_MDIO (output) CPSW2G_MDIO_TIMING_01 Figure 6-22. CPSW3G MDIO Timing Requirements and Switching Characteristics www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 145 Product Folder Links: AM2434 AM2432 AM2431

6.11.5.1.2 CPSW3G RMII Timing

Table 6-28 , Table 6-29 , Figure 6-23 , Table 6-30 , Figure 6-24 Table 6-31 , and Figure 6-25 present timing conditions, timing requirements, and switching characteristics for CPSW3G RMII. Table 6-28. CPSW3G RMII Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate VDD(1) = 1.8V 0.18 5 V/ns VDD(1) = 3.3V 0.4 5 V/ns OUTPUT CONDITIONS CL Output load capacitance 3 25 pF (1) VDD stands for corresponding power supply. For more information on the power supply name and the corresponding ball(s), see POWER column of the Pin Attributes table. Table 6-29. RMII[x]_REF_CLK Timing Requirements – RMII Mode see Figure 6-23 NO. PARAMETER DESCRIPTION MIN MAX UNIT RMII1 tc(REF_CLK) Cycle time, RMII[x]_REF_CLK 19.999 20.001 ns RMII2 tw(REF_CLKH) Pulse Duration, RMII[x]_REF_CLK High 7 13 ns RMII3 tw(REF_CLKL) Pulse Duration, RMII[x]_REF_CLK Low 7 13 ns RMII[x]_REF_CLK RMII2 RMII3 RMII1 Figure 6-23. CPSW3G RMII[x]_REF_CLK Timing Requirements – RMII Mode Table 6-30. RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RX_ER Timing Requirements – RMII Mode see Figure 6-24 NO. PARAMETER DESCRIPTION MIN MAX UNIT RMII4 tsu(RXD-REF_CLK) Setup time, RMII[x]_RXD[1:0] valid before RMII[x]_REF_CLK 4 ns tsu(CRS_DV-REF_CLK) Setup time, RMII[x]_CRS_DV valid before RMII[x]_REF_CLK 4 ns tsu(RX_ER-REF_CLK) Setup time, RMII[x]_RX_ER valid before RMII[x]_REF_CLK 4 ns RMII5 th(REF_CLK-RXD) Hold time RMII[x]_RXD[1:0] valid after RMII[x]_REF_CLK 2 ns th(REF_CLK-CRS_DV) Hold time, RMII[x]_CRS_DV valid after RMII[x]_REF_CLK 2 ns th(REF_CLK-RX_ER) Hold time, RMII[x]_RX_ER valid after RMII[x]_REF_CLK 2 ns RMII4 RMII5 RMII[x]_ _REF CLK RMII[x]_RXD[1:0], RMII[x]_CRS_DV, RMII[x]_RX_ER Figure 6-24. CPSW3G RMII[x]_RXD[1:0], RMII[x]_CRS_DV, RMII[x]_RX_ER Timing Requirements – RMII Mode AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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Table 6-31. RMII[x]_TXD[1:0], and RMII[x]_TX_EN Switching Characteristics – RMII Mode see Figure 6-25 NO. PARAMETER DESCRIPTION MIN MAX UNIT RMII6 td(REF_CLK-TXD) Delay time, RMII[x]_REF_CLK High to RMII[x]_ TXD[1:0] valid 2 10 ns td(REF_CLK-TX_EN) Delay time, RMII[x]_REF_CLK to RMII[x]_TX_EN valid 2 10 ns RMII[x]_TXD[1:0], RMII[x]_TX_EN RMII6 RMII[x]_REF_CLK Figure 6-25. RMII[x]_TXD[1:0], and RMII[x]_TX_EN Switching Characteristics – RMII Mode www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 147 Product Folder Links: AM2434 AM2432 AM2431

6.11.5.1.3 CPSW3G RGMII Timing

Table 6-32 , Table 6-33 , Table 6-34 , Figure 6-26 , Table 6-35 , Table 6-36 , and Figure 6-27 present timing conditions, timing requirements, and switching characteristics for CPSW3G RGMII. Table 6-32. CPSW3G RGMII Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate VDD(1) = 1.8V 1.44 5 V/ns VDD(1) = 3.3V 2.64 5 OUTPUT CONDITIONS CL Output load capacitance 2 20 pF PCB CONNECTIVITY REQUIREMENTS td(Trace Mismatch Delay) Propagation delay mismatch across all traces RGMII[x]_RXC, RGMII[x]_RD[3:0], RGMII[x]_RX_CTL 50 ps RGMII[x]_TXC, RGMII[x]_TD[3:0], RGMII[x]_TX_CTL 50 ps (1) VDD stands for corresponding power supply. For more information on the power supply name and the corresponding ball(s), see POWER column of the Pin Attributes table. AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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Table 6-33. RGMII[x]_RXC Timing Requirements – RGMII Mode see Figure 6-26 NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT RGMII1 tc(RXC) Cycle time, RGMII[x]_RXC 10Mbps 360 440 ns 100Mbps 36 44 ns 1000Mbps 7.2 8.8 ns RGMII2 tw(RXCH) Pulse duration, RGMII[x]_RXC high 10Mbps 160 240 ns 100Mbps 16 24 ns 1000Mbps 3.6 4.4 ns RGMII3 tw(RXCL) Pulse duration, RGMII[x]_RXC low 10Mbps 160 240 ns 100Mbps 16 24 ns 1000Mbps 3.6 4.4 ns Table 6-34. RGMII[x]_RD[3:0], and RGMII[x]_RX_CTL Timing Requirements – RGMII Mode see Figure 6-26 NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT RGMII4 tsu(RD-RXC) Setup time, RGMII[x]_RD[3:0] valid before RGMII[x]_RXC high/low 10Mbps 1 ns 100Mbps 1 ns 1000Mbps 1 ns tsu(RX_CTL-RXC) Setup time, RGMII[x]_RX_CTL valid before RGMII[x]_RXC high/low 10Mbps 1 ns 100Mbps 1 ns 1000Mbps 1 ns RGMII5 th(RXC-RD) Hold time, RGMII[x]_RD[3:0] valid after RGMII[x]_RXC high/low 10Mbps 1 ns 100Mbps 1 ns 1000Mbps 1 ns th(RXC-RX_CTL) Hold time, RGMII[x]_RX_CTL valid after RGMII[x]_RXC high/low 10Mbps 1 ns 100Mbps 1 ns 1000Mbps 1 ns RGMII[x] RD 3_ [ :0] (B) RGMII[x] RX_CTL_ (B) RGMII[x] RXC_ (A) RGMII4 RXERRRXDV 2nd Half-byte1st Half-byte RGMII2 RGMII3 RGMII1 RGMII5 A. RGMII[x]_RXC must be externally delayed relative to the data and control pins. B. Data and control information is received using both edges of the clocks. RGMII[x]_RD[3:0] carries data bits 3-0 on the rising edge of RGMII[x]_RXC and data bits 7-4 on the falling edge of RGMII[x]_RXC. Similarly, RGMII[x]_RX_CTL carries RXDV on rising edge of RGMII[x]_RXC and RXERR on falling edge of RGMII[x]_RXC. Figure 6-26. CPSW3G RGMII[x]_RXC, RGMII[x]_RD[3:0], RGMII[x]_RX_CTL Timing Requirements - RGMII Mode www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 149 Product Folder Links: AM2434 AM2432 AM2431

Table 6-35. RGMII[x]_TXC Switching Characteristics – RGMII Mode see Figure 6-27 NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT RGMII6 tc(TXC) Cycle time, RGMII[x]_TXC 10Mbps 360 440 ns 100Mbps 36 44 ns 1000Mbps 7.2 8.8 ns RGMII7 tw(TXCH) Pulse duration, RGMII[x]_TXC high 10Mbps 160 240 ns 100Mbps 16 24 ns 1000Mbps 3.6 4.4 ns RGMII8 tw(TXCL) Pulse duration, RGMII[x]_TXC low 10Mbps 160 240 ns 100Mbps 16 24 ns 1000Mbps 3.6 4.4 ns Table 6-36. RGMII[x]_TD[3:0] and RGMII[x]_TX_CTL Switching Characteristics – RGMII Mode see Figure 6-27 NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT RGMII9 tosu(TD-TXC) Output setup time, RGMII[x]_TD[3:0] valid to RGMII[x]_TXC high/low 10Mbps 1.2 ns 100Mbps 1.2 ns 1000Mbps 1.2 ns tosu(TX_CTL-TXC) Output setup time, RGMII[x]_TX_CTL valid to RGMII[x]_TXC high/low 10Mbps 1.2 ns 100Mbps 1.2 ns 1000Mbps 1.2 ns RGMII10 toh(TXC-TD) Output hold time, RGMII[x]_TD[3:0] valid after RGMII[x]_TXC high/low 10Mbps 1.2 ns 100Mbps 1.2 ns 1000Mbps 1.2 ns toh(TXC-TX_CTL) Output hold time, RGMII[x]_TX_CTL valid after RGMII[x]_TXC high/low 10Mbps 1.2 ns 100Mbps 1.2 ns 1000Mbps 1.2 ns RGMII[x]_TXC (A) RGMII[x]_TD[3:0] (B) RGMII[x] TX_CTL_ (B) RGMII9 1st Half-byte TXERRTXEN 2nd Half-byte RGMII7 RGMII8 RGMII6 RGMII10 A. TXC is delayed internally before being driven to the RGMII[x]_TXC pin. This internal delay is always enabled. B. Data and control information is received using both edges of the clocks. RGMII[x]_TD[3:0] carries data bits 3-0 on the rising edge of RGMII[x]_TXC and data bits 7-4 on the falling edge of RGMII[x]_TXC. Similarly, RGMII[x]_TX_CTL carries TXEN on rising edge of RGMII[x]_TXC and TXERR on falling edge of RGMII[x]_TXC. Figure 6-27. CPSW3G RGMII[x]_TXC, RGMII[x]_TD[3:0], and RGMII[x]_TX_CTL Switching Characteristics - RGMII Mode AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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6.11.5.1.4 CPSW3G IOSETs

Table 6-37 defines valid pin combinations of each CPSW3G MDIO0 IOSET. Table 6-37. CPSW3G MDIO0 IOSETs SIGNALS IOSET1 IOSET2 BALL NAME MUXMODE BALL NAME MUXMODE MDIO0_MDIO PRG0_PRU1_GPO18 4 PRG1_MDIO0_MDIO 4 MDIO0_MDC PRG0_PRU1_GPO19 4 PRG1_MDIO0_MDC 4 Table 6-38 defines valid pin combinations of each CPSW3G RMII1 and RMII2 IOSET. Table 6-38. CPSW3G RMII1 and RMII2 IOSETs SIGNALS IOSET1 IOSET2 BALL NAME MUXMODE BALL NAME MUXMODE RMII_REF_CLK(1) PRG1_PRU0_GPO10 5 PRG0_PRU0_GPO10 5 RMII1_CRS_DV PRG1_PRU1_GPO19 5 PRG0_PRU1_GPO19 5 RMII1_RX_ER PRG1_PRU0_GPO9 5 PRG0_PRU0_GPO9 5 RMII1_RXD0 PRG1_PRU1_GPO7 5 PRG0_PRU1_GPO7 5 RMII1_RXD1 PRG1_PRU1_GPO9 5 PRG0_PRU1_GPO9 5 RMII1_TXD0 PRG1_PRU1_GPO10 5 PRG0_PRU1_GPO10 5 RMII1_TXD1 PRG1_PRU1_GPO17 5 PRG0_PRU1_GPO17 5 RMII1_TX_EN PRG1_PRU1_GPO18 5 PRG0_PRU1_GPO18 5 RMII2_CRS_DV PRG1_PRU1_GPO13 5 PRG1_PRU1_GPO13 5 RMII2_RX_ER PRG1_PRU1_GPO4 5 PRG1_PRU1_GPO4 5 RMII2_RXD0 PRG1_PRU1_GPO0 5 PRG1_PRU1_GPO0 5 RMII2_RXD1 PRG1_PRU1_GPO1 5 PRG1_PRU1_GPO1 5 RMII2_TXD0 PRG1_PRU1_GPO11 5 PRG1_PRU1_GPO11 5 RMII2_TXD1 PRG1_PRU1_GPO12 5 PRG1_PRU1_GPO12 5 RMII2_TX_EN PRG1_PRU1_GPO15 5 PRG1_PRU1_GPO15 5 (1) RMII_REF_CLK is common to both RMII1 and RMII2. For proper operation, all pin multiplexed signal assignments must use the same IOSET. Table 6-39 defines valid pin combinations of each CPSW3G RGMII1 IOSET. Table 6-39. CPSW3G RGMII1 IOSETs SIGNALS IOSET1 IOSET2 BALL NAME MUXMODE BALL NAME MUXMODE RGMII1_TX_CTL PRG1_PRU0_GPO9 4 PRG1_PRU0_GPO9 4 RGMII1_TXC PRG1_PRU0_GPO10 4 PRG1_PRU0_GPO10 4 RGMII1_TD0 PRG1_PRU1_GPO7 4 PRG1_PRU1_GPO7 4 RGMII1_TD1 PRG1_PRU1_GPO9 4 PRG1_PRU1_GPO9 4 RGMII1_TD2 PRG1_PRU1_GPO10 4 PRG1_PRU1_GPO10 4 RGMII1_TD3 PRG1_PRU1_GPO17 4 PRG1_PRU1_GPO17 4 RGMII1_RX_CTL PRG0_PRU0_GPO9 4 PRG1_PRU0_GPO5 4 RGMII1_RXC PRG0_PRU0_GPO10 4 PRG1_PRU0_GPO8 4 RGMII1_RD0 PRG0_PRU1_GPO7 4 PRG1_PRU1_GPO5 4 RGMII1_RD1 PRG0_PRU1_GPO9 4 PRG1_PRU1_GPO8 4 RGMII1_RD2 PRG0_PRU1_GPO10 4 PRG1_PRU1_GPO18 4 RGMII1_RD3 PRG0_PRU1_GPO17 4 PRG1_PRU1_GPO19 4 www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 151 Product Folder Links: AM2434 AM2432 AM2431

6.11.5.2 DDRSS

For more details about features and additional description information on the device (LP)DDR4 Memory Interface, see the corresponding subsections within Signal Descriptions and Detailed Description sections. Table 6-40 and Figure 6-28 present switching characteristics for DDRSS. Table 6-40. DDRSS Switching Characteristics see Figure 6-28 NO. PARAMETER DDR TYPE MIN MAX UNIT 1 tc(DDR_CKP/ DDR_CKN) Cycle time, DDR_CKP and DDR_CKN LPDDR4 1.25(1) 20 ns DDR4 1.25(1) 1.6 ns (1) Minimum DDR clock Cycle time will be limited based on the specific memory type (vendor) used in a system and by PCB implementation. Refer to AM64x\\AM243x DDR Board Design and Layout Guidelines for the proper PCB implementation to achieve maximum DDR frequency. DDR0_CKP DDR0_CKN Figure 6-28. DDRSS Switching Characteristics For more information, see DDR Subsystem (DDRSS) section in Memory Controllers chapter in the device TRM. AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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6.11.5.3 ECAP

Table 6-41, Table 6-42, Figure 6-29, Table 6-43, and Figure 6-30 present timing conditions, timing requirements, and switching characteristics for ECAP. Table 6-41. ECAP Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate 1 4 V/ns OUTPUT CONDITIONS CL Output load capacitance 2 7 pF Table 6-42. ECAP Timing Requirements see Figure 6-29 NO. PARAMETER DESCRIPTION MIN MAX UNIT CAP1 tw(CAP) Pulse duration, CAP (asynchronous) 2 + 2P (1) ns (1) P = MAIN_SYSCLK0/4 period in ns. CAP CAP1 EPERIPHERALS_TIMNG_01 Figure 6-29. ECAP Timings Requirements Table 6-43. ECAP Switching Characteristics see Figure 6-30 NO. PARAMETER DESCRIPTION MIN MAX UNIT CAP2 tw(APWM) Pulse duration, APWMx high/low -2 + 2P (1) ns (1) P = MAIN_SYSCLK0/4 period in ns. APWM CAP2 EPERIPHERALS_TIMNG_02 Figure 6-30. ECAP Switching Characteristics For more information, see Enhanced Capture (ECAP) Module section in Peripherals chapter in the device TRM. www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 153 Product Folder Links: AM2434 AM2432 AM2431

6.11.5.4 EPWM

Table 6-44, Table 6-45, Figure 6-31 , Table 6-46, Figure 6-32 , Figure 6-33 , and Figure 6-34 present timing conditions, timing requirements, and switching characteristics for EPWM. Table 6-44. EPWM Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate 1 4 V/ns OUTPUT CONDITIONS CL Output load capacitance 2 7 pF Table 6-45. EPWM Timing Requirements see Figure 6-31 NO. PARAMETER DESCRIPTION MIN MAX UNIT PWM6 tw(SYNCIN) Pulse duration, EHRPWM_SYNCI 2 + 2P(1) ns PWM7 tw(TZ) Pulse duration, EHRPWM_TZn_IN low 2 + 3P(1) ns (1) P = MAIN_SYSCLK0/2 period in ns. EHRPWM_TZn_IN PWM7 EPERIPHERALS_TIMNG_07 EHRPWM_SYNCI PWM6 Figure 6-31. EPWM Timing Requirements AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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6.11.5.5 EQEP

Table 6-47 , Table 6-48 , Figure 6-35 , and Table 6-49 present timing conditions, timing requirements, and switching characteristics for EQEP. Table 6-47. EQEP Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate 1 4 V/ns OUTPUT CONDITIONS CL Output load capacitance 2 7 pF Table 6-48. EQEP Timing Requirements see Figure 6-35 NO. PARAMETER DESCRIPTION MIN MAX UNIT QEP1 tw(QEP) Pulse duration, QEP_A/B 2 + 2P (1) ns QEP2 tw(QEPIH) Pulse duration, QEP_I high 2 + 2P (1) ns QEP3 tw(QEPIL) Pulse duration, QEP_I low 2 + 2P (1) ns QEP4 tw(QEPSH) Pulse duration, QEP_S high 2 + 2P (1) ns QEP5 tw(QEPSL) Pulse duration, QEP_S low 2 + 2P (1) ns (1) P = MAIN_SYSCLK0/4 period in ns QEP_S QEP4 EPERIPHERALS_TIMNG_03 QEP_I QEP2 QEP_A/B QEP1 QEP3 QEP5 Figure 6-35. EQEP Timing Requirements Table 6-49. EQEP Switching Characteristics NO. PARAMETER DESCRIPTION MIN MAX UNIT QEP6 td(QEP-CNTR) Delay time, external clock to counter increment 24 ns For more information, see Enhanced Quadrature Encoder Pulse (EQEP) Module section in Peripherals chapter in the device TRM. AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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6.11.5.6 FSI

Table 6-50 , Table 6-51 , Figure 6-36 , Table 6-52 , Figure 6-37 , Table 6-53 , and Figure 6-38 present timing conditions, timing requirements, and switching characteristics for FSI. Table 6-50. FSI Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate 0.8 4 V/ns OUTPUT CONDITIONS CL Output load capacitance 1 7 pF Table 6-51. FSI Timing Requirements see Figure 6-36 NO. MIN MAX UNIT FSIR1 tc(RX_CLK) Cycle time, FSI_RXn_CLK 20 ns FSIR2 tw(RX_CLK) Pulse width, FSI_RXn_CLK low or FSI_RXn_CLK high 0.5P - 1 (1) 0.5P + 1 (1) ns FSIR3 tsu(RX_D-RX_CLK) Setup time, FSI_RXn_D[1:0] valid before FSI_RXn_CLK 3 ns FSIR4 th(RX_CLK-RX_D) Hold time, FSI_RXn_D[1:0] valid after FSI_RXn_CLK 2.5 ns (1) P = FSI_RXn_CLK period in ns. FSI_RXn_CLK FSIR2 FSIR1 FSIR3 FSI_RXn_D0 FSI_RXn_D1 FSIR4 FSIR2 Figure 6-36. FSI Timing Requirements www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 157 Product Folder Links: AM2434 AM2432 AM2431

Table 6-52. FSI Switching Characteristics - FSI Mode see Figure 6-37 NO. PARAMETER MODE MIN MAX UNIT FSIT1 tc(TX_CLK) Cycle time, FSI_TXn_CLK FSI Mode 20 ns FSIT2 tw(TX_CLK) Pulse width, FSI_TXn_CLK low or FSI_TXn_CLK high FSI Mode 0.5p + 1 (1) 0.5P - 1 (1) ns FSIT3 td(TX_CLK-TX_D) Delay time, FSI_TXn_D[1:0] valid after FSI_TXn_CLK high or FSI_TXn_CLK low FSI Mode 0.25P - 2 (1) 0.25P + 2.5 (1) ns (1) P = FSI_TXn_CLK period in ns. FSI_TXn_CLK FSIT2 FSIT1 FSIT3 FSI_TXn_D0 FSI_TXn_D1 FSIT2 FSIT1 Figure 6-37. FSI Switching Characteristics - FSI Mode Table 6-53. FSI Switching Characteristics - SPI Mode see Figure 6-38 NO. PARAMETER MODE MIN MAX UNIT FSIT4 tc(TX_CLK) Cycle time, FSI_TXn_CLK SPI Mode 20 ns FSIT5 tw(TX_CLK) Pulse width, FSI_TXn_CLK low or FSI_TXn_CLK high SPI Mode 0.5P + 1 (1) 0.5P - 1 (1) ns FSIT6 td(TX_CLKH-TX_D0) Delay time, FSI_TXn_CLK high to FSI_TXn_D0 valid SPI Mode 3 ns FSIT7 td(TX_D1-TX_CLK) Delay time, FSI_TXn_D1 low to FSI_TXn_CLK high SPI Mode P - 3 (1) ns FSIT8 td(TX_CLK-TX_D1) Delay time, FSI_TXn_CLK low to FSI_TXn_D1 high SPI Mode P - 2 (1) ns (1) P = FSI_TXn_CLK period in ns. FSI_TXn_CLK FSIT5 FSIT4 FSI_TXn_D0 FSI_TXn_D1 FSIT6 FSIT7 FSIT8 FSIT5 Figure 6-38. FSI Switching Characteristics - SPI Mode For more information, see Fast Serial Interface section in Peripherals chapter in the device TRM. AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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6.11.5.7 GPIO

Table 6-54 , Table 6-55 , and Table 6-56 present timing conditions, timing requirements, and switching characteristics for GPIO. The device has three instances of the GPIO module.

MCU_GPIO0
GPIO0
GPIO1 Note GPIOn_x is generic name used to describe a GPIO signal, where n represents the specific GPIO module and x represents one of the input/output signals associated with the module. For additional description information on the device GPIO, see the corresponding subsections within Signal Descriptions and Detailed Description sections. Table 6-54. GPIO Timing Conditions PARAMETER BUFFER TYPE MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate LVCMOS V/ns LVCMOS I2C OD FS I2C OD FS OUTPUT CONDITIONS CL Output load capacitance LVCMOS 3 10 pF I2C OD FS 3 100 pF (1) VDD stands for corresponding power supply. For more information on the power supply name and the corresponding ball(s), see POWER column of the Pin Attributes table. Table 6-55. GPIO Timing Requirements NO. PARAMETER DESCRIPTION MIN MAX UNIT GPIO1 tw(GPIO_IN) Pulse width, GPIOn_x 2P(1) + 30 ns (1) P = functional clock period in ns. Table 6-56. GPIO Switching Characteristics NO. PARAMETER DESCRIPTION BUFFER TYPE MIN MAX UNIT GPIO2 tw(GPIO_OUT) Pulse width, GPIOn_x LVCMOS 0.975P(1) - 3.6 ns I2C OD FS 160 ns (1) P = functional clock period in ns. For more information, see General-Purpose Interface (GPIO) section in Peripherals chapter in the device TRM. www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 159 Product Folder Links: AM2434 AM2432 AM2431

6.11.5.8 GPMC

For more details about features and additional description information on the device General-Purpose Memory Controller, see the corresponding subsections within Signal Descriptions and Detailed Description sections. Note GPMC has one or more signals which can be multiplexed to more than one pin. Timing requirements and switching characteristics defined in this section are only valid for specific pin combinations known Table 6-57 presents timing conditions for GPMC. Table 6-57. GPMC Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate 1.65 4 V/ns OUTPUT CONDITIONS CL Output load capacitance 133MHz Synchronous Mode 3 20 pF All other modes 3 30 pF PCB CONNECTIVITY REQUIREMENTS td(Trace Delay) Propagation delay of each trace 133MHz Synchronous Mode 140 360 ps All other modes 140 720 ps td(Trace Mismatch Delay) Propagation delay mismatch across all traces 200 ps For more information, see General-Purpose Memory Controller (GPMC) section in Peripherals chapter in the device TRM.

6.11.5.8.1 GPMC and NOR Flash — Synchronous Mode

Table 6-58 and Table 6-59 present timing requirements and switching characteristics for GPMC and NOR Flash - Synchronous Mode. Table 6-58. GPMC and NOR Flash Timing Requirements — Synchronous Mode see Figure 6-39, Figure 6-40, and Figure 6-43 NO. PARAMETER DESCRIPTION MODE(4) MIN MAX MIN MAX UNIT32-bit data bus (up to 100MHz) (1) 16-bit data bus (up to 133MHz) (1) F12 tsu(dV-clkH) Setup time, GPMC0_ADn:0 valid before GPMC0_CLK high div_by_1_mode 1.81 1.12 ns not_div_by_1_mode 1.06 3.5 ns F13 th(clkH-dV) Hold time, GPMC0_ADn:0 valid after GPMC0_CLK high div_by_1_mode 2.29 2.29 ns not_div_by_1_mode 2.29 2.29 ns F21 tsu(waitV-clkH) Setup time, GPMC0_WAITj (3) valid before GPMC0_CLK high div_by_1_mode 1.81 1.12 ns not_div_by_1_mode 1.06 3.5 ns F22 th(clkH-waitV) Hold time, GPMC0_WAITj (3) valid after GPMC0_CLK high div_by_1_mode 2.29 2.29 ns not_div_by_1_mode 2.29 2.29 ns (1) Synchronous Mode supports a 32-bit data bus (GPMC0_AD[31:0]) with GPMC0_CLK up to 100MHz and a 16-bit data bus (GPMC0_AD[15:0]) with GPMC0_CLK up to 133MHz. Select the clock source of GPMC0_FCLK which feeds GPMC0_CLK by writing to the CTRLMMR_GPMC0_CLKSEL register:

133MHz: CLK_SEL = 0h - MAIN_PLL0_HSDIV3_CLKOUT (default)
100MHz: CLK_SEL = 1h - MAIN_PLL2_HSDIV3_CLKOUT (2) In GPMC_WAIT[j], j is equal to 0 or 1. (3) Wait monitoring support is limited to a WaitMonitoringTime value > 0. For a full description of wait monitoring feature, see General- Purpose Memory Controller (GPMC) section in the device TRM. AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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(4) For div_by_1_mode:

GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h: – GPMC0_CLK frequency = GPMC0_FCLK frequency For not_div_by_1_mode:
GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 1h to 3h: – GPMC0_CLK frequency = GPMC0_FCLK frequency / (2 to 4) Table 6-59. GPMC and NOR Flash Switching Characteristics – Synchronous Mode see Figure 6-39, Figure 6-40, Figure 6-41, Figure 6-42, and Figure 6-43 NO. PARAMETER DESCRIPTION MIN MAX UNIT F0 tc(clk) Cycle time, GPMC0_CLK(16) 7.52(1) ns F1 tw(clkH) Typical pulse duration, GPMC0_CLK high 0.475P(14) - 0.3 ns F1 tw(clkL) Typical pulse duration, GPMC0_CLK low 0.475P(14) - 0.3 ns F2 td(clkH-csn[i]V) Delay time, GPMC0_CLK rising edge to GPMC0_CSni transition F3 td(clkH-csn[i]IV) Delay time, GPMC0_CLK rising edge to GPMC0_CSni invalid F4 td(aV-clk) Delay time, GPMC0_A[27:1] valid to GPMC0_CLK first edge B(3) - 2.3 B(3) + 4.5 ns F5 td(clkH-aIV) Delay time, GPMC0_CLK rising edge to GPMC0_A[27:1] invalid -2.3 4.5 ns F6 td(be[x]nV-clk) Delay time, GPMC0_BE0n_CLE, GPMC0_BE1n, GPMC0_BE2n, GPMC0_BE3n valid to GPMC0_CLK first edge F7 td(clkH-be[x]nIV) Delay time, GPMC0_CLK rising edge to GPMC0_BE0n_CLE, GPMC0_BE1n, GPMC0_BE2n, GPMC0_BE3n invalid F8 td(clkH-advn) Delay time, GPMC0_CLK rising edge to GPMC0_ADVn_ALE transition F9 td(clkH-advnIV) Delay time, GPMC0_CLK rising edge to GPMC0_ADVn_ALE invalid F10 td(clkH-oen) Delay time, GPMC0_CLK rising edge to GPMC0_OEn_REn transition F11 td(clkH-oenIV) Delay time, GPMC0_CLK rising edge to GPMC0_OEn_REn invalid F14 td(clkH-wen) Delay time, GPMC0_CLK rising edge to GPMC0_WEn transition F15 td(clkH-do) Delay time, GPMC0_CLK rising edge to GPMC0_ADn:0 transition(10) -2.3 2.7 ns F15 td(clkL-do) Delay time, GPMC0_CLK falling edge to GPMC0_ADn:0 transition(11) -2.3 2.7 ns F15 td(clkL-do) Delay time, GPMC0_CLK falling edge to GPMC0_ADn:0 transition(12) -2.3 2.7 ns F17 td(clkH-be[x]n) Delay time, GPMC0_CLK rising edge to GPMC0_BE0n_CLE, GPMC0_BE1n, GPMC0_BE2n, GPMC0_BE3n transition(10) -2.3 1.9 ns F17 td(clkL-be[x]n) Delay time, GPMC0_CLK falling edge to GPMC0_BE0n_CLE, GPMC0_BE1n, GPMC0_BE2n, GPMC0_BE3n transition(11) -2.3 1.9 ns F17 td(clkL-be[x]n) Delay time, GPMC0_CLK falling edge to GPMC0_BE0n_CLE, GPMC0_BE1n, GPMC0_BE2n, GPMC0_BE3n transition(12) -2.3 1.9 ns F18 tw(csnV) Pulse duration, GPMC0_CSni low A(2) ns F19 tw(be[x]nV) Pulse duration, GPMC0_BE0n_CLE, GPMC0_BE1n, GPMC0_BE2n, GPMC0_BE3n low C(4) ns www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 161 Product Folder Links: AM2434 AM2432 AM2431

Table 6-59. GPMC and NOR Flash Switching Characteristics – Synchronous Mode (continued) see Figure 6-39, Figure 6-40, Figure 6-41, Figure 6-42, and Figure 6-43 NO. PARAMETER DESCRIPTION MIN MAX UNIT F20 tw(advnV) Pulse duration, GPMC0_ADVn_ALE low K(15) ns (1) Synchronous Mode supports a 32-bit data bus (GPMC0_AD[31:0]) with GPMC0_CLK up to 100MHz and a 16-bit data bus (GPMC0_AD[15:0]) with GPMC0_CLK up to 133MHz. Select the clock source of GPMC0_FCLK which feeds GPMC0_CLK by writing to the CTRLMMR_GPMC0_CLKSEL register:

133MHz: CLK_SEL = 0h - MAIN_PLL0_HSDIV3_CLKOUT (default)
100MHz: CLK_SEL = 1h - MAIN_PLL2_HSDIV3_CLKOUT (2) For single read: A = (CSRdOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC0_FCLK(14) For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC0_FCLK(14) For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC0_FCLK(14) With n being the page burst access number. (3) Address bus / Byte Enables become valid at start of cycle, GPMC0_CLK activation time may be delayed after start of cycle B = ClkActivationTime × GPMC0_FCLK(14) (4) For single read: C = RdCycleTime × (TimeParaGranularity + 1) × GPMC0_FCLK(14) For burst read: C = (RdCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC0_FCLK(14) For burst write: C = (WrCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC0_FCLK(14) With n being the page burst access number. (5) For single read: D = (RdCycleTime - RdAccessTime) × (TimeParaGranularity + 1) × GPMC0_FCLK(14) For single write: D = (WrCycleTime - WrAccessTime) × (TimeParaGranularity + 1) × GPMC0_FCLK(14) For burst read: D = (RdCycleTime - RdAccessTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC0_FCLK(14) For burst write: D = (WrCycleTime - WrAccessTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC0_FCLK(14) With n being the page burst access number. (6) For CSn falling edge (CS activated):
Case GPMCFCLKDIVIDER = 0: – F = 0.5 × CSExtraDelay × GPMC0_FCLK(14)
Case GPMCFCLKDIVIDER = 1: – F = 0.5 × CSExtraDelay × GPMC0_FCLK(14) if (ClkActivationTime and CSOnTime are odd) or (ClkActivationTime and CSOnTime are even) – F = (1 + 0.5 × CSExtraDelay) × GPMC0_FCLK(14) otherwise
Case GPMCFCLKDIVIDER = 2: – F = 0.5 × CSExtraDelay × GPMC0_FCLK(14) if ((CSOnTime - ClkActivationTime) is a multiple of 3) – F = (1 + 0.5 × CSExtraDelay) × GPMC0_FCLK(14) if ((CSOnTime - ClkActivationTime - 1) is a multiple of 3) – F = (2 + 0.5 × CSExtraDelay) × GPMC0_FCLK(14) if ((CSOnTime - ClkActivationTime - 2) is a multiple of 3) For CSn rising edge (CS deactivated) in Reading mode:
Case GPMCFCLKDIVIDER = 0: – F = 0.5 × CSExtraDelay × GPMC0_FCLK(14)
Case GPMCFCLKDIVIDER = 1: – F = 0.5 × CSExtraDelay × GPMC0_FCLK(14) if (ClkActivationTime and CSRdOffTime are odd) or (ClkActivationTime and CSRdOffTime are even) – F = (1 + 0.5 × CSExtraDelay) × GPMC0_FCLK(14) otherwise
Case GPMCFCLKDIVIDER = 2: – F = 0.5 × CSExtraDelay × GPMC0_FCLK(14) if ((CSRdOffTime - ClkActivationTime) is a multiple of 3) – F = (1 + 0.5 × CSExtraDelay) × GPMC0_FCLK(14) if ((CSRdOffTime - ClkActivationTime - 1) is a multiple of 3) – F = (2 + 0.5 × CSExtraDelay) × GPMC0_FCLK(14) if ((CSRdOffTime - ClkActivationTime - 2) is a multiple of 3) For CSn rising edge (CS deactivated) in Writing mode:
Case GPMCFCLKDIVIDER = 0: – F = 0.5 × CSExtraDelay × GPMC0_FCLK(14)
Case GPMCFCLKDIVIDER = 1: – F = 0.5 × CSExtraDelay × GPMC0_FCLK(14) if (ClkActivationTime and CSWrOffTime are odd) or (ClkActivationTime and CSWrOffTime are even) – F = (1 + 0.5 × CSExtraDelay) × GPMC0_FCLK(14) otherwise
Case GPMCFCLKDIVIDER = 2: AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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– F = 0.5 × CSExtraDelay × GPMC0_FCLK(14) if ((CSWrOffTime - ClkActivationTime) is a multiple of 3) – F = (1 + 0.5 × CSExtraDelay) × GPMC0_FCLK(14) if ((CSWrOffTime - ClkActivationTime - 1) is a multiple of 3) – F = (2 + 0.5 × CSExtraDelay) × GPMC0_FCLK(14) if ((CSWrOffTime - ClkActivationTime - 2) is a multiple of 3) (7) For ADV falling edge (ADV activated):

Case GPMCFCLKDIVIDER = 0: – G = 0.5 × ADVExtraDelay × GPMC0_FCLK(14)
Case GPMCFCLKDIVIDER = 1: – G = 0.5 × ADVExtraDelay × GPMC0_FCLK(14) if (ClkActivationTime and ADVOnTime are odd) or (ClkActivationTime and ADVOnTime are even) – G = (1 + 0.5 × ADVExtraDelay) × GPMC0_FCLK(14) otherwise
Case GPMCFCLKDIVIDER = 2: – G = 0.5 × ADVExtraDelay × GPMC0_FCLK(14) if ((ADVOnTime - ClkActivationTime) is a multiple of 3) – G = (1 + 0.5 × ADVExtraDelay) × GPMC0_FCLK(14) if ((ADVOnTime - ClkActivationTime - 1) is a multiple of 3) – G = (2 + 0.5 × ADVExtraDelay) × GPMC0_FCLK(14) if ((ADVOnTime - ClkActivationTime - 2) is a multiple of 3) For ADV rising edge (ADV deactivated) in Reading mode:
Case GPMCFCLKDIVIDER = 0: – G = 0.5 × ADVExtraDelay × GPMC0_FCLK(14)
Case GPMCFCLKDIVIDER = 1: – G = 0.5 × ADVExtraDelay × GPMC0_FCLK(14) if (ClkActivationTime and ADVRdOffTime are odd) or (ClkActivationTime and ADVRdOffTime are even) – G = (1 + 0.5 × ADVExtraDelay) × GPMC0_FCLK(14) otherwise
Case GPMCFCLKDIVIDER = 2: – G = 0.5 × ADVExtraDelay × GPMC0_FCLK(14) if ((ADVRdOffTime - ClkActivationTime) is a multiple of 3) – G = (1 + 0.5 × ADVExtraDelay) × GPMC0_FCLK(14) if ((ADVRdOffTime - ClkActivationTime - 1) is a multiple of 3) – G = (2 + 0.5 × ADVExtraDelay) × GPMC0_FCLK(14) if ((ADVRdOffTime - ClkActivationTime - 2) is a multiple of 3) For ADV rising edge (ADV deactivated) in Writing mode:
Case GPMCFCLKDIVIDER = 0: – G = 0.5 × ADVExtraDelay × GPMC0_FCLK(14)
Case GPMCFCLKDIVIDER = 1: – G = 0.5 × ADVExtraDelay × GPMC0_FCLK(14) if (ClkActivationTime and ADVWrOffTime are odd) or (ClkActivationTime and ADVWrOffTime are even) – G = (1 + 0.5 × ADVExtraDelay) × GPMC0_FCLK(14) otherwise
Case GPMCFCLKDIVIDER = 2: – G = 0.5 × ADVExtraDelay × GPMC0_FCLK(14) if ((ADVWrOffTime - ClkActivationTime) is a multiple of 3) – G = (1 + 0.5 × ADVExtraDelay) × GPMC0_FCLK(14) if ((ADVWrOffTime - ClkActivationTime - 1) is a multiple of 3) – G = (2 + 0.5 × ADVExtraDelay) × GPMC0_FCLK(14) if ((ADVWrOffTime - ClkActivationTime - 2) is a multiple of 3) (8) For OE falling edge (OE activated) and IO DIR rising edge (Data Bus input direction):
Case GPMCFCLKDIVIDER = 0: – H = 0.5 × OEExtraDelay × GPMC0_FCLK(14)
Case GPMCFCLKDIVIDER = 1: – H = 0.5 × OEExtraDelay × GPMC0_FCLK(14) if (ClkActivationTime and OEOnTime are odd) or (ClkActivationTime and OEOnTime are even) – H = (1 + 0.5 × OEExtraDelay) × GPMC0_FCLK(14) otherwise
Case GPMCFCLKDIVIDER = 2: – H = 0.5 × OEExtraDelay × GPMC0_FCLK(14) if ((OEOnTime - ClkActivationTime) is a multiple of 3) – H = (1 + 0.5 × OEExtraDelay) × GPMC0_FCLK(14) if ((OEOnTime - ClkActivationTime - 1) is a multiple of 3) – H = (2 + 0.5 × OEExtraDelay) × GPMC0_FCLK(14) if ((OEOnTime - ClkActivationTime - 2) is a multiple of 3) For OE rising edge (OE deactivated):
Case GPMCFCLKDIVIDER = 0: – H = 0.5 × OEExtraDelay × GPMC0_FCLK(14)
Case GPMCFCLKDIVIDER = 1: www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 163 Product Folder Links: AM2434 AM2432 AM2431

– H = 0.5 × OEExtraDelay × GPMC0_FCLK(14) if (ClkActivationTime and OEOffTime are odd) or (ClkActivationTime and OEOffTime are even) – H = (1 + 0.5 × OEExtraDelay) × GPMC0_FCLK(14) otherwise

Case GPMCFCLKDIVIDER = 2: – H = 0.5 × OEExtraDelay × GPMC0_FCLK(14) if ((OEOffTime - ClkActivationTime) is a multiple of 3) – H = (1 + 0.5 × OEExtraDelay) × GPMC0_FCLK(14) if ((OEOffTime - ClkActivationTime - 1) is a multiple of 3) – H = (2 + 0.5 × OEExtraDelay) × GPMC0_FCLK(14) if ((OEOffTime - ClkActivationTime - 2) is a multiple of 3) (9) For WE falling edge (WE activated):
Case GPMCFCLKDIVIDER = 0: – I = 0.5 × WEExtraDelay × GPMC0_FCLK(14)
Case GPMCFCLKDIVIDER = 1: – I = 0.5 × WEExtraDelay × GPMC0_FCLK(14) if (ClkActivationTime and WEOnTime are odd) or (ClkActivationTime and WEOnTime are even) – I = (1 + 0.5 × WEExtraDelay) × GPMC0_FCLK(14) otherwise
Case GPMCFCLKDIVIDER = 2: – I = 0.5 × WEExtraDelay × GPMC0_FCLK(14) if ((WEOnTime - ClkActivationTime) is a multiple of 3) – I = (1 + 0.5 × WEExtraDelay) × GPMC0_FCLK(14) if ((WEOnTime - ClkActivationTime - 1) is a multiple of 3) – I = (2 + 0.5 × WEExtraDelay) × GPMC0_FCLK(14) if ((WEOnTime - ClkActivationTime - 2) is a multiple of 3) For WE rising edge (WE deactivated):
Case GPMCFCLKDIVIDER = 0: – I = 0.5 × WEExtraDelay × GPMC0_FCLK (14)
Case GPMCFCLKDIVIDER = 1: – I = 0.5 × WEExtraDelay × GPMC0_FCLK(14) if (ClkActivationTime and WEOffTime are odd) or (ClkActivationTime and WEOffTime are even) – I = (1 + 0.5 × WEExtraDelay) × GPMC0_FCLK(14) otherwise
Case GPMCFCLKDIVIDER = 2: – I = 0.5 × WEExtraDelay × GPMC0_FCLK(14) if ((WEOffTime - ClkActivationTime) is a multiple of 3) – I = (1 + 0.5 × WEExtraDelay) × GPMC0_FCLK(14) if ((WEOffTime - ClkActivationTime - 1) is a multiple of 3) – I = (2 + 0.5 × WEExtraDelay) × GPMC0_FCLK(14) if ((WEOffTime - ClkActivationTime - 2) is a multiple of 3) (10) Case GPMC0_CLK in div_by_1_mode(17), first transfer only: Data and byte enables transition on rise edge of GPMC0_CLK
Non-multiplexed mode: data transition at start of cycle
Multiplexed mode: data transition at WRDATAONADMUXBUS × (TimeParaGranularity + 1) × GPMC0_FCLK(14) (11) Case GPMC0_CLK in div_by_1_mode(17), all data and byte enables after initial transfer: Data and byte enables transition on fall edge of GPMC0_CLK (Half cycle of GPMC0_CLK) (12) Case GPMC0_CLK in not_div_by_1_mode(17) (GPMC0_CLK divided down from GPMC0_FCLK): All data and byte enables transition on fall edge of GPMC0_CLK (Half cycle of GPMC0_CLK). ClkActivationTime, GPMCFCLKDIVIDER, RDACCESSTIME/ WRACCESSTIME, and PAGEBURSTACCESSTIME configuration must be configured to enforce data and byte enables transition on falling edge of GPMC0_CLK (to be latched on rise edge of GPMC0_CLK) (13) In GPMC0_CSn[i], i is equal to 0, 1, 2 or 3. (14) P = GPMC0_CLK period in ns (15) For read: K = (ADVRdOffTime - ADVOnTime) × (TimeParaGranularity + 1) × GPMC0_FCLK(14) For write: K = (ADVWrOffTime - ADVOnTime) × (TimeParaGranularity + 1) × GPMC0_FCLK(14) (16) Related to the GPMC0_CLK output clock maximum and minimum frequencies programmable in the GPMC module by setting the GPMC0_CONFIG1_i configuration register bit field GPMCFCLKDIVIDER. (17) For div_by_1_mode:
GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h: – GPMC0_CLK frequency = GPMC0_FCLK frequency For not_div_by_1_mode:
GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 1h to 3h: – GPMC0_CLK frequency = GPMC0_FCLK frequency / (2 to 4) AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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GPMC_CLK GPMC_CSn[i] GPMC_A[MSB:1] GPMC_BE0n_CLE GPMC_BE1n GPMC_ADVn_ALE GPMC_OEn_REn GPMC_AD[15:0] GPMC_WAIT[j] Valid Address D 0 F12 F13 F11 F19 F18 F20 F10 F19 F12 F12 GPMC_01 A. In GPMC0_CSn[i], i is equal to 0, 1, 2 or 3. B. In GPMC0_WAIT[j], j is equal to 0 or 1. Figure 6-39. GPMC and NOR Flash — Synchronous Single Read (GPMCFCLKDIVIDER = 0) www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 165 Product Folder Links: AM2434 AM2432 AM2431

GPMC_CLK GPMC_CSn[i] GPMCA[MSB:1] GPMC_BE0n_CLE GPMC_BE1n GPMC_ADVn_ALE GPMC_OEn_REn GPMC_AD[15:0] GPMC_WAIT[j] Valid Address D 0 D 1 D 2 F12 F13 F13 F12 F8 F8 F9 F10 F11 F21 F22 D 3 GPMC_02 A. In GPMC0_CSn[i], i is equal to 0, 1, 2 or 3. B. In GPMC0_WAIT[j], j is equal to 0 or 1. Figure 6-40. GPMC and NOR Flash — Synchronous Burst Read — 4x16–bit (GPMCFCLKDIVIDER = 0) GPMC_CLK GPMC_CSn[i] GPMC_A[MSB:1] GPMC_BE0n_CLE GPMC_BE1n GPMC_ADVn_ALE GPMC_WEn GPMC_AD[15:0] GPMC_WAIT[j] D 0 D 1 D 2 D 3 F15 F15 F15 F8F8 F14F14 F17 F17 F17 F9F6 F17 F17 F17 Valid Address GPMC_03 A. In GPMC0_CSn[i], i is equal to 0, 1, 2 or 3. AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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GPMC_CLK GPMC_CSn[i] GPMC_A[27:17] GPMC_BE1n BPMC_BE0n_CLE GPMC_ADVn_ALE GPMC_WEn GPMC_WAIT[j] Address (LSB) D 0 D 1 D 2 D 3 F15 F15 F15 F8F8 F17 F17 F17 F6 F17 F17 F17 F18 F20 F14 F22 F21 Address (MSB) GPMC_AD[15:0] F14 GPMC_05 A. In GPMC0_CSn[i], i is equal to 0, 1, 2 or 3. B. In GPMC0_WAIT[j], j is equal to 0 or 1. Figure 6-43. GPMC and Multiplexed NOR Flash — Synchronous Burst Write AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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6.11.5.8.2 GPMC and NOR Flash — Asynchronous Mode

Table 6-60 and Table 6-61 present timing requirements and switching characteristics for GPMC and NOR Flash — Asynchronous Mode. Table 6-60. GPMC and NOR Flash Timing Requirements – Asynchronous Mode see Figure 6-44, Figure 6-45, Figure 6-46, and Figure 6-48 NO. PARAMETER DESCRIPTION MIN MAX UNIT FA5(1) tacc(d) Data access time H(5) ns FA20(2) tacc1-pgmode(d) Page mode successive data access time P(4) ns FA21(3) tacc2-pgmode(d) Page mode first data access time H(5) ns (1) The FA5 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active functional clock edge. FA5 value must be stored inside the AccessTime register bit field. (2) The FA20 parameter illustrates amount of time required to internally sample successive input page data. It is expressed in number of GPMC functional clock cycles. After each access to input page data, next input page data is internally sampled by active functional clock edge after FA20 functional clock cycles. The FA20 value must be stored in the PageBurstAccessTime register bit field. (3) The FA21 parameter illustrates amount of time required to internally sample first input page data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input page data is internally sampled by active functional clock edge. FA21 value must be stored inside the AccessTime register bit field. (4) P = PageBurstAccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(6) (5) H = AccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(6) (6) GPMC_FCLK is а general-purpose memory controller internal functional clock period in ns. Table 6-61. GPMC and NOR Flash Switching Characteristics – Asynchronous Mode see Figure 6-44, Figure 6-45, Figure 6-46, Figure 6-47, Figure 6-48, and Figure 6-49 NO. PARAMETER DESCRIPTION MIN MAX UNIT FA0 tw(be[x]nV) Pulse duration, output lower-byte enable and command latch enable GPMC_BE0n_CLE, output upper-byte enable GPMC_BE1n valid time N(12) ns FA1 tw(csnV) Pulse duration, output chip select GPMC_CSni low A(1) ns FA3 td(csnV-advnIV) Delay time, output chip select GPMC_CSni valid to output address valid and address latch enable GPMC_ADVn_ALE invalid FA4 td(csnV-oenIV) Delay time, output chip select GPMC_CSni valid to output enable GPMC_OEn_REn invalid (Single read) FA9 td(aV-csnV) Delay time, output address GPMC_A[27:1] valid to output chip select GPMC_CSni valid FA10 td(be[x]nV-csnV) Delay time, output lower-byte enable and command latch enable GPMC_BE0n_CLE, output upper-byte enable GPMC_BE1n valid to output chip select GPMC_CSni valid FA12 td(csnV-advnV) Delay time, output chip select GPMC_CSni valid to output address valid and address latch enable GPMC_ADVn_ALE valid FA13 td(csnV-oenV) Delay time, output chip select GPMC_CSni valid to output enable GPMC_OEn_REn valid FA16 tw(aIV) Pulse duration output address GPMC_A[26:1] invalid between 2 successive read and write accesses G(7) ns FA18 td(csnV-oenIV) Delay time, output chip select GPMC_CSni valid to output enable GPMC_OEn_REn invalid (Burst read) FA20 tw(aV) Pulse duration, output address GPMC_A[27:1] valid - 2nd, 3rd, and 4th accesses D(4) ns FA25 td(csnV-wenV) Delay time, output chip select GPMC_CSni valid to output write enable GPMC_WEn valid FA27 td(csnV-wenIV) Delay time, output chip select GPMC_CSni valid to output write enable GPMC_WEn invalid FA28 td(wenV-dV) Delay time, output write enable GPMC_WEn valid to output data GPMC_AD[15:0] valid 2.1 ns www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 169 Product Folder Links: AM2434 AM2432 AM2431

Table 6-61. GPMC and NOR Flash Switching Characteristics – Asynchronous Mode (continued) see Figure 6-44, Figure 6-45, Figure 6-46, Figure 6-47, Figure 6-48, and Figure 6-49 NO. PARAMETER DESCRIPTION MIN MAX UNIT FA29 td(dV-csnV) Delay time, output data GPMC_AD[15:0] valid to output chip select GPMC_CSni valid FA37 td(oenV-aIV) Delay time, output enable GPMC_OEn_REn valid to output address GPMC_AD[15:0] phase end 2.1 ns (1) For single read: A = (CSRdOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14) For single write: A = (CSWrOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14) For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14) For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14) with n being the page burst access number (2) For reading: B = ((ADVRdOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) × GPMC_FCLK(14) For writing: B = ((ADVWrOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) × GPMC_FCLK(14) (3) C = ((OEOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14) (4) D = PageBurstAccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(14) (5) E = ((WEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14) (6) F = ((WEOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14) (7) G = Cycle2CycleDelay × GPMC_FCLK(14) (8) I = ((OEOffTime + (n - 1) × PageBurstAccessTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14) (9) J = (CSOnTime × (TimeParaGranularity + 1) + 0.5 × CSExtraDelay) × GPMC_FCLK(14) (10) K = ((ADVOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) × GPMC_FCLK(14) (11) L = ((OEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14) (12) For single read: N = RdCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK(14) For single write: N = WrCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK(14) For burst read: N = (RdCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14) For burst write: N = (WrCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14) (13) In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. (14) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns. GPMC_FCLK GPMC_CLK GPMC_CSn[i] GPMC_A[MSB:1] GPMC_BE0n_CLE GPMC_BE1n GPMC_ADVn_ALE GPMC_OEn_REn GPMC_AD[15:0] GPMC_WAIT[j] Valid Address Valid Valid Data IN 0 Data IN 0 FA0 FA9 FA10 FA3 FA1 FA4 FA12 FA13 FA0 FA10 FA5 GPMC_06 A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], jis equal to 0 or 1. AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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GPMC_FCLK GPMC_CLK GPMC_CSn[i] GPMC_A[MSB:1] GPMC_BE0n_CLE GPMC_BE1n GPMC_ADVn_ALE GPMC_OEn_REn GPMC_AD[15:0] GPMC_WAIT[j] Add0 Add1 Add2 Add3 Add4 D0 D1 D2 D3 D3 FA1 FA0 FA18 FA13 FA12 FA0 FA9 FA10 FA10 FA21 FA20 FA20FA20 GPMC_08 A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1. B. FA21 parameter illustrates amount of time required to internally sample first input page data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input page data will be internally sampled by active functional clock edge. FA21 calculation must be stored inside AccessTime register bits field. C. FA20 parameter illustrates amount of time required to internally sample successive input page data. It is expressed in number of GPMC functional clock cycles. After each access to input page data, next input page data will be internally sampled by active functional clock edge after FA20 functional clock cycles. FA20 is also the duration of address phases for successive input page data (excluding first input page data). FA20 value must be stored in PageBurstAccessTime register bits field. D. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally. Figure 6-46. GPMC and NOR Flash — Asynchronous Read — Page Mode 4x16–Bit AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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GPMC_FCLK GPMC_CLK GPMC_CSn[i] GPMC_A[MSB:1] GPMC_BE0n_CLE GPMC_BE1n GPMC_ADVn_ALE GPMC_WEn GPMC_AD[15:0] GPMC_WAIT[j] Valid Address Data OUT FA0 FA1 FA10 FA3 FA25 FA29 FA9 FA12 FA27 FA0 FA10 GPMC_09 A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1. Figure 6-47. GPMC and NOR Flash — Asynchronous Write — Single Word www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 173 Product Folder Links: AM2434 AM2432 AM2431

GPMC_FCLK GPMC_CLK GPMC_CSn[i] GPMC_BE0n_CLE GPMC_BE1n GPMC_ADVn_ALE GPMC_OEn_REn GPMC_WAIT[j] Address (MSB) Valid Valid Address (LSB) Data IN Data IN FA0 FA9 FA10 FA3 FA13 FA29 FA1 FA37 FA12 FA4 FA10 FA0 FA5 GPMC_A[27:17] GPMC_AD[15:0] GPMC_10 A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1. B. FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally sampled by active functional clock edge. FA5 value must be stored inside AccessTime register bits field. C. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally. Figure 6-48. GPMC and Multiplexed NOR Flash — Asynchronous Read — Single Word AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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GPMC_FCLK GPMC_CLK GPMC_CSn[i] GPMC_A[27:17] GPMC_BE0n_CLE GPMC_BE1n GPMC_ADVn_ALE GPMC_WEn GPMC_AD[15:0] GPMC_WAIT[j] Address (MSB) Valid Address (LSB) Data OUT FA0 FA1 FA9 FA10 FA3 FA25 FA29 FA12 FA27 FA28 FA0 FA10 GPMC_11 A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1. Figure 6-49. GPMC and Multiplexed NOR Flash — Asynchronous Write — Single Word www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 175 Product Folder Links: AM2434 AM2432 AM2431

6.11.5.8.3 GPMC and NAND Flash — Asynchronous Mode

Table 6-62 and Table 6-63 present timing requirements and switching characteristics for GPMC and NAND Flash — Asynchronous Mode. Table 6-62. GPMC and NAND Flash Timing Requirements – Asynchronous Mode see Figure 6-52 NO. PARAMETER DESCRIPTION MIN MAX UNIT GNF12(1) tacc(d) Access time, input data GPMC_AD15:0 J(2) ns (1) The GNF12 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC functional clock cycles. From start of the read cycle and after GNF12 functional clock cycles, input data is internally sampled by the active functional clock edge. The GNF12 value must be stored inside AccessTime register bit field. (2) J = AccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(3) (3) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns. Table 6-63. GPMC and NAND Flash Switching Characteristics – Asynchronous Mode see Figure 6-50, Figure 6-51, Figure 6-52 and Figure 6-53 NO. PARAMETER MIN MAX UNIT GNF0 tw(wenV) Pulse duration, output write enable GPMC_WEn valid A(1) ns GNF1 td(csnV-wenV) Delay time, output chip select GPMC_CSni valid to output write enable GPMC_WEn valid GNF2 tw(cleH-wenV) Delay time, output lower-byte enable and command latch enable GPMC_BE0n_CLE high to output write enable GPMC_WEn valid GNF3 tw(wenV-dV) Delay time, output data GPMC_AD[15:0] valid to output write enable GPMC_WEn valid GNF4 tw(wenIV-dIV) Delay time, output write enable GPMC_WEn invalid to output data GPMC_AD[15:0] invalid GNF5 tw(wenIV-cleIV) Delay time, output write enable GPMC_WEn invalid to output lower-byte enable and command latch enable GPMC_BE0n_CLE invalid GNF6 tw(wenIV-CSn[i]V) Delay time, output write enable GPMC_WEn invalid to output chip select GPMC_CSni invalid GNF7 tw(aleH-wenV) Delay time, output address valid and address latch enable GPMC_ADVn_ALE high to output write enable GPMC_WEn valid GNF8 tw(wenIV-aleIV) Delay time, output write enable GPMC_WEn invalid to output address valid and address latch enable GPMC_ADVn_ALE invalid GNF9 tc(wen) Cycle time, write H(8) ns GNF10 td(csnV-oenV) Delay time, output chip select GPMC_CSni valid to output enable GPMC_OEn_REn valid GNF13 tw(oenV) Pulse duration, output enable GPMC_OEn_REn valid K(10) ns GNF14 tc(oen) Cycle time, read L(11) ns GNF15 tw(oenIV-CSn[i]V) Delay time, output enable GPMC_OEn_REn invalid to output chip select GPMC_CSni invalid (1) A = (WEOffTime - WEOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14) (2) B = ((WEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14) (3) C = ((WEOnTime - ADVOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - ADVExtraDelay)) × GPMC_FCLK(14) Note: For DeviceType: NAND

During Command Latch Cycle: CLE signal is controlled by the ADVOnTime and ADVWrOffTime timing parameters
During Address Latch Cycle: ALE signal is controlled by the ADVOnTime and ADVWrOffTime timing parameters. (4) D = (WEOnTime × (TimeParaGranularity + 1) + 0.5 × WEExtraDelay) × GPMC_FCLK(14) (5) E = ((WrCycleTime - WEOffTime) × (TimeParaGranularity + 1) - 0.5 × WEExtraDelay) × GPMC_FCLK(14) (6) F = ((ADVWrOffTime - WEOffTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - WEExtraDelay)) × GPMC_FCLK(14) Note: For DeviceType: NAND
During Command Latch Cycle: CLE signal is controlled by the ADVOnTime and ADVWrOffTime timing parameters
During Address Latch Cycle: ALE signal is controlled by the ADVOnTime and ADVWrOffTime timing parameters. (7) G = ((CSWrOffTime - WEOffTime) × (TimeParaGranularity + 1) + 0.5 × (CSExtraDelay - WEExtraDelay)) × GPMC_FCLK(14) (8) H = WrCycleTime × (1 + TimeParaGranularity) × GPMC_FCLK(14) AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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GPMC_CSn[i] GPMC_BE0n_CLE GPMC_ADVn_ALE GPMC_OEn_REn GPMC_FCLK GPMC_WAIT[j] GNF10 GNF14 GNF15 GNF12 GNF13 DA T AGPMC_AD[15:0] GPMC_14 A. GNF12 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after GNF12 functional clock cycles, input data will be internally sampled by active functional clock edge. GNF12 value must be stored inside AccessTime register bits field. B. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally. C. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1. Figure 6-52. GPMC and NAND Flash — Data Read Cycle GPMC_FCLK GPMC_CSn[i] GPMC_BE0n_CLE GPMC_ADVn_ALE GPMC_OEn_REn GPMC_WEn DA T A GNF0 GNF1 GNF4 GNF9 GNF3 GNF6 GPMC_AD[15:0] GPMC_15 A. \`In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. Figure 6-53. GPMC and NAND Flash — Data Write Cycle AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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6.11.5.8.4 GPMC0 IOSETs (ALV/ANI)

Table 6-64 defines valid pin combinations of each ALV/ANI package GPMC0 IOSET. Table 6-64. GPMC0 IOSETs (ALV/ANI) SIGNALS IOSET1 IOSET2 BALL NAME (ALV/ANI) MUXMODE BALL NAME (ALV/ANI) MUXMODE GPMC0_AD0 GPMC0_AD0 0 GPMC0_AD0 0 GPMC0_AD1 GPMC0_AD1 0 GPMC0_AD1 0 GPMC0_AD2 GPMC0_AD2 0 GPMC0_AD2 0 GPMC0_AD3 GPMC0_AD3 0 GPMC0_AD3 0 GPMC0_AD4 GPMC0_AD4 0 GPMC0_AD4 0 GPMC0_AD5 GPMC0_AD5 0 GPMC0_AD5 0 GPMC0_AD6 GPMC0_AD6 0 GPMC0_AD6 0 GPMC0_AD7 GPMC0_AD7 0 GPMC0_AD7 0 GPMC0_AD8 GPMC0_AD8 0 GPMC0_AD8 0 GPMC0_AD9 GPMC0_AD9 0 GPMC0_AD9 0 GPMC0_AD10 GPMC0_AD10 0 GPMC0_AD10 0 GPMC0_AD11 GPMC0_AD11 0 GPMC0_AD11 0 GPMC0_AD12 GPMC0_AD12 0 GPMC0_AD12 0 GPMC0_AD13 GPMC0_AD13 0 GPMC0_AD13 0 GPMC0_AD14 GPMC0_AD14 0 GPMC0_AD14 0 GPMC0_AD15 GPMC0_AD15 0 GPMC0_AD15 0 GPMC0_CLK GPMC0_CLK 0 GPMC0_CLK 0 GPMC0_ADVn_ALE GPMC0_ADVn_ALE 0 GPMC0_ADVn_ALE 0 GPMC0_OEn_REn GPMC0_OEn_REn 0 GPMC0_OEn_REn 0 GPMC0_WEn GPMC0_WEn 0 GPMC0_WEn 0 GPMC0_BE0n_CLE GPMC0_BE0n_CLE 0 GPMC0_BE0n_CLE 0 GPMC0_BE1n GPMC0_BE1n 0 GPMC0_BE1n 0 GPMC0_WAIT0 GPMC0_WAIT0 0 GPMC0_WAIT0 0 GPMC0_WAIT1 GPMC0_WAIT1 0 GPMC0_WAIT1 0 GPMC0_WPn GPMC0_WPn 0 GPMC0_WPn 0 GPMC0_DIR GPMC0_DIR 0 GPMC0_DIR 0 GPMC0_CSn0 GPMC0_CSn0 0 GPMC0_CSn0 0 GPMC0_CSn1 GPMC0_CSn1 0 GPMC0_CSn1 0 GPMC0_CSn2 GPMC0_CSn2 0 GPMC0_CSn2 0 GPMC0_CSn3 GPMC0_CSn3 0 GPMC0_CSn3 0 GPMC0_AD16 PRG1_PRU0_GPO0 8 PRG1_PRU0_GPO0 8 GPMC0_AD17 PRG1_PRU0_GPO1 8 PRG1_PRU0_GPO1 8 GPMC0_AD18 PRG1_PRU0_GPO2 8 PRG1_PRU0_GPO2 8 GPMC0_AD19 PRG1_PRU0_GPO3 8 PRG1_PRU0_GPO3 8 GPMC0_AD20 PRG1_PRU0_GPO4 8 PRG1_PRU0_GPO4 8 GPMC0_AD21 PRG1_PRU0_GPO5 8 PRG1_PRU0_GPO5 8 GPMC0_AD22 PRG1_PRU0_GPO6 8 PRG1_PRU0_GPO6 8 GPMC0_AD23 PRG1_PRU0_GPO7 8 PRG1_PRU0_GPO7 8 GPMC0_AD24 PRG1_PRU0_GPO8 8 PRG1_PRU0_GPO8 8 GPMC0_AD25 PRG1_PRU0_GPO9 8 PRG1_PRU0_GPO9 8 GPMC0_AD26 PRG1_PRU0_GPO10 8 PRG1_PRU0_GPO10 8 www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 179 Product Folder Links: AM2434 AM2432 AM2431

Table 6-64. GPMC0 IOSETs (ALV/ANI) (continued) SIGNALS IOSET1 IOSET2 BALL NAME (ALV/ANI) MUXMODE BALL NAME (ALV/ANI) MUXMODE GPMC0_AD27 PRG1_PRU0_GPO11 8 PRG1_PRU0_GPO11 8 GPMC0_AD28 PRG1_PRU0_GPO12 8 PRG1_PRU0_GPO12 8 GPMC0_AD29 PRG1_PRU0_GPO13 8 PRG1_PRU0_GPO13 8 GPMC0_AD30 PRG1_PRU0_GPO14 8 PRG1_PRU0_GPO14 8 GPMC0_AD31 PRG1_PRU0_GPO15 8 PRG1_PRU0_GPO15 8 GPMC0_BE2n PRG1_PRU0_GPO16 8 PRG1_PRU0_GPO16 8 GPMC0_A0 PRG1_PRU0_GPO17 8 PRG0_PRU0_GPO2 9 GPMC0_A1 PRG1_PRU0_GPO18 8 PRG0_PRU0_GPO4 9 GPMC0_A2 PRG1_PRU0_GPO19 8 PRG0_PRU0_GPO8 9 GPMC0_A3 PRG1_PRU1_GPO0 8 PRG0_PRU0_GPO14 9 GPMC0_A4 PRG1_PRU1_GPO1 8 PRG0_PRU0_GPO16 9 GPMC0_A5 PRG1_PRU1_GPO2 8 PRG0_PRU0_GPO18 9 GPMC0_A6 PRG1_PRU1_GPO3 8 PRG0_PRU0_GPO19 9 GPMC0_A7 PRG1_PRU1_GPO4 8 PRG0_PRU1_GPO12 9 GPMC0_A8 PRG1_PRU1_GPO5 8 PRG0_PRU1_GPO13 9 GPMC0_A9 PRG1_PRU1_GPO6 8 PRG0_PRU1_GPO14 9 GPMC0_A10 PRG1_PRU1_GPO7 8 PRG0_PRU1_GPO15 9 GPMC0_A11 PRG1_PRU1_GPO8 8 PRG0_PRU1_GPO16 9 GPMC0_A12 PRG1_PRU1_GPO9 8 PRG0_MDIO0_MDIO 9 GPMC0_A13 PRG1_PRU1_GPO10 8 PRG0_MDIO0_MDC 9 GPMC0_A14 PRG1_PRU1_GPO11 8 PRG0_PRU0_GPO12 9 GPMC0_A15 PRG1_PRU1_GPO12 8 PRG0_PRU0_GPO13 9 GPMC0_A16 PRG1_PRU1_GPO13 8 PRG0_PRU0_GPO15 9 GPMC0_A17 PRG1_PRU1_GPO14 8 PRG0_PRU0_GPO17 9 GPMC0_A18 PRG1_PRU1_GPO15 8 PRG0_PRU1_GPO3 9 GPMC0_A19 PRG1_PRU1_GPO16 8 PRG0_PRU1_GPO6 9 GPMC0_BE3n PRG1_PRU1_GPO17 8 PRG1_PRU1_GPO17 8 GPMC0_A20 GPMC0_CSn3 4 GPMC0_CSn3 4 GPMC0_A21 GPMC0_WAIT1 4 GPMC0_WAIT1 4 GPMC0_A22 GPMC0_WPn 4 GPMC0_WPn 4 AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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6.11.5.9 I2C

The device contains six multicontroller Inter-Integrated Circuit (I2C) controllers. Each I2C controller was designed to be compliant to the Philips I 2C-bus™ specification version 2.1. However, the device IOs are not fully compliant to the I2C electrical specification. The speeds supported and exceptions are described per port below:

MCU_I2C1, I2C1, I2C2, and I2C3 – Speeds:
Standard-mode (up to 100Kbits/s) – 1.8V – 3.3V
Fast-mode (up to 400Kbits/s) – 1.8V – 3.3V – Exceptions:
The IOs associated with these ports are not compliant to the fall time requirements defined in the I2C specification because they are implemented with higher performance LVCMOS push-pull IOs that were designed to support other signal functions that could not be implemented with I2C compatible IOs. The LVCMOS IOs being used on these ports are connected such they emulate open-drain outputs. This emulation is achieved by forcing a constant low output and disabling the output buffer to enter the Hi-Z state.
The I2C specification defines a maximum input voltage VIH of (VDDmax + 0.5V), which exceeds the absolute maximum ratings for the device IOs. The system must be designed to ensure the I2C signals never exceed the limits defined in the Absolute Maximum Ratings section of this datasheet.
MCU_I2C0 and I2C0 – Speeds:
Standard-mode (up to 100Kbits/s) – 1.8V – 3.3V
Fast-mode (up to 400Kbits/s) – 1.8V – 3.3V
Hs-mode (up to 3.4Mbit/s) – 1.8V – Exceptions:
The IOs associated with these ports were not design to support Hs-mode while operating at 3.3V. So Hs-mode is limited to 1.8V operation.
The rise and fall times of the I2C signals connected to these ports must not exceed a slew rate of 0.08V/ns (or 8E+7V/s) when operating at 3.3V. This limit is more restrictive than the minimum fall time limits defined in the I2C specification. Therefore, it may be necessary to add additional capacitance to the I2C signals to slow the rise and fall times such that they do not exceed a slew rate of 0.08V/ns.
The I2C specification defines a maximum input voltage VIH of (VDDmax + 0.5V), which exceeds the absolute maximum ratings for the device IOs. The system must be designed to ensure the I2C signals never exceed the limits defined in the Absolute Maximum Ratings section of this datasheet. Note I2C2 has one or more signals which can be multiplexed to more than one pin. Timing is only valid for specific pin combinations known as IOSETs. Valid pin combinations or IOSETs for this interface are defined in the SysConfig-PinMux Tool. Refer to the Philips I2C-bus specification version 2.1 for timing details. For more details about features and additional description information on the device Inter-Integrated Circuit, see the corresponding subsections within Signal Descriptions and Detailed Description sections. www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 181 Product Folder Links: AM2434 AM2432 AM2431

6.11.5.10 MCAN

Table 6-65 and Table 6-66 presents timing conditions and switching characteristics for MCAN. For more details about features and additional description information on the device Controller Area Network Interface, see the corresponding subsections within Signal Descriptions and Detailed Description sections. Note The device has multiple MCAN modules. MCANn is a generic prefix applied to MCAN signal names, where n represents the specific MCAN module. Table 6-65. MCAN Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate 2 15 V/ns OUTPUT CONDITIONS CL Output load capacitance 5 20 pF Table 6-66. MCAN Switching Characteristics NO. PARAMETER DESCRIPTION MIN MAX UNIT MCAN1 td(MCAN_TX) Delay time, transmit shift register to MCANn_TX 10 ns MCAN2 td(MCAN_RX) Delay time, MCANn_RX to receive shift register 10 ns For more information, see Controller Area Network (MCAN) section in Peripherals chapter in the device TRM. AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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6.11.5.11 MCSPI

For more details about features and additional description information on the device Serial Port Interface, see the corresponding subsections within Signal Descriptions and Detailed Description sections. Table 6-67 presents timing conditions for MCSPI. Table 6-67. MCSPI Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate 2 8.5 V/ns OUTPUT CONDITIONS CL Output load capacitance 6 12 pF For more information, see Multichannel Serial Peripheral Interface (MCSPI) section in Peripherals chapter in the device TRM. www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 183 Product Folder Links: AM2434 AM2432 AM2431

6.11.5.11.1 MCSPI — Controller Mode

Table 6-68, Figure 6-54, Table 6-69, and Figure 6-55 present timing requirements and switching characteristics for SPI – Controller Mode. Table 6-68. MCSPI Timing Requirements – Controller Mode see Figure 6-54 NO. PARAMETER DESCRIPTION MIN MAX UNIT SM4 tsu(POCI-SPICLK) Setup time, SPIn_D[x] valid before SPIn_CLK active edge 2.8 ns SM5 th(SPICLK-POCI) Hold time, SPIn_D[x] valid after SPIn_CLK active edge 3 ns SPI_CS[i] (OUT) SPI_SCLK (OUT) SPI_SCLK (OUT) SPI_D[x] (IN) SPI_CS[i] (OUT) SPI_SCLK (OUT) SPI_SCLK (OUT) SPI_D[x] (IN) Bit n-1 Bit n-2 Bit n-3 Bit n-4 Bit 0 Bit n-1 Bit n-2 Bit n-3 Bit 1 Bit 0 PHA=0 EPOL=1 PHA=1 EPOL=1 POL=0 POL=1 POL=0 POL=1 SM8 SM9 SM3 SM1 SM2 SM1 SM8 SM9SM3 SM1 SM2 SM1 SM2 SM3 SM2 SM3 SM4 SM5 SM4 SM5 SM4 SM4 SM5 SM5 SPRSP08_TIMING_McSPI_02 Figure 6-54. MCSPI Controller Mode Receive Timing AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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Table 6-69. MCSPI Switching Characteristics - Controller Mode see Figure 6-55 NO. PARAMETER MIN MAX UNIT SM1 tc(SPICLK) Cycle time, SPIn_CLK 20 ns SM2 tw(SPICLKL) Pulse duration, SPIn_CLK low 0.5P - 1 (1) ns SM3 tw(SPICLKH) Pulse duration, SPIn_CLK high 0.5P - 1 (1) ns SM6 td(SPICLK-PICO) Delay time, SPIn_CLK active edge to SPIn_D[x] -3 2.5 ns SM7 td(CS-PICO) Delay time, SPIn_CSi active edge to SPIn_D[x] 5 ns SM8 td(CS-SPICLK) Delay time, SPIn_CSi active to SPIn_CLK first edge PHA = 0 B - 4(2) ns PHA = 1 A - 4(3) ns SM9 td(SPICLK-CS) Delay time, SPIn_CLK last edge to SPIn_CSi inactive PHA = 0 A - 4(4) ns PHA = 1 B - 4(5) ns (1) P = SPI_CLK period in ns. (2) T_ref is the period of the McSPI functional clock in ns. Fratio is the divide ratio of McSPI functional clock frequency to SPIn_CLK clock frequency, controlled by the CLKD and CLKG bit fields in the MCSPI_CH(i)CONF register and the EXTCLK bit field in the MCSPI_CH(i)CTRL register. TCS(i) is the value programmed into the chip select time control bit field of the MCSPI_CH(i)CONF register.

When Fratio = 1; B = (TCS(i) + 0.5) * T_ref.
When Fratio ≥ 2 and even value; B = (TCS(i) + 0.5) * Fratio * T_ref.
When Fratio ≥ 3 and odd value; B = ((TCS(i) * Fratio) + ((Fratio + 1) / 2 )) * T_ref. (3) T_ref is the period of the McSPI functional clock. Fratio is the divide ratio of McSPI functional clock frequency to SPIn_CLK clock frequency, controlled by the CLKD and CLKG bit fields in the MCSPI_CH(i)CONF register and the EXTCLK bit field in the MCSPI_CH(i)CTRL register. TCS(i) is the value programmed into the chip select time control bit field of the MCSPI_CH(i)CONF register.
When Fratio = 1; A = (TCS(i) + 1) * T_ref.
When Fratio ≥ 2 and even value; A = (TCS(i) + 0.5) * Fratio * T_ref.
When Fratio ≥ 3 and odd value; A = ((TCS(i) * Fratio) + ((Fratio - 1) / 2 )) * T_ref. (4) T_ref is the period of the McSPI functional clock. Fratio is the divide ratio of McSPI functional clock frequency to SPIn_CLK clock frequency, controlled by the CLKD and CLKG bit fields in the MCSPI_CH(i)CONF register and the EXTCLK bit field in the MCSPI_CH(i)CTRL register. TCS(i) is the value programmed into the chip select time control bit field of the MCSPI_CH(i)CONF register.
When Fratio = 1; A = (TCS(i) + 1) * T_ref.
When Fratio ≥ 2 and even value; A = (TCS(i) + 0.5) * Fratio * T_ref.
When Fratio ≥ 3 and odd value; A = ((TCS(i) * Fratio) + ((Fratio + 1) / 2 )) * T_ref. (5) T_ref is the period of the McSPI functional clock. Fratio is the divide ratio of McSPI functional clock frequency to SPIn_CLK clock frequency, controlled by the CLKD and CLKG bit fields in the MCSPI_CH(i)CONF register and the EXTCLK bit field in the MCSPI_CH(i)CTRL register. TCS(i) is the value programmed into the chip select time control bit field of the MCSPI_CH(i)CONF register.
When Fratio = 1; B = (TCS(i) + 0.5) * T_ref.
When Fratio ≥ 2 and even value; B = (TCS(i) + 0.5) * Fratio * T_ref.
When Fratio ≥ 3 and odd value; B = ((TCS(i) * Fratio) + ((Fratio - 1) / 2 )) * T_ref. www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 185 Product Folder Links: AM2434 AM2432 AM2431

SPI_CS[i] (OUT) SPI_SCLK (OUT) SPI_SCLK (OUT) SPI_D[x] (OUT) SPI_CS[i] (OUT) SPI_SCLK (OUT) SPI_SCLK (OUT) SPI_D[x] (OUT) Bit n-1 Bit n-2 Bit n-3 Bit n-4 Bit 0 Bit n-1 Bit n-2 Bit n-3 Bit 1 Bit0 PHA=0 EPOL=1 POL=0 POL=1 PHA=1 EPOL=1 POL=0 POL=1 SM8 SM9 SM6 SM3 SM1 SM2 SM1 SM8 SM9SM3 SM1 SM2 SM1 SM6 SM7 SM6 SM2 SM3 SM2 SM3 SM6 SM6 SM6 SPRSP08_TIMING_McSPI_01 Figure 6-55. MCSPI Controller Mode Transmit Timing AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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6.11.5.11.2 MCSPI — Peripheral Mode

Table 6-70, Figure 6-56, Table 6-71, and Figure 6-57 present timing requirements and switching characteristics for SPI – Peripheral Mode. Table 6-70. MCSPI Timing Requirements – Peripheral Mode see Figure 6-56 NO. PARAMETER DESCRIPTION MIN MAX UNIT SS1 tc(SPICLK) Cycle time, SPIn_CLK 20 ns SS2 tw(SPICLKL) Pulse duration, SPIn_CLK low 0.45P (1) ns SS3 tw(SPICLKH) Pulse duration, SPIn_CLK high 0.45P (1) ns SS4 tsu(PICO-SPICLK) Setup time, SPIn_D[x] valid before SPIn_CLK active edge 5 ns SS5 th(SPICLK-PICO) Hold time, SPIn_D[x] valid after SPIn_CLK active edge 5 ns SS8 tsu(CS-SPICLK) Setup time, SPIn_CSi valid before SPIn_CLK first edge 5 ns SS9 th(SPICLK-CS) Hold time, SPIn_CSi valid after SPIn_CLK last edge 5 ns (1) P = SPIn_CLK period in ns. SPI_CS[i] (IN) SPI_SCLK (IN) SPI_SCLK (IN) SPI_D[x] (IN) SPI_CS[i] (IN) SPI_SCLK (IN) SPI_SCLK (IN) SPI_D[x] (IN) Bit n-1 Bit n-2 Bit n-3 Bit n-4 Bit 0 Bit n-1 Bit n-2 Bit n-3 Bit 1 Bit 0 PHA=0 EPOL=1 POL=0 POL=1 POL=0 POL=1 PHA=1 EPOL=1 SS3 SS1 SS3 SS1 SS3 SS1 SS2 SS1 SS8 SS9 SS8 SS9 SS2 SS3 SS2 SS2 SS4 SS5 SS5 SS4 SS4 SS5 SS4 SS5 SPRSP08_TIMING_McSPI_04 Figure 6-56. SPI Peripheral Mode Receive Timing www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 187 Product Folder Links: AM2434 AM2432 AM2431

Table 6-71. MCSPI Switching Characteristics – Peripheral Mode see Figure 6-57 NO. PARAMETER DESCRIPTION MIN MAX UNIT SS6 td(SPICLK-POCI) Delay time, SPIn_CLK active edge to SPIn_D[x] 2 10.5 ns SS7 tsk(CS-POCI) Delay time, SPIn_CSi active edge to SPIn_D[x] 18.5 ns SPI_CS[i] (IN) SPI_SCLK (IN) SPI_SCLK (IN) SPI_D[x] (OUT) SPI_CS[i] (IN) SPI_SCLK (IN) SPI_SCLK (IN) SPI_D[x] (OUT) Bit n-1 Bit n-2 Bit n-3 Bit n-4 Bit 0 Bit n-1 Bit n-2 Bit n-3 Bit 1 Bit 0 PHA=0 EPOL=1 POL=0 POL=1 POL=0 POL=1 PHA=1 EPOL=1 SS6 SS3 SS1 SS3 SS1 SS3 SS1 SS2 SS1 SS6 SS6 SS8 SS9 SS7 SS8 SS2 SS3 SS2 SS2 SS6 SS6SS6 SS9 SPRSP08_TIMING_McSPI_03 Figure 6-57. SPI Peripheral Mode Transmit Timing AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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6.11.5.12 MMCSD

The MMCSD Host Controller provides an interface to embedded Multi-Media Card (MMC), Secure Digital (SD), and Secure Digital IO (SDIO) devices. The MMCSD Host Controller deals with MMC/SD/SDIO protocol at transmission level, data packing, adding cyclic redundancy checks (CRCs), start/end bit insertion, and checking for syntactical correctness. For more details about MMCSD interfaces, see the corresponding MMC0 and MMC1 subsections within Signal Descriptions and Detailed Description sections. Note Some operating modes require software configuration of the MMC DLL delay settings, as shown in Table 6-72 and Table 6-82. The modes which show a value of "Tuning" in the ITAPDLYSEL column of Table 6-72 and Table 6-82 require a tuning algorithm to be used for optimizing input timing. Refer to the MMCSD Programming Guide in the device TRM for more information on the tuning algorithm and configuration of input delays required to optimize input timing. For more information, see Multi-Media Card/Secure Digital (MMCSD) Interface section in Peripherals chapter in the device TRM.

6.11.5.12.1 MMC0 - eMMC Interface

MMC0 interface is compliant with the JEDEC eMMC electrical standard v5.1 (JESD84-B51) and supports the following eMMC applications:

Legacy speed
High speed SDR
High speed DDR
HS200 Table 6-72 presents the required DLL software configuration settings for MMC0 timing modes. Table 6-72. MMC0 DLL Delay Mapping for all Timing Modes REGISTER NAME MMCSD0_MMC_SSCFG_PHY_CTRL_x_REG x = 1 x = 4 x = 5 BIT FIELD NAME ENDLL STRBSEL OTAPDLYENA OTAPDLYSEL ITAPDLYENA ITAPDLYSEL SELDLYTXCLK SELDLYRXCLK FRQSEL CLKBUFSEL MODE DESCRIPTION ENABLE DLL STROBE DELAY OUTPUT DELAY ENABLE OUTPUT DELAY VALUE INPUT DELAY ENABLE INPUT DELAY VALUE DLL DELAY CHAIN SELECT DLL REF FREQUENCY DELAY BUFFER DURATION Legacy SDR 8-bit PHY operating 1.8V, 25MHz 0x0 0x0 NA(1) NA(1) 0x1 0x10 0x1 or 0x3(2) NA(3) 0x7 High Speed SDR 8-bit PHY operating 1.8V, 50MHz 0x0 0x0 NA(1) NA(1) 0x1 0xA 0x1 or 0x3(2) NA(3) 0x7 High Speed DDR 8-bit PHY operating 1.8V, 50MHz 0x1 0x0 0x1 0x6 0x1 0x3 0x0 0x4 NA(4) HS200 8-bit PHY operating 1.8V, 200MHz 0x1 0x0 0x1 0x7 0x1 Tuning(5) 0x0 0x0 NA(4) (1) NA means this register field has no function when operating with half-cycle timing, which is required for this mode. (2) The SELDLYTXCLK bit has no function when operating with half-cycle timing, which is required for this mode. (3) NA means this register field has no function when ENDLL is set to 0x0. (4) NA means this register field has no function when ENDLL is set to 0x1. (5) Tuning means this mode requires a tuning algorithm to be used to determine optimal input timing Table 6-73 presents timing conditions for MMC0. www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 189 Product Folder Links: AM2434 AM2432 AM2431

Table 6-73. MMC0 Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate Legacy SDR 0.14 1.44 V/ns High Speed SDR 0.3 0.9 V/ns High Speed DDR (CMD) 0.3 0.9 V/ns High Speed DDR (DAT[7:0]) 0.45 0.9 V/ns OUTPUT CONDITIONS CL Output load capacitance Legacy SDR 1 12 pF High Speed SDR 1 12 pF High Speed DDR 1 12 pF HS200 1 6 pF PCB CONNECTIVITY REQUIREMENTS td(Trace Delay) Propagation delay of each trace All modes 126 756 ps td(Trace Mismatch Delay) Propagation delay mismatch across all traces Legacy SDR, High Speed SDR 100 ps High Speed DDR, HS200 8 ps AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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Table 6-74, Figure 6-58, Table 6-75, and Figure 6-59 present timing requirements and switching characteristics for MMC0 – Legacy SDR Mode. Table 6-74. MMC0 Timing Requirements – Legacy SDR Mode see Figure 6-58 NO. MIN MAX UNIT LSDR1 tsu(cmdV-clkH) Setup time, MMC0_CMD valid before MMC0_CLK rising edge 1.56 ns LSDR2 th(clkH-cmdV) Hold time, MMC0_CMD valid after MMC0_CLK rising edge 5.44 ns LSDR3 tsu(dV-clkH) Setup time, MMC0_DAT[7:0] valid before MMC0_CLK rising edge 1.56 ns LSDR4 th(clkH-dV) Hold time, MMC0_DAT[7:0] valid after MMC0_CLK rising edge 5.44 ns Figure 6-58. MMC0 – Legacy SDR – Receive Mode Table 6-75. MMC0 Switching Characteristics – Legacy SDR Mode see Figure 6-59 NO. PARAMETER MIN MAX UNIT fop(clk) Operating frequency, MMC0_CLK 25 MHz LSDR5 tc(clk) Cycle time, MMC0_CLK 40 ns LSDR6 tw(clkH) Pulse duration, MMC0_CLK high 18.7 ns LSDR7 tw(clkL) Pulse duration, MMC0_CLK low 18.7 ns LSDR8 td(clkL-cmdV) Delay time, MMC0_CLK falling edge to MMC0_CMD transition -2.3 2.9 ns LSDR9 td(clkL-dV) Delay time, MMC0_CLK falling edge to MMC0_DAT[7:0] transition -2.3 2.9 ns Figure 6-59. MMC0 – Legacy SDR – Transmit Mode www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 191 Product Folder Links: AM2434 AM2432 AM2431

Table 6-76, Figure 6-60, Table 6-77, and Figure 6-61 present timing requirements and switching characteristics for MMC0 – High Speed SDR Mode. Table 6-76. MMC0 Timing Requirements – High Speed SDR Mode see Figure 6-60 NO. MIN MAX UNIT HSSDR1 tsu(cmdV-clkH) Setup time, MMC0_CMD valid before MMC0_CLK rising edge 2.55 ns HSSDR2 th(clkH-cmdV) Hold time, MMC0_CMD valid after MMC0_CLK rising edge 2.67 ns HSSDR3 tsu(dV-clkH) Setup time, MMC0_DAT[7:0] valid before MMC0_CLK rising edge 2.55 ns HSSDR4 th(clkH-dV) Hold time, MMC0_DAT[7:0] valid after MMC0_CLK rising edge 2.67 ns Figure 6-60. MMC0 – High Speed SDR Mode – Receive Mode Table 6-77. MMC0 Switching Characteristics – High Speed SDR Mode see Figure 6-61 NO. PARAMETER MIN MAX UNIT fop(clk) Operating frequency, MMC0_CLK 50 MHz HSSDR5 tc(clk) Cycle time, MMC0_CLK 20 ns HSSDR6 tw(clkH) Pulse duration, MMC0_CLK high 9.2 ns HSSDR7 tw(clkL) Pulse duration, MMC0_CLK low 9.2 ns HSSDR8 td(clkL-cmdV) Delay time, MMC0_CLK falling edge to MMC0_CMD transition -2.3 2.9 ns HSSDR9 td(clkL-dV) Delay time, MMC0_CLK falling edge to MMC0_DAT[7:0] transition -2.3 2.9 ns Figure 6-61. MMC0 – High Speed SDR Mode – Transmit Mode AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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Table 6-78, Figure 6-62, Table 6-79, and Figure 6-63 present timing requirements and switching characteristics for MMC0 – High Speed DDR Mode. Table 6-78. MMC0 Timing Requirements – High Speed DDR Mode see Figure 6-62 NO. MIN MAX UNIT HSDDR1 tsu(cmdV-clk) Setup time, MMC0_CMD valid before MMC0_CLK rising edge 1.62 ns HSDDR2 th(clk-cmdV) Hold time, MMC0_CMD valid after MMC0_CLK rising edge 2.52 ns HSDDR3 tsu(dV-clk) Setup time, MMC0_DAT[7:0] valid before MMC0_CLK transition 0.83 ns HSDDR4 th(clk-dV) Hold time, MMC0_DAT[7:0] valid after MMC0_CLK transition 1.76 ns Figure 6-62. MMC0 – High Speed DDR Mode – Receive Mode Table 6-79. MMC0 Switching Characteristics – High Speed DDR Mode see Figure 6-63 NO. PARAMETER MIN MAX UNIT fop(clk) Operating frequency, MMC0_CLK 50 MHz HSDDR5 tc(clk) Cycle time, MMC0_CLK 20 ns HSDDR6 tw(clkH) Pulse duration, MMC0_CLK high 9.2 ns HSDDR7 tw(clkL) Pulse duration, MMC0_CLK low 9.2 ns HSDDR8 td(clk-cmdV) Delay time, MMC0_CLK rising edge to MMC0_CMD transition 3.31 7.65 ns HSDDR9 td(clk-dV) Delay time, MMC0_CLK transition to MMC0_DAT[7:0] transition 2.81 6.94 ns Figure 6-63. MMC0 – High Speed DDR Mode – Transmit Mode www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 193 Product Folder Links: AM2434 AM2432 AM2431

Table 6-80, Figure 6-64, Table 6-81, and Figure 6-65 present switching characteristics for MMC0 – HS200 Mode. Table 6-80. MMC0 Timing Requirements – HS200 Mode see Figure 6-64 NO. MIN MAX UNIT HS2004 tDVW Input data valid window, MMC0_CMD and MMC0_DAT[7:0] 2.0(1) ns (1) This parameter defines the minimum data valid window required by the host, where any data valid window presented to the host greater than this value ensures the host is able to capture valid data. The value defined by this parameter is smaller than the smallest possible data valid window defined for any eMMC device operating in HS200 mode. MMC0_CMD MMC0_DAT[7:0] VIH VIL Valid Window HS2004 Figure 6-64. MMC0 – HS200 – Receive Mode Table 6-81. MMC0 Switching Characteristics – HS200 Mode see Figure 6-65 NO. PARAMETER MIN MAX UNIT fop(clk) Operating frequency, MMC0_CLK 200 MHz HS2005 tc(clk) Cycle time, MMC0_CLK 5 ns HS2006 tw(clkH) Pulse duration, MMC0_CLK high 2.08 ns HS2007 tw(clkL) Pulse duration, MMC0_CLK low 2.08 ns HS2008 td(clkL-cmdV) Delay time, MMC0_CLK rising edge to MMC0_CMD transition 0.99 3.28 ns HS2009 td(clkL-dV) Delay time, MMC0_CLK rising edge to MMC0_DAT[7:0] transition 0.99 3.28 ns Figure 6-65. MMC0 – HS200 Mode – Transmit Mode AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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6.11.5.12.2 MMC1 - SD/SDIO Interface

MMC1 interface is compliant with the SD Host Controller Standard Specification 4.10 and SD Physical Layer Specification v3.01 as well as SDIO Specification v3.00 and it supports the following SD Card applications:

Default speed
High speed
UHS–I SDR12
UHS–I SDR25
UHS–I SDR50
UHS–I SDR104
UHS–I DDR50 Table 6-82 presents the required DLL software configuration settings for MMC1 timing modes. Table 6-82. MMC1 DLL Delay Mapping for all Timing Modes REGISTER NAME MMCSD1_MMC_SSCFG_PHY_CTRL_4_REG BIT FIELD [20] [15:12] [8] [4:0] BIT FIELD NAME OTAPDLYENA OTAPDLYSEL ITAPDLYENA ITAPDLYSEL MODE DESCRIPTION DELAY ENABLE DELAY VALUE INPUT DELAY ENABLE INPUT DELAY VALUE Default Speed 4-bit PHY operating 3.3V, 25MHz NA(1) NA(1) 0x1 0x0 High Speed 4-bit PHY operating 3.3V, 50MHz NA(1) NA(1) 0x1 0x0 UHS-I SDR12 4-bit PHY operating 1.8V, 25MHz 0x1 0xF 0x1 0x0 UHS-I SDR25 4-bit PHY operating 1.8V, 50MHz 0x1 0xF 0x1 0x0 UHS-I SDR50 4-bit PHY operating 1.8V, 100MHz 0x1 0xC 0x1 Tuning(2) UHS-I DDR50 4-bit PHY operating 1.8V, 50MHz 0x1 0x9 0x1 Tuning(2) UHS-I SDR104 4-bit PHY operating 1.8V 200MHz 0x1 0x6 0x1 Tuning(2) (1) NA means this register field has no function when operating with half-cycle timing, which is required for this mode. (2) Tuning means this mode requires a tuning algorithm to be used to determine optimal input timing Table 6-83 presents timing conditions for MMC1. www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 195 Product Folder Links: AM2434 AM2432 AM2431

Table 6-83. MMC1 Timing Conditions PARAMETER MIN MAX UNIT Input Conditions SRI Input slew rate Default Speed, High Speed 0.69 2.06 V/ns UHS–I SDR12, UHS–I SDR25 0.34 1.34 V/ns UHS–I DDR50 1 2 V/ns Output Conditions CL Output load capacitance UHS–I DDR50 3 10 pF All other modes 1 10 pF PCB Connectivity Requirements td(Trace Delay) Propagation delay of each trace UHS–I DDR50 240 1134 ps All other modes 126 1386 ps td(Trace Mismatch Delay) Propagation delay mismatch across all traces UHS–I DDR50, UHS–I SDR104 20 ps All other modes 100 ps AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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Table 6-84, Figure 6-66, Table 6-85, and Figure 6-67 present timing requirements and switching characteristics for MMC1 – Default Speed Mode. Table 6-84. Timing Requirements for MMC1 – Default Speed Mode see Figure 6-66 NO. MIN MAX UNIT DS1 tsu(cmdV-clkH) Setup time, MMC1_CMD valid before MMCi_CLK rising edge 2.15 ns DS2 th(clkH-cmdV) Hold time, MMC1_CMD valid after MMC1_CLK rising edge 1.67 ns DS3 tsu(dV-clkH) Setup time, MMC1_DAT[3:0] valid before MMC1_CLK rising edge 2.15 ns DS4 th(clkH-dV) Hold time, MMC1_DAT[3:0] valid after MMC1_CLK rising edge 1.67 ns MMC[ ]_CLKx M [ ]_MC CMDx MMC DA T[ ]_ [3:0]x DS1 DS2 DS3 DS4 Figure 6-66. MMC1 – Default Speed – Receive Mode Table 6-85. Switching Characteristics for MMC1 – Default Speed Mode see Figure 6-67 NO. PARAMETER MIN MAX UNIT fop(clk) Operating frequency, MMC1_CLK 25 MHz DS5 tc(clk) Cycle time, MMC1_CLK 40 ns DS6 tw(clkH) Pulse duration, MMC1_CLK high 18.7 ns DS7 tw(clkL) Pulse duration, MMC1_CLK low 18.7 ns DS8 td(clkL-cmdV) Delay time, MMC1_CLK falling edge to MMC1_CMD transition -1.8 1.8 ns DS9 td(clkL-dV) Delay time, MMC1_CLK falling edge to MMC1_DAT[3:0] transition -1.8 1.8 ns MMC[ ]_CLKx MMC CMD[ ]_ x MMC DA T[ _ [3:0]x] D 5 S D 7 S D 8 S D 9 S DS6 Figure 6-67. MMC1 – Default Speed – Transmit Mode www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 197 Product Folder Links: AM2434 AM2432 AM2431

Table 6-86, Figure 6-68, Table 6-87, and Figure 6-69 present timing requirements and switching characteristics for MMC1 – High Speed Mode. Table 6-86. Timing Requirements for MMC1 – High Speed Mode see Figure 6-68 NO. MIN MAX UNIT HS1 tsu(cmdV-clkH) Setup time, MMC1_CMD valid before MMC1_CLK rising edge 2.15 ns HS2 th(clkH-cmdV) Hold time, MMC1_CMD valid after MMC1_CLK rising edge 1.67 ns HS3 tsu(dV-clkH) Setup time, MMC1_DAT[3:0] valid before MMC1_CLK rising edge 2.15 ns HS4 th(clkH-dV) Hold time, MMC1_DAT[3:0] valid after MMC1_CLK rising edge 1.67 ns MMC[ ]_CLKx MMC[ ]_CMDx MMC DA T[ ]_ [3:0]x H 1 S H 2 S H 3 S H 4 S Figure 6-68. MMC1 – High Speed – Receive Mode Table 6-87. Switching Characteristics for MMC1 – High Speed Mode see Figure 6-69 NO. PARAMETER MIN MAX UNIT fop(clk) Operating frequency, MMC1_CLK 50 MHz HS5 tc(clk) Cycle time. MMC1_CLK 20 ns HS6 tw(clkH) Pulse duration, MMC1_CLK high 9.2 ns HS7 tw(clkL) Pulse duration, MMC1_CLK low 9.2 ns HS8 td(clkL-cmdV) Delay time, MMC1_CLK falling edge to MMC1_CMD transition -1.8 1.8 ns HS9 td(clkL-dV) Delay time, MMC1_CLK falling edge to MMC1_DAT[3:0] transition -1.8 1.8 ns MMC[x]_CLK MMC CMD[ ]_ x MMC DA T[ ]_ [3:0]x H 5 S H 7 S H 8 S H 9 S HS6 Figure 6-69. MMC1 – High Speed – Transmit Mode AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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Table 6-88, Figure 6-70, Table 6-89, and Figure 6-71 present timing requirements and switching characteristics for MMC1 – UHS-I SDR12 Mode. Table 6-88. Timing Requirements for MMC1 – UHS-I SDR12 Mode see Figure 6-70 NO. MIN MAX UNIT SDR121 tsu(cmdV-clkH) Setup time, MMC1_CMD valid before MMC1_CLK rising edge 2.35 ns SDR122 th(clkH-cmdV) Hold time, MMC1_CMD valid after MMC1_CLK rising edge 1.67 ns SDR123 tsu(dV-clkH) Setup time, MMC1_DAT[3:0] valid before MMC1_CLK rising edge 2.35 ns SDR124 th(clkH-dV) Hold time, MMC1_DAT[3:0] valid after MMC1_CLK rising edge 1.67 ns MMC[ ]_CMDx MMC DA T[ ]_ [3:0]x SDR121 SDR122 SDR123 SDR124 MMC[ ]_CLKx Figure 6-70. MMC1 – UHS-I SDR12 – Receive Mode Table 6-89. Switching Characteristics for MMC1 – UHS-I SDR12 Mode see Figure 6-71 NO. PARAMETER MIN MAX UNIT fop(clk) Operating frequency, MMC1_CLK 25 MHz SDR125 tc(clk) Cycle time, MMC1_CLK 40 ns SDR126 tw(clkH) Pulse duration, MMC1_CLK high 18.7 ns SDR127 tw(clkL) Pulse duration, MMC1_CLK low 18.7 ns SDR128 td(clkL-cmdV) Delay time, MMC1_CLK rising edge to MMC1_CMD transition 1.2 8 ns SDR129 td(clkL-dV) Delay time, MMC1_CLK rising edge to MMC1_DAT[3:0] transition 1.2 8 ns MMC[ ]_CLKx MMC CMD[ ]_ x MMC DA T[ ]_ [3:0]x SDR125 SDR127SDR126 SDR128 SDR129 SDR128 SDR129 Figure 6-71. MMC1 – UHS-I SDR12 – Transmit Mode www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 199 Product Folder Links: AM2434 AM2432 AM2431

Table 6-90, Figure 6-72, Table 6-91, and Figure 6-73 present timing requirements and switching characteristics for MMC1 – UHS-I SDR25 Mode. Table 6-90. Timing Requirements for MMC1 – UHS-I SDR25 Mode see Figure 6-72 NO. MIN MAX UNIT SDR251 tsu(cmdV-clkH) Setup time, MMC1_CMD valid before MMC1_CLK rising edge 1.95 ns SDR252 th(clkH-cmdV) Hold time, MMC1_CMD valid after MMC1_CLK rising edge 1.67 ns SDR253 tsu(dV-clkH) Setup time, MMC1_DAT[3:0] valid before MMC1_CLK rising edge 1.95 ns SDR254 th(clkH-dV) Hold time, MMC1_DAT[3:0] valid after MMC1_CLK rising edge 1.67 ns MMC[ ]_CLKx MMC[ ]_CMDx MMC DA T[ ]_ [3:0]x SDR251 SDR252 SDR253 SDR254 Figure 6-72. MMC1 – UHS-I SDR25 – Receive Mode Table 6-91. Switching Characteristics for MMC1 – UHS-I SDR25 Mode see Figure 6-73 NO. PARAMETER MIN MAX UNIT fop(clk) Operating frequency, MMC1_CLK 50 MHz SDR255 tc(clk) Cycle time, MMC1_CLK 20 ns SDR256 tw(clkH) Pulse duration, MMC1_CLK high 9.2 ns SDR257 tw(clkL) Pulse duration, MMC1_CLK low 9.2 ns SDR258 td(clkL-cmdV) Delay time, MMC1_CLK rising edge to MMC1_CMD transition 2.4 8 ns SDR259 td(clkL-dV) Delay time, MMC1_CLK rising edge to MMC1_DAT[3:0] transition 2.4 8 ns MMC[ ]_CLKx MMC CMD[ ]_ x MMC DA T[ _ [3:0]x] SDR255 SDR257SDR256 SDR258 SDR259 SDR258 SDR259 Figure 6-73. MMC1 – UHS-I SDR25 – Transmit Mode AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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Table 6-92, and Figure 6-74 presents switching characteristics for MMC1 – UHS-I SDR50 Mode. Table 6-92. Switching Characteristics for MMC1 – UHS-I SDR50 Mode see Figure 6-74 NO. PARAMETER MIN MAX UNIT fop(clk) Operating frequency, MMC1_CLK 100 MHz SDR505 tc(clk) Cycle time, MMC1_CLK 10 ns SDR506 tw(clkH) Pulse duration, MMC1_CLK high 4.45 ns SDR507 tw(clkL) Pulse duration, MMC1_CLK low 4.45 ns SDR508 td(clkL-cmdV) Delay time, MMC1_CLK rising edge to MMC1_CMD transition 1.2 6.35 ns SDR509 td(clkL-dV) Delay time, MMC1_CLK rising edge to MMC1_DAT[3:0] transition 1.2 6.35 ns MMC[ ]_CLKx MMC CMD[ ]_ x MMC DA T[x]_ [3:0] SDR505 SDR507SDR506 SDR508 SDR509 SDR508 SDR509 Figure 6-74. MMC1 – UHS-I SDR50 – Transmit Mode www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 201 Product Folder Links: AM2434 AM2432 AM2431

Table 6-93, and Figure 6-75 present switching characteristics for MMC1 – UHS-I DDR50 Mode. Table 6-93. Switching Characteristics for MMC1 – UHS-I DDR50 Mode see Figure 6-75 NO. PARAMETER MIN MAX UNIT fop(clk) Operating frequency, MMC1_CLK 50 MHz DDR505 tc(clk) Cycle time, MMC1_CLK 20 ns DDR506 tw(clkH) Pulse duration, MMC1_CLK high 9.2 ns DDR507 tw(clkL) Pulse duration, MMC1_CLK low 9.2 ns DDR508 td(clk-cmdV) Delay time, MMC1_CLK rising edge to MMC1_CMD transition 1.2 6.35 ns DDR509 td(clk-dV) Delay time, MMC1_CLK transition to MMC1_DAT[3:0] transition 1.2 6.35 ns MMC[x] CLK_ MMC[x] CMD_ MMC[x] DAT□3_ [ :0] DDR508 DDR509 DDR509 DDR505 DDR506 DDR507 Figure 6-75. MMC1 – UHS-I DDR50 – Transmit Mode AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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Table 6-94, and Figure 6-76 present switching characteristics for MMC1 – UHS-I SDR104 Mode. Table 6-94. Switching Characteristics for MMC1 – UHS-I SDR104 Mode see Figure 6-76 NO. PARAMETER MIN MAX UNIT fop(clk) Operating frequency, MMC1_CLK 200 MHz SDR1045 tc(clk) Cycle time, MMC1_CLK 5 ns SDR1046 tw(clkH) Pulse duration, MMC1_CLK high 2.12 ns SDR1047 tw(clkL) Pulse duration, MMC1_CLK low 2.12 ns SDR1048 td(clkL-cmdV) Delay time, MMC1_CLK rising edge to MMC1_CMD transition 1.08 3.2 ns SDR1049 td(clkL-dV) Delay time, MMC1_CLK rising edge to MMC1_DAT[3:0] transition 1.08 3.2 ns MMC[ ]_CLKx MMC CMD[ ]_ x MMC DA T[ ]_ [3:0]x SDR1045 SDR1047SDR1046 SDR1048 SDR1049 SDR1048 SDR1049 Figure 6-76. MMC1 – UHS-I SDR104 – Transmit Mode www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 203 Product Folder Links: AM2434 AM2432 AM2431

6.11.5.13 CPTS

Table 6-95, Table 6-96, Figure 6-77, Table 6-97, and Figure 6-78 present timing conditions, timing requirements, and switching characteristics for CPTS. Table 6-95. CPTS Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate 0.5 5 V/ns OUTPUT CONDITIONS CL Output load capacitance 2 10 pF Table 6-96. CPTS Timing Requirements see Figure 6-77 NO. PARAMETER DESCRIPTION MIN MAX UNIT T1 tw(HWTSPUSHH) Pulse duration, HWnTSPUSH high 12P(1) + 2 ns T2 tw(HWTSPUSHL) Pulse duration, HWnTSPUSH low 12P(1) + 2 ns T3 tc(RFT_CLK) Cycle time, RFT_CLK 5 8 ns T4 tw(RFT_CLKH) Pulse duration, RFT_CLK high 0.45T(2) ns T5 tw(RFT_CLKL) Pulse duration, RFT_CLK low 0.45T(2) ns (1) P = functional clock period in ns. (2) T = RFT_CLK period in ns. RFT_CLK T3 T4 T5 HWn_TSPUSH T1 T2 Figure 6-77. CPTS Timing Requirements AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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Table 6-97. CPTS Switching Characteristics see Figure 6-78 NO. PARAMETER DESCRIPTION SOURCE MIN MAX UNIT T6 tw(TS_COMPH) Pulse duration, TS_COMP high 36P(1) - 2 ns T7 tw(TS_COMPL) Pulse duration, TS_COMP low 36P(1) - 2 ns T8 tw(TS_SYNCH) Pulse duration, TS_SYNC high 36P(1) - 2 ns T9 tw(TS_SYNCL) Pulse duration, TS_SYNC low 36P(1) - 2 ns T10 tw(SYNC_OUTH) Pulse duration, SYNCn_OUT high TS_SYNC 36P(1) - 2 ns GENF 5P(1) - 2 ns T11 tw(SYNC_OUTL) Pulse duration, SYNCn_OUT low TS_SYNC 36P(1) - 2 ns GENF 5P(1) - 2 ns (1) P = functional clock period in ns. TS_COMP T6 T7 TS_SYNC T8 T9 SYNCn_OUT T10 T1 1 Figure 6-78. CPTS Switching Characteristics For more information, see Data Movement Architecture (DMA) chapter in the device TRM. www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 205 Product Folder Links: AM2434 AM2432 AM2431

6.11.5.14 OSPI

OSPI0 offers two data capture modes, PHY mode and Tap mode. PHY mode uses an internal reference clock to transmit and receive data via a DLL based PHY, where each reference clock cycle produces a single cycle of OSPI0_CLK for Single Data Rate (SDR) transfers or a half cycle of OSPI0_CLK for Double Data Rate (DDR) transfers. PHY mode supports four clocking topologies for the receive data capture clock. Internal PHY Loopback - uses the internal reference clock as the PHY receive data capture clock. Internal Pad Loopback - uses OSPI0_LBCLKO looped back into the PHY from the OSPI0_LBCLKO pin as the PHY receive data capture clock. External Board Loopback - uses OSPI0_LBCLKO looped back into the PHY from the OSPI0_DQS pin as the PHY receive data capture clock. DQS - uses the DQS output from the attached device as the PHY receive data capture clock. SDR transfers are not supported when using the Internal Pad Loopback and DQS clocking topologies. DDR transfers are not supported when using the Internal PHY Loopback or Internal Pad Loopback clocking topologies. Tap mode uses an internal reference clock with selectable taps to adjusted data transmit and receive capture delays relative to OSPI0_CLK, which is a divide by 4 of the internal reference clock for SDR transfers or a divide by 8 of the internal reference clock for DDR transfers. Tap mode only supports one clocking topology for the receive data capture clock. No Loopback - uses the internal reference clock as the Tap receive data capture clock. This clocking topology supports a maximum internal reference clock rate of 200MHz, which produces an OSPI0_CLK rate up to 50MHz for SDR mode or 25MHz for DDR mode. For more details about features and additional description information on the device Octal Serial Peripheral Interface, see the corresponding subsections within Signal Descriptions and Detailed Description sections. Section 6.11.5.14.1 defines timing requirements and switching characteristics associated with PHY mode and Table 6-98 presents timing conditions for OSPI0. Table 6-98. OSPI0 Timing Conditions PARAMETER MODE MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate 1 6 V/ns OUTPUT CONDITIONS CL Output load capacitance 3 10 pF PCB CONNECTIVITY REQUIREMENTS td(Trace Delay) Propagation delay of OSPI0_CLK trace No Loopback Internal PHY Loopback Internal Pad Loopback 450 ps Propagation delay of OSPI0_LBCLKO trace External Board Loopback 2L(1) - 30 2L(1) + 30 ps Propagation delay of OSPI0_DQS trace DQS L(1) - 30 L(1) + 30 ps td(Trace Mismatch Delay) Propagation delay mismatch of OSPI0_D[7:0] and OSPI0_CSn[3:0] relative to OSPI0_CLK All modes 60 ps (1) L = Propagation delay of OSPI0_CLK trace For more information, see Octal Serial Peripheral Interface (OSPI) section in Peripherals chapter in the device TRM. AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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6.11.5.14.1 OSPI0 PHY Mode

Read and write data valid windows will shift due to variation in process, voltage, temperature, and operating frequency. A data training method may be implemented to dynamically configure optimal read and write timing. Implementing data training enables proper operation across temperature with a specific process, voltage, and frequency operating condition, while achieving a higher operating frequency. Data transmit and receive timing parameters are not defined for the data training use case since they are dynamically adjusted based on the operating condition. Table 6-99 defines DLL delays required for OSPI0 with Data Training. Table 6-100, Figure 6-79, Table 6-101, and Figure 6-80 present timing requirements and switching characteristics for OSPI0 with Data Training. Table 6-99. OSPI0 DLL Delay Mapping for PHY Data Training MODE REGISTER BIT FIELD DELAY VALUE OSPI_PHY_CONFIGURATION_REG Transmit All modes PHY_CONFIG_TX_DLL_DELAY_FLD (1) Receive All modes PHY_CONFIG_RX_DLL_DELAY_FLD (2) PHY_MASTER_CONTROL_REG All modes PHY_MASTER_PHASE_DETECT_SELECTOR_FLD 0x3 (1) Transmit DLL delay value determined by training software (2) Receive DLL delay value determined by training software Table 6-100. OSPI0 Timing Requirements – PHY Data Training see Figure 6-79 NO. MODE MIN MAX UNIT O15 tsu(D-LBCLK) Setup time, OSPI0_D[7:0] valid before active OSPI0_DQS edge DDR with DQS (1) ns O16 th(LBCLK-D) Hold time, OSPI0_D[7:0] valid after active OSPI0_DQS edge DDR with DQS (1) ns (1) Minimum setup and hold time requirements for OSPI0_D[7:0] inputs are not defined when Data Training is used to find the optimum data valid window. OSPI_DQS O16O15 OSPI_TIMING_04 OSPI_D[i:0] O16O15 Figure 6-79. OSPI0 Timing Requirements – PHY Data Training, DDR with DQS www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 207 Product Folder Links: AM2434 AM2432 AM2431

Table 6-101. OSPI Switching Characteristics – PHY Data Training See Figure 6-80 NO. PARAMETER MODE MIN MAX UNIT O1 tc(CLK) Cycle time, OSPI0_CLK 1.8V, DDR 6.02 7.52 ns 3.3V, DDR 7.52 7.52 ns O2 tw(CLKL) Pulse duration, OSPI0_CLK low DDR ((0.475P(1)) - 0.3) ns O3 tw(CLKH) Pulse duration, OSPI0_CLK high DDR ((0.475P(1)) - 0.3) ns O4 td(CSn-CLK) Delay time, OSPI0_CSn[3:0] active edge to OSPI0_CLK rising edge DDR ((0.475P(1)) + (0.975M(2)R(4)) + (0.04TD(5)) - 1) ((0.525P(1)) + (1.025M(2)R(4)) + (0.11TD(5)) + 1) ns O5 td(CLK-CSn) Delay time, OSPI0_CLK rising edge to OSPI0_CSn[3:0] inactive edge DDR ((0.475P(1)) + (0.975N(3)R(4)) - (0.11TD(5)) - 1) ((0.525P(1)) + (1.025N(3)R(4)) - (0.04TD(5)) + 1) ns O6 td(CLK-D) Delay time, OSPI0_CLK active edge to OSPI0_D[7:0] transition DDR (6) (6) ns (1) P = SCLK cycle time in ns = OSPI0_CLK cycle time in ns (2) M = OSPI_DEV_DELAY_REG[D_INIT_FLD] (3) N = OSPI_DEV_DELAY_REG[D_AFTER_FLD] (4) R = reference clock cycle time in ns (5) TD = PHY_CONFIG_TX_DLL_DELAY_FLD (6) Minimum and maximum delay times for OSPI0_D[7:0] outputs are not defined when Data Training is used to find the optimum data valid window. OSPI_CLK OSPI_TIMING_01 OSPI_CSn OSPI_D[i:0] Figure 6-80. OSPI0 Switching Characteristics – PHY DDR Data Training AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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Timing parameters defined in this section are only applicable when data training is not implemented and DLL delays are configured as described in Table 6-102 and Table 6-105. Table 6-102 defines DLL delays required for OSPI0 PHY SDR Mode. Table 6-103, Figure 6-81 , Figure 6-82 , Table 6-104, and Figure 6-83 present timing requirements and switching characteristics for OSPI0 PHY SDR Mode. Table 6-102. OSPI0 DLL Delay Mapping for PHY SDR Timing Modes MODE REGISTER BIT FIELD DELAY VALUE OSPI_PHY_CONFIGURATION_REG Transmit All modes PHY_CONFIG_TX_DLL_DELAY_FLD 0x0 Receive All modes PHY_CONFIG_RX_DLL_DELAY_FLD 0x0 PHY_MASTER_CONTROL_REG All modes PHY_MASTER_PHASE_DETECT_SELECTOR_FLD 0x3 Table 6-103. OSPI0 Timing Requirements – PHY SDR Mode see Figure 6-81 and Figure 6-82 NO. MODE MIN MAX UNIT O19 tsu(D-CLK) Setup time, OSPI0_D[7:0] valid before active OSPI0_CLK edge 1.8V, SDR with Internal PHY Loopback 4.8 ns 3.3V, SDR with Internal PHY Loopback 5.19 ns O20 th(CLK-D) Hold time, OSPI0_D[7:0] valid after active OSPI0_CLK edge 1.8V, SDR with Internal PHY Loopback -0.5 ns 3.3V, SDR with Internal PHY Loopback -0.5 ns O21 tsu(D-LBCLK) Setup time, OSPI0_D[7:0] valid before active OSPI0_DQS edge 1.8V, SDR with External Board Loopback 0.6 ns 3.3V, SDR with External Board Loopback 0.9 ns O22 th(LBCLK-D) Hold time, OSPI0_D[7:0] valid after active OSPI0_DQS edge 1.8V, SDR with External Board Loopback 1.7 ns 3.3V, SDR with External Board Loopback 2.0 ns OSPI_CLK OSPI_D[i:0] OSPI_TIMING_05 O 9 1 O20 Figure 6-81. OSPI0 Timing Requirements – PHY SDR with Internal PHY Loopback OSPI_DQS OSPI_TIMING_06 O21 O 2 2 OSPI_D[i:0] Figure 6-82. OSPI0 Timing Requirements – PHY SDR with External Board Loopback www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 209 Product Folder Links: AM2434 AM2432 AM2431

Table 6-104. OSPI0 Switching Characteristics – PHY SDR Mode see Figure 6-83 NO. PARAMETER MODE MIN MAX UNIT O7 tc(CLK) Cycle time, OSPI0_CLK 1.8V 7 ns 3.3V 6.03 ns O8 tw(CLKL) Pulse duration, OSPI0_CLK low ((0.475P(1)) - 0.3) ns O9 tw(CLKH) Pulse duration, OSPI0_CLK high ((0.475P(1)) - 0.3) ns O10 td(CSn-CLK) Delay time, OSPI0_CSn[3:0] active edge to OSPI0_CLK rising edge ((0.475P(1)) + (0.975M(2)R(4)) + (0.04TD(5)) - 1) ((0.525P(1)) + (1.025M(2)R(4)) + (0.11TD(5)) + 1) ns O11 td(CLK-CSn) Delay time, OSPI0_CLK rising edge to OSPI0_CSn[3:0] inactive edge ((0.475P(1)) + (0.975N(3)R(4)) - (0.11TD(5)) - 1) ((0.525P(1)) + (1.025N(3)R(4)) - (0.04TD(5)) + 1) ns O12 td(CLK-D) Delay time, OSPI0_CLK active edge to OSPI0_D[7:0] transition 1.8V -1.16 1.25 ns 3.3V -1.33 1.51 ns (1) P = SCLK cycle time in ns = OSPI0_CLK cycle time in ns (2) M = OSPI_DEV_DELAY_REG[D_INIT_FLD] (3) N = OSPI_DEV_DELAY_REG[D_AFTER_FLD] (4) R = reference clock cycle time in ns (5) TD = PHY_CONFIG_TX_DLL_DELAY_FLD OSPI_CLK OSPI_TIMING_02 OSPI_CSn O10 O1 1 O9 O8 O12 OSPI_D[i:0] Figure 6-83. OSPI0 Switching Characteristics – PHY SDR AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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Table 6-105 defines DLL delays required for OSPI0 PHY DDR Mode. Table 6-106, Figure 6-84, Table 6-107, and Figure 6-85 present timing requirements and switching characteristics for OSPI0 PHY DDR Mode. Table 6-105. OSPI0 DLL Delay Mapping for PHY DDR Timing Modes MODE REGISTER BIT FIELD DELAY VALUE OSPI_PHY_CONFIGURATION_REG Transmit 1.8V PHY_CONFIG_TX_DLL_DELAY_FLD 0x3E 3.3V PHY_CONFIG_TX_DLL_DELAY_FLD 0x3B Receive 1.8V, DQS PHY_CONFIG_RX_DLL_DELAY_FLD 0x15 3.3V, DQS PHY_CONFIG_RX_DLL_DELAY_FLD 0x3A All other modes PHY_CONFIG_RX_DLL_DELAY_FLD 0x0 PHY_MASTER_CONTROL_REG All modes PHY_MASTER_PHASE_DETECT_SELECTOR_FLD 0x3 Table 6-106. OSPI0 Timing Requirements – PHY DDR Mode see Figure 6-84 NO. MODE MIN MAX UNIT O15 tsu(D-LBCLK) Setup time, OSPI0_D[7:0] valid before active OSPI0_DQS edge 1.8V, DDR with External Board Loopback 0.53 ns 1.8V, DDR with DQS -0.46 ns 3.3V, DDR with External Board Loopback 1.23 ns 3.3V, DDR with DQS -0.66 ns O16 th(LBCLK-D) Hold time, OSPI0_D[7:0] valid after active OSPI0_DQS edge 1.8V, DDR with External Board Loopback 1.24(1) ns 1.8V, DDR with DQS 3.59 ns 3.3V, DDR with External Board Loopback 1.44(1) ns 3.3V, DDR with DQS 7.92 ns (1) This Hold time requirement is larger than the Hold time provided by a typical OSPI/QSPI/SPI device. Therefore, the trace length between the SoC and attached OSPI/QSPI/SPI device must be sufficiently long enough to ensure that the Hold time is met at the SoC. The length of the SoC's external loopback clock (OSPI0_LBCLKO to OSPI0_DQS) may need to be shortened to compensate. OSPI_DQS O16O15 OSPI_TIMING_04 OSPI_D[i:0] O16O15 Figure 6-84. OSPI0 Timing Requirements – PHY DDR with External Board Loopback or DQS www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 211 Product Folder Links: AM2434 AM2432 AM2431

Table 6-107. OSPI0 Switching Characteristics – PHY DDR Mode see Figure 6-85 NO. PARAMETER MODE MIN MAX UNIT O1 tc(CLK) Cycle time, OSPI0_CLK 19 ns O2 tw(CLKL) Pulse duration, OSPI0_CLK low ((0.475P(1)) - 0.3) ns O3 tw(CLKH) Pulse duration, OSPI0_CLK high ((0.475P(1)) - 0.3) ns O4 td(CSn-CLK) Delay time, OSPI0_CSn[3:0] active edge to OSPI0_CLK rising edge ((0.475P(1)) + (0.975M(2)R(4)) + (0.04TD(5)) - 1) ((0.525P(1)) + (1.025M(2)R(4)) + (0.11TD(5)) + 1) ns O5 td(CLK-CSn) Delay time, OSPI0_CLK rising edge to OSPI0_CSn[3:0] inactive edge ((0.475P(1)) + (0.975N(3)R(4)) - (0.11TD(5)) - 1) ((0.525P(1)) + (1.025N(3)R(4)) - (0.04TD(5)) + 1) ns O6 td(CLK-D) Delay time, OSPI0_CLK active edge to OSPI0_D[7:0] transition (1) P = SCLK cycle time in ns = OSPI0_CLK cycle time in ns (2) M = OSPI_DEV_DELAY_REG[D_INIT_FLD] (3) N = OSPI_DEV_DELAY_REG[D_AFTER_FLD] (4) R = reference clock cycle time in ns (5) TD = PHY_CONFIG_TX_DLL_DELAY_FLD OSPI_CLK OSPI_TIMING_01 OSPI_CSn OSPI_D[i:0] Figure 6-85. OSPI0 Switching Characteristics – PHY DDR AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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6.11.5.14.2 OSPI0 Tap Mode

Table 6-108 , Figure 6-86 , Table 6-109 , and Figure 6-87 present timing requirements and switching characteristics for OSPI0 Tap SDR Mode. Table 6-108. OSPI0 Timing Requirements – Tap SDR Mode see Figure 6-86 NO. MODE MIN MAX UNIT O19 tsu(D-CLK) Setup time, OSPI0_D[7:0] valid before active OSPI0_CLK edge No Loopback (15.4 - O20 th(CLK-D) Hold time, OSPI0_D[7:0] valid after active OSPI0_CLK edge No Loopback (- 4.3 + (1) T = OSPI_RD_DATA_CAPTURE_REG[DELAY_FLD] (2) R = reference clock cycle time in ns OSPI_CLK OSPI_D[i:0] OSPI_TIMING_05 O 9 1 O20 Figure 6-86. OSPI0 Timing Requirements – Tap SDR, No Loopback www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 213 Product Folder Links: AM2434 AM2432 AM2431

Table 6-109. OSPI0 Switching Characteristics – Tap SDR Mode see Figure 6-87 NO. PARAMETER MODE MIN MAX UNIT O7 tc(CLK) Cycle time, OSPI0_CLK 20 ns O8 tw(CLKL) Pulse duration, OSPI0_CLK low ((0.475P(1)) - 0.3) ns O9 tw(CLKH) Pulse duration, OSPI0_CLK high ((0.475P(1)) - 0.3) ns O10 td(CSn-CLK) Delay time, OSPI0_CSn[3:0] active edge to OSPI0_CLK rising edge ((0.475P(1)) + ((0.525P(1)) + O11 td(CLK-CSn) Delay time, OSPI0_CLK rising edge to OSPI0_CSn[3:0] inactive edge ((0.475P(1)) + ((0.525P(1)) + O12 td(CLK-D) Delay time, OSPI0_CLK active edge to OSPI0_D[7:0] transition - 4.25 7.25 ns (1) P = SCLK cycle time in ns = OSPI0_CLK cycle time in ns (2) M = OSPI_DEV_DELAY_REG[D_INIT_FLD] (3) N = OSPI_DEV_DELAY_REG[D_AFTER_FLD] (4) R = reference clock cycle time in ns OSPI_CLK OSPI_TIMING_02 OSPI_CSn O10 O1 1 O9 O8 O12 OSPI_D[i:0] Figure 6-87. OSPI0 Switching Characteristics – Tap SDR, No Loopback AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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Table 6-110, Figure 6-88, Table 6-111, and Figure 6-89 present timing requirements and switching characteristics for OSPI0 Tap DDR Mode. Table 6-110. OSPI0 Timing Requirements – Tap DDR Mode see Figure 6-88 NO. MODE MIN MAX UNIT O13 tsu(D-CLK) Setup time, OSPI0_D[7:0] valid before active OSPI0_CLK edge No Loopback (17.04 - O14 th(CLK-D) Hold time, OSPI0_D[7:0] valid after active OSPI0_CLK edge No Loopback (- 3.16 + (1) T = OSPI_RD_DATA_CAPTURE_REG[DELAY_FLD] (2) R = reference clock cycle time in ns OSPI_CLK O14O13 OSPI_TIMING_03 OSPI_D[i:0] O14O13 Figure 6-88. OSPI0 Timing Requirements – Tap DDR, No Loopback www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 215 Product Folder Links: AM2434 AM2432 AM2431

Table 6-111. OSPI0 Switching Characteristics – Tap DDR Mode see Figure 6-89 NO. PARAMETER MODE MIN MAX UNIT O1 tc(CLK) Cycle time, OSPI0_CLK 40 ns O2 tw(CLKL) Pulse duration, OSPI0_CLK low ((0.475P(1)) - 0.3) ns O3 tw(CLKH) Pulse duration, OSPI0_CLK high ((0.475P(1)) - 0.3) ns O4 td(CSn-CLK) Delay time, OSPI0_CSn[3:0] active edge to OSPI0_CLK rising edge ((0.475P(1)) + ((0.525P(1)) + O5 td(CLK-CSn) Delay time, OSPI0_CLK rising edge to OSPI0_CSn[3:0] inactive edge ((0.475P(1)) + ((0.525P(1)) + O6 td(CLK-D) Delay time, OSPI0_CLK active edge to OSPI0_D[7:0] transition (- 5.04 + - (0.525P(1))) (3.64 + - (0.475P(1))) ns (1) P = SCLK cycle time in ns = OSPI0_CLK cycle time in ns (2) M = OSPI_DEV_DELAY_REG[D_INIT_FLD] (3) N = OSPI_DEV_DELAY_REG[D_AFTER_FLD] (4) T = OSPI_RD_DATA_CAPTURE_REG[DDR_READ_DELAY_FLD] (5) R = reference clock cycle time in ns OSPI_CLK OSPI_TIMING_01 OSPI_CSn OSPI_D[i:0] Figure 6-89. OSPI0 Switching Characteristics – Tap DDR, No Loopback

6.11.5.15 PCIe

The PCI-Express Subsystem is compliant with the PCIe ® Base Specification, Revision 4.0. Refer to the specification for timing details. For more details about features and additional description information on the device Peripheral Component Interconnect Express (PCIe), see the SERDES0 Signal Descriptions and the corresponding subsection within Detailed Description. For more information, see Peripheral Component Interconnect Express (PCIe) Subsystem section in Peripherals chapter of the device TRM. AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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6.11.5.16 PRU_ICSSG

The device has integrated two identical Programmable Real-Time Unit Subsystem and Industrial Communication Subsystems - Gigabit (PRU_ICSSG), PRU_ICSSG0 and PRU_ICSSG1. The programmable nature of the PRU cores, along with their access to pins, events and all device resources, provides flexibility in implementing fast real-time responses, specialized data handling operations, custom peripheral interfaces, and in offloading tasks from the other processor cores in the device. For more details about features and additional description information on the device PRU_ICSSG, see the corresponding subsections within Signal Descriptions and Detailed Description sections. Note The PRU_ICSSG contains a second layer of multiplexing to enable additional functionality on the PRU GPO and GPI signals. This internal wrapper multiplexing is described in the PRU_ICSSG chapter in the device TRM.

6.11.5.16.1 PRU_ICSSG Programmable Real-Time Unit (PRU)

The PRU_ICSSG PRU signals have different functionality depending on the mode of operation. The signal naming in this section matches the naming used in the PRU Module Interface section in the device TRM. Table 6-112. PRU_ICSSG PRU Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate 1 3 V/ns OUTPUT CONDITIONS CL Output load capacitance 2 30 pF Table 6-113. PRU_ICSSG PRU Switching Characteristics – Direct Output Mode see Figure 6-90 NO. PARAMETER DESCRIPTION MIN MAX UNIT PRDO1 tsk(GPO-GPO) Skew, GPO to GPO 2 ns GPO[n:0] PRDO1 PRU_TIMING_02 A. n in GPO[n:0] = 19. Figure 6-90. PRU_ICSSG PRU Direct Output Timing www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 217 Product Folder Links: AM2434 AM2432 AM2431

Table 6-114. PRU_ICSSG PRU Timing Requirements – Parallel Capture Mode see Figure 6-91 and Figure 6-92 NO. PARAMETER DESCRIPTION MIN MAX UNIT PRPC1 tc(CLOCK) Cycle time, CLOCKIN 20 ns PRPC2 tw(CLOCKL) Pulse duration, CLOCKIN low 0.45P(1) ns PRPC3 tw(CLOCKH) Pulse duration, CLOCKIN high 0.45P(1) ns PRPC4 tsu(DATAIN-CLOCK) Setup time, DATAIN valid before CLOCKIN active edge 4 ns PRPC5 th(CLOCK-DATAIN) Hold time, DATAIN valid after CLOCKIN active edge 0 ns (1) P = CLOCKIN cycle time in ns CLOCKIN DA T AIN PRPC1 PRPC3 PRPC2 PRPC4 PRPC5 PRU_TIMING_03 Figure 6-91. PRU_ICSSG PRU Parallel Capture Timing Requirements – Rising Edge Mode CLOCKIN DA T AIN PRPC1 PRPC2 PRPC3 PRPC5 PRU_TIMING_04PRPC4 Figure 6-92. PRU_ICSSG PRU Parallel Capture Timing Requirements – Falling Edge Mode AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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Table 6-115. PRU_ICSSG PRU Timing Requirements – Shift In Mode see Figure 6-93 NO. PARAMETER DESCRIPTION MIN MAX UNIT PRSI1 tw(DATAINH) Pulse duration, DATAIN high 2P(1) + 2 ns PRSI2 tw(DATAINL) Pulse duration, DATAIN low 2P(1) + 2 ns (1) P = Internal shift in clock period, defined by PRUn_GPI_DIV0 and PRUn_GPI_DIV1 bit fields in the ICSSG_GPCFGn_REG register. PRUn represents the respective PRU0 or PRU1 instance. DA T AIN PRSI1 PRSI2 PRU_TIMING_05 Figure 6-93. PRU_ICSSG PRU Shift In Timing www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 219 Product Folder Links: AM2434 AM2432 AM2431

Table 6-116. PRU_ICSSG PRU Switching Characteristics – Shift Out Mode see Figure 6-94 NO. PARAMETER DESCRIPTION MIN MAX UNIT PRSO1 tc(CLOCKOUT) Cycle time, CLOCKOUT 10 ns PRSO2L tw(CLOCKOUTL) Pulse duration, CLOCKOUT low 0.475P(1)Z(2) - 0.3 ns PRSO2H tw(CLOCKOUTH) Pulse duration, CLOCKOUT high 0.475P(1)Y(3) - 0.3 ns PRSO3 td(CLOCKOUT-DATAOUT) Delay time, CLOCKOUT to DATAOUT valid -1 4 ns (1) P = Software programmable shift out clock period, defined by PRUn_GPO_DIV0 and PRUn_GPO_DIV1 bit fields in the ICSSG_GPCFGn_REG register, where PRUn represents the respective PRU0 or PRU1 instance. (2) The Z parameter is defined as follows, where PRUn represents the respective PRU0 or PRU1 instance. a. If PRUn_GPI_DIV0 and PRUn_GPI_DIV1 are INTEGERS -or- if PRUn_GPI_DIV0 is a NON-INTEGER and PRUn_GPI_DIV1 is an EVEN INTEGER then, Z equals (PRUn_GPI_DIV0 * PRUn_GPI_DIV1). b. If PRUn_GPI_DIV0 is a NON-INTEGER and PRUn_GPI_DIV1 is an ODD INTEGER then, Z equals (PRUn_GPI_DIV0 * PRUn_GPI_DIV1 + 0.5). c. If PRUn_GPI_DIV0 is an INTEGER and PRUn_GPI_DIV1 is a NON-INTEGER then, Z equals (PRUn_GPI_DIV0 * PRUn_GPI_DIV1 + 0.5 * PRUn_GPI_DIV0). d. If PRUn_GPI_DIV0 and PRUn_GPI_DIV1 are NON-INTEGERS then, Z equals (PRUn_GPI_DIV0 * PRUn_GPI_DIV1 + 0.25 * PRUn_GPI_DIV0). (3) The Y parameter is defined as follows, where PRUn represents the respective PRU0 or PRU1 instance. a. If PRUn_GPI_DIV0 and PRUn_GPI_DIV1 are INTEGERS -or- if PRUn_GPI_DIV0 is a NON-INTEGER and PRUn_GPI_DIV1 is an EVEN INTEGER then, Y equals (PRUn_GPI_DIV0 * PRUn_GPI_DIV1). b. If PRUn_GPI_DIV0 is a NON-INTEGER and PRUn_GPI_DIV1 is an ODD INTEGER then, Y equals (PRUn_GPI_DIV0 * PRUn_GPI_DIV1 - 0.5). c. If PRUn_GPI_DIV0 is an INTEGER and PRUn_GPI_DIV1 is a NON-INTEGER then, Y equals (PRUn_GPI_DIV0 * PRUn_GPI_DIV1 - 0.5 * PRUn_GPI_DIV0). d. If PRUn_GPI_DIV0 and PRUn_GPI_DIV1 are NON-INTEGERS then, Y1 equals (PRUn_GPI_DIV0 * PRUn_GPI_DIV1 - 0.25 * PRUn_GPI_DIV0) and Y2 equals (PRUn_GPI_DIV0 * PRUn_GPI_DIV1 + 0.25 * PRUn_GPI_DIV0), where Y1 is the first high pulse and Y2 is the second high pulse. CLOCKOUT DA T AO U T PRSO1 PRSO2H PRSO3 PRU_TIMING_06 PRSO2L Figure 6-94. PRU_ICSSG PRU Shift Out Timing AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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Table 6-117. PRU_ICSSG PRU Sigma Delta and Peripheral Interface Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate 1 3 V/ns OUTPUT CONDITIONS CL Output load capacitance 2 18 pF Table 6-118. PRU_ICSSG PRU Timing Requirements – Sigma Delta Mode see Figure 6-95 and Figure 6-96 NO. PARAMETER DESCRIPTION MIN MAX UNIT PRSD1 tc(SD_CLK) Cycle time, SDx_CLK 40 ns PRSD2L tw(SD_CLKL) Pulse duration, SDx_CLK low 20 ns PRSD2H tw(SD_CLKH) Pulse duration, SDx_CLK high 20 ns PRSD3 tsu(SD_D-SD_CLK) Setup time, SDx_D valid before SDx_CLK active edge 10 ns PRSD4 th(SD_CLK-SD_D) Hold time, SDx_D valid after SDx_CLK active edge 5 ns SDx_CLK PRU_TIMING_07 PRSD2H PRSD2L PRSD4 PRSD3 SDx_D PRSD1 Figure 6-95. PRU_ICSSG PRU SD_CLK Falling Active Edge SDx_CLK PRSD2L PRSD3 PRSD4 PRU_TIMING_08 SDx_D Figure 6-96. PRU_ICSSG PRU SD_CLK Rising Active Edge www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 221 Product Folder Links: AM2434 AM2432 AM2431

Table 6-119. PRU_ICSSG PRU Timing Requirements – Peripheral Interface Mode see Figure 6-97 NO. PARAMETER DESCRIPTION MIN MAX UNIT PRPIF1 tw(PIF_DATA_INH) Pulse duration, PIF_DATA_IN high 2 + 0.475*(4*P) (1) ns PRPIF2 tw(PIF_DATA_INL) Pulse duration, PIF_DATA_IN low 2 + 0.475*(4*P) (1) ns (1) P = 1x (or TX) clock period in ns, defined by PRUn_ED_TX_DIV_FACTOR and PRUn_ED_TX_DIV_FACTOR_FRAC in the ICSSG_PRUn_ED_TX_CFG_REG register. PRUn represents the respective PRU0 or PRU1 instance. P I F _ DA T A _ I N PRPIF1 PRUPIF_TIMING_01 PRPIF2 Figure 6-97. PRU_ICSSG PRU Peripheral Interface Timing Requirements Table 6-120. PRU_ICSSG PRU Switching Characteristics – Peripheral Interface Mode see Figure 6-98 NO. PARAMETER DESCRIPTION MIN MAX UNIT PRPIF3 tc(PIF_CLK) Cycle time, PIF_CLK 30 ns PRPIF4 tw(PIF_CLKH) Pulse duration, PIF_CLK high 0.475*P (1) ns PRPIF5 tw(PIF_CLKL) Pulse duration, PIF_CLK low 0.475*P (1) ns PRPIF6 td(PIF_CLK- PIF_DATA_OUT) Delay time, PIF_CLK fall to PIF_DATA_OUT -5 5 ns PRPIF7 td(PIF_CLK-PIF_DATA_EN) Delay time, PIF_CLK fall to PIF_DATA_EN -5 5 ns (1) P = 1x (or TX) clock period in ns, defined by PRUn_ED_TX_DIV_FACTOR and PRUn_ED_TX_DIV_FACTOR_FRAC in the ICSSG_PRUn_ED_TX_CFG_REG register. PRUn represents the respective PRU0 or PRU1 instance. PIF_CLK P I F _ DA T A _O U T PRPIF3 PRPIF4 PRPIF6 PRPIF5 PIF_DA T A_EN PRPIF7 Figure 6-98. PRU_ICSSG PRU Peripheral Interface Switching Characteristics AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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6.11.5.16.2 PRU_ICSSG Pulse Width Modulation (PWM)

Table 6-121. PRU_ICSSG PWM Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate 1 4 V/ns OUTPUT CONDITIONS CL Output load capacitance 2 7 pF Table 6-122. PRU_ICSSG PWM Switching Characteristics see Figure 6-99 NO. PARAMETER DESCRIPTION MIN MAX UNIT PRPWM1 tsk(PWM_A-PWM_B) Skew, PWM_A to PWM_B 5 ns PWM_A/B PRU_PWM_TIMING_01 PRPWM1 Figure 6-99. PRU_ICSSG PWM Timing www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 223 Product Folder Links: AM2434 AM2432 AM2431

6.11.5.16.3 PRU_ICSSG Industrial Ethernet Peripheral (IEP)

Table 6-123. PRU_ICSSG IEP Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate 1 3 V/ns OUTPUT CONDITIONS CL Output load capacitance EDC_SYNC_OUTx EDIO_OUTVALID 2 7 pF EDIO_DATA_OUT 3 10 pF Table 6-124. PRU_ICSSG IEP Timing Requirements – Input Validated with SYNC see Figure 6-100 NO. PARAMETER DESCRIPTION MIN MAX UNIT PRIEP1 tw(EDC_SYNC_OUTxL) Pulse duration, EDC_SYNC_OUTx low 20P(1) - 2 ns PRIEP2 tw(EDC_SYNC_OUTxH) Pulse duration, EDC_SYNC_OUTx high 20P(1) - 2 ns PRIEP3 tsu(EDIO_DATA_IN- EDC_SYNC_OUTx) Setup time, EDIO_DATA_IN valid before EDC_SYNC_OUTx active edge 20 ns PRIEP4 th(EDC_SYNC_OUTx- EDIO_DATA_IN) Hold time, EDIO_DATA_IN valid after EDC_SYNC_OUTx active edge 20 ns (1) P = PRU_ICSSG IEP clock source period in ns. EDC_SYNC_OUTx PRIEP4 PRIEP2 PRIEP3 EDIO_DA T A_IN[7:0] PRU_IEP_TIMING_01 PRIEP1 Figure 6-100. PRU_ICSSG IEP SYNC Timing Requirements AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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6.11.5.16.4 PRU_ICSSG Universal Asynchronous Receiver Transmitter (UART)

Table 6-127. PRU_ICSSG UART Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate 0.5 5 V/ns OUTPUT CONDITIONS CL Output load capacitance 1 30(1) pF (1) This value represents an absolute maximum load capacitance. As the UART baud rate increases, it may be necessary to reduce the load capacitance to a value less than this maximum limit to provide enough timing margin for the attached device. The output rise/fall times increase as capacitive load increases, which decreases the time data is valid for the receiver of the attached devices. Therefore, it is important to understand the minimum data valid time required by the attached device at the operating baud rate. Then use the device IBIS models to verify the actual load capacitance on the UART signals does not increase the rise/fall times beyond the point where the minimum data valid time of the attached device is violated. Table 6-128. PRU_ICSSG UART Timing Requirements see Figure 6-103 NO. PARAMETER DESCRIPTION MIN MAX UNIT 1 tw(RXD) Pulse width, receive data bit high or low 0.95U(1) (2) 1.05U(1) (2) ns 2 tw(RXDS) Pulse width, receive start bit low 0.95U(1) (2) ns (1) U = UART baud time in ns = 1/programmed baud rate. (2) This value defines the data valid time, where the input voltage is required to be above VIH or below VIL. Table 6-129. PRU_ICSSG UART Switching Characteristics see Figure 6-103 NO. PARAMETER DESCRIPTION MIN MAX UNIT f(baud) Programmed baud rate 12 Mbps 3 tw(TXD) Pulse width, transmit data bit high or low U(1) - 2 U(1) + 2 ns 4 tw(TXDS) Pulse width, transmit start bit low U(1) - 2 U(1) + 2 ns (1) U = UART baud time in ns = 1/actual baud rate, where the actual baud rate is defined in the UART Baud Rate Settings table of the device TRM. Start Bit Data Bits PRG _UART0_TXDi PRU_UART_TIMING_01_RCVRVIHVIL Data Bits Bit Start PRG _UART0_RXDi VIH VIL Figure 6-103. PRU_ICSSG UART Timing Requirements and Switching Characteristics AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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6.11.5.16.5 PRU_ICSSG Enhanced Capture Peripheral (ECAP)

Table 6-130. PRU_ICSSG ECAP Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate 1 3 V/ns OUTPUT CONDITIONS CL Output load capacitance 2 7 pF Table 6-131. PRU_ICSSG ECAP Timing Requirements see Figure 6-104 NO. PARAMETER DESCRIPTION MIN MAX UNIT PREP1 tw(CAP) Pulse Duration, CAP (asynchronous) 2P(1) + 2 ns PREP2 tw(SYNCI) Pulse Duration, SYNCI (asynchronous) 2P(1) + 2 ns (1) P = CORE_CLK period in ns. CAP PREP1 SYNCI PREP2 Figure 6-104. PRU_ICSSG ECAP Timing Table 6-132. PRU_ICSSG ECAP Switching Characteristics see Figure 6-105 NO. PARAMETER DESCRIPTION MIN MAX UNIT PREP3 tw(APWM) Pulse Duration, APWM high/low 2P(1) - 2 ns PREP4 tw(SYNCO) Pulse Duration, SYNCO (asynchronous) P(1) - 2 ns (1) P = CORE_CLK period in ns. APWM PREP3 SYNCO PREP4 Figure 6-105. PRU_ICSSG ECAP Switching Characteristics www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 227 Product Folder Links: AM2434 AM2432 AM2431

6.11.5.16.6 PRU_ICSSG RGMII, MII_RT, and Switch

For more information, see Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem - Gigabit (PRU_ICSSG) section in Processors and Accelerators chapter in the device TRM. Table 6-133, Table 6-134, Table 6-135, and Figure 6-106 present timing conditions, timing requirements, and switching characteristics for PRU_ICSSG MDIO. Table 6-133. PRU_ICSSG MDIO Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate 0.9 3.6 V/ns OUTPUT CONDITIONS CL Output load capacitance 10 470 pF Table 6-134. PRU_ICSSG MDIO Timing Requirements see Figure 6-106 NO. PARAMETER MIN MAX UNIT MDIO1 tsu(MDIO_MDC) Setup time, MDIO[x]_MDIO valid before MDIO[x]_MDC high 90 ns MDIO2 th(MDC_MDIO) Hold time, MDIO[x]_MDIO valid after MDIO[x]_MDC high 0 ns Table 6-135. PRU_ICSSG MDIO Switching Characteristics see Figure 6-106 NO. PARAMETER MIN MAX UNIT MDIO3 tc(MDC) Cycle time, MDIO[x]_MDC 400 ns MDIO4 tw(MDCH) Pulse Duration, MDIO[x]_MDC high 160 ns MDIO5 tw(MDCL) Pulse Duration, MDIO[x]_MDC low 160 ns MDIO7 td(MDC_MDIO) Delay time, MDIO[x]_MDC low to MDIO[x]_MDIO valid -150 150 ns MDIO3 MDIO1 MDIO2 MDIO7 MDIO4 MDIO5 MDIO[x]_MDC MDIO[x]_MDIO (input) MDIO[x]_MDIO (output) CPSW2G_MDIO_TIMING_01 Figure 6-106. PRU_ICSSG MDIO Timing Requirements and Switching Characteristics AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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In order to ensure the MII_G_RT I/O timing values published in the device data sheet, the PRU_ICSSG ICSSGn_CORE_CLK (where n = 0 to 1) core clock must be configured for 200MHz, 225MHz, or 250MHz and the TX_CLK_DELAYn (where n = 0 or 1) bit field in the ICSSG_TXCFG0/1 register must be set to 0h (default value). Table 6-136, Table 6-137, Figure 6-107, Table 6-138, Figure 6-108, Table 6-139, Figure 6-109, Table 6-140, and Figure 6-110 present timing conditions, timing requirements, and switching characteristics for PRU_ICSSG MII. Table 6-136. PRU_ICSSG MII Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate 0.9 3.6 V/ns OUTPUT CONDITIONS CL Output load capacitance 2 20 pF Table 6-137. PRU_ICSSG MII Timing Requirements – MII[x]_RX_CLK see Figure 6-107 NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT PMIR1 tc(RX_CLK) Cycle time, MII[x]_RX_CLK 10Mbps 399.96 400.04 ns 100Mbps 39.996 40.004 ns PMIR2 tw(RX_CLKH) Pulse Duration, MII[x]_RX_CLK High 10Mbps 140 260 ns 100Mbps 14 26 ns PMIR3 tw(RX_CLKL) Pulse Duration, MII[x]_RX_CLK Low 10Mbps 140 260 ns 100Mbps 14 26 ns MII_RX_CLK PMIR2 PMIR3 PMIR1 PRU_MII_RT_TIMING_04 Figure 6-107. PRU_ICSSG MII[x]_RX_CLK Timing www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 229 Product Folder Links: AM2434 AM2432 AM2431

Table 6-138. PRU_ICSSG MII Timing Requirements – MII[x]_RXD[3:0], MII[x]_RX_DV, and MII[x]_RX_ER see Figure 6-108 NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT PMIR4 tsu(RXD-RX_CLK) Setup time, MII[x]_RXD[3:0] valid before MII[x]_RX_CLK 10Mbps 8 ns tsu(RX_DV-RX_CLK) Setup time, MII[x]_RX_DV valid before MII[x]_RX_CLK 8 ns tsu(RX_ER-RX_CLK) Setup time, MII[x]_RX_ER valid before MII[x]_RX_CLK 8 ns tsu(RXD-RX_CLK) Setup time, MII[x]_RXD[3:0] valid before MII[x]_RX_CLK 100Mbps 8 ns tsu(RX_DV-RX_CLK) Setup time, MII[x]_RX_DV valid before MII[x]_RX_CLK 8 ns tsu(RX_ER-RX_CLK) Setup time, MII[x]_RX_ER valid before MII[x]_RX_CLK 8 ns PMIR5 th(RX_CLK-RXD) Hold time, MII[x]_RXD[3:0] valid after MII[x]_ RX_CLK 10Mbps 8 ns th(RX_CLK-RX_DV) Hold time, MII[x]_RX_DV valid after MII[x]_RX_CLK 8 ns th(RX_CLK-RX_ER) Hold time, MII[x]_RX_ER valid after MII[x]_RX_CLK 8 ns th(RX_CLK-RXD) Hold time, MII[x]_RXD[3:0] valid after MII[x]_ RX_CLK 100Mbps 8 ns th(RX_CLK-RX_DV) Hold time, MII[x]_RX_DV valid after MII[x]_RX_CLK 8 ns th(RX_CLK-RX_ER) Hold time, MII[x]_RX_ER valid after MII[x]_RX_CLK 8 ns MII_RX_CLK PMIR4 PMIR5 MII_RXD[3:0], MII_RX_DV, MII_RX_ER Figure 6-108. PRU_ICSSG MII[x]_RXD[3:0], MII[x]_RX_DV, and MII[x]_RX_ER Timing Table 6-139. PRU_ICSSG MII Timing Requirements – MII[x]_TX_CLK see Figure 6-109 NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT PMIT1 tc(TX_CLK) Cycle time, MII[x]_TX_CLK 10Mbps 399.96 400.04 ns 100Mbps 39.996 40.004 ns PMIT2 tw(TX_CLKH) Pulse Duration, MII[x]_TX_CLK High 10Mbps 140 260 ns 100Mbps 14 26 ns PMIT3 tw(TX_CLKL) Pulse Duration, MII[x]_TX_CLK Low 10Mbps 140 260 ns 100Mbps 14 26 ns MII_TX_CLK PMIT2 PMIT3 PMIT1 Figure 6-109. PRU_ICSSG MII[x]_TX_CLK Timing AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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Table 6-140. PRU_ICSSG MII Switching Characteristics – MII[x]_TXD[3:0] and MII[x]_TX_EN see Figure 6-110 NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT PMIT4 td(TX_CLK-TXD) Delay time, MII[x]_TX_CLK High to MII[x]_TXD[3:0] valid 10Mbps 0 25 ns td(TX_CLK-TX_EN) Delay time, MII[x]_TX_CLK to MII[x]_TX_EN valid 0 25 ns td(TX_CLK-TXD) Delay time, MII[x]_TX_CLK High to MII[x]_TXD[3:0] valid 100Mbps 0 25 ns td(TX_CLK-TX_EN) Delay time, MII[x]_TX_CLK to MII[x]_TX_EN valid 0 25 ns PMIT4 MII_TX_CLK MII_TXD[3:0], MII_TX_EN Figure 6-110. PRU_ICSSG MII[x]_TXD[3:0], MII[x]_TX_EN Timing www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 231 Product Folder Links: AM2434 AM2432 AM2431

Table 6-141, Table 6-142, Table 6-143, Figure 6-111, Table 6-144, Table 6-145, and Figure 6-112 present timing conditions, timing requirements, and switching characteristics for PRU_ICSSG RGMII. Table 6-141. PRU_ICSSG RGMII Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate VDD(1) = 1.8V 1.44 5 V/ns VDD(1) = 3.3V 2.65 5 V/ns OUTPUT CONDITIONS CL Output load capacitance 2 20 pF PCB CONNECTIVITY REQUIREMENTS td(Trace Mismatch Delay) Propagation delay mismatch across all traces RGMII[x]_RXC, RGMII[x]_RD[3:0], RGMII[x]_RX_CTL 50 ps RGMII[x]_TXC, RGMII[x]_TD[3:0], RGMII[x]_TX_CTL 50 ps (1) VDD stands for corresponding power supply. For more information on the power supply name and the corresponding ball(s), see POWER column of the Pin Attributes table. AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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Table 6-142. PRU_ICSSG RGMII Timing Requirements – RGMII[x]_RXC see Figure 6-111 NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT RGMII1 tc(RXC) Cycle time, RGMII[x]_RXC 10Mbps 360 440 ns 100Mbps 36 44 ns 1000Mbps 7.2 8.8 ns RGMII2 tw(RXCH) Pulse duration, RGMII[x]_RXC high 10Mbps 160 240 ns 100Mbps 16 24 ns 1000Mbps 3.6 4.4 ns RGMII3 tw(RXCL) Pulse duration, RGMII[x]_RXC low 10Mbps 160 240 ns 100Mbps 16 24 ns 1000Mbps 3.6 4.4 ns Table 6-143. PRU_ICSSG RGMII Timing Requirements – RGMII[x]_RD[3:0] and RGMII[x]_RX_CTL see Figure 6-111 NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT RGMII4 tsu(RD-RXC) Setup time, RGMII[x]_RD[3:0] valid before RXC high/low 10Mbps 1 ns 100Mbps 1 ns 1000Mbps 1 ns tsu(RX_CTL-RXC) Setup time, RGMII[x]_RX_CTL valid before RGMII[x]_RXC high/low 10Mbps 1 ns 100Mbps 1 ns 1000Mbps 1 ns RGMII5 th(RXC-RD) Hold time, RGMII[x]_RD[3:0] valid after RGMII[x]_RXC high/low 10Mbps 1 ns 100Mbps 1 ns 1000Mbps 1 ns th(RXC-RX_CTL) Hold time, RGMII[x]_RX_CTL valid after RGMII[x]_RXC high/low 10Mbps 1 ns 100Mbps 1 ns 1000Mbps 1 ns RGMII[x] RD 3_ [ :0] (B) RGMII[x] RX_CTL_ (B) RGMII[x] RXC_ (A) RGMII4 RXERRRXDV 2nd Half-byte1st Half-byte RGMII2 RGMII3 RGMII1 RGMII5 A. RGMII[x]_RXC must be externally delayed relative to the data and control pins. B. Data and control information is received using both edges of the clocks. RGMII[x]_RD[3:0] carries data bits 3-0 on the rising edge of RGMII[x]_RXC and data bits 7-4 on the falling edge of RGMII[x]_RXC. Similarly, RGMII[x]_RX_CTL carries RXDV on rising edge of RGMII[x]_RXC and RXERR on falling edge of RGMII[x]_RXC. Figure 6-111. PRU_ICSSG RGMII[x]_RXC, RGMII[x]_RD[3:0], RGMII[x]_RX_CTL Timing Requirements - RGMII Mode www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 233 Product Folder Links: AM2434 AM2432 AM2431

Table 6-144. PRU_ICSSG RGMII Switching Characteristics – RGMII[x]_TXC see Figure 6-112 NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT RGMII6 tc(TXC) Cycle time, RGMII[x]_TXC 10Mbps 360 440 ns 100Mbps 36 44 ns 1000Mbps 7.2 8.8 ns RGMII7 tw(TXCH) Pulse duration, RGMII[x]_TXC high 10Mbps 160 240 ns 100Mbps 16 24 ns 1000Mbps 3.6 4.4 ns RGMII8 tw(TXCL) Pulse duration, RGMII[x]_TXC low 10Mbps 160 240 ns 100Mbps 16 24 ns 1000Mbps 3.6 4.4 ns Table 6-145. PRU_ICSSG RGMII Switching Characteristics – RGMII[x]_TD[3:0] and RGMII[x]_TX_CTL see Figure 6-112 NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT RGMII9 tosu(TD-TXC) Output setup time, RGMII[x]_TD[3:0] valid to RGMII[x]_TXC high/low 10Mbps 1.2 ns 100Mbps 1.2 ns 1000Mbps 1.2 ns tosu(TX_CTL-TXC) Output setup time, RGMII[x]_TX_CTL valid to RGMII[x]_TXC high/low 10Mbps 1.2 ns 100Mbps 1.2 ns 1000Mbps 1.2 ns RGMII10 toh(TXC-TD) Output setup time, RGMII[x]_TD[3:0] valid after RGMII[x]_TXC high/low 10Mbps 1.2 ns 100Mbps 1.2 ns 1000Mbps 1.2 ns toh(TXC-TX_CTL) Output setup time, RGMII[x]_TX_CTL valid after RGMII[x]_TXC high/low 10Mbps 1.2 ns 100Mbps 1.2 ns 1000Mbps 1.2 ns RGMII[x]_TXC (A) RGMII[x]_TD[3:0] (B) RGMII[x] TX_CTL_ (B) RGMII9 1st Half-byte TXERRTXEN 2nd Half-byte RGMII7 RGMII8 RGMII6 RGMII10 A. TXC is delayed internally before being driven to the RGMII[x]_TXC pin. This internal delay is always enabled. B. Data and control information is received using both edges of the clocks. RGMII[x]_TD[3:0] carries data bits 3-0 on the rising edge of RGMII[x]_TXC and data bits 7-4 on the falling edge of RGMII[x]_TXC. Similarly, RGMII[x]_TX_CTL carries TXEN on rising edge of RGMII[x]_TXC and TXERR on falling edge of RGMII[x]_TXC. Figure 6-112. PRU_ICSSG RGMII[x]_TXC, RGMII[x]_TD[3:0], and RGMII[x]_TX_CTL Switching Characteristics - RGMII Mode AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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6.11.5.17 Timers

For more details about features and additional description information on the device Timers, see the corresponding subsections within Signal Descriptions and Detailed Description sections. Table 6-146. Timer Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate 0.5 5 V/ns OUTPUT CONDITIONS CL Output load capacitance 2 10 pF Table 6-147. Timer Input Timing Requirements see Figure 6-113 NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT T1 tw(TINPH) Pulse duration, high CAPTURE 2 + 4P (1) ns T2 tw(TINPL) Pulse duration, low CAPTURE 2 + 4P (1) ns (1) P = functional clock period in ns. Table 6-148. Timer Output Switching Characteristics see Figure 6-113 NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT T3 tw(TOUTH) Pulse duration, high PWM -2 + 4P (1) ns T4 tw(TOUTL) Pulse duration, low PWM -2 + 4P (1) ns (1) P = functional clock period in ns. T1 T2 TIMER_IOx (inputs) TIMER_01 T3 T4 TIMER_IOx (outputs) Figure 6-113. Timer Timing Requirements and Switching Characteristics For more information, see Timers section in Peripherals chapter in the device TRM. www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 235 Product Folder Links: AM2434 AM2432 AM2431

6.11.5.18 UART

For more details about features and additional description information on the device Universal Asynchronous Receiver Transmitter, see the corresponding subsections within Signal Descriptions and Detailed Description sections. Table 6-149. UART Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate 0.5 5 V/ns OUTPUT CONDITIONS CL Output load capacitance 1 30(1) pF (1) This value represents an absolute maximum load capacitance. As the UART baud rate increases, it may be necessary to reduce the load capacitance to a value less than this maximum limit to provide enough timing margin for the attached device. The output rise/fall times increase as capacitive load increases, which decreases the time data is valid for the receiver of the attached devices. Therefore, it is important to understand the minimum data valid time required by the attached device at the operating baud rate. Then use the device IBIS models to verify the actual load capacitance on the UART signals does not increase the rise/fall times beyond the point where the minimum data valid time of the attached device is violated. Table 6-150. UART Timing Requirements see Figure 6-114 NO. PARAMETER DESCRIPTION MIN MAX UNIT 1 tw(RXD) Pulse width, receive data bit high or low 0.95U(1) (2) 1.05U(1) (2) ns 2 tw(RXDS) Pulse width, receive start bit low 0.95U(1) (2) ns (1) U = UART baud time in ns = 1/programmed baud rate. (2) This value defines the data valid time, where the input voltage is required to be above VIH or below VIL. Table 6-151. UART Switching Characteristics see Figure 6-114 NO. PARAMETER DESCRIPTION MIN MAX UNIT f(baud) Programmable baud rate for Main Domain UARTs 12 Mbps Programmable baud rate for MCU Domain UARTs 3.7 Mbps 3 tw(TXD) Pulse width, transmit data bit high or low U(1) - 2.2 U(1) + 2.2 ns 4 tw(TXDS) Pulse width, transmit start bit low U(1) - 2.2 ns (1) U = UART baud time in ns = 1/programmed baud rate. UARTi_TXD Start Bit Data Bits UARTi_RXD Data Bits Bit Start VIH VIL UART_TIMING_01_RCVRVIHVIL Figure 6-114. UART Timing Requirements and Switching Characteristics AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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For more information, see Universal Asynchronous Receiver/Transmitter (UART) section in Peripherals chapter in the device TRM.

6.11.5.19 USB

The USB 2.0 subsystem is compliant with the Universal Serial Bus (USB) Specification, revision 2.0. Refer to the specification for timing details. The USB 3.1 GEN1 subsystem is compliant with the Universal Serial Bus (USB) 3.1 Specification, revision 1.0. Refer to the specification for timing details. For more details about features and additional description information on the device Universal Serial Bus Subsystem (USB), see the SERDES0 Signal Descriptions and the corresponding subsection within Detailed Description. www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 237 Product Folder Links: AM2434 AM2432 AM2431

6.11.6 Emulation and Debug

For more details about features and additional description information on the device Trace and JTAG interfaces, see the corresponding subsections within Signal Descriptions and Detailed Description sections.

6.11.6.1 Trace

Table 6-152. Trace Timing Conditions PARAMETER MIN MAX UNIT OUTPUT CONDITIONS CL Output load capacitance 2 5 pF PCB CONNECTIVITY REQUIREMENTS td(Trace Mismatch) Propagation delay mismatch across all traces VDDSHV3 = 1.8V 200 ps VDDSHV3 =3.3V 100 ps Table 6-153. Trace Switching Characteristics NO. PARAMETER MIN MAX UNIT 1.8V Mode DBTR1 tc(TRC_CLK) Cycle time, TRC_CLK 6.50 ns DBTR2 tw(TRC_CLKH) Pulse width, TRC_CLK high 2.50 ns DBTR3 tw(TRC_CLKL) Pulse width, TRC_CLK low 2.50 ns DBTR4 tosu(TRC_DATAV- TRC_CLK) Output setup time, TRC_DATA valid to TRC_CLK edge 0.81 ns DBTR5 toh(TRC_CLK-TRC_DATAI) Output hold time, TRC_CLK edge to TRC_DATA invalid 0.81 ns DBTR6 tosu(TRC_CTLV-TRC_CLK) Output setup time, TRC_CTL valid to TRC_CLK edge 0.81 ns DBTR7 toh(TRC_CLK-TRC_CTLI) Output hold time, TRC_CLK edge to TRC_CTL invalid 0.81 ns 3.3V Mode DBTR1 tc(TRC_CLK) Cycle time, TRC_CLK 8.67 ns DBTR2 tw(TRC_CLKH) Pulse width, TRC_CLK high 3.58 ns DBTR3 tw(TRC_CLKL) Pulse width, TRC_CLK low 3.58 ns DBTR4 tosu(TRC_DATAV- TRC_CLK) Output setup time, TRC_DATA valid to TRC_CLK edge 1.08 ns DBTR5 toh(TRC_CLK-TRC_DATAI) Output hold time, TRC_CLK edge to TRC_DATA invalid 1.08 ns DBTR6 tosu(TRC_CTLV-TRC_CLK) Output setup time, TRC_CTL valid to TRC_CLK edge 1.08 ns DBTR7 toh(TRC_CLK-TRC_CTLI) Output hold time, TRC_CLK edge to TRC_CTL invalid 1.08 ns TRC_DATA TRC_CTL TRC_CLK ( ) ( ) (Ideal) Worst Case 1 Worst Case 2 DBTR1 DBTR2 DBTR3 DBTR4 DBTR6 DBTR5 DBTR7 DBTR4 DBTR6 DBTR5 DBTR7 SPRSP08_Debug_01 Figure 6-115. Trace Switching Characteristics AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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6.11.6.2 JTAG

Table 6-154. JTAG Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate 0.5 2.0 V/ns OUTPUT CONDITIONS CL Output load capacitance 5 15 pF PCB CONNECTIVITY REQUIREMENTS td(Trace Delay) Propagation delay of each trace 83.5 1000(1) ps td(Trace Mismatch Delay) Propagation delay mismatch across all traces 100 ps (1) Maximum propagation delay associated with the JTAG signal traces has a significant impact on maximum TCK operating frequency. It may be possible to increase the trace delay beyond this value, but the operating frequency of TCK must be reduced to account for the additional trace delay. Table 6-155. JTAG Timing Requirements see Figure 6-116 NO. MIN MAX UNIT J1 tc(TCK) Cycle time minimum, TCK 45.5(1) ns J2 tw(TCKH) Pulse width minimum, TCK high 0.4P(2) ns J3 tw(TCKL) Pulse width minimum, TCK low 0.4P(2) ns tsu(TDI-TCK) Input setup time minimum, TDI valid to TCK high 4 ns tsu(TMS-TCK) Input setup time minimum, TMS valid to TCK high 4 ns th(TCK-TDI) Input hold time minimum, TDI valid from TCK high 2 ns th(TCK-TMS) Input hold time minimum, TMS valid from TCK high 2 ns (1) The maximum TCK operating frequency assumes the following timing requirements and switching characteristics for the attached debugger. The operating frequency of TCK must be reduced to provide appropriate timing margin if the debugger exceeds any of these assumptions.

Minimum TDO setup time of 2.2ns relative to the rising edge of TCK
TDI and TMS output delay in the range of -16.1ns to 14.1ns relative to the falling edge of TCK (2) P = TCK cycle time in ns Table 6-156. JTAG Switching Characteristics see Figure 6-116 NO. PARAMETER MIN MAX UNIT J6 td(TCKL-TDOI) Delay time minimum, TCK low to TDO invalid 0 ns J7 td(TCKL-TDOV) Delay time maximum, TCK low to TDO valid 14 ns TDO TCK TDI / TMS J6 J7 J4 J5 Figure 6-116. JTAG Timing Requirements and Switching Characteristics www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 239 Product Folder Links: AM2434 AM2432 AM2431

7 Detailed Description

7.1 Overview

AM243x is an extension of the Sitara™ industrial-grade family of heterogeneous Arm processors. AM243x is built for industrial applications, such as motor drives and programmable logic controllers (PLCs), which require a unique combination of real-time processing and communications with applications processing. AM243x combines two instances of Sitara’s gigabit TSN-enabled PRU-ICSSG, up to four Cortex-R5F MCUs, and a Cortex-M4F MCU domain. AM243x is architected to provide real-time performance through the high-performance R5Fs, Tightly-Coupled Memory banks, configurable SRAM partitioning, and low-latency paths to and from peripherals for rapid data movement in and out of the SoC. This deterministic architecture allows for AM243x to handle the tight control loops found in servo drives, while the peripherals like FSI, GPMC, PWMs, sigma delta decimation filters, and absolute encoder interfaces help enable a number of different architectures found in these systems. The PRU_ICSSG in AM243x provides the flexible industrial communications capability necessary to run gigabit TSN, EtherCAT, PROFINET, EtherNet/IP, and various other protocols. In addition, the PRU_ICSSG also enables additional interfaces in the SoC including sigma delta decimation filter modules and absolute encoder interfaces. Functional safety features can be enabled through the MCU domain with an integrated Cortex-M4F and dedicated peripheral set which can all be shared or isolated from the rest of the SoC. AM243x also supports secure boot. Note For more information on features, subsystems, and architecture of superset device System on Chip (SoC), see the device TRM. AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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7.2 Processor Subsystems

7.2.1 Arm Cortex-R5F Subsystem (R5FSS)

The R5FSS is a dual-core implementation of the Arm ® Cortex®-R5F processor configured for dual/single-core operation. It also includes accompanying memories (L1 caches and tightly-coupled memories), standard Arm ® CoreSight™ debug and trace architecture, integrated Vectored Interrupt Manager (VIM), ECC Aggregators, and various wrappers for protocol conversion and address translation for easy integration into the SoC. Note The Cortex®-R5F processor is a Cortex-R5 processor that includes the optional Floating Point Unit (FPU) extension. For more information, see Dual-R5F Subsystem (R5FSS) section in Processors and Accelerators chapter in the device TRM.

7.2.2 Arm Cortex-M4F (M4FSS)

The M4FSS module on the AM243x device provides a safety channel (secondary channel - working in conjunction with an external microcontroller)- or- a general purpose MCU. The M4FSS module supports the following features:

Cortex M4F With MPU
ARMv7-M architecture
Support for Nested Vectored Interrupt Controller (NVIC) with 64 inputs
Ability to executed code from internal or external memories
192 KB of SRAM (I-Code)
64 KB of SRAM (D-Code)
External access to internal memories if allowed
Debug Support Including: – DAP based Debug to the CPU Core – Full Debug Features of CPU Core are enabled – Standard ITM trace – CTM Cross Trigger – ETM Trace Support
Fault Detection and Correction – SECDED ECC protection on I-CODE – SECDED ECC protection on D-CODE – Fault Error Interrupt Output For more information, see Arm Cortex M4F Subsystem (M4FSS) section in Processors and Accelerators chapter in the device TRM. www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 241 Product Folder Links: AM2434 AM2432 AM2431

7.3 Accelerators and Coprocessors

7.3.1 Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU_ICSSG)

The PRU_ICSSG module supports the following main features:

3x PRUs – General-Purpose PRU (PRU) – Real-Time PRU(RTU_PRU) – Transmit PRU (TX_PRU)
2x Ethernet MII_G_RT configurable connection to PRUs – Up to 2x RGMII ports – Up to 2x MII ports – RX Classifier
2x Industrial Ethernet Peripheral (IEP) to manage and generate industrial Ethernet functions
2x Industrial Ethernet 64-bit timers, each with 10 capture and 16 compare events, along with slow and fast compensation.
1x MDIO
1x UART, with a dedicated 192MHz clock input
Supports up to 4 sets of 3-phased motor control, with 12 primary and 12 complimentary programmable PWM outputs.
Supports up to 9 safety events with optional external trip I/O per PWM set with hardware glitch filter.
1x Enhanced Capture Module (ECAP)
1x Interrupt Controller (INTC) – 160 input events supported – 96 external, 64 internal
Flexible power management support
Integrated switched central resource with programmable priority
All memories support ECC For more information, see Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem - Gigabit (PRU_ICSSG) section in Processors and Accelerators chapter in the device TRM.

7.4 Other Subsystems

7.4.1 PDMA Controller

The Peripheral DMA is a simple DMA which has been architected to specifically meet the data transfer needs of peripherals, which perform data transfers using memory mapped registers accessed via a standard non-coherent bus fabric. The PDMA module is intended to be located close to one or more peripherals which require an external DMA for data movement and is architected to reduce cost by using VBUSP interfaces and supporting only statically configured Transfer Request (TR) operations. The PDMA is only responsible for performing the data movement transactions which interact with the peripherals themselves. Data which is read from a given peripheral is packed by a PDMA source channel into a PSI-L data stream which is then sent to a remote peer UDMA-P destination channel which then performs the movement of the data into memory. Likewise, a remote UDMA-P source channel fetches data from memory and transfers it to a peer PDMA destination channel over PSI-L which then performs the writes to the peripheral. The PDMA architecture is intentionally heterogeneous (UDMA-P + PDMA) to right size the data transfer complexity at each point in the system to match the requirements of whatever is being transferred to or from. Peripherals are typically FIFO based and do not require multi-dimensional transfers beyond their FIFO dimensioning requirements, so the PDMA transfer engines are kept simple with only a few dimensions (typically for sample size and FIFO depth), hardcoded address maps, and simple triggering capabilities. Multiple source and destination channels are provided within the PDMA which allow multiple simultaneous transfer operations to be ongoing. The DMA controller maintains state information for each of the channels and employs round-robin scheduling between channels in order to share the underlying DMA hardware. There are five PDMA modules in the device. AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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For more information, see PDMA Controller section in DMA Controllers chapter in the device TRM.

7.4.2 Peripherals

7.4.2.1 ADC

The analog-to-digital converter (ADC) module is a single-channel general purpose analog-to-digital converter with an 8-input analog multiplexer, which supports 12-bit conversion samples from an analog front end (AFE). There is one ADC module in the device. Note The AM243x_ALX package only supports 10-bits of data from the 12-bit conversion. For more information, see Analog-to-Digital Converter (ADC) section in Peripherals chapter in the device TRM.

7.4.2.2 DCC

The Dual Clock Comparator (DCC) is used to determine the accuracy of a clock signal during the time execution of an application. Specifically, the DCC is designed to detect drifts from the expected clock frequency. The desired accuracy can be programed based on calculation for each application. The DCC measures the frequency of a selectable clock source using another input clock as a reference. The device has seven instances of DCC modules. For more information, see Dual Clock Comparator (DCC) section in Peripherals chapter in the device TRM.

7.4.2.3 Dual Date Rate (DDR) External Memory Interface (DDRSS)

Integrated in MAIN domain: one instance of DDR Subsystem (DDRSS) is used as an interface to external RAM devices which can be utilized for storing program or data. DDRSS provides the following main features:

Support of DDR4 / LPDDR4 memory types
16-bit memory bus interface with in-line ECC
System bus interface: little Endian only with 128-bit data width
Configuration bus Interface: little Endian only with 32-bit data width
Support of dual rank configuration
Support of automatic idle power saving mode when no or low activity is detected
Class of Service (CoS) - three latency classes supported
Prioritized refresh scheduling
Statistical counters for performance management For more information, see DDR Subsystem (DDRSS) section in Peripherals chapter in the device TRM.

7.4.2.4 ECAP

This section describes the Enhanced Capture (ECAP) module for the device. For more information, see Enhanced Capture (ECAP) Module section in Peripherals chapter in the device TRM.

7.4.2.5 EPWM

An effective PWM peripheral must be able to generate complex pulse width waveforms with minimal CPU overhead or intervention. It needs to be highly programmable and very flexible while being easy to understand and use. The EPWM unit described here addresses these requirements by allocating all needed timing and control resources on a per PWM channel basis. Cross coupling or sharing of resources has been avoided; instead, the EPWM is built up from smaller single channel modules with separate resources and that can operate together as required to form a system. This modular approach results in an orthogonal architecture and provides a more transparent view of the peripheral structure, helping users to understand its operation quickly. In the further description the letter x within a signal or module name is used to indicate a generic EPWM instance on a device. For example, output signals EPWMxA and EPWMxB refer to the output signals from the EPWM_x www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 243 Product Folder Links: AM2434 AM2432 AM2431

instance. Thus, EPWM1A and EPWM1B belong to EPWM1, EPWM2A and EPWM2B belong to EPWM2, and so forth. Additionally, the EPWM integration allows this synchronization scheme to be extended to the capture peripheral modules (ECAP). The number of modules is device-dependent and based on target application needs. Modules can also operate stand-alone. The device has six instances of EPWM modules. For more information, see Enhanced Pulse Width Modulation (EPWM) Module section in Peripherals chapter in the device TRM.

7.4.2.6 ELM

The Error Location Module (ELM) is used with the GPMC. Syndrome polynomials generated on-the-fly when reading a NAND flash page and stored in GPMC registers are passed to the ELM. A host processor can then correct the data block by flipping the bits to which the ELM error-location outputs point. When reading from NAND flash memories, some level of error-correction is required. In the case of NAND modules with no internal correction capability, sometimes referred to as bare NANDs, the correction process is delegated to the memory controller. ELM can be also used to support parallel NOR flash or NAND flash. The General-Purpose Memory Controller (GPMC) probes data read from an external NAND flash and uses this to compute checksum-like information, called syndrome polynomials, on a per-block basis. Each syndrome polynomial gives a status of the read operations for a full block, including 512 bytes of data, parity bits, and an optional spare-area data field, with a maximum block size of 1023 bytes. Computation is based on a Bose-Chaudhuri-Hocquenghem (BCH) algorithm. The ELM extracts error addresses from these syndrome polynomials. For more information, see Error Location Module (ELM) section in Peripherals chapter in the device TRM.

7.4.2.7 ESM

The Error Signaling Module (ESM) aggregates safety-related events and/or errors from throughout the device into one location. The module can signal both low and high priority interrupts to a processor to deal with a safety event and/or manipulate an I/O error pin to signal external hardware that an error has occurred. This allows an external controller to reset the device or keep the system in safe, known state. For more information, see Error Signaling Module (ESM) section in Peripherals chapter in the device TRM.

7.4.2.8 GPIO

The general-purpose input/output (GPIO) peripheral provides dedicated general-purpose pins that can be configured as either inputs or outputs. When configured as an output, user can write to an internal register to control the state driven on the output pin. When configured as an input, user can obtain the state of the input by reading the state of an internal register. In addition, the GPIO peripheral can produce host CPU interrupts and DMA synchronization events in different interrupt/event generation modes. For more information, see General-Purpose Interface (GPIO) section in Peripherals chapter in the device TRM.

7.4.2.9 EQEP

The Enhanced Quadrature Encoder Pulse (EQEP) peripheral is used for direct interface with a linear or rotary incremental encoder to get position, direction and speed information from a rotating machine for use in high performance motion and position control system. The disk of an incremental encoder is patterned with a single track of slots patterns. These slots create an alternating pattern of dark and light lines. The disk count is defined as the number of dark/light line pairs that occur per revolution (lines per revolution). As a rule, a second track is added to generate a signal that occurs once per revolution (index signal: QEPI), which can be used to indicate an absolute position. Encoder manufacturers identify the index pulse using different terms such as index, marker, home position and zero reference. AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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To derive direction information, the lines on the disk are read out by two different photo-elements that "look" at the disk pattern with a mechanical shift of 1/4 the pitch of a line pair between them. This shift is realized with a reticle or mask that restricts the view of the photo-element to the desired part of the disk lines. As the disk rotates, the two photo-elements generate signals that are shifted 90 degrees out of phase from each other. These are commonly called the quadrature QEPA and QEPB signals. The clockwise direction for most encoders is defined as the QEPA channel going positive before the QEPB channel and vice versa. The encoder wheel typically makes one revolution for every revolution of the motor or the wheel can be at a geared rotation ratio with respect to the motor. Therefore, the frequency of the digital signal coming from the QEPA and QEPB outputs varies proportionally with the velocity of the motor. For example, a 2000-line encoder directly coupled to a motor running at 5000 revolutions per minute (rpm) results in a frequency of 166.6KHz, so by measuring the frequency of either the QEPA or QEPB output, the processor can determine the velocity of the motor. For more information, see Enhanced Quadrature Encoder Pulse (EQEP) Module section in Peripherals chapter in the device TRM.

7.4.2.10 General-Purpose Memory Controller (GPMC)

The General-Purpose Memory Controller is a unified memory controller dedicated for interfacing with external memory devices like:

Asynchronous SRAM-like memories and application-specific integrated circuit (ASIC) devices
Asynchronous, synchronous, and page mode (available only in non-multiplexed mode) burst NOR flash devices
NAND flash
Pseudo-SRAM devices For more information, see General-Purpose Memory Controller section in Peripherals chapter in the device TRM.

7.4.2.11 I2C

The Inter-IC Bus (I2C) interface is implemented using the mshsi2c module. This peripheral implements the multi-controller I2C bus, which allows serial transfer of 8-bit data to and from other I2C controller and target devices, through a two-wire interface. The I2C module supports the following main features:

Compliant with Philips I2C specification version 2.1
Supported Speeds: – Standard mode (up to 100 K bits/s) – Fast mode (up to 400 K bits/s) – High-speed mode (up to 3.4M bits/s), I2C0 and MCU_I2C0 only
Multi-controller transmitter and target receiver mode
Multi-controller receiver and target transmitter mode
Combined controller transmit/receive and receive/transmit modes
7-bit and 10-bit device addressing modes
Built-in 32-byte FIFO for buffered read or write
Programmable multi-target channel (responds to 4 separates addresses)
Programmable clock generation
Support for asynchronous wake-up
One interrupt line For more information, see Inter-Integrated Circuit (I2C) Interface section in Peripherals chapter in the device TRM.

7.4.2.12 MCAN

The Controller Area Network (CAN) is a serial communications protocol which efficiently supports distributed real-time control with a high level of security. CAN has high immunity to electrical interference and the ability www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 245 Product Folder Links: AM2434 AM2432 AM2431

to self-diagnose and repair data errors. In a CAN network, many short messages are broadcast to the entire network, which provides for data consistency in every node of the system. The MCAN module supports both classic CAN and CAN FD (CAN with Flexible Data-Rate) specifications. CAN FD feature allows high throughput and increased payload per data frame. The classic CAN and CAN FD devices can coexist on the same network without any conflict. The device supports 2 MCAN modules For more information, see Modular Controller Area Network (MCAN) section in Peripherals chapter in the device TRM.

7.4.2.13 MCRC Controller

VBUSM CRC controller is a module which is used to perform CRC (Cyclic Redundancy Check) to verify the integrity of a memory system. A signature representing the contents of the memory is obtained when the contents of the memory are read into MCRC Controller. The responsibility of MCRC controller is to calculate the signature for a set of data and then compare the calculated signature value against a pre-determined good signature value. MCRC controller provides four channels to perform CRC calculation on multiple memories in parallel and can be used on any memory system. Channel 1 can also be put into data trace mode, where MCRC controller compresses each data being read through CPU read data bus. For more information, see MCRC Controller section in Interprocessor Communication chapter in the device TRM.

7.4.2.14 MCSPI

The MCSPI module is a multichannel transmit/receive, controller/peripheral synchronous serial bus. There are total of seven MCSPI modules in the device. For more information, see Multichannel Serial Peripheral Interface (MCSPI) section in Peripherals chapter in the device TRM.

7.4.2.15 MMCSD

There are two Multi-Media Card/Secure Digital (MMCSD) modules inside the device - MMCSD0 and MMCSD1. Each MMCSD module includes one MMCSD Host Controller, where MMCSD0 is associated with MMC0 and MMCSD1 is associated with MMC1. The MMCSD Host Controller supports:

One controller with 8-bit wide data bus
One controller with 4-bit wide data bus
Support of eMMC5.1 Host Specification (JESD84-B51)
Support of SD Host Controller Standard Specification - SDIO 3.00
Integrated DMA controller supporting SD Advanced DMA - ADMA2 and ADMA3
eMMC Electrical Standard 5.1 (JESD84-B51)
Multi-Media card features: – Backward compatible with earlier eMMC standards – Legacy MMC SDR: 1.8V, 8/4/1-bit bus width, 0-25MHz, 25/12.5/3.125 MB/s – High Speed SDR: 1.8V, 8/4/1-bit bus width, 0-50MHz, 50/25/6.25 MB/s – High Speed DDR: 1.8V, 8/4-bit bus width, 0-50MHz, 100/50 MB/s – HS200 SDR: 1.8V, 0-200MHz, 8/4-bit bus width, 200/100 MB/s
SD card support: SDIO, SDR12, SDR25, SDR50, DDR50
System bus interface: CBA 4.0 VBUSM initiator port with 64-bit data width and 64-bit address, little Endian only
Configuration bus interface: CBA 4.0 VBUSM with 32-bit data width, 32-bit aligned accesses only, linear incrementing addressing mode, little Endian only For more information, see Multi-Media Card/Secure Digital (MMCSD) Interface section in Peripherals chapter in the device TRM. AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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7.4.2.16 OSPI

The Octal Serial Peripheral Interface (OSPI) module is a kind of Serial Peripheral Interface (SPI) module which allows single, dual, quad or octal read and write access to external flash devices. This module has a memory mapped register interface, which provides a direct memory interface for accessing data from external flash devices, simplifying software requirements. The OSPI module is used to transfer data, either in a memory mapped direct mode (for example a processor wishing to execute code directly from external flash memory), or in an indirect mode where the module is set-up to silently perform some requested operation, signaling its completion via interrupts or status registers. For indirect operations, data is transferred between system memory and external flash memory via an internal SRAM which is loaded for writes and unloaded for reads by a device controller at low latency system speeds. Interrupts or status registers are used to identify the specific times at which this SRAM should be accessed using user programmable configuration registers. For more information, see Octal Serial Peripheral Interface (OSPI) section in Peripherals chapter in the device TRM.

7.4.2.17 Peripheral Component Interconnect Express (PCIe)

The PCIe subsystem supports the following main features:

Dual mode – root port (RP) or end point (EP) modes.
1-lane configuration with up to 5.0GT/lane.
62.5/125MHz operation on PIPE interface for Gen1/Gen2 respectively
Constant 32-bit PIPE width for Gen1/Gen2 modes
Maximum outbound payload size of 128 bytes
Maximum inbound payload size of 128 bytes
Maximum remote read request size of 4K bytes
Maximum number of nonposted outstanding transactions: 8 on each VBUSM interface.
Four virtual channels (4VC)
Resizable BAR capability
SRIS support
Power Management – L1 Power Management Substate support – D1 support – L1 Power Shutoff support
Legacy, MSI, and MSI-X interrupt support
32 outbound address translation regions
Precision time measurement (PTM) For more information, see Peripheral Component Interconnect Express (PCIe) Subsystem section in Peripherals chapter in the device TRM.

7.4.2.18 Serializer/Deserializer (SerDes) PHY

Integrated in the MAIN domain is one instance of high-speed differential interface implemented with Serializer/ Deserializer (SerDes) Multi-protocol Multi-link PHY with the following main blocks:

Single-lane SerDes PHY with common module for peripheral and Tx clocking handling
Physical coding sub-block for data translation from/to the parallel interface, as well as data encoding/ decoding and symbol alignment
MUX module for device interface multiplexing into a single SerDes lane (Tx and Rx)
A wrapper for sending control and reporting status signals from the SerDes and muxes For more information, see Serializer/Deserializer (SerDes) section in Peripherals chapter in the device TRM.

7.4.2.19 Real Time Interrupt (RTI/WWDT)

This section describes the Real Time Interrupt (RTI) modules with Windowed Watchdog Timer (WWDT) functionality for the device. www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 247 Product Folder Links: AM2434 AM2432 AM2431

For more information, see Real Time Interrupt (RTI/WWDT) Module section in Peripherals chapter of the device TRM.

7.4.2.20 Dual Mode Timer (DMTIMER)

The Dual Mode Timer (DMTIMER) module supports the following main features:

Interrupts generated on overflow, compare, and capture events
Free running 32-bit upward counter
Supported operating modes: – Compare and capture modes – Auto-reload mode – Start-stop mode
Programmable divider clock source (2n with n=[0:8])
Dedicated input trigger for capture mode, and dedicated output trigger/PWM (pulse width modulation) signal
On the fly read/write register (while counting)
Generate 1ms tick with 32768Hz functional clock For more information, see Timers section in Peripherals chapter in the device TRM.

7.4.2.21 UART

The UART module supports the following main features:

16C750 compatibility
Baud rate from 300bps up to 12Mbps (MCU_UART0 and MCU_UART1 limited to 3.7Mbps)
Auto-baud between 1200bps and 115.2Kbps
Software/hardware flow control – Programmable Xon/Xoff characters – Programmable Auto-RTS and Auto CTS
Programmable serial interface characteristics – 5-, 6-, 7-, 8-bit characters – Even, odd, mark (always 1), space (always 0), or no parity (non-parity bit frame) bit generation and detection – 1-, 1.5-, or 2-stop bit generation
Optional multi-drop transmission
Configurable time-guard feature
False start bit detection
Line break generation and detection
Modem control functions on UART0 (CTS, RTS, DSR, DTR, RI, and DCD)
Fully prioritized interrupt system controls
Internal test and loopback capabilities
RS-485 External transceiver auto flow control support For more information, see Universal Synchronous/Asynchronous Receiver/Transmitter (UART) section in Peripherals chapter in the device TRM.

7.4.2.22 Universal Serial Bus Subsystem (USBSS)

The Universal Serial Bus Subsystem (USBSS) module supports the following main features: General USB interface:

Compliant with USB 3.1 specification
Compliant with xHCI 1.1 specification
Port configurable as: – USB host:
SuperSpeed Gen 1 (5Gbps)
High-speed (480Mbps) AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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Full-speed (12Mbps)
Low-speed (1.5Mbps) – USB device/peripheral:
High-speed (480Mbps)
Full-speed (12Mbps) – USB Dual-Role device USB Host mode features:
64 slots
Up to 96 periodic simultaneous endpoints
256 primary streams
MSI
Root hub For more information, see Universal Serial Bus (USB) Subsystem section in Peripherals chapter in the device TRM. www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 249 Product Folder Links: AM2434 AM2432 AM2431

8 Applications, Implementation, and Layout

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

8.1 Device Connection and Layout Fundamentals

8.1.1 Power Supply

8.1.1.1 Power Supply Designs

The power supply implementation for this device requires a minimum of four sources when using ALX packaged devices (or five sources when using ALV/ANI packaged devices) for the following voltage domains: 0.85V CORE and RAM supplies, 3.3V IO supply, 1.8V IO supply and 1V8 analog supply. The ALV/ANI package requires an additional source to supply the 1.1V/1.2V DDR IO supply. Refer to the evaluation module or starter kit design files to better understand how specific supply pins can be grouped together. The power solution can be implemented with general purpose Power Management ICs (PMICs) or discrete regulators like DCDCs and LDOs. TPS65219 is an example of a cost and space optimized PMIC with integrated DCDCs, LDOs, multi-function digital signals, sequencer, and supervisor providing the full power solution to supply the processor and principal peripherals. For the most up to date power collateral, visit the TI’s Power supply solutions website. Note The device power supply implementation requires a dedicated 1.8V LDO to supply VPP only during eFuse programming. This LDO is optional and only needed if on-board eFuse programming is required.

8.1.1.2 Power Distribution Network Implementation Guidance

The Sitara Processor Power Distribution Networks: Implementation and Analysis provides guidance for successful implementation of the power distribution network. This includes PCB stackup guidance as well as guidance for optimizing the selection and placement of the decoupling capacitors. TI only supports designs that follow the board design guidelines contained in the application report.

8.1.2 External Oscillator

For more information about External Oscillators, see the Clock Specifications section.

8.1.3 JTAG, EMU, and TRACE

Texas Instruments supports a variety of eXtended Development System ( XDS™) JTAG controllers with various debug capabilities beyond only JTAG support. A summary of this information is available in the XDS Target Connection Guide. For recommendations on JTAG, EMU, and TRACE routing, see the Emulation and Trace Headers Technical Reference Manual

8.1.4 Unused Pins

For more information about Unused Pins, see the Pin Connectivity Requirements section. AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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8.2 Peripheral- and Interface-Specific Design Information

8.2.1 General Routing Guidelines

The following paragraphs detail the routing guidelines that must be observed when routing the various functional LVCMOS interfaces.

Line spacing: – For a line width equal to W, the spacing between two lines must be 2W, at least. This minimizes the crosstalk between switching signals between the different lines. On the PCB, this is not achievable everywhere (for example, when breaking signals out from the device package), but it is recommended to follow this rule as much as possible. When violating this guideline, minimize the length of the traces running parallel to each other (see Figure 8-1). W S = 2 W = 200 µm SWPS040-185 Figure 8-1. Ground Guard Illustration
Length matching (unless otherwise specified): – For bus or traces at frequencies less than 10MHz, the trace length matching (maximum length difference between the longest and the shortest lines) must be less than 25mm. – For bus or traces at frequencies greater than 10MHz, the trace length matching (maximum length difference between the longest and the shortest lines) must be less than 2.5mm.
Characteristic impedance – Unless otherwise specified, the characteristic impedance for single-ended interfaces is recommended to be between 35-Ω and 65-Ω.
Multiple peripheral support – For interfaces where multiple peripherals have to be supported in the star topology, the length of each branch has to be balanced. Before closing the PCB design, it is highly recommended to verify signal integrity based on simulations including actual PCB extraction.

8.2.2 DDR Board Design and Layout Guidelines

The goal of the AM64x\\AM243x DDR Board Design and Layout Guidelines is to make the DDR system implementation straightforward for all designers. Requirements have been distilled down to a set of layout and routing rules that allow designers to successfully implement a robust design for the topologies that TI supports. TI only supports board designs using DDR4 or LPDDR4 memories that follow the guidelines in this document. www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 251 Product Folder Links: AM2434 AM2432 AM2431

8.2.3 OSPI/QSPI/SPI Board Design and Layout Guidelines

The following section details the PCB routing guidelines that must be observed when connecting OSPI, QSPI, or SPI devices.

8.2.3.1 No Loopback, Internal PHY Loopback, and Internal Pad Loopback

The OSPI[x]_CLK output pin must be connected to the CLK input pin of the attached OSPI/QSPI/SPI device
The signal propagation delay from the OSPI[x]_CLK pin to the attached OSPI/QSPI/SPI device CLK pin (A to B) must be ≤ 450ps (~7cm as stripline or ~8cm as microstrip)
The signal propagation delay of each OSPI[x]_D[y] and OSPI[x]_CSn[z] pin to the corresponding attached OSPI/QSPI/SPI device data and control pin (E to F, or F to E) must be approximately equal to the signal propagation delay from the OSPI[x]_CLK pin to the attached OSPI/QSPI/SPI device CLK pin (A to B)
50Ω PCB routing is recommended along with series terminations, as shown in Figure 8-2
Propagation delays and matching: – (A to B) ≤ 450ps – (E to F, or F to E) = ((A to B) ± 60ps) A B E F OSPI[x]_CLK OSPI/QSPI/SPI Device Clock Input OSPI/QSPI/SPI Device IO[y], CS# OSPI[x]_D[y], OSPI[x]_CSn[z] 0 * Ω OSPI_Board_01 OSPI[x]_LBCLKO OSPI[x]_DQS OSPI Device DQS * 0Ω resistor (R1), located as close as possible to the OSPI[x]_CLK pin, is placeholder for fine tuning, if needed. Figure 8-2. OSPI Connectivity Schematic for No Loopback, Internal PHY Loopback, and Internal Pad Loopback AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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8.2.3.2 External Board Loopback

The OSPI[x]_CLK output pin must be connected to the CLK input pin of the attached OSPI/QSPI/SPI device
The OSPI[x]_LBCLKO output pin must be looped back to the OSPI[x]_DQS input pin
The signal propagation delay of the OSPI[x]_LBCLKO pin to the OSPI[x]_DQS pin (C to D) must be approximately twice the propagation delay of the OSPI[x]_CLK pin to the attached OSPI/QSPI/SPI device CLK pin (A to B)
The signal propagation delay of each OSPI[x]_D[y] and OSPI[x]_CSn[z] pin to the corresponding attached OSPI/QSPI/SPI device data and control pin (E to F, or F to E) must be approximately equal to the signal propagation delay from the OSPI[x]_CLK pin to the attached OSPI/QSPI/SPI device CLK pin (A to B)
50Ω PCB routing is recommended along with series terminations, as shown in Figure 8-3
Propagation delays and matching: – (C to D) = 2 x ((A to B) ± 30ps), see the exception note below. – (E to F, or F to E) = ((A to B) ± 60ps) Note The External Board Loopback hold time requirement (defined by parameter number O16 in Table 6-106, OSPI0 Timing Requirements - PHY DDR Mode ) may be larger than the hold time provided by a typical OSPI/QSPI/SPI device. In this case, the propagation delay of OPSI[x]_LBCLKO pin to the OSPI[x]_DQS pin (C to D) can be reduced to provide additional hold time. A B E F OSPI[x]_CLK OSPI/QSPI/SPI Device Clock Input OSPI/QSPI/SPI Device IO[y], CS# OSPI[x]_D[y], OSPI[x]_CSn[z] 0 * Ω OSPI_Board_02 C D OSPI[x]_LBCLKO OSPI[x]_DQS 0 * Ω OSPI Device DQS * 0Ω resistor (R1), located as close as possible to the OSPI[x]_CLK and OSPI[x]_LBCLKO pins, is a placeholder for fine tuning, if needed. Figure 8-3. OSPI Connectivity Schematic for External Board Loopback www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 253 Product Folder Links: AM2434 AM2432 AM2431

8.2.3.3 DQS (only available in Octal SPI devices)

The OSPI[x]_CLK output pin must be connected to the CLK input pin of the attached OSPI/QSPI/SPI device
The DQS pin of the attached OSPI/QSPI/SPI device must be connected to OSPI[x]_DQS pin
The signal propagation delay from the attached OSPI/QSPI/SPI device DQS pin to the OSPI[x]_DQS pin (D to C) must be approximately equal to the signal propagation delay from the OSPI[x]_CLK pin to the attached OSPI/QSPI/SPI device CLK pin (A to B)
The signal propagation delay of each OSPI[x]_D[y] and OSPI[x]_CSn[z] pin to the corresponding attached OSPI/QSPI/SPI device data and control pin (E to F, or F to E) must be approximately equal to the signal propagation delay from the OSPI[x]_CLK pin to the attached OSPI/QSPI/SPI device CLK pin (A to B)
50Ω PCB routing is recommended along with series terminations, as shown in Figure 8-4
Propagation delays and matching: – (D to C) = ((A to B) ± 30ps) – (E to F, or F to E) = ((A to B) ± 60ps) A B E F OSPI[x]_CLK OSPI/QSPI/SPI Device Clock Input OSPI/QSPI/SPI Device IO[y], CS# OSPI[x]_D[y], OSPI[x]_CSn[z] 0 * Ω OSPI_Board_03 C D OSPI[x]_LBCLKO OSPI[x]_DQS OSPI Device DQS * 0Ω resistor (R1), located as close as possible to the OSPI[x]_CLK pin, is a placeholder for fine tuning, if needed. Figure 8-4. OSPI Connectivity Schematic for DQS AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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8.2.4 USB VBUS Design Guidelines

The USB 3.1 specification allows the VBUS voltage to be as high as 5.5V for normal operation, and as high as 20V when the Power Delivery addendum is supported. Some automotive applications require a max voltage to be 30V. The device requires the VBUS signal voltage be scaled down using an external resistor divider (as shown in the Figure 8-5), which limits the voltage applied to the actual device pin (USB0_VBUS). The tolerance of these external resistors should be equal to or less than 1%, and the leakage current of Zener diode at 5V should be less than 100nA. Device USBn_VBUS J7ES_USB_VBUS_01 VSS VSS 16.5 kΩ 1% ± 10 kΩ 1% ± 3.48 kΩ 1% ± VBUS signal (BZX84C6V8 or equivalent) 6.8V Figure 8-5. USB VBUS Detect Voltage Divider / Clamp Circuit The USB0_VBUS pin can be considered to be fail-safe because the external circuit in Figure 8-5 limits the input current to the actual device pin in a case where VBUS is applied while the device is powered off.

8.2.5 System Power Supply Monitor Design Guidelines

The VMON_VSYS pin provides a way to monitor a system power supply. This system power supply is typically a single pre-regulated power source for the entire system and can be connected to the VMON_VSYS pin via and external resistor divider circuit. This system supply is monitored by comparing the external voltage divider output voltage to an internal voltage reference, where a power fail event is triggered when the voltage applied to VMON_VSYS drops below the internal reference voltage. The actual system power supply voltage trip point is determined by the system designer when selecting component values used to implement the external resistor voltage divider circuit. When building the resistor divider circuit the designer must understand various factors which contribute to variability in the system power supply monitor trip point. The first thing to consider is the initial accuracy of the VMON_VSYS input threshold which has a nominal value of 0.45V, with a variation of ±3%. Precision 1% resistors with similar thermal coefficient are recommended for implementing the resistor voltage divider. This minimizes variability contributed by resistor value tolerances. Input leakage current associated with VMON_VSYS must also be considered since any current flowing into the pin creates a loading error on the voltage divider output. The VMON_VSYS input leakage current can be in the range of 10nA to 2.5µA when applying 0.45V. Note The resistor voltage divider shall be designed such that the output voltage never exceeds the maximum value defined in the Recommended Operating Conditions section, during normal operating conditions. Figure 8-6 presents an example, where the system power supply is nominally 5V and the maximum trigger threshold is 5V - 10%, or 4.5V. www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 255 Product Folder Links: AM2434 AM2432 AM2431

For this example, the designer must understand which variables effect the maximum trigger threshold when selecting resistor values. A device which has a VMON_VSYS input threshold of 0.45V + 3% needs to be considered when trying to design a voltage divider that doesn’t trip until the system supply drops 10%. The effect of resistor tolerance and input leakage also needs to be considered, but the contribution to the maximum trigger point is not obvious. When selecting component values which produce a maximum trigger voltage, the system designer must consider a condition where the value of R1 is 1% low and the value of R2 is 1% high combined with a condition where input leakage current for the VMON_VSYS pin is 2.5µA. When implementing a resistor divider where R1 = 4.81KΩ and R2 = 40.2KΩ, the result is a maximum trigger threshold of 4.517V. Once component values have been selected to satisfy the maximum trigger voltage as described above, the system designer can determine the minimum trigger voltage by calculating the applied voltage that produces an output voltage of 0.45V - 3% when the value of R1 is 1% high and the value of R2 is 1% low, and the input leakage current is 10nA, or zero. Using an input leakage of zero with the resistor values given above, the result is a minimum trigger threshold of 4.013V. This example demonstrates a system power supply voltage trip point that ranges from 4.013V to 4.517V. Approximately 250mV of this range is introduced by VMON_VSYS input threshold accuracy of ±3%, approximately 150mV of this range is introduced by resistor tolerance of ±1%, and approximately 100mV of this range is introduced by loading error when VMON_VSYS input leakage current is 2.5µA. The resistor values selected in this example produces approximately 100µA of bias current through the resistor divider when the system supply is 4.5V. The 100mV of loading error mentioned above can be reduced to about 10mV by increasing the bias current through the resistor divider to approximately 1mA. So resistor divider bias current vs loading error is something the system designer needs to consider when selecting component values. The system designer must also consider implementing a noise filter on the voltage divider output since VMON_VSYS has minimum hysteresis and a high-bandwidth response to transients. This can be done by installing a capacitor across R1 as shown in Figure 8-6 . However, the system designer must determine the response time of this filter based on system supply noise and expected response to transient events. Device VMON_VSYS SPRSP56_VMON_ER_MON_01 VSS 4.81 k Ω 40.2 k 1%Ω ± VSYS Value = Determined by system designer (System Power Supply) Figure 8-6. System Supply Monitor Voltage Divider Circuit VMON_1P8_MCU and VMON_1P8_SOC pins provide a way to monitor external 1.8V power supplies. These pins must be connected directly to their respective power source. An internal resistor divider with software control is implemented inside the SoC for each of these pins. Software can program each internal resistor divider to create appropriate under voltage and over voltage interrupts. VMON_3P3_MCU and VMON_3P3_SOC pins provide a way to monitor external 3.3V power supplies. These pins must be connected directly to their respective power source. An internal resistor divider with software control is implemented inside the SoC for each of these pins. Software can program each internal resistor divider to create appropriate under voltage and over voltage interrupts. AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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8.2.6 High Speed Differential Signal Routing Guidance

The High Speed Interface Layout Guidelines provides guidance for successful routing of the high speed differential signals. This includes PCB stackup and materials guidance as well as routing skew, length and spacing limits. TI supports only designs that follow the board design guidelines contained in the application note.

8.2.7 Thermal Solution Guidance

The Thermal Design Guide for DSP and ARM Application Processors provides guidance for successful implementation of a thermal solution for system designs containing this device. This document provides background information on common terms and methods related to thermal solutions. TI only supports designs that follow system design guidelines contained in the application note. www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 257 Product Folder Links: AM2434 AM2432 AM2431

8.3 Clock Routing Guidelines

8.3.1 Oscillator Routing

When designing the printed-circuit board:

Place all crystal circuit components as close as possible to the respective device pins.
Route the crystal circuit traces on the outer layer of the PCB and minimize trace lengths to reduce parasitic capacitance and minimize crosstalk from other signals.
Place a continuous ground plane on the adjacent layer of the PCB such that it is under all crystal circuit components and crystal circuit traces.
Route a ground guard around the crystal circuit components to shield it from any adjacent signals routed on the same layer as the crystal circuit traces. Insert multiple vias to stitch down the ground guard such that it does not have any unterminated stubs.
Route a ground guard between the MCU_OSC0_XI and MCU_OSC0_XO signals to shield the MCU_OSC0_XI signal from the MCU_OSC0_X0 signal. Insert multiple vias to stitch down the ground guard such that it does not have any unterminated stubs.
Connect all crystal circuit ground connections and ground guard connections directly to the adjacent layer ground plane, and the device VSS ground plane if they are implemented separately on different layers of the PCB. Note Implementing a ground guard between the MCU_OSC0_XI and MCU_OSC0_XO signals is critical to minimize shunt capacitance between the two signals. Routing these two signals adjacent to each other without a ground guard between them will effectively reduce the gain of the oscillator amplifier, which reduces its ability to start oscillation. Cap Device Cap Crystal MCU_OSC0_XI MCU_OSC0_XO GND vias GND guard GND vias GND plane Figure 8-7. MCU_OSC0 PCB requirements

8.3.2 Oscillator Ground Connection

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9 Device and Documentation Support

9.1 Device Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all embedded processor devices and support tools. Each device has one of three prefixes: X, P, or null (no prefix) (for example, XAM2434ASFGGAALX). Texas Instruments recommends two of three possible prefix designators for related support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMDX) through fully qualified production devices and tools (TMDS). Device development evolutionary flow: X Experimental device that is not necessarily representative of the device's final electrical specifications and may not use production assembly flow. P Prototype device that is not necessarily the final silicon die and may not necessarily meet final electrical specifications. null (BLANK) Production version of the silicon die that is fully qualified and meets final electrical specifications. Support tool development evolutionary flow: TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing. TMDS Fully-qualified development-support product. X and P devices and TMDX development-support tools are shipped against the following disclaimer: "Developmental product is intended for internal evaluation purposes." Production devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies. Predictions show that prototype devices (X or P) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. For orderable part numbers of AM243x devices in the ALV/ANI or ALX package type, see the Package Option Addendum at the end of this document, the TI website (ti.com), or contact your TI sales representative. www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 259 Product Folder Links: AM2434 AM2432 AM2431

9.1.1 Standard Package Symbolization

Some devices may have a cosmetic circular marking visible on the top of the device package which results from the production test process. In addition, some devices may also show a color variation in the package substrate which results from the substrate manufacturer. These differences are cosmetic only with no reliability impact. aBBBBBBr ZfYytPPPQ A1 (PIN ONE INDICATOR) O G1YYY ZZZ XXXXXXX SITARA aBBBBBBr ZfYytPPPQ1 XXXXXXX A1 (PIN ONE INDICATOR) O G1YYY SITARA Figure 9-1. Printed Device Reference AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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9.1.2 Device Naming Convention

Table 9-1. Nomenclature Description FIELD PARAMETER FIELD DESCRIPTION VALUE DESCRIPTION a Device Evolution Stage X Prototype P Preproduction (production test flow, no reliability data) BLANK(1) Production BBBBBB Base Production Part Number AM2434 (See Device Comparison)AM2432 AM2431 r Device Revision A Silicon Revision (SR) 1.0 B Silicon Revision (SR) 2.0 Z Device Speed Grades S (See Speed Grade Maximum Frequency) K f

Features

(See Device Comparison) C All PRU_ICSSG features are enabled except for industrial communication support. PRU_ICSSG industrial communication interfaces include Ethernet networking (MII/RGMII, MDIO), Sigma-Delta (SD) decimation, and three channel peripheral interface (EnDat 2.2 and BiSS) D Features supported by C, plus PRU_ICSSG industrial communication subsystem are enabled E Features supported by D, plus CAN FD, and hardware support for EtherCAT and other Ethernet protocols requiring hardware auto-forwarding feature are enabled F Features supported by E, plus Pre-integrated Stacks are enabled Y Functional Safety G Non-Functional Safety F Functional Safety y Security G Non-Secure H Secure t Temperature(2) A -40°C to 105°C - Extended Industrial (See Recommended Operating Conditions) I -40°C to 125°C - 125°C Industrial (See Recommended Operating Conditions and Section 6.3 Power-On Hours (POH)) FCBGA-N441 (17.2mm × 17.2mm - 0.8mm pitch) FCBGA-N441 (17.2mm × 17.2mm - 0.8mm pitch) FCCSP-N293 (11.0mm × 11.0mm - 0.5mm pitch) c Carrier Type R Tape and Reel BLANK Tray Q1 Automotive Designator Q Auto Qualified (Q100) EP Enhanced Product BLANK(1) Standard XXXXXXX Lot Trace Code (LTC) YYY Production Code; For TI use only O Pin one designator G1 ECAT—Green package designator (1) BLANK fields in the symbol or part number are collapsed so there are no gaps between characters. (2) Applies to device max junction temperature. See Power-On Hours (POH) for more details. www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 261 Product Folder Links: AM2434 AM2432 AM2431

9.2 Tools and Software

The following Development Tools support development for TI's Embedded Processing platforms: Development Tools Code Composer Studio ™ Integrated Development Environment Code Composer Studio (CCS) Integrated Development Environment (IDE) is a development environment that supports TI's Microcontroller and Embedded Processors portfolio. Code Composer Studio comprises a suite of tools used to develop and debug embedded applications. The tool includes an optimizing C/C++ compiler, source code editor, project build environment, debugger, profiler, and many other features. The intuitive IDE provides a single user interface taking you through each step of the application development flow. Familiar tools and interfaces allow users to get started faster than ever before. Code Composer Studio combines the advantages of the Eclipse® software framework with advanced embedded debug capabilities from TI resulting in a compelling feature-rich development environment for embedded developers. SysConfig Tool The System Configuration tool provides a graphical user interface (GUI) that simplifies device configuration. The tool is designed to simplify hardware and software configuration challenges to accelerate software development. SysConfig is available as part of the Code Composer Studio ™ integrated development environment as well as a standalone application. Additionally SysConfig can be run in the cloud by visiting the TI developer zone. SysConfig allows developers to configure pins, peripherals, and other components, and automatically detects, exposes, and resolves conflicts to speed software development. In addition, the clock tree tool provides a visual implementation of the device clock connectivity. The SysConfig tool generates output C header/code files that can be imported into software development kits (SDKs), enabling customers to configure their software in alignment with the specific hardware requirements. For a complete listing of development-support tools for the processor platform, visit the Texas Instruments website at ti.com. For information on pricing and availability, contact the nearest TI field sales office or authorized distributor.

9.3 Documentation Support

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click the Subscribe to updates bell to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. The current documentation that describes the processor, related peripherals, and other technical collateral is listed below. The following documents describe the AM243x family of devices. Technical Reference Manual AM243x/AM64x Processors Technical Reference Manual (SPRUIM2) The technical reference document details the overview, integration, environment, programming models, and functional descriptions for each peripheral and subsystem in the AM243x family of devices. Errata AM243x/AM64x Processors Silicon Errata (SPRZ457) The silicon errata document describes any known exceptions to the functional specifications for the device. Note Search for literature numbers on ti.com.

9.3.1 Information About Cautions and Warnings

This document may contain cautions and warnings. AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

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A warning in documentation indicates that an action or precaution must be taken to avoid the risk of injury or death to personnel. CAUTION A caution in documentation indicates that an action or precaution must be taken to avoid the risk of damage to components or equipment. The information in a caution or a warning is provided for your protection. Read each caution and warning carefully.

9.4 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

9.5 Trademarks

Sitara™, XDS™, Code Composer Studio™, and TI E2E™ are trademarks of Texas Instruments. CoreSight™ is a trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. TrustZone®, Arm® are registered trademarks of Arm. Cortex® is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. PCI-Express® is a registered trademark of PCI-SIG. EtherCAT® is a registered trademark of Beckhoff Automation GmbH. Eclipse® is a registered trademark of Eclipse Foundation AISBL. All trademarks are the property of their respective owners.

9.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

9.7 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 263 Product Folder Links: AM2434 AM2432 AM2431

Changes from December 22, 2025 to June 3, 2026 (from Revision H (DECEMBER 2025) to Revision I (June 2026)) Page

(GPMC): Widened range of output load capacitance. Specified separate ranges for 133MHz Synchronous
(GPMC and NOR Flash Timing Requirements — Synchronous Mode): Simplified MODE column to include only div_by_1_mode and not_div_by_1_mode. Changed column headers from GPMC_FCLK = 100MHz/ 133MHz to 32-bit data bus (up to 100MHz)/16-bit data bus (up to 133MHz). Simplified several parameter
(GPMC and NOR Flash Switching Characteristics – Synchronous Mode): Removed the MODE column. Combined the GPMC_FCLK=100MHz and GPMC_FCLK=133MHz columns. Reduced F2 and F3 clk-csn maximum output delays. Changed the timing variable in parameters F3 and F11 to "D". Removed 2 of the F7 rows. Removed the "J" timing variable from the F15 and F17 parameters. Added byte enables for 32-bit data bus to F6, F7, F17, F19. Simplified several parameter descriptions. Updated pin names to match Pin
(GPMC and NOR Flash Timing Requirements – Asynchronous Mode): Removed the MODE column and the table note that described register configuration for div_by_1_mode. Added the correct table note for
(GPMC and NOR Flash Switching Characteristics – Asynchronous Mode): Removed the MODE column and redundant rows. Also removed the table note that described register configuration for div_by_1_mode. Moved
(GPMC and NAND Flash Timing Requirements – Asynchronous Mode): Removed the MODE column and the
(GPMC and NAND Flash Switching Characteristics – Asynchronous Mode): Removed the MODE column and the table note that described register configuration for div_by_1_mode. Added table notes and associated AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

Product Folder Links: AM2434 AM2432 AM2431

Changes from June 3, 2026 to June 12, 2026 (from Revision I (JUNE 2026) to Revision J (JUNE 2026)) Page www.ti.com AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 265 Product Folder Links: AM2434 AM2432 AM2431

11 Mechanical, Packaging, and Orderable Information

11.1 Packaging Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. AM2434, AM2432, AM2431 SPRSP65J – APRIL 2021 – REVISED JUNE 2026 www.ti.com

Product Folder Links: AM2434 AM2432 AM2431

www.ti.com 18-Jun-2026 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) AM2431BSDFHIALVR Active Production FCBGA (ALV) | 441 500 | LARGE T&R Yes Call TI Level-3-250C-168 HR -40 to 125 AM2431B SDFHIALV 709 AM2431BSDFHIALVR.B Active Production FCBGA (ALV) | 441 500 | LARGE T&R Yes Call TI Level-3-250C-168 HR -40 to 125 AM2431B SDFHIALV 709 AM2431BSDFHIALXR Active Production FCCSP (ALX) | 293 1000 | LARGE T&R Yes Call TI Level-3-250C-168 HR -40 to 125 AM2431B SDFHIALX 709 AM2431BSDFHIALXR.B Active Production FCCSP (ALX) | 293 1000 | LARGE T&R Yes Call TI Level-3-250C-168 HR -40 to 125 AM2431B SDFHIALX 709 AM2431BSDGHIALVR Active Production FCBGA (ALV) | 441 500 | LARGE T&R Yes Call TI Level-3-250C-168 HR -40 to 125 AM2431B SDGHIALV 709 AM2431BSDGHIALVR.B Active Production FCBGA (ALV) | 441 500 | LARGE T&R Yes Call TI Level-3-250C-168 HR -40 to 125 AM2431B SDGHIALV 709 AM2431BSDGHIALXR Active Production FCCSP (ALX) | 293 1000 | LARGE T&R Yes Call TI Level-3-250C-168 HR -40 to 125 AM2431B SDGHIALX 709 AM2431BSDGHIALXR.B Active Production FCCSP (ALX) | 293 1000 | LARGE T&R Yes Call TI Level-3-250C-168 HR -40 to 125 AM2431B SDGHIALX 709 AM2432BKEGHIALXR Active Production FCCSP (ALX) | 293 1000 | LARGE T&R Yes Call TI Level-3-250C-168 HR -40 to 125 AM2432B KEGHIALX 709 AM2432BKEGHIALXR.B Active Production FCCSP (ALX) | 293 1000 | LARGE T&R Yes Call TI Level-3-250C-168 HR -40 to 125 AM2432B KEGHIALX 709 AM2432BKFGHIALXR Active Production FCCSP (ALX) | 293 1000 | LARGE T&R Yes Call TI Level-3-250C-168 HR -40 to 125 AM2432B KFGHIALX 709 Addendum-Page 1

www.ti.com 18-Jun-2026 Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) AM2432BKFGHIALXR.B Active Production FCCSP (ALX) | 293 1000 | LARGE T&R Yes Call TI Level-3-250C-168 HR -40 to 125 AM2432B KFGHIALX 709 AM2432BSDFHIALVR Active Production FCBGA (ALV) | 441 500 | LARGE T&R Yes Call TI Level-3-250C-168 HR -40 to 125 AM2432B SDFHIALV 709 AM2432BSDFHIALVR.B Active Production FCBGA (ALV) | 441 500 | LARGE T&R Yes Call TI Level-3-250C-168 HR -40 to 125 AM2432B SDFHIALV 709 AM2432BSDFHIALXR Active Production FCCSP (ALX) | 293 1000 | LARGE T&R Yes Call TI Level-3-250C-168 HR -40 to 125 AM2432B SDFHIALX 709 AM2432BSDFHIALXR.B Active Production FCCSP (ALX) | 293 1000 | LARGE T&R Yes Call TI Level-3-250C-168 HR -40 to 125 AM2432B SDFHIALX 709 AM2432BSDGHIALVR Active Production FCBGA (ALV) | 441 500 | LARGE T&R Yes Call TI Level-3-250C-168 HR -40 to 125 AM2432B SDGHIALV 709 AM2432BSDGHIALVR.B Active Production FCBGA (ALV) | 441 500 | LARGE T&R Yes Call TI Level-3-250C-168 HR -40 to 125 AM2432B SDGHIALV 709 AM2432BSDGHIALXR Active Production FCCSP (ALX) | 293 1000 | LARGE T&R Yes Call TI Level-3-250C-168 HR -40 to 125 AM2432B SDGHIALX 709 AM2432BSDGHIALXR.B Active Production FCCSP (ALX) | 293 1000 | LARGE T&R Yes Call TI Level-3-250C-168 HR -40 to 125 AM2432B SDGHIALX 709 AM2432BSEFHIALVR Active Production FCBGA (ALV) | 441 500 | LARGE T&R Yes Call TI Level-3-250C-168 HR -40 to 125 AM2432B SEFHIALV 709 AM2432BSEFHIALVR.B Active Production FCBGA (ALV) | 441 500 | LARGE T&R Yes Call TI Level-3-250C-168 HR -40 to 125 AM2432B SEFHIALV 709 AM2432BSEFHIALXR Active Production FCCSP (ALX) | 293 1000 | LARGE T&R Yes Call TI Level-3-250C-168 HR -40 to 125 AM2432B SEFHIALX 709 Addendum-Page 2

www.ti.com 18-Jun-2026 Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) AM2432BSEFHIALXR.B Active Production FCCSP (ALX) | 293 1000 | LARGE T&R Yes Call TI Level-3-250C-168 HR -40 to 125 AM2432B SEFHIALX 709 AM2432BSFFHIALVR Active Production FCBGA (ALV) | 441 500 | LARGE T&R Yes Call TI Level-3-250C-168 HR -40 to 125 AM2432B SFFHIALV 709 AM2432BSFFHIALVR.B Active Production FCBGA (ALV) | 441 500 | LARGE T&R Yes Call TI Level-3-250C-168 HR -40 to 125 AM2432B SFFHIALV 709 AM2432BSFFHIALXR Active Production FCCSP (ALX) | 293 1000 | LARGE T&R Yes Call TI Level-3-250C-168 HR -40 to 125 AM2432B SFFHIALX 709 AM2432BSFFHIALXR.B Active Production FCCSP (ALX) | 293 1000 | LARGE T&R Yes Call TI Level-3-250C-168 HR -40 to 125 AM2432B SFFHIALX 709 AM2432BSFFHIANIR Active Production FCCSP (ANI) | 441 1000 | LARGE T&R Yes Call TI Level-3-250C-168 HR -40 to 125 TI AM243 2BSFFHI AM2434BSDFHIALVR Active Production FCBGA (ALV) | 441 500 | LARGE T&R Yes Call TI Level-3-250C-168 HR -40 to 125 AM2434B SDFHIALV 709 AM2434BSDFHIALVR.B Active Production FCBGA (ALV) | 441 500 | LARGE T&R Yes Call TI Level-3-250C-168 HR -40 to 125 AM2434B SDFHIALV 709 AM2434BSDFHIALXR Active Production FCCSP (ALX) | 293 1000 | LARGE T&R Yes Call TI Level-3-250C-168 HR -40 to 125 AM2434B SDFHIALX 709 AM2434BSDFHIALXR.B Active Production FCCSP (ALX) | 293 1000 | LARGE T&R Yes Call TI Level-3-250C-168 HR -40 to 125 AM2434B SDFHIALX 709 AM2434BSDGHIALVR Active Production FCBGA (ALV) | 441 500 | LARGE T&R Yes Call TI Level-3-250C-168 HR -40 to 125 AM2434B SDGHIALV 709 AM2434BSDGHIALVR.B Active Production FCBGA (ALV) | 441 500 | LARGE T&R Yes Call TI Level-3-250C-168 HR -40 to 125 AM2434B SDGHIALV 709 Addendum-Page 3

www.ti.com 18-Jun-2026 Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) AM2434BSDGHIALXR Active Production FCCSP (ALX) | 293 1000 | LARGE T&R Yes Call TI Level-3-250C-168 HR -40 to 125 AM2434B SDGHIALX 709 AM2434BSDGHIALXR.B Active Production FCCSP (ALX) | 293 1000 | LARGE T&R Yes Call TI Level-3-250C-168 HR -40 to 125 AM2434B SDGHIALX 709 AM2434BSEFHIALVR Active Production FCBGA (ALV) | 441 500 | LARGE T&R Yes Call TI Level-3-250C-168 HR -40 to 125 AM2434B SEFHIALV 709 AM2434BSEFHIALVR.B Active Production FCBGA (ALV) | 441 500 | LARGE T&R Yes Call TI Level-3-250C-168 HR -40 to 125 AM2434B SEFHIALV 709 AM2434BSEFHIALXR Active Production FCCSP (ALX) | 293 1000 | LARGE T&R Yes Call TI Level-3-250C-168 HR -40 to 125 AM2434B SEFHIALX 709 AM2434BSEFHIALXR.B Active Production FCCSP (ALX) | 293 1000 | LARGE T&R Yes Call TI Level-3-250C-168 HR -40 to 125 AM2434B SEFHIALX 709 AM2434BSFFHIALVR Active Production FCBGA (ALV) | 441 500 | LARGE T&R Yes Call TI Level-3-250C-168 HR -40 to 125 AM2434B SFFHIALV 709 AM2434BSFFHIALVR.B Active Production FCBGA (ALV) | 441 500 | LARGE T&R Yes Call TI Level-3-250C-168 HR -40 to 125 AM2434B SFFHIALV 709 AM2434BSFFHIALXR Active Production FCCSP (ALX) | 293 1000 | LARGE T&R Yes Call TI Level-3-250C-168 HR -40 to 125 AM2434B SFFHIALX 709 AM2434BSFFHIALXR.B Active Production FCCSP (ALX) | 293 1000 | LARGE T&R Yes Call TI Level-3-250C-168 HR -40 to 125 AM2434B SFFHIALX 709 AM2434BSFFHIANIR Active Production FCCSP (ANI) | 441 1000 | LARGE T&R Yes Call TI Level-3-250C-168 HR -40 to 125 TI AM243 4BSFFHI (1) Status: For more details on status, see our product life cycle. Addendum-Page 4

www.ti.com 18-Jun-2026 (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 5

PACKAGE MATERIALS INFORMATION www.ti.com 19-Jun-2026 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 19-Jun-2026 Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 19-Jun-2026 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) AM2431BSDFHIALVR FCBGA ALV 441 500 336.6 336.6 41.3 AM2431BSDFHIALXR FCCSP ALX 293 1000 336.6 336.6 41.3 AM2431BSDGHIALVR FCBGA ALV 441 500 336.6 336.6 41.3 AM2431BSDGHIALXR FCCSP ALX 293 1000 336.6 336.6 41.3 AM2432BKEGHIALXR FCCSP ALX 293 1000 336.6 336.6 41.3 AM2432BKFGHIALXR FCCSP ALX 293 1000 336.6 336.6 41.3 AM2432BSDFHIALVR FCBGA ALV 441 500 336.6 336.6 41.3 AM2432BSDFHIALXR FCCSP ALX 293 1000 336.6 336.6 41.3 AM2432BSDGHIALVR FCBGA ALV 441 500 336.6 336.6 41.3 AM2432BSDGHIALXR FCCSP ALX 293 1000 336.6 336.6 41.3 AM2432BSEFHIALVR FCBGA ALV 441 500 336.6 336.6 41.3 AM2432BSEFHIALXR FCCSP ALX 293 1000 336.6 336.6 41.3 AM2432BSFFHIALVR FCBGA ALV 441 500 336.6 336.6 41.3 AM2432BSFFHIALXR FCCSP ALX 293 1000 336.6 336.6 41.3 AM2432BSFFHIANIR FCCSP ANI 441 1000 336.6 336.6 41.3 AM2434BSDFHIALVR FCBGA ALV 441 500 336.6 336.6 41.3 AM2434BSDFHIALXR FCCSP ALX 293 1000 336.6 336.6 41.3 AM2434BSDGHIALVR FCBGA ALV 441 500 336.6 336.6 41.3 Pack Materials-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 19-Jun-2026 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) AM2434BSDGHIALXR FCCSP ALX 293 1000 336.6 336.6 41.3 AM2434BSEFHIALVR FCBGA ALV 441 500 336.6 336.6 41.3 AM2434BSEFHIALXR FCCSP ALX 293 1000 336.6 336.6 41.3 AM2434BSFFHIALVR FCBGA ALV 441 500 336.6 336.6 41.3 AM2434BSFFHIALXR FCCSP ALX 293 1000 336.6 336.6 41.3 AM2434BSFFHIANIR FCCSP ANI 441 1000 336.6 336.6 41.3 Pack Materials-Page 4

www.ti.com PACKAGE OUTLINE 11.1 10.9 11.1 10.9

1 MAX

0.29 0.15 293X 0.37 0.27

10 TYP

0.5 TYP

(0.5) (0.5) FCCSP - 1 mm max heightALX0293A PLASTIC BALL GRID ARRAY 4226368/B 02/2023 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. BALL A1 CORNER 0.15 C 0.1 C SEATING PLANE 0.2 C

0.15 C A B

0.05 C SYMM SYMM A B C D E F G H J K L M N P R T U V W Y AA 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 SCALE 1.500 AB C

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

0.05 MIN

(0.5) TYP (0.5) TYP 293X ( 0.3) ( 0.3) METAL EDGE ( 0.3) SOLDER MASK OPENING FCCSP - 1 mm max heightALX0293A PLASTIC BALL GRID ARRAY 4226368/B 02/2023 NOTES: (continued) 3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For information, see Texas Instruments literature number SPRAA99 (www.ti.com/lit/spraa99). LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM SYMM A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 B C D E F G H J K L M N P R T U V W Y AA EXPOSED METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL SOLDER MASK DETAILS NOT TO SCALE NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN (0.5) TYP (0.5) TYP 293X ( 0.3) FCCSP - 1 mm max heightALX0293A PLASTIC BALL GRID ARRAY 4226368/B 02/2023 NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 B C D E F G H J K L M N P R T U V W Y AA

www.ti.com PACKAGE OUTLINE C 2.652 2.332 0.5

0.3 TYP

16 TYP

0.8 TYP

441X 0.55 0.45 PIN 1 ID (OPTIONAL) B 17.3 17.1 A 17.3 17.1 (0.6) TYP (0.6) TYP ( 12.8) ( 10.8) ( 16.8) (1.45) (0.662) FCBGA - 2.657 mm max heightALV0441A BALL GRID ARRAY 4225999/A 06/2020 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. BALL A1 CORNER 0.1 C SEATING PLANE 0.15 C 0.2 C 1 2 3

0.25 C A B

0.1 C SYMM SYMM 4 5 6 7 8 9 10 A B C D E F G H J K L M N P R T U V W Y AA SCALE 0.900

www.ti.com EXAMPLE BOARD LAYOUT (0.8) TYP ( 0.4) METAL

0.07 MAX

( 0.4) SOLDER MASK OPENING

0.07 MIN

FCBGA - 2.657 mm max heightALV0441A BALL GRID ARRAY 4225999/A 06/2020 NOTES: (continued) 3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For more information, see Texas Instruments literature number SPRU811 (www.ti.com/lit/spru811). SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SNOWN SCALE:6X A B C D E F G H J K L M N P 2 3 4 5 6 7 8 9 10 11 12 13 14 R T 15 16 U V W Y AA 17 18 19 20 21 NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS NOT TO SCALE EXPOSED METAL SOLDER MASK DEFINED EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN 441X 0.4 (0.8) TYP (0.8) TYP FCBGA - 2.657 mm max heightALV0441A BALL GRID ARRAY 4225999/A 06/2020 NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. SOLDER PASTE EXAMPLE BASED ON 0.15 mm THICK STENCIL SCALE: 6X SYMM SYMM A B C D E F G H J K L M N P 2 3 4 5 6 7 8 9 10 11 12 13 14 R T 15 16 U V W Y AA 17 18 19 20 21

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you fully indemnify TI and its representatives against any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale, TI’s General Quality Guidelines, or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Unless TI explicitly designates a product as custom or customer-specified, TI products are standard, catalog, general purpose devices. TI objects to and rejects any additional or different terms you may propose. IMPORTANT NOTICE Copyright © 2026, Texas Instruments Incorporated Last updated 10/2025

Product Information

AM2434BSEFHIALXR specifications and overview.

Summary

AM243x Sitara™ Microcontrollers REVISED JUNE 2026

Description

AM243x Sitara™ Microcontrollers REVISED JUNE 2026

Source title AM2434BSEFHIALXR Datasheet(PDF) - Texas Instruments

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