ALVC125

SN74ALVC125 TI | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 11

Technical content

www.ti.com

FEATURES

D, DGV, NS, OR PW PACKAGE (TOP VIEW) 1OE 2OE GND V CC 4OE 3OE DESCRIPTION/ORDERING INFORMATION 1OE 21A 1Y3 2OE 52A 2Y6 3OE 93A 3Y8 4OE 124A 4Y11 SN74ALVC125 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCES110H JULY 1997 REVISED SEPTEMBER 2004 Operates from 1.65 V to 3.6 V Max t pd of 2.8 ns at 3.3 V 24-mA Output Drive at 3.3 V Latch-up Performance Exceeds 250 mA Per JESD ESD Performance Exceeds JESD 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101) This quadruple bus buffer gate is designed for 1.65-V to 3.6-V V CC operation. The SN74ALVC125 outputs. Each output is disabled when the associated output-enable OE input is high. To ensure the high-impedance state during power up or power down, OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION T A PACKAGE (1) ORDERABLE PART NUMBER TOP-SIDE MARKING Tube SN74ALVC125D SOIC D ALVC125 Tape and reel SN74ALVC125DR SOP NS Tape and reel SN74ALVC125NSR ALVC125 -40 C to C Tube SN74ALVC125PW TSSOP PW VA125 Tape and reel SN74ALVC125PWR TVSOP DGV Tape and reel SN74ALVC125DGVR VA125 (1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each buffer) INPUTS OUTPUT Y OE A L H H L L L H X Z LOGIC DIAGRAM (POSITIVE LOGIC) Please be aware that an important notice concerning availability, standard warranty, and use in critical

applications

sheet. PRODUCTION DATA information is current as of publication date. Copyright 1997 2004, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

www.ti.com ABSOLUTE MAXIMUM RATINGS (1) RECOMMENDED OPERATING CONDITIONS (1) SN74ALVC125 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCES110H JULY 1997 REVISED SEPTEMBER 2004 over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT V CC Supply voltage range -0.5 4.6 V V I Input voltage range (2) -0.5 4.6 V V O Output voltage range (2) (3) -0.5 V CC 0.5 V I IK Input clamp current V I -50 mA I OK Output clamp current V O -50 mA I O Continuous output current mA Continuous current through V CC or GND 100 mA D package DGV package 127 θ JA Package thermal impedance (4) C/W NS package PW package 113 T stg Storage temperature range -65 150 C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. (3) This value is limited to 4.6 V maximum. (4) The package thermal impedance is calculated in accordance with JESD 51-7. MIN MAX UNIT V CC Supply voltage 1.65 3.6 V V CC 1.65 V to 1.95 V 0.65 V CC V IH High-level input voltage V CC 2.3 V to 2.7 V 1.7 V V CC 2.7 V to 3.6 V V CC 1.65 V to 1.95 V 0.35 V CC V IL Low-level input voltage V CC 2.3 V to 2.7 V 0.7 V V CC 2.7 V to 3.6 V 0.8 V I Input voltage 3.6 V V O Output voltage V CC V V CC 1.65 V V CC 2.3 V -12 I OH High-level output current mA V CC 2.7 V -12 V CC V -24 V CC 1.65 V V CC 2.3 V I OL Low-level output current mA V CC 2.7 V V CC V T A Operating free-air temperature -40 C (1) All unused inputs of the device must be held at V CC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs literature number SCBA004.

www.ti.com ELECTRICAL CHARACTERISTICS SWITCHING CHARACTERISTICS OPERATING CHARACTERISTICS SN74ALVC125 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCES110H JULY 1997 REVISED SEPTEMBER 2004 over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS V CC MIN TYP (1) MAX UNIT I OH -100 µ A 1.65 V to 3.6 V V CC 0.2 I OH mA 1.65 V 1.2 I OH mA 2.3 V V OH 2.3 V 1.7 V I OH -12 mA 2.7 V 2.2 V 2.4 I OH -24 mA V I OL 100 µ A 1.65 V to 3.6 V 0.2 I OL mA 1.65 V 0.45 I OL mA 2.3 V 0.4 V OL V 2.3 V 0.7 I OL mA 2.7 V 0.4 I OL mA V 0.55 I I V I V CC or GND 3.6 V µ A I OZ V O V CC or GND 3.6 V µ A I CC V I V CC or GND, I O 3.6 V µ A Δ I CC One input at V CC 0.6 Other inputs at V CC or GND V to 3.6 V 750 µ A Control inputs 3.5 C i V I V CC or GND 3.3 V pF Data inputs 3.5 C o Outputs V O V CC or GND 3.3 V 5.5 pF (1) All typical values are at V CC 3.3 T A over recommended operating free-air temperature range (unless otherwise noted) (see Figure V CC 1.8 V V CC 2.5 V V CC 3.3 V V CC 2.7 V FROM TO 0.15 V 0.2 V 0.3 V PARAMETER UNIT (INPUT) (OUTPUT) MIN MAX MIN MAX MIN MAX MIN MAX t pd A Y 1.3 5.3 3.2 3.1 1.1 2.8 ns t en OE Y 1.4 6.4 4.1 4.3 3.5 ns t dis OE Y 1.8 5.9 3.4 1.4 ns T A C V CC 1.8 V V CC 2.5 V V CC 3.3 V TEST PARAMETER UNIT CONDITIONS TYP TYP TYP Outputs enabled Power dissipation C L C pd pF capacitance per gate f MHz Outputs disabled

www.ti.com PARAMETER MEASUREMENT INFORMATION VM VM VMVM VMVM VMVM VOH VOL thtsu From Output Under Test CL (see Note A) LOAD CIRCUIT S1 Open GND RL RL Output Control (low-level enabling) Output Waveform 1 S1 at VLOAD (see Note B) Output Waveform 2 S1 at GND (see Note B) tPZL tPZH tPLZ tPHZ 0 V VOL + VΔ VOH − VΔ 0 V VI 0 V 0 V tw VI VI VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES Timing Input Data Input Input tpd tPLZ/tPZL tPHZ/tPZH Open VLOAD GND TEST S1 NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ /char????????10 MHz, ZO = 50 Ω . D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. 0 V VI VM tPHL VM VM VI 0 V VOH VOL Input Output VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VM VM tPLH VLOAD VLOAD/2 2.7 V 1 kΩ 500 Ω 500 Ω 500 Ω VCC RL 2 × VCC 2 × VCC 6 V 6 V VLOAD CL 30 pF 30 pF 50 pF 50 pF 0.15 V 0.15 V 0.3 V 0.3 V VΔ VCC VCC 2.7 V 2.7 V VI VCC/2 VCC/2 1.5 V 1.5 V VM tr/tf ≤ 2 ns ≤ 2 ns ≤ 2.5 ns ≤ 2.5 ns INPUT SN74ALVC125 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCES110H JULY 1997 REVISED SEPTEMBER 2004 Figure Load Circuit and Voltage Waveforms

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) SN74ALVC125D ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALVC125DE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALVC125DGVR ACTIVE TVSOP DGV 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALVC125DGVRE4 ACTIVE TVSOP DGV 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALVC125DR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALVC125DRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALVC125DRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALVC125NSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALVC125NSRE4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALVC125PW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALVC125PWE4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALVC125PWG4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALVC125PWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALVC125PWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALVC125PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. PACKAGE OPTION ADDENDUM www.ti.com 18-Jul-2006 Addendum-Page 1

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 18-Jul-2006 Addendum-Page 2

MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE

24 PINS SHOWN

3,70 3,50 4,90 5,10 20DIM PINS ** 4073251/E 08/00 1,20 MAX Seating Plane 0,05 0,15 0,25 0,50 0,75 0,23 0,13 11 2 24 13 4,30 4,50 0,16 NOM Gage Plane A 7,90 7,70 382416 4,90 5,103,70 3,50 A MAX A MIN 6,60 6,20 11,20 11,40 9,60 9,80 0,08 M0,070,40 0°–8° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. D. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,65 M0,10 0,10 0,25 0,50 0,75 0,15 NOM Gage Plane 9,80 9,60 7,90 7,70 2016 6,60 6,40 4040064/F 01/97 0,30 6,60 6,20 0,19 4,30 4,50 0,15 A 1,20 MAX 5,10 4,90 3,10 2,90 A MAX A MIN DIM PINS ** 0,05 4,90 5,10 Seating Plane 0°–8° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security Low Power Wireless www.ti.com/lpw Telephony www.ti.com/telephony Video & Imaging www.ti.com/video Wireless www.ti.com/wireless Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright  2006, Texas Instruments Incorporated