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Technical content

Features

ESD Protection:Level 4 Working voltage : 5V Low clamping voltage

100 Watts peak pulse power per line(tp=8/20µs)

Protection one line I/O port ESD/ALSD05BT IEC Compatibility EN61000 -4 IEC61000-4-2(ESD):Level 4,Contact:±30kv,Air:±30kv IEC61000-4-4(EFT):40A -5/50ns IEC61000-4-5(Surge):4A -8/20µs Mechanical Characteristics Molding Compound Flammability Rating : UL 94V-O Quantity Per Reel : 10,000pcs Reel Size : 7 inch Lead Finish : Lead Free

Applications

USB 2.0 Power and Data line Protection 0402 Pin Configuration REV 2017 07 24 AEC-Q101

/UNI77ac/UNI96f7/UNI7535/UNI5b50 SPSEMI www.spsemi.cn Page 2 of 3 Parameter Symbol Value Units Peak Pulse Power(tp=8/20µs) Operating Temperature Range Storage Temperature Range P PP T J T STG 100 -55~150 -55~150 Watts Maximum Ratings (T =25 unless otherwise specified ) A

Electrical Characteristics

(T =25 unless otherwise specified ) A Ratings and Characteristic Curves Fig.2 Pulse Waveform 501 0 3 0 150 Time( ) µs 20 25 100 110 Percent of I PP t= I / 2 d PP Waveform Parameters: tr=8µs t =20µs d e Parameter Symbol Conditions UnitsMin. Max. ALSD05BT(Marking:None) Reverse Stand-off Voltage Reverse Breakdown Voltage Reverse Leakage Current Forward Voltage Clamping Voltage Peak Pulse Current Junction Capacitance V RWM V BR R I F V C V PP I C I/O 9.4 1.15 Pin2 to 1 / Pin1 to 2 Iz=1mA,Pin2 to 1 / Pin1 to 2 RWM I =15mA F I =1A,tp=8/20µs PP tp=8/20µs 5.6 V V µA V V A F p 0Vdc,f=1MHz Between I/O Pins and GND Fig.1 Power Derating Curve 250 500 T ,Ambient Temperature( ) A 75 100 100 Peak Power Dissipation (%) 125 150 120 .. . ESD/ALSD05BT REV 2017 07 24

www.spsemi.cn Page 3 of 3 /UNI77ac/UNI96f7/UNI7535/UNI5b50 SPSEMI Dimensions(0402) 0402 Recommended Mounting Pad Layout 1.20 0.047 0.75 0.030 0.75 0.030 A B C DIM A B C D1/D2 Millimeters Min 0.90 0.50 0.10 Max 1.10 0.70 0.60 0.40 Min 0.035 0.020 0.004 Max 0.043 0.027 0.023 0.016 Inches D1 D2 C B .. . ESD/ALSD05BT

Application Information

PCB Layout Recommendations The location and circuit board layout is critical to maximize the effectiveness of the I/O protection circuit. The following guidelines are recommended: Locate the protection devices as close as possible to the I/O connector. This allows the protection devices to absorb the energy of the transient voltage before it can be coupled into the adjacent traces on the PCB. Minimize the loop area for the high.speed data lines, power and ground lines to reduce the radiated emissions. Avoid running protection conductors in parallel with unprotected conductors Use ground planes wherever possible to reduce the parasitic capacitance and inductance of the PCB that degrades the effectiveness of a filter device. Using shared transient return paths to a common ground point. I/O Protection REV 2017 07 24